54HC164_V01 SS | Alldatasheet
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Technical content
High Speed CMOS Logic – 54HC164 8-Bit Serial-Input / Parallel-Output Shift Register in bare die form Rev 1.0 24/11/17 Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54LS164 Full Military Temperature Range. Features:
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT The 54HC164 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. The device consists of x2 serial data inputs, A and B, provided so that one input can be used as a data enable. Data is entered on each rising edge of the clock. A LOW on the master reset input (CLR) clears the register, forcing all outputs LOW, independent of other inputs. Inputs are compatible with standard CMOS outputs and LSTTL via use of pull-up resistors. All inputs are equipped with protection circuits against static discharge & transient excess voltage.
Description
Die Dimensions in µm (mils) 1060 (41) 1370 (54) “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Die Size (Unsawn) 1060 x 1370 41 x 54 µm mils Minimum Bond Pad Size 100 x 100 3.94 x 3.94 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Page 1 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com d High Speed CMOS Logic – 54HC164 Rev 1.0 24/11/17 Logic Diagram 1060µm (41.73 mils) 1370µm (53.93 mils) 0,0 10 9 6 5 4 3 2 11 12 13 DIE ID COORDINATES (mm) PAD FUNCTION X Y 1 A 0.117 0.439 2 B 0.124 0.115 3 QA 0.3195 0.115 4 QB 0.4875 0.115 5 QC 0.6555 0.115 6 QD 0.8235 0.115 7 GND 0.841 0.61 8 CLK 0.841 0.831 9 CLR 0.833 1.155 10 QE 0.6385 1.155 11 QF 0.4705 1.155 12 QG 0.3025 1.155 13 QH 0.1345 1.155 14 VCC 0.117 0.662 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions D = Data Input QAn - QGn = Data shift from preceding register on rising edge clock input Function Table INPUTS OUTPUTS CLR CLK A B Q A Q B … QH L H H H H X L X X H L X X X H X L L Q H L L L Q QAN QAN QAN L QH0 QGN QGN QGn PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise and Fall Time VCC = 6.0V tr, tf 0 400 Ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pin IIN ±20 mA DC Output Current, per pin IOUT ±25 mA DC VCC or GND Current, per pin ICC ±50 mA Power Dissipation in Still Air PD 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 54HC164 Rev 1.0 24/11/17 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. For proper opera tion, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or VCC). Unused outputs must be left open. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 1.5 1.5 1.5 3V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2V 0.5 0.5 0.5 3V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC164 Rev 1.0 24/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 2.48 2.34 2.20 V 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.20 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 0.26 0.33 0.40 V 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 V Maximum Low-Level Output Voltage VOL 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 4 40 160 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 10 10 10 3.0V 20 20 20 4.5V 40 35 30 Maximum Clock Frequency, (50% duty cycle) fmax 6.0V CL = 50pF, tr = tf = 6ns 50 45 40 ns 2.0V 160 200 250 3.0V 100 150 200 4.5V 32 40 48 Maximum Propagation Delay, CLK to Q tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 27 34 42 ns 5. Not production tested in die form, characterized by chip design and tested in package. PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC164 Rev 1.0 24/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 175 220 265 3.0V 100 150 200 4.5V 35 44 53 Maximum Propagation Delay, CLR to Q tPHL 6.0V CL = 50pF, tr = tf = 6ns 30 37 45 ns 2.0V 75 95 110 3.0V 27 32 36 4.5V 15 19 22 Maximum Output Transition time, Any Output tTLH, tTHL 6.0V CL = 50pF, tr = tf = 6ns 13 16 19 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance Per Gate6 CPD - TJ = 25°C, VCC =5.0V 180 pF 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Timing Requirements5 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 25 35 40 3.0V 15 20 25 4.5V 7 8 9 Minimum Setup Time, A or B to Clock tsu 6.0V tr = tf = 6ns 5 6 6 ns 2.0V 3 3 3 3.0V 3 3 3 4.5V 3 3 3 Minimum Hold Time, Clocl to A or B th 6.0V tr = tf = 6ns 3 3 3 ns 2.0V 3 3 3 3.0V 3 3 3 4.5V 3 3 3 Minimum Recovery Time, Reset Inactive to Clock trec 6.0V tr = tf = 6ns 3 3 3 ns 2.0V 50 60 75 3.0V 26 35 45 4.5V 12 15 20 Minimum Pulse Width, Clock tw 6.0V tr = tf = 6ns 10 12 15 ns 2.0V 1000 1000 1000 3.0V 800 800 800 4.5V 500 500 500 Maximum Input Rise & Fall Times tr, tf 6.0V tr = tf = 6ns 400 400 400 ns PART OBSOLETE - DISCONTINUED