54HC154

54HC154_V01 SS | Alldatasheet

Document overview

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Technical content

www.siliconsupplies.com Die Size (Unsawn) 2400 x 1650 95 x 65 µm mils Minimum Bond Pad Size 120 x 120 4.72 x 4.72 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si High Speed CMOS Logic – 54HC154 Dual 1-of-16 Decoder / Demultiplexer in bare die form  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1µA  Outputs directly inter face CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with 54LS154  Full Military Temperature Range. Rev 1.0 30/05/22 Features:

Ordering Information

The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (100 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request The 54HC154 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. The device consists of x4 active-high binary address inputs, x16 active-low outputs & x2 active-low chip-selects. The x2 active-low chip-selects can be used to strobe & eliminate normal decoding ‘glitches’ on the outputs, or can be used to expand the decoder. Both chip-selects must be low to enable the outputs. The demultiplexing function is executed by use of one chip-select input as multiplexed data input. When the other chip-select input is low, the addressed output will follow the state of the applied data.

Description

Die Dimensions in µm (mils) 2400 (95) 1650 (65) PART OBSOLETE - DISCONTINUED

d High Speed CMOS Logic – 54HC154 Rev 1.0 30/05/22Pad Layout and Functions COORDINATES (mm) PAD FUNCTION X Y 1 Y0 0.140 0.522 2 Y1 0.140 0.377 3 Y2 0.140 0.142 4 Y3 0.645 0.132 5 Y4 0.833 0.132 6 Y5 1.021 0.132 7 Y6 1.210 0.132 8 Y7 1.490 0.132 9 Y8 2.138 0.142 10 Y9 2.138 0.342 11 Y10 2.138 0.537 12 GND 2.138 0.724 13 Y11 2.138 0.992 14 Y12 2.138 1.187 15 Y13 2.138 1.387 16 Y14 1.397 1.490 17 Y15 1.210 1.397 18 CS1 1.005 1.397 19 CS2 0.795 1.397 20 A3 0.590 1.397 21 A2 0.140 1.387 22 A1 0.140 1.179 23 A0 0.140 0.971 24 VCC 0.140 0.707 CONNECT CHIP BACK TO VCC OR FLOAT Truth Table 2400µm (94.49 mils) 1650µm (64.96 mils) 0,0 19 20 21 16 17 18 3 4 5 6 7 8 9 DIE ID Logic Diagram SEE PAGE 5 Pad 24 = VCC Pad 12 = GND Page 2 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise and Fall Time VCC = 6.0V tr, tf 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pin IIN ±20 mA DC Output Current, per pin IOUT ±25 mA DC VCC or GND Current, per pin ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 54HC154 Rev 1.0 30/05/22 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. For proper opera tion, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or VCC). Unused outputs must be left open. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0V 0.3 0.3 0.3 4.5V 0.9 0.9 0.9 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.2 1.2 1.2 V PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com High Speed CMOS Logic – 54HC154 Rev 1.0 30/05/22 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.20 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 Maximum Low-Level Output Voltage VOL 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 8 80 160 µA 6. Not production tested in die form, characterized by chip design and tested in package. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 190 240 285 4.5V 38 48 57 Maximum Propagation Delay, Select to Output Y (Figure 1, 3) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 32 41 48 ns 2.0V 175 220 265 4.5V 35 44 53 Maximum Propagation Delay, Input A to Output Y (Figure 2,3) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 30 37 45 ns 2.0V 75 95 110 4.5V 15 19 22 Maximum Output Transition Time, Any Output (Figure 1,3) tTLH, tTHL 6.0V CL = 50pF, tr = tf = 6ns 13 16 19 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance7 CPD - TJ = 25°C, VCC = 5.0V 80 pF PART OBSOLETE - DISCONTINUED

High Speed CMOS Logic – 54HC154 Rev 1.0 30/05/22 Pad Description ADDRESS INPUTS A0, A1, A2, A3 (Pads 23, 22, 21, 20) These inputs, when the 1-of-16 decoder is enabled, determine which of its sixteen active-low outputs is selected. CONTROL INPUTS CS1, CS2 (Pads 18, 19) Active-low chip-select inputs. With a low level on both inputs, the outputs of the decoder follow the Address inputs. A high level on either input forces all outputs to a high level. OUTPUTS Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15 (Pads 1-11, Pads 13-17) Active-low outputs. These outputs assume a low level when addressed and both chip-select inputs are active. These outputs remain high when not addressed or when a chip-select input is high. Truth Table Page 5 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED