54HC14 SS | Alldatasheet
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High Speed CMOS Logic – 54HC14 Hex Schmitt-Trigger Inverter Logic IC in bare die form Die Size (Unsawn) 1250 x 1250 49 x 49 µm mils Minimum Bond Pad Size 100 x 100 3.94 x 3.94 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54LS14 Full Military Temperature Range. Rev 1.0 24/11/17 Features:
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The 54HC14 Hex Schmitt-Trigger Inverter is fabricated using a 2.5µm 5V CMOS process with the same high speed performance of LSTTL combined with CMOS low power consumption. The device performs the Boolean function Y = Ᾱ in positive logic. Device inputs are compatible with Standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Schmitt-Trigger inputs transform slow input rise and fall times into sharply defined jitter-free output signals. Due to the hysteresis voltage of the Schmitt trigger, the 54HC14 is useful in noisy environments. Die Dimensions in µm (mils) The following part suffixes apply: 1250 (49) No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT 1250 (49) “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com d High Speed CMOS Logic – 54HC14 Rev 1.0 24/11/17 COORDINATES (mm) PAD FUNCTION X Y 1 1A 0.14 0.345 2 1Y 0.14 0.141 3 2A 0.319 0.141 4 2Y 0.577 0.141 5 3A 0.817 0.141 6 3Y 1.019 0.141 7 GND 1.036 0.47 8 4Y 1.036 0.749 9 4A 1.006 1.007 10 5Y 0.8 1.007 11 5A 0.584 1.007 12 6Y 0.334 1.007 13 6A 0.141 0.969 14 VCC 0.14 0.663 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Logic Diagram 1250µm (49.21 mils) 1250µm (49.21 mils) 0,0 2 3 4 5 6 9 10 11 12 DIE ID Function Table INPUTS A OUTPUT Y L H H L H = High level (steady state) L = Low level (steady state) Pad 14 = VCC Pad 7 = GND Y = Ᾱ A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 54HC14 Rev 1.0 24/11/17 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 2.0V VCC = 4.5V Input Rise or Fall Times tr, tf VCC = 6.0V - No limit* ns * When VIN = 50% VCC, ICC > 1mA. Recommended Operating Conditions3 (Voltages Referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.50 1.50 1.50 3.0V 2.15 2.15 2.15 4.5V 3.15 3.15 3.15 Maximum Positive- Going Input Threshold Voltage VT+ MAX 6.0V VOUT = 0.1V │IOUT│≤ 20µA 4.20 4.20 4.20 V 2.0V 1.0 0.95 0.95 3.0V 1.5 1.45 1.45 4.5V 2.3 2.25 2.25 Minimum Positive- Going Input Threshold Voltage VT+ MIN 6.0V VOUT = 0.1V │IOUT│≤ 20µA 3.0 2.95 2.95 V 2.0V 0.9 0.95 0.95 3.0V 1.4 1.45 1.45 4.5V 2.0 2.05 2.05 Maximum Negative-Going Input Threshold Voltage VT- MAX 6.0V VOUT = VCC -0.1V │IOUT│≤ 20µA 2.6 2.65 2.65 V 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 54HC14 Rev 1.0 24/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 0.3 0.3 0.3 3.0V 0.5 0.5 0.5 4.5V 0.9 0.9 0.9 Minimum Negative- Going Input Threshold Voltage VT- MIN 6.0V VOUT = VCC -0.1V │IOUT│≤ 20µA 1.2 1.2 1.2 V 2.0V 1.20 1.20 1.20 3.0V 1.65 1.65 1.65 4.5V 2.25 2.25 2.25 Maximum Hysteresis Voltage4 VH MAX 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 3.00 3.00 3.00 V 2.0V 0.20 0.20 0.20 3.0V 0.25 0.25 0.25 4.5V 0.40 0.40 0.40 Minimum Hysteresis Voltage3 VH MIN 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 0.50 0.50 0.50 V 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN ≤ VT- MIN │IOUT│≤ 20µA 5.9 5.9 5.9 V 3.0V VIN ≤ VT- MIN │IOUT│≤ 2.4mA 2.48 2.34 2.20 V 4.5V VIN ≤ VT- MIN │IOUT│≤ 4.0mA 3.98 3.84 3.70 V Minimum High-Level Output Voltage VOH 6.0V VIN ≤ VT- MIN │IOUT│≤ 5.2mA 5.48 5.34 5.20 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN ≥ VT+ MAX │IOUT│≤ 20µA 0.1 0.1 0.1 V
3.0 VIN ≥ VT+ MAX
│IOUT│≤ 2.4mA 0.26 0.33 0.4 V 4.5V VIN ≥ VT+ MAX │IOUT│≤ 4.0mA 0.26 0.33 0.4 V Maximum Low-Level Output Voltage VOL 6.0V VIN ≥ VT+ MAX │IOUT│≤ 5.2mA 0.26 0.33 0.4 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 1.0 10 40 µA 4. -55˚C ≤ TJ ≤ +125˚C 5. VH MIN > (VT+ MIN) - (VT- MAX); VH MAX = (VT+ MAX)+(VT- MIN) A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 54HC14 Rev 1.0 24/11/17 AC Electrical Characteristics6 LIMITS PARAMETER DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 2.0V 75 95 110 3.0V 30 40 55 4.5V 15 19 22 Maximum Propagation CL = 50pF, Delay, Input A or B to Output Y (Figure 1) tPLH, tPHL ns tr = tf = 6ns 6.0V 13 16 19 2.0V 75 95 110 3.0V 27 32 36 4.5V 15 19 22 Maximum Transition CL = 50pF, Time, Any Output (Figure 1) tTLH, tTHL ns tr = tf = 6ns 6.0V 13 16 19 Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation TJ = 25°C, VCC pF Capacitance7 CPD - = 5.0V 22 6. Not production tested in die form, characterized by chip design and tested in package LAT. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Switching Waveform DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Figure 1 – Propagation Delay, Transition Timing A ll data sheet.com