74HC138 SS | Alldatasheet
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Technical content
High Speed CMOS Logic – 74HC138 Rev 1.0 23/11/17 3-Line to 8-Line Decoder / Demultiplexer in bare die form Features: Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS138.
Ordering Information
The following part suffixes apply: The 74HC138 is fabricated using a 2.5µm 5V CMOS process with the same high speed performance of LSTTL combined with CMOS low power consumption. Inputs are compatible with standard CMOS outputs and LSTTL outputs by using pull-up resistors. The device decodes a three–bit Address to one–of–eight active–low outputs. Featuring three Chip Select inputs, two active–low & one active–high to facilitate the demultiplexing, cascading, and chip–selecting functions. The demultiplexing function uses the Address inputs to select desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states.
Description
Die Dimensions in µm (mils) 1450 (57) No suffix - MIL-STD-883 /2010B Visual Inspection Die Size (Unsawn) 1450 x 1500 57 x 59 µm mils Minimum Bond Pad Size 100 x 100 4 x 4 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si For High Reliability versions of this product please see 54HC138 Supply Formats: Mechanical Specification 1500 (59) Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 6 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com d High Speed CMOS Logic – 74HC138 Rev 1.0 23/11/17 COORDINATES (mm) PAD FUNCTION X Y 1 A0 0.149 0.823 2 A1 0.149 0.409 3 A2 0.111 0.239 4 CS2 0.446 0.129 5 CS3 0.723 0.129 6 CS1 1.004 0.129 7 Y7 1.195 0.203 8 GND 1.217 0.566 9 Y6 1.207 0.832 10 Y5 1.197 1.204 11 Y4 1.000 1.294 12 Y3 0.827 1.294 13 Y2 0.653 1.294 14 Y1 0.479 1.294 15 Y0 0.178 1.238 16 VCC 0.147 0.980 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions 1450µm (57.09 mils) Truth Table 1500µm (59.05 mils) 0,0 12 11 6 5 4 DIE ID 13 14 INPUTS OUTPUTS CS1 CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L H = High level (steady state) L = Low level (steady state) X = Don’t care A ll data sheet.com
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ 0 +85 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise and Fall Times (Figure 2) VCC = 6.0V tr, tf 0 400 ns Recommended Operating Conditions (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC VCC or GND Current, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 74HC138 Rev 1.0 23/11/17 Logic Diagram 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PIN 14 = VCC PIN 7 = GND Pad Descriptions ADDRESS INPUTS A0, A1, A2 (Pads 1, 2, 3) Address inputs. These inputs, when the chip is selected, determine which of the eight outputs is active–low. CONTROL INPUTS CS1, CS2, CS3 (Pads 6, 4, 5) Chip select inputs. For CS1 at a high level and CS2, CS3 at a low level, the chip is selected and the outputs follow the Address inputs. For any other combination of CS1, CS2, and CS3, the outputs are at a logic high. OUTPUTS Y0 – Y7 (Pads 15, 14, 13, 12, 11, 10, 9, 7) Active–low Decoded outputs. These outputs assume a low level when addressed and the chip is selected. These outputs remain high when not addressed or the chip is not selected. A ll data sheet.com
High Speed CMOS Logic – 74HC138 Rev 1.0 23/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE3 UNITS 2.0V 1.5 1.5 1.5 3.0V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 VOUT = 0.1V or VCC -0.1V Minimum High-Level Input Voltage VIH V │IOUT│≤ 20µA 6.0V 4.2 4.2 4.2 2.0V 0.5 0.5 0.5 3.0V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 2.48 2.34 2.34 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.84 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.34 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 0.26 0.33 0.33 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage VOL 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.33 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Leakage Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 4 40 40 µA Page 4 of 6 www.siliconsupplies.com A ll data sheet.com
High Speed CMOS Logic – 74HC138 Rev 1.0 23/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE3 25°C 85°C 2.0V 135 170 170 3.0V 90 125 125 4.5V 27 34 34 Maximum Propagation CL = 50pF, Delay, Input A to Output Y (Figure 1, 4) tPLH, tPHL ns tr = tf = 6ns 6.0V 23 29 29 2.0V 110 140 140 3.0V 85 100 100 4.5V 22 28 28 Maximum Propagation CL = 50pF, Delay, CS1 to Output Y (Figure 2, 4) tPLH, tPHL ns tr = tf = 6ns 6.0V 19 24 24 2.0V 120 150 150 3.0 90 120 120 4.5V 24 30 30 Maximum Propagation CL = 50pF, Delay, CS2 or CS3 to Output Y (Figure 3, 4) tPLH, tPHL ns tr = tf = 6ns 6.0V 20 26 26 2.0V 75 95 95 3.0V 30 40 40 4.5V 15 19 19 Maximum Output Rise and Fall Time, Any CL = 50pF, Output (Figure 2, 4) tTLH, tTHL ns tr = tf = 6ns 6.0V 13 16 16 Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation TJ = 25°C, VCC pF Capacitance5 CPD - = 5.0V 55 4. Not production tested in die form, characterized by chip design and tested in package. 5. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Switching Waveforms Figure 1 – Propagation Delay, Input A to Output Y Figure 2 - Propagation Delay, Input CS1 to Output Y Page 5 of 6 www.siliconsupplies.com A ll data sheet.com