54HC132_V01 SS | Alldatasheet
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High Speed CMOS Logic – 54HC132 Quadruple 2-Input NAND Gate IC with Schmitt-Trigger Inputs in bare die form Rev 1.0 21/11/17 High Speed: t PD = 11ns @ 5V (Typ.) Low Input Current: 1µA Features: The 54HC132 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. The hysteresis characteristics (around 20% VCC) of all inputs allow slowly changing input signals to be transformed into sharply defined jitter-free output signals. All inputs are compatible with standard CMOS outputs; using pull-up resistors, they are compatible with LSTTL outputs. Inputs are also equipped with protection circuits against static discharge and transient excess voltage. Output Drive Capability: 10 LSTTL loads Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54LS132 Full Military Temperature Range.
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Die Dimensions in µm (mils) The following part suffixes apply: 1300 (51) 1200 (47) No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Die Size (Unsawn) 1300 x 1200 51 x 47 µm mils Minimum Bond Pad Size 106 x 106 4 x 4 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com d High Speed CMOS Logic – 54HC132 Rev 1.0 21/11/17 COORDINATES (mm) PAD FUNCTION X Y 1 1A 0.143 0.434 2 1B 0.153 0.14 3 1Y 0.383 0.14 4 2A 0.551 0.14 5 2B 0.834 0.14 6 2Y 1.062 0.14 7 GND 1.064 0.458 8 3Y 1.064 0.697 9 3A 1.064 0.96 10 3B 0.826 0.96 11 4Y 0.619 0.96 12 4A 0.333 0.96 13 4B 0.143 0.96 14 VCC 0.143 0.634 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Logic Diagram 1300µm (51.18 mils) 1200µm (47.24 mils) 13 12 11 10 9 6 5 4 3 2 DIE ID 0,0 Function Table INPUTS OUTPUT A B Y L L H H L H L H H H H L H = High level (steady state) L = Low level (steady state) Pad 14 = VCC Pad 7 = GND PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Input Rise or Fall Times tr, tf VCC = 2.0V - No limit* ns * When VIN ~ 0.5 VCC, ICC >> quiescent current. Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V Clamp Diode Current IIK, IOK ±20 mA DC Output Current, per pad IOUT ±25 mA DC VCC or GND Current, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. High Speed CMOS Logic – 54HC132 Rev 1.0 21/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Maximum Positive- Going Input Threshold Voltage VT+ MAX 6.0V VOUT = 0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2V 1.0 0.95 0.95 4.5V 2.3 2.25 2.25 Minimum Positive- Going Input Threshold Voltage VT+ MIN 6.0V VOUT = 0.1V │IOUT│≤ 20µA 3.0 2.95 2.95 V 2V 0.9 0.95 0.95 4.5V 2.0 2.05 2.05 Maximum Negative- Going Input Threshold Voltage VT- MAX 6.0V VOUT = VCC -0.1V │IOUT│≤ 20µA 2.6 2.65 2.65 V 2V 0.3 0.3 0.3 4.5V 0.9 0.9 0.9 Minimum Negative- Going Input Threshold Voltage VT- MIN 6.0V VOUT = VCC -0.1V │IOUT│≤ 20µA 1.2 1.2 1.2 V 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC132 Rev 1.0 21/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 1.2 1.2 1.2 4.5V 2.25 2.25 2.25 Maximum Hysteresis Voltage5 VH MAX 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 3.0 3.0 3.0 V 2V 0.2 0.2 0.2 4.5V 0.4 0.4 0.4 Minimum Hysteresis Voltage VH MIN 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 0.5 0.5 0.5 V 2V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN ≤ VT- MIN or VT+ MAX │IOUT│≤ 20µA 5.9 5.9 5.9 V 4.5V VIN ≤ VT- MIN or VT+ MAX │IOUT│≤ 4.0mA 3.98 3.84 3.7 V Minimum High-Level Output Voltage VOH 6.0V VIN ≤ VT- MIN or VT+ MAX │IOUT│≤ 5.2mA 5.48 5.34 5.2 V 2V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN ≥ VT+ MAX │IOUT│≤ 20µA 0.1 0.1 0.1 V 4.5V VIN ≥ VT+ MAX │IOUT│≤ 4.0mA 0.26 0.33 0.4 V Maximum Low-Level Output Voltage VOL 6.0V VIN ≥ VT+ MAX │IOUT│≤ 5.2mA 0.26 0.33 0.4 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 1.0 10 40 µA 5. VH MIN > (VT+ MIN) - (VT- MAX); VH MAX = (VT+ MAX)+(VT- MIN) PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC132 Rev 1.0 21/11/17 LIMITS PARAMETER DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 2V 125 155 190 4.5V 25 31 38 Maximum Propagation CL = 50pF, Delay, Input A or B to Output Y tPLH, tPHL ns tr = tf = 6ns 6.0V 21 26 32 2V 75 95 110 4.5V 15 19 22 Maximum Output Rise CL = 50pF, and Fall Time, Any Output tTLH, tTHL ns tr = tf = 6ns 6.0V 13 16 19 Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation TA = 25°C, Capacitance Per Gate7 CPD - pF VCC =5.0V 24 6. Not production tested in die form, characterized by chip design and tested in package. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Switching Waveform Test Circuit DUT CL* OUTPUT TEST POINT * Includes all probe and jig capacitance PART OBSOLETE - DISCONTINUED