54HC04 SS | Alldatasheet
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Technical content
High Speed CMOS Logic – 54HC04 Hex Inverter Gate Logic IC in bare die form Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Rev 1.0 22/04/19 Features: Operating Voltage Range: 2V to 6V Function compatible with 54LS04 High Noise Immunity CMOS process Full Military Temperature Range.
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection The 54HC04 hex inverter gate is fabricated on a .35µm advanced CMOS process combining high speed LSTTL performance with CMOS low power. The device contains six independent inverters with standard push-pull outputs which perform the Boolean function Y = Ᾱ in positive logic. Internal circuitry comprises of three stages and includes buffered output for high noise immunity and stability. Inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. The product die size is significantly smaller than industry peers due to its re-design and production using a more advanced CMOS process.
Description
Die Dimensions in µm (mils) 560 (22) Die Size (Unsawn) 560 x 750 22 x 30 µm mils Minimum Bond Pad Size 90 x 90 3.54 x 3.54 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request 750 (30) Die Thickness <> 350µm(14 Mils) – On request Top Metal Composition Al 1%Si 1.1µm Assembled into Ceramic Package – On request Back Metal Composition N/A – Bare Si Page 1 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com d High Speed CMOS Logic – 54HC04 Rev 1.0 22/04/19Pad Layout and Functions Pad 14 = VCC Pad 7 = GND Logic Diagram Truth Table INPUTS A OUTPUT Y H L L H H = High level (steady state) L = Low level (steady state) 4 5 3 2 12 11 10 9 DIE ID 750µm (30 mils) COORDINATES (µm) PAD FUNCTION X Y 1 1A 210 155 2 1Y 210 320 3 2A 60 320 4 2Y -103 320 5 3A -210 320 6 3Y -210 117
7 GND -210 0
14 VCC 210 9
CONNECT CHIP BACK TO VCC OR FLOAT 0,0 560µm (22 mils) A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 54HC04 Rev 1.0 22/04/19 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 2V 0 1000 VCC = 4.5V 0 500 Input Rise or Fall Times tr, tf VCC = 6.0V 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.5 1.5 1.5 3.0V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0V 0.5 0.5 0.5 3.0V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V A ll data sheet.com
High Speed CMOS Logic – 54HC04 Rev 1.0 22/04/19 LIMITS PARAMETER 5. Not production tested in die form, characterized by chip design and tested in package. SYMBOL VCC CONDITIONS FULL RANGE4 UNITS 25°C 85°C 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 VIN = VIH or VIL V │IOUT│≤ 20µA 6.0V 5.9 5.9 5.9 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 2.48 2.34 2.20 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.20 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 VIN = VIL or VIL │IOUT│≤ 20µA 6.0V 0.1 0.1 0.1 V 3.0V VIN = VIL or VIL │IOUT│≤ 2.4mA 0.26 0.33 0.40 4.5V VIN = VIL or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 Maximum Low-Level Output Voltage VOL 6.0V VIN = VIL or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Leakage Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 1 10 40 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 75 95 110 3.0V 30 40 55 4.5V 15 19 22 Maximum Propagation Delay, Input A or B to Output Y (Figure 1,2) tPLH, tPHL CL = 50pF, tr = tf = 6ns ns 6.0V 13 16 19 2.0V 75 95 110 3.0V 27 32 36 4.5V 15 19 22 Maximum Output Rise and Fall Time, CL = 50pF, Any Output (Figure 1,2) tTLH, tTHL ns tr = tf = 6ns 6.0V 13 16 19 Page 4 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 54HC04 Rev 1.0 22/04/19 6. Used to determine the no-load dynamic power consumption: P D = CPD VCC LIMITS PARAMETER DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Switching Waveform DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Figure 1 – Propagation Delay & Output Transition Time Figure 2 f + ICC VCC. SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation TA = 25°C, pF Capacitance Per Gate6 CPD - VCC =5.0V 20 A ll data sheet.com