54ALS174

54ALS174 SS | Alldatasheet

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Advanced Low Power Schottky Logic - 54ALS174 Hex D-type Flip-Flop in bare die form Die Size (Unsawn) 2100 x 1800 83 x 71 µm mils Minimum Bond Pad Size 130 x 130 5.12 x 5.12 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si  High speed – 2ns (Min) propagation delay  Full Military Temperature Range.  Direct drop-in replacement for obsolete components in long term programs. Rev 1.1 20/01/24 Features: Description The 54ALS174 Hex D-type Flip-Flop is fabricated using a 2µm 40V Bipolar process. The device is comprised of six flip-flops each having independent data input and data output. Load and clear is simultaneous, triggered by common clock and master reset respectively. D-Input levels transfer to Q output with the positive clock pulse. Ordering Information Die Dimensions in µm (mils) The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT 2100 (83) 1800 (71) LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (100 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com

www.siliconsupplies.com d Advanced Low Power Schottky Logic - 54ALS174 Rev 1.1 20/01/24 Pad Layout and Functions COORDINATES (mm) PAD FUNCTION X Y 1 CLR 0.200 DIE ID 1012 13 14 15 11 0.435 2 1Q 0.200 0.240 3 1D 0.600 0.200 4 2D 0.840 0.200 5 2Q 1.130 0.200 6 3D 1.370 0.200 7 3Q 1.770 0.240 8 GND 1.770 0.590 9 CLK 1.770 1.240 10 4Q 1.770 1.435 11 4D 1.370 1.470 12 5Q 1.130 1.470 13 5D 0.840 1.470 14 6D 0.600 1.470 15 6Q 0.200 1.435 16 VCC 0.200 1.120 CONNECT CHIP BACK TO GND 2100µm (82.67 mils) 1800µm (70.87 mils) 0,0 Function Table Logic Diagram 765 4 3 2 INPUTS OUTPUT CLR CLK D Q L X X L H H H H L L H L X Q0 H = High level (steady state) L = Low level (steady state) = Low-to-High clock transition X = Don’t care Page 2 of 5

www.siliconsupplies.com Advanced Low Power Schottky Logic - 54ALS174 Rev 1.1 20/01/24 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V High-Level Input Voltage VIH 2 - V Low-Level Input Voltage VIL - 0.8 V High-Level Output Current IOH - -0.4 mA Low-Level Output Current IOL - 4 mA Operating Temperature Range TJ -55 +125 °C Recommended Operating Conditions Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage VCC 7.0 V DC Input Voltage VIN 7.0 V Storage Temperature Range TSTG -65 to 150 °C LIMITS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Minimum High-Level Input Voltage VIH - 2 - - V Maximum Low-Level Input Voltage VIL - - - 0.8 V Input Clamp Diode Voltage VIK VCC = MIN IIN = -18mA - - -1.5 V Output Voltage High VOH VCC = 4.5V to 5.5V, IOH = -0.4mA VCC -2 - - V Output Voltage Low VOL VCC = 4.5V IOL = 4mA - 0.25 0.4 V Input Current IIN VCC = 5.5V, VIN = 7V - - 0.1 mA Input High Current IIH VCC = 5.5V, VIN = 2.7V - - 20 µA Input Low Current IIL VCC = 5.5, VIN = 0.4V - - -0.1 mA Output Current3 IO VCC = 5.5, VOUT = 2.25V -20 - -112 mA Power Supply Current (Total) ICC VCC = 5.5V , VIN = 4.5V - 11 19 mA 2. All typical values @ VCC = 5V, TJ = 25°C. 3. Output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability.

www.siliconsupplies.com Advanced Low Power Schottky Logic - 54ALS174 Rev 1.1 20/01/24AC Electrical Characteristics4 TJ = -55°C to 125°C unless otherwise specified LIMITS PARAMETER SYMBOL VCC CONDITIONS MIN TYP MAX UNITS Maximum Clock Frequency fmax 5V ±10% CL = 50pF, RL = 500Ω 40 - - MHz tPLH, 3 - 20 Maximum Propagation Delay, CLR to Q (Figure 1) tPHL 5V ±10% CL = 50pF, RL = 500Ω 5 - 30 ns tPLH, 3 - 20 Maximum Propagation Delay, CLK to Q (Figure 1) tPHL 5V ±10% CL = 50pF, RL = 500Ω 5 - 24 ns 4. Not production tested in die form, characterized by chip design and tested in package. Timing Requirements4 TJ = -55°C to 125°C unless otherwise specified LIMITS PARAMETER SYMBOL V CC CONDITIONS MIN TYP MAX UNITS Minimum Pulse Width, CLK (Figure 3) tw(H), tw(L), 5V ±10% CL = 50pF, RL = 500Ω 12.5 - - ns Minimum Pulse Width, CLR (Figure 3) tw(L) 5V ±10% CL = 50pF, RL = 500Ω 15 - - ns Minimum Setup Time Before CLK (Figure 2) tSU 5V ±10% Data, CL = 50pF, RL = 500Ω 15 - - ns Minimum Setup Time Before CLK (Figure 2) tSU 5V ±10% CLR Inactive, CL = 50pF, RL = 500Ω 8 - - ns Hold Time, Data after CLK (Figure 2) th 5V ±10% CL = 50pF, RL = 500Ω s 0 - - ns