54AHC595 SS | Alldatasheet
Document overview
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Technical content
Advanced High Speed CMOS Logic - 54AHC595 8-bit shift registers with 3-state output latches in bare die form Rev 1.0 26/02/26 Features: High Frequency: 90 MHz (Min) V CC = 5V, CL = 15pF The 54AHC595 is an 8–bit serial-in to parallel-out shift register which drives an 8–bit D–type latch with 3–state outputs. Both register and latch have independent positive triggered clock inputs. All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the output register. The shift register also features asynchronous reset. Device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs Output Drive Capability: 15 LSTTL Loads Low Input Current: 0.1µA Outputs directly inter face CMOS, NMOS and TTL CMOS High Noise Immunity Function compatible with 54LS595 Performance upgrade for 54AC595, 54HC595 Full Military Temperature Range.
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT
Description
Die Dimensions in µm (mils) 1030 (41) 770 (30) “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Die Size (Unsawn) 1030 x 770 41 x 30 µm mils Minimum Bond Pad Size 70 x 70 2.76 x 2.76 µm mils Die Thickness 280 (±10) 11.02 (±0.39) µm mils Top Metal Composition Al-Si-Cu 2.8 µm Back Metal Composition Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 280µm(11 Mils) – On request Assembled into Ceramic Package – On request N/A – Bare Si Page 1 of 8 www.siliconsupplies.com
d Advanced High Speed CMOS Logic - 54AHC595 Rev 1.0 26/02/26 Pad Layout and Functions Logic Diagram 770µm (30.32 mils) 1030µm (40.55 mils) 2 3 4 5 6 101112 13 14 DIE ID 0,0 COORDINATES (µm) PAD FUNCTION X Y 1 QB -401.8 -102 2 QC -401.8 -246 3 QD -205.8 -273 4 QE -95.8 -273 5 QF 95.8 -273 6 QG 205.8 -273 7 QH 401.8 -230.2 8 GND 401.8 -84.6 9 QH’ 401.8 62.6 10 SRCLR 401.8 243.2
11 SRCLK 272 273
12 RCLK 103.2 273 13 OE -54.4 273 14 SER -233.2 273 15 QA -401.8 237.6 16 VCC -401.8 46 CONNECT CHIP BACK TO VCC OR FLOAT Page 2 of 8 www.siliconsupplies.com
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 3.3V ± 0.3V 0 100 ns/V Input Transition Rise or Fall Rate VCC = 5V ± 0.5V Δt/Δv 0 20 ns/V Recommended Operating Conditions4 (Voltages referenced to GND) Absolute Maximum Ratings2 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to +7.0 V DC Output Voltage VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC VCC or GND Current ICC ±75 mA Power Dissipation in Still Air3 P D 500 mW Storage Temperature Range TSTG -65 to 150 °C Rev 1.0 26/02/26 2. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 3. Measured in plastic SOP-16 package, results in die form are dependent on die attach and assembly method. Function Table1 4. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. INPUTS OUTPUTS SRCLK RCLK OE SRCLR SER QH’ Q N FUNCTION X X L L X L NC LOW level on SRCLR only affects the shift registers X ↑ L L X L L Empty shift-register loaded into storage register X X H L X L Z Shift-register clear. Parallel outputs in high- impedance OFF- state ↑ X L H H QG’ NC Logic high level shifted into shift register stage 0. Content of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q 6’) appears on serial output(QH’) X ↑ L H X NC Qn’ Contents of shift register stages (internal Qn’) transfers to the storage register and parallel output stages ↑ ↑ L H X QG’ Q n ’ Shift register contents shifted through. Previous shift register content transfers to storage register & parallel output stages. 1. H=HIGH voltage level; L=LOW voltage level; ↑ =LOW-to-HIGH transition; Z=high-impedance OFF-state; NC=no change; X=don’t care. Advanced High Speed CMOS Logic - 54AHC595
www.siliconsupplies.com Advanced High Speed CMOS Logic - 54AHC595 Rev 1.0 26/02/26 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 1.5 1.5 1.5 3.0V 2.1 2.1 2.1 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 3.85 3.85 3.85 V 2.0V 0.5 0.5 0.5 3.0V 0.9 0.9 0.9 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.65 1.65 1.65 V 2.0V 1.9 1.9 1.9 3.0V 2.9 2.9 2.9 4.5V VIN = VIH or VIL │IOUT│≤ 50µA 4.4 4.4 4.4 V 3.0V VIN = VIH or VIL │IOUT│≤ 4mA 2.58 2.48 2.40 Minimum High-Level Output Voltage VOH 4.5V VIN = VIH or VIL │IOUT│≤ 8mA 3.94 3.80 3.70 V 2.0V 0.1 0.1 0.1 3.0V 0.1 0.1 0.1 4.5V VIN = VIH or VIL │IOUT│≤ 50µA 0.1 0.1 0.1 V 3.0V VIN = VIH or VIL │IOUT│≤ 4mA 0.36 0.44 0.55 Maximum Low-Level Output Voltage VOL 4.5V VIN = VIH or VIL │IOUT│≤ 8mA 0.36 0.44 0.55 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±2.0 µA Maximum Three-State Leakage Current IOZ 5.5V High-Impedance Output State, VIN = VIH or VIL, VOUT=VCC or GND ±0.25 ±2.5 ±10 µA Maximum Quiescent Supply Current ICC 5.5V VIN = VCC or GND, IOUT = 0µA 4 40 80 µA 6. Not production tested in die form, characterized by chip design and tested in package. LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 5 UNITS CL = 15pF 80 60 50 3.3V ±0.3V CL = 50pF 55 40 30 CL = 15pF 135 110 90 Minimum Clock Frequency (Figure 5) fmin ±0.5V CL = 50pF 95 85 70 MHz
www.siliconsupplies.com Advanced High Speed CMOS Logic - 54AHC595 Rev 1.0 26/02/26 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS CL = 15pF 13 14 16 3.3V ±0.3V CL = 50pF 16 17.2 19 CL = 15pF 9 10 11 Maximum Propagation delay from input RCLK to output QA-QH (Figure 3,5) tPLH, tPHL ±0.5V CL = 50pF 11 12 13 ns CL = 15pF 13 15 16.5 3.3V ±0.3V CL = 50pF 16.5 18.5 20.1 CL = 15pF 8.2 9.4 10.5 Maximum Propagation delay from input SRCLK to output QH' (Figure 3, 5) tPLH, tPHL ±0.5V CL = 50pF 11 11.4 13 ns CL = 15pF 12.8 13.7 15 3.3V ±0.3V CL = 50pF 16.3 17.2 18.7 CL = 15pF 8 9.1 10 Maximum Propagation delay from input SRCLR to output QH' (Figure 3, 5) tPHL ±0.5V CL = 50pF 10 11.1 12 ns CL = 15pF 11.5 13.5 15 3.3V ±0.3V CL = 50pF 15 17 18.5 CL = 15pF 8.6 10 11 tPZH, tPZL ±0.5V CL = 50pF 10.6 12 13 ns CL = 15pF 15.7 16.2 17.5 3.3V ±0.3V CL = 50pF 10.3 11 12 CL = 15pF 15.7 16.2 17.5 Maximum Propagation delay from input OE to output QA-QH (Figure 4, 5) tPHZ, tPLZ ±0.5V CL = 50pF 10.3 11 12 ns Timing Requirements (Voltages referenced to GND) LIMITS PARAMETER SYMBOL CONDITIONS 25°C 85°C FULL RANGE5 UNITS 3.3V ±0.3V 5 5 5 Minimum pulse duration, SRCLK high or low (Figure 1,5) 5V ±0.5V 5 5 5 3.3V ±0.3V 5 5 5 Minimum pulse duration, RCLK high or low (Figure 1, 5) 5V ±0.5V 5 5 5 3.3V ±0.3V 5 5 5 Minimum pulse duration, SRCLR low (Figure 1,5) tw 5V ±0.5V 5 5 5 ns
www.siliconsupplies.com Advanced High Speed CMOS Logic - 54AHC595 Rev 1.0 26/02/26 Timing Diagram DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.