54AC14

54AC14_V01 SS | Alldatasheet

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Advanced CMOS Logic – 54AC14 Rev 2.0 12/03/26 Hex Schmitt-Trigger Inverter Logic IC in bare die form Features:  Outputs Sink/Source 24mA The 54AC14 Hex Schmitt-Trigger Inverter is fabricated using a 5V CMOS process with the same high speed performance of LSTTL combined with CMOS low power consumption. The device performs the Boolean function Y = Ᾱ in positive logic. Device inputs are compatible with Standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Schmitt-Trigger inputs transform slow input rise and fall times into sharply defined jitter-free output signals. Due to the hysteresis voltage of the Schmitt trigger, the 54AC14 is useful in noisy environments.  Low Input Current: 1µA  Outputs directly inter face CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with 54HC14 or 54LS14  Full Military Temperature Range.

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Die Dimensions in µm (mils) The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection 1270 (50) 1100 (43)  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (400 per tray capacity) 1270 x 1100 50 x 43 µm Die Size (Unsawn) mils  Sawn Wafer on Tape – On request Minimum Bond Pad Size 70 x 70 2.76 x 2.76 µm mils Die Thickness 280 (±20)  Unsawn Wafer – On request 11.02 (±0.79) µm mils Top Metal Composition Al-Si-Cu Back Metal Composition N/A – Bare Si  Die Thickness <> 280µm(11 Mils) – On request  Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com

www.siliconsupplies.com d Advanced CMOS Logic – 54AC14 Rev 2.0 12/03/26 COORDINATES (µm) PAD FUNCTION X Y 1 1A -502 -263.5 2 1Y -364.9 -410 3 2A -157.7 -410 4 2Y 188.9 -410 5 3A 413 -410 6 3Y 495 -298

7 GND 495 -140

8 GND 495 140

11 5Y 188.9 410 12 5A -157.7 410 13 6Y -364.9 410 14 6A -495 263 15 VCC -495 64.2 16 VCC -495 -64.2 CHIP BACK IS ISOLATED Pad Layout and Functions 1270µm (50 mils) 1100µm (43.31 mils) Function Table INPUTS A OUTPUT Y H L L H H = High level (steady state) L = Low level (steady state) Pad 15,16 = VCC Pad 7,8 = GND Y = Ᾱ 0,0 Logic Diagram 2 3 4 5 10111213 DIE ID

www.siliconsupplies.com Advanced CMOS Logic – 54AC14 Rev 2.0 12/03/26Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±50 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Output Current – High IOH - -24 mA Output Current – Low IOL - 24 mA VCC = 3.0V 0 150 VCC = 4.5V 0 40 Input Rise and Fall Time (Except Schmitt Inputs), VIN from 30% to 70% VCC VCC = 5.5V tr, tf 0 24 ns/V Recommended Operating Conditions3 (Voltages referenced to GND) LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 3.0V 2.2 2.2 2.2 4.5V 3.2 3.2 3.2 Maximum Positive Threshold VT+ 5.5V VOUT = 0.1V 3.9 3.9 3.9 V 3.0V 0.5 0.5 0.5 4.5V 0.9 0.9 0.9 Minimum Negative Threshold VT- 5.5V VOUT = 0.1V 1.1 1.1 1.1 V

Advanced CMOS Logic – 54AC14 Rev 2.0 12/03/26 LIMITS PARAMETER SYMBOL VCC CONDITIONS FULL RANGE4 UNITS 25°C 85°C 3.0V 1.2 1.2 1.2 V 4.5V 1.4 1.4 1.4 V Maximum Hysteresis Voltage5 VH MAX 5.5V VOUT = 0.1V or VCC -0.1V 1.6 1.6 1.6 V 3.0V 0.3 0.3 0.3 V 4.5V 0.4 0.4 0.4 V Minimum Hysteresis Voltage5 VH MIN 5.5V VOUT = 0.1V or VCC -0.1V 0.5 0.5 0.5 V 3.0V 2.9 2.9 2.9 4.5V 4.4 4.4 4.4 IOUT ≤ -50µA 5.5V 5.4 5.4 5.4 VIN ≤ VT- min, IOH = -12mA6 2.56 2.46 2.40 3.0V 4.5V VIN ≤ VT- min, IOH = -24mA6 3.86 3.76 3.70 5.5V VIN ≤ VT- min, IOH = -24mA6 4.86 4.76 4.70 Minimum High-Level Output Voltage VOH 5.5V VIN ≤ VT- min, IOH = -50mA7 - - 3.85 V 3.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 5.5V IOUT ≤ 50µA 0.1 0.1 0.1 VIN ≥ VT- min, IOL = 12mA6 0.36 0.44 0.5 3.0V 4.5V VIN ≥ VT- min, IOL = 24mA6 0.36 0.44 0.5 5.5V VIN ≥ VT- min, IOL = 24mA6 0.36 0.44 0.5 Maximum Low-Level Output Voltage VOL 5.5V VIN ≥ VT- min, IOL = 50mA7 - - 1.65 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA IOLD 5.5V VOLD = 1.65V Max - 75 50 Minimum Dynamic Output Current8 IOHD 5.5V VOHD = 3.85V Min - -75 -50 mA Maximum Quiescent Supply Current ICC 5.5V VIN = VCC or GND 4 40 80 µA 5. VH = (VT+) - (VT-) 6. All outputs loaded; thresholds on input associated with output under test. 7. Test time 1sec max, measurement made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 75Ω transmission-line drive capability at 125°C 8. Maximum test duration 2ms, one output loaded at a time. Page 4 of 5 www.siliconsupplies.com

www.siliconsupplies.com Advanced CMOS Logic – 54AC14 Rev 2.0 12/03/26 AC Electrical Characteristics9 LIMITS VCC PARAMETER SYMBOL CONDITIONS UNITS FULL RANGE4 25°C 85°C 3.3V 13.5 15.0 16.0 CL = 50pF, tPLH 5.0V Input tr=tf= 3ns 10.0 11.0 12.0 ns 3.3V 11.5 13.0 14.0 Maximum Propagation Delay, Input A or B to Output Y CL = 50pF, ns tPHL (Figure 1,2) Input tr=tf= 3ns 5.0V 8.5 9.5 10.0 Maximum Input Capacitance CIN 5 - 4.5 4.5 4.5 pF TYPICAL Power Dissipation TA = 25°C, pF Capacitance Per Gate11 CPD - VCC =5.0V 25 9. Not production tested in die form, characterized by chip design and tested in package. 10. ± 10% 11. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Switching Waveform DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Figure 1 – Propagation Delay & Output Transition Time Figure 2 DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.