54AC139_V01 SS | Alldatasheet

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Advanced CMOS Logic – 54AC139 Dual 1-of-4 Decoder / Demultiplexer in bare die form  Outputs Sink/Source 24mA  Low Input Current: 1µA  Outputs directly inter face CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with 54LS139  Full Military Temperature Range. Rev 1.1 21/07/20 Features:

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The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection The 54AC139 is fabricated using a 1.5µm 5V advanced CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. This device consists of x2 independent 1–of–4 decoders, each decoding a 2 bit address to 1–of–4 active–low outputs. Active–low Selects facilitate the demultiplexing and cascading functions. The demultiplexing function is executed by using the Address inputs to select the desired device output and utilizing the Select as a data input. Inputs accept standard CMOS outputs or LSTTL outputs using pull-up resistors.

Description

Die Dimensions in µm (mils) Die Size (Unsawn) 1400 x 1750 55 x 68 µm mils Minimum Bond Pad Size 120 x 120 4.72 x 4.72 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification 1400 (55) 1750 (68)  Default – Die in Waffle Pack (100 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request Page 1 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com d Advanced CMOS Logic – 54AC139 Rev 1.1 21/07/20Pad Layout and Functions COORDINATES (mm) PAD FUNCTION X Y 1 1G 0.100 0.487 2 1A 0.100 0.150 3 1B 0.440 0.100 4 1Y0 0.640 0.100 5 1Y1 0.835 0.100 6 1Y2 1.030 0.100 7 1Y3 1.180 0.440 8 GND 1.180 0.720 8 GND 1.180 0.880 9 2Y3 1.180 1.190 10 2Y2 1.120 1.530 11 2Y1 0.826 1.530 12 2Y0 0.630 1.530 13 2B 0.436 1.530 14 2A 0.100 1.530 15 2G 0.100 1.260 16 VCC 0.100 0.895 16 VCC 0.100 0.735 CONNECT CHIP BACK TO VCC OR FLOAT Truth Table Logic Diagram Pad 16 = VCC Pad 8 = GND 1750µm (68.89 mils) 0,0 1400µm (55.11 mils) 13 12 11 10 6 5 4 3 2 DIE ID PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Output Current – High IOH - -24 mA Output Current – Low IOL - 24 mA VCC = 3.0V 0 150 VCC = 4.5V 0 40 Input Rise and Fall Time (VIN from 30% to 70%) VCC = 5.5V tr, tf 0 24 ns/V Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pin IIN ±20 mA DC Output Current, per pin IOUT ±50 mA DC VCC or GND Current, per pin ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C Advanced CMOS Logic – 54AC139 Rev 1.1 21/07/20 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. For proper opera tion, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or VCC). Unused outputs must be left open. Pad Description A 1A, 1B, 2A (Pad When the resp OUTPUTS 1Y0, 1Y1, 1Y2, (Pad Active–low remain hig CONTROL IN 1G, 2G (Pads 1, 15) Active–low DDRESS INPUTS , 2B s 2, 3, 14, 13) ective 1–of–4 decoder is enabled these inputs determine which of its four active–low outputs is selected. 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 outputs. These outputs assume a low level when addressed and the appropriate Select input is active. These outputs h when not addressed or the appropriate Select input is inactive. PUTS select inputs. For a low level on this input, the outputs for that particular decoder follow the Address inputs. A high level on this input forces all outputs to a high level. PART OBSOLETE - DISCONTINUED

Advanced CMOS Logic – 54AC139 Rev 1.1 21/07/20 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 3.0V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V V │IOUT│≤ 20µA 3.85 3.85 3.85 3.0V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA Maximum Low-Level Input Voltage VIL V 5.5V 1.65 1.65 1.65 3.0V 2.9 2.9 2.9 4.5V 4.4 4.4 4.4 5.5V IOUT = -50µA 5.4 5.4 5.4 3.0V VIN = VIL or VIH IOH = -12 mA 2.56 2.46 2.40 4.5V VIN = VIL or VIH IOH = -24mA5 3.86 3.76 3.70 5.5V VIN = VIL or VIH IOH = -24mA5 4.86 4.76 4.70 Minimum High-Level Output Voltage VOH 5.5V VIN = VIL or VIH IOH = -50mA6 - - 3.85 V 3.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 IOUT = 50µA 5.5V 0.1 0.1 0.1 VIN = VIH or VIL 3.0V │IOUT│≤ 12mA 0.36 0.44 0.5 4.5V VIN = VIH or VIL │IOUT│≤ 24mA5 0.36 0.44 0.5 VIN = VIH or VIL 5.5V │IOUT│≤ 24mA5 0.36 0.44 0.5 Maximum Low-Level Output Voltage VOL 5.5V VIN = VIH or VIL │IOUT│50mA6 - - 1.65 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA IOLD 5.5V VOLD = 1.65V Max - 75 50 Minimum Dynamic Output Current7 IOHD 5.5V VOHD = 3.85V Min - -75 -50 mA Maximum Quiescent Supply Current ICC 5.5V VIN = VCC or GND IOUT = 0µA 8 80 160 µA 4. -55˚C ≤ T J ≤ +125˚C 5. All outputs loaded; thresholds on input associated with outpu t under test. 6. Test time 1sec max, measurement made by forcing indicated current and measuring voltage to minimize power dissipation. Test veri fies a minimum 75Ω transmission-line drive capability at 125°C 7. Maximum test duration 2ms, one output loaded at a time Page 4 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

Advanced CMOS Logic – 54AC139 Rev 1.1 21/07/20 8. Not production tested in die form, characterized by chip design and tested in package. 9. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. LIMITS PARAMETER Switching Waveforms Figure 1 – Propogation Delay & Timing, Input to Output Figure 2 – Propagation Delay & Timing , Input Select to Output SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 3.3V 11.5 13 14.7 CL = 50pF, tPLH, ns 5.0V tr = tf = 3ns 8.5 9.5 10.5 3.3V 10 11 14.7 Maximum Propagation Delay, A or B to Y CL = 50pF, (Figure 1,3) tPHL ns tr = tf = 3ns 5.0V 7.5 8.5 10.5 3.3V 12 13 14.7 CL = 50pF, tPLH, ns 5.0V tr = tf = 3ns 8.5 10 10.5 3.3V 10 11 14.7 Maximum Propagation Delay, G to Y CL = 50pF, (Figure 2,3) tPHL ns tr = tf = 3ns 5.0V 7.5 8.5 10.5 Maximum Input Capacitance CIN - - 4.5 4.5 4.5 pF TYPICAL Power Dissipation TJ = 25°C, Capacitance (Per Decoder)9 CPD - VCC = 5.0V 40 pF Page 5 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

Advanced CMOS Logic – 54AC139 Rev 1.1 21/07/20Test Circuit Page 6 of 6 www.siliconsupplies.com DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. DUT CL* OUTPUT TEST POINT * Includes all probe and jig capacitance Figure 3 – Test Circuit PART OBSOLETE - DISCONTINUED