54AC00 SS | Alldatasheet
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Advanced CMOS Logic – 54AC00 Rev 1.0 19/02/21 Quad 2-Input NAND Gates in bare die form Description Features: Outputs Sink/Source 24mA 54AC00 provides x4 independent 2-input NAND gates performing the Boolean function Y = A • B or Y = A + B. The device is fabricated using a 1.5µm 5V CMOS process combining high speed LSTTL performance with CMOS low power. Internal circuitry comprises of 3 stages and includes buffered output for high noise immunity and stability. Device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54HC00 or 54LS00 Full Military Temperature Range. Ordering Information Die Dimensions in µm (mils) The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection 1200 (47) 1200 (47) “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) 1200 x 1200 µm Die Size (Unsawn) 47 x 47 mils Sawn Wafer on Tape – On request 120 x 120 µm Minimum Bond Pad Size 4.72 x 4.72 mils Unsawn Wafer – On request 350 (±20) µm Die Thickness 13.78 (±0.79) mils Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Page 1 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com d Advanced CMOS Logic – 54AC00 Rev 1.0 19/02/21 COORDINATES (µm) PAD FUNCTION X Y 1 1A 150 350 2 1B 150 100 3 1Y 480 100 4 2A 660 100 5 2B 990 100 6 2Y 990 350
7 GND 990 540
14 VCC 100 540
CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Logic Diagram Function Table INPUTS OUTPUT A B Y L L H H L H L H H H H L H = High level (steady state) L = Low level (steady state) Pad 14 = V CC Pad 7 = GND 1200µm (47.24 mils) 1200µm (47.24 mils) 12 11 10 2 3 4 5 DIE ID 0,0 A ll data sheet.com
www.siliconsupplies.com Advanced CMOS Logic – 54AC00 Rev 1.0 19/02/21Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Output Current – High IOH - -24 mA Output Current – Low IOL - 24 mA VCC = 3.0V 0 150 VCC = 4.5V 0 40 Input Rise and Fall Time (VIN from 30% to 70%) VCC = 5.5V tr, tf 0 24 ns/V Recommended Operating Conditions3 (Voltages referenced to GND) LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 3.0V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 3.85 3.85 3.85 V 3.0V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.65 1.65 1.65 V A ll data sheet.com
Advanced CMOS Logic – 54AC00 Rev 1.0 19/02/21 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 3.0V 2.9 2.9 2.9 4.5V 4.4 4.4 4.4 5.5V IOUT = -50µA 5.4 5.4 5.4 VIN = VIL or VIH IOH = -12 mA 3.0V 2.56 2.46 2.40 4.5V VIN = VIL or VIH IOH = -24mA5 3.86 3.76 3.70 5.5V VIN = VIL or VIH IOH = -24mA5 4.86 4.76 4.70 Minimum High-Level Output Voltage VOH V 5.5V VIN = VIL or VIH IOH = -50mA6 - - 3.85 3.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 5.5V IOUT = 50µA 0.1 0.1 0.1 3.0V VIN = VIH or VIL │IOUT│≤ 12mA 0.36 0.44 0.5 4.5V VIN = VIH or VIL │IOUT│≤ 24mA5 0.36 0.44 0.5 5.5V VIN = VIH or VIL │IOUT│≤ 24mA5 0.36 0.44 0.5 Maximum Low-Level Output Voltage VOL V VIN = VIH or V IL5.5V │IOUT│50mA6 - - 1.65 Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA IOLD 5.5V VOLD = 1.65V Max - 75 50 Minimum Dynamic mA Output Current7 IOHD 5.5V VOHD = 3.85V Min - -75 -50 Maximum Quiescent VIN = VCC or GND Supply Current ICC 5.5V IOUT = 0µA 4 40 80 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 3.3V 9.5 10.0 11 CL = 50pF, tPLH 5.0V Input ns tr = tf = 3ns 8 8.5 9 3.3V 8.0 8.5 8.5 Maximum Propagation Delay, Input A or B to Output Y CL = 50pF, (Figure 1,2) ns tPHL Input tr = tf = 3ns 5.0V 6.5 7.0 7.0 Page 4 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com Advanced CMOS Logic – 54AC00 Rev 1.0 19/02/21 LIMITS PARAMETER DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. SYMBOL VCC CONDITIONS 85°C FULL RANGE4 UNITS 25°C Maximum Input Capacitance CIN 5 - 4.5 4.5 4.5 pF TYPICAL Power Dissipation Capacitance Per Gate6 CPD - TA = 25°C, VCC =5.0V pF 5. All outputs loaded; thresholds on input associated with output under test. 6. Test time 1sec max, measurement made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 75Ω transmission-line drive capability at 125°C 7. Maximum test duration 2ms, one output loaded at a time Not production tested in die form, characterized by chip design and tested in package. 8. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Switching Waveform DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance – Propagation Delay & Output Transition Time Figure 2 Figure 1 A ll data sheet.com