5241

CAT5241 CATALYST | Alldatasheet

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Technical content

DESCRIPTION

The CAT5241 is four Digitally Programmable Potentiometers (DPPs™) integrated with control logic and 16 bytes of NVRAM memory. Each DPP consists of a series of 63 resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 6-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data CAT5241 Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and 2-wire Interface

FEATURES

I Four linear-taper digitally programmable potentiometers I 64 resistor taps per potentiometer I End to end resistance 2.5kΩ , 10kΩ , 50kΩ or 100kΩ I Potentiometer control and memory access via 2-wire interface (I 2C like) I Low wiper resistance, typically 80ΩΩΩΩΩ I Nonvolatile memory storage for up to four wiper settings for each potentiometer I Automatic recall of saved wiper settings at power up I 2.5 to 6.0 volt operation I Standby current less than 1µA I 1,000,000 nonvolatile WRITE cycles I 100 year nonvolatile memory data retention I 20-lead SOIC and TSSOP packages I Industrial temperature range PIN CONFIGURATION FUNCTIONAL DIAGRAM © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Document No. 2011, Rev. J registers is via a 2-wire serial bus (I2C-like). On power- up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register (WCR). The CAT5241 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. HALOGEN FREE TM LEAD F REE R H0 H1 H2 H3R R R R L0 L1 L2 L3R R R WIPER CONTROL REGISTERS NONVOLATILE DATA REGISTERS 2-WIRE BUS INTERFACE CONTROL LOGIC SCL SDA R R R R CAT 5241 R W0 R L0 R H0 R W1 R L1 RH 1 SDA GND VCC R W3 R L3 R H3 SCL R W2 R L2 R H2

Document No. 2011, Rev. J PIN DESCRIPTION Pin (SOIC) Name Function 1R W0 Wiper Terminal for Potentiometer 0 2R L0 Low Reference Terminal for Potentiometer 0 3R H0 High Reference Terminal for Potentiometer 0

4 A0 Device Address, LSB

5 A2 Device Address

6R W1 Wiper Terminal for Potentiometer 1 7R L1 Low Reference Terminal for Potentiometer 1 8R H1 High Reference Terminal for Potentiometer 1

9 SDA Serial Data Input/Output

10 GND Ground

11 R H2 High Reference Terminal for Potentiometer 2

12 R L2 Low Reference Terminal for Potentiometer 2

13 R W2 Wiper Terminal for Potentiometer 2

14 SCL Bus Serial Clock

15 A3 Device Address

16 A1 Device Address

17 R H3 High Reference Terminal for Potentiometer 3

18 R L3 Low Reference Terminal for Potentiometer 3

19 R W3 Wiper Terminal for Potentiometer 3

20 VCC Supply Voltage

SCL: Serial Clock The CAT5241 serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data The CAT5241 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire- or'd with the other open drain or open collector outputs. A0, A1, A2, A3:Device Address Inputs These inputs set the device address when ad- dressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5241. R H , RL: Resistor End Points The four sets of RH and RL pins are equivalent to the terminal connections on a mechanical potenti- ometer. R W : Wiper The four RW pins are equivalent to the wiper terminal of a mechanical potentiometer. DEVICE OPERATION The CAT5241 is four resistor arrays integrated with 2- wire serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (R W ) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.

Document No. 2011, Rev. J ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Package Power Dissipation Notes: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (4) LSB = R TOT / 63 or (RH - RL) / 63, single pot Recommended Operating Conditions: VCC = +2.5V to +6.0V Temperature Min Max Industrial -40 °C8 5 °C POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units R POT Potentiometer Resistance (-00) 100 k Ω R POT Potentiometer Resistance (-50) 50 k Ω R POT Potentiometer Resistance (-10) 10 k Ω R POT Potentiometer Resistance (-25) 2.5 k Ω Potentiometer Resistance +20 % Tolerance R POT Matching 1 % Power Rating 25 °C, each pot 50 mW IW Wiper Current +6 mA R W Wiper Resistance I W = +3mA @ V CC =3V 300 Ω R W Wiper Resistance I W = +3mA @ V CC = 5V 80 150 Ω VTERM Voltage on any RH or RL Pin V SS = 0V GND V CC V VN Noise (1) TBD nV/ Hz Resolution 1.6 % Absolute Linearity (2) R w(n)(actual)-R(n)(expected)(5) +1 LSB (4) Relative Linearity (3) R w(n+1)-Rw(n)+LSB +0.2 LSB (4) TC RPOT Temperature Coefficient of RPOT (1) +300 ppm/ °C TC RATIO Ratiometric Temp. Coefficient (1) 20 ppm/ °C C H /CL/CW Potentiometer Capacitances (1) 10/10/25 pF fc Frequency Response R POT = 50kΩ (1) 0.4 MHz

Document No. 2011, Rev. J Symbol Parameter Min Typ Max Units fSCL Clock Frequency 400 kHz TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA SLC Low to SDA Data Out and ACK Out 0.9 µs tBUF (1) Time the Bus Must be Free Before a New 1.2 µs Transmission Can Start tHD:STA Start Condition Hold Time 0.6 µs tLOW Clock Low Period 1.2 µs tHIGH Clock High Period 0.6 µs tSU:STA Start Condition SetupTime (For a Repeated Start Condition) 0.6 µs tHD:DAT Data in Hold Time 0 ns tSU:DAT Data in Setup Time 100 ns tR (1) SDA and SCL Rise Time 0.3 µs tF(1) SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Out Hold Time 50 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Conditions Min Typ Max Units C I/O(1) Input/Output Capacitance (SDA) V I/O = 0V 8 pF C IN(1) Input Capacitance (A0, A1, A2, A3, SCL) VIN = 0V 6 pF POWER UP TIMING (1) Over recommended operating conditions unless otherwise stated. Symbol Parameter Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units ICC Power Supply Current f SCL = 400kHz 1 mA ISB Standby Current (VCC = 5.0V) V IN = GND or VCC; SDA Open 1 µA ILI Input Leakage Current V IN = GND to VCC 10 µA ILO Output Leakage Current V OUT = GND to VCC 10 µA VIL Input Low Voltage -1 V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 1.0 V VOL1 Output Low Voltage (VCC = 3.0V) I OL = 3 mA 0.4 V A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated.

be interpreted as a START or STOP condition. these pins to establish the device's address. its address matches the transmitted slave address. data transmission and waits for a STOP condition. Figure 4. Acknowledge Timing

5020 FHD F06

Document No. 2011, Rev. J INSTRUCTION AND REGISTER The first byte sent to the CAT5241 from the master/ processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5241 are fixed at 0101[B] (refer to Table 1). The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5241 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to V CC or VSS . INSTRUCTION BYTE The next byte sent to the CAT5241 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The P1 and P0 bits point to one of four Wiper Control Registers. The least two significant bits, R1 and R0, point to one of the four data registers of each associated potentiometer. The format is shown in Table 2. Table 1. Identification Byte Format Table 2. Instruction Byte Format

Table 3. Instruction Set instruction (see Instruction section for more details). loses its contents when the CAT5241 is powered-down. the value present at power-down. parameters or user preference data. Four of the nine instructions are three bytes in length.

Figure 10. Increment/Decrement Timing Limits

Document No. 2011, Rev. J DEVICE ADDRESS INSTRUCTION 0 1 0 1 A3 A2 A1 A0 1 1 1 0 P1 P0 R1R0 DEVICE ADDRESS INSTRUCTION 0 1 0 1 A 3 A 2A 1A 0 10 00 00 R 1 R 0 Global Transfer Wiper Control Register (WCR) to Data Register (DR) INSTRUCTION FORMAT (continued) Transfer Wiper Control Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A C K A C K S T O P Increment (I)/Decrement (D) Wiper Control Register (WCR) Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. Global Transfer Data Register (DR) to Wiper Control Register (WCR) A C K A C K S T O P S T A R T DEVICE ADDRESS INSTRUCTION 0 1 0 1 A3 A2 A1 A0 0 0 0 1 0 0 R1R0 A C K A C K S T O P S T A R T DEVICE ADDRESS INSTRUCTION 0 1 0 1 A3 A2 A1 A0 1 1 1 0 P1 P0 R1R0 A C K A C K S T O P S T A R T DEVICE ADDRESS INSTRUCTION DATA 0 1 0 1 A3 A2 A1 A0 0 0 1 0 P1 P0 0 0 I/D I/D I/D I/D S T A R T A C K A C K A C K S T O P• • •

Document No. 2011, Rev. J Notes: (1) The device used in the above example is a CAT5241JI-10-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel)

ORDERING INFORMATION

-10 -25: 2.5kohm -10: 10kohm -50: 50kohm -00: 100kohm 5241 U: TSSOP W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free)

Document No. 2011, Rev. J 20-LEAD 300 MIL WIDE SOIC (J, W) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.0926 (2.35) 0.1043 (2.65) 0.0040 (0.10) 0.0118 (0.30) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0 — 8 0.0091 (0.23) 0.0125 (0.32) 0.010 (0.25) 0.029 (0.75) X 45 0.016 (0.40) 0.050 (1.27) 0.5985 (15.20) 0.6141 (15.60) PACKAGING INFORMATION

Document No. 2011, Rev. J 20-LEAD 300 MIL WIDE TSSOP (U, Y) 1.0 1.0 D A1 A2 A b eb 0.20 R GAUGE PLANE L L1DETAIL A c SECTION A-A 0.076MM SEATING PLANE E DETAIL A AA SYMBOL A L D E R b c e N REF DIMENSION IN MM DIMENSION IN INCH MIN MINNOM NOMMAX MAX 1.20 0.15 1.05 0.75 6.60 6.50 4.50 0.30 0.25 0.20 0.16 0.05 0.80 0.50 6.40 6.30 4.30 0.09 0.09 0.19 0.19 0.09 0.09 0.90 0.60 6.50 6.40 4.40 0.22 .002 .031 .020 .252 .248 .169 .004 .004 .007 .007 .004 .004 .035 .024 .256 .252 .173 .009 .043 .006 .041 .030 .260 .256 .177 .012 .010 .008 .006

1.0 REF

0.65 BSC

.039 REF .026 BSC 08 08

12 REF

Catalyst Semiconductor, Inc. Corporate Headquarters

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Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: 2011 Revison: J Issue date: 4/5/04 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ DPPs ™ AE 2 ™ I2C is a trademark of Philips Corporation Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.

REVISION HISTORY

Date Rev. Reason 9/30/2003 G Deleted WP from Functional Diagram, pg. 1 3/3/2004 H Added TSSOP package in all areas 3/29/2004 I Eliminated data sheet designation Eliminated Commercial temp range in all areas Updated Absolute Max Ratings and Potentiometer Characteristics notes 4/5/2004 J Corrected Potentiometer Resistance [Changed (-2.5) to (-25)] in table