DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 43
Technical content
Datasheet sections
Features
■ 24-MHz ARM Cortex-M0 CPU with single-cycle multiply ■ Up to 32 kB of flash with Read Accelerator ■ Up to 4 kB of SRAM Programmable Analog ■ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability ■ 12-bit 806 ksps SAR ADC with differential and single-ended modes and Channel Sequencer with signal averaging ■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ■ Two low-power comparators that operate in Deep Sleep Low Power 1.71-V to 5.5-V operation ■ 20-nA Stop Mode with GPIO pin wakeup ■ Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs Capacitive Sensing ■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and water tolerance ■ Cypress supplied software component makes capacitive sensing design easy ■ Automatic hardware tuning (SmartSense™) Segment LCD Drive ■ LCD drive supported on all pins (common or segment) ■ Operates in Deep Sleep mode with 4 bits per pin memory Serial Communication ■ Two independent run-time reconfigurable serial communi- cation blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality Timing and Pulse-Width Modulation ■ Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks ■ Center-aligned, Edge, and Pseudo-random modes ■ Comparator-based triggering of Kill signals for motor drive and other high reliability digital logic applications Up to 36 Programmable GPIOs ■ Any GPIO pin can be CapSense, LCD, analog, or digital ■ Drive modes, strengths, and slew rates are programmable Five different packages ■ 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and 28-pin SSOP package ■ 35-ball WLCSP package is shipped with I2C Bootloader in Flash Extended Industrial Temperature Operation ■ –40 °C to + 105 °C operation PSoC Creator Design Environment ■ Integrated Development Environment provides schematic design entry and build (with analog and digital automatic routing) ■ Applications Programming Interface (API Component) for all fixed-function and programmable peripherals Industry Standard Tool Compatibility ■ After schematic entry, development can be done with ARM-based industry-standard development tools
In addition, PSoC Creator includes a device selection tool. ❐ Architecture TRM details each PSoC 4 functional block. ❐ Registers TRM describes each of the PSoC 4 registers. low-cost alternative to sampling PSoC 4 devices.
- Drag and drop component icons to build your hardware
- Codesign your application firmware with the PSoC hardware,
- Configure components using the configuration tools
- Explore the library of 100+ components
- Review component datasheets
Figure 1. Multiple-Sensor Example Project in PSoC Creator
Figure 2. Block Diagram programming and debug features of the device. connections are required to fully support debug. reprogram the device with new firmware that enables debugging.
24 MHz
system functions requested by the user. (address) comparators and two watchpoint (data) comparators. used to emulate EEPROM operation if required. set back to Open but only after completely erasing the Flash. prevent inadvertent Writes as well as selectively block Reads. internal code using system calls. SRAM memory is retained during Hibernate. system ensures that no metastable conditions occur. provision for an external clock. Figure 3. PSoC 4100 MCU Clocking Architecture frequency values and is fully supported in PSoC Creator.
accuracy. Trim values are stored in nonvolatile latches (NVL). tolerance with Cypress-provided calibration settings is ±2%. generate clocks for peripheral operation in Deep Sleep mode. XRES pin has an internal pull-up resistor that is always enabled. frequency to do a 12-bit conversion. appropriate references are used and system noise levels permit. internal reference amplifier. have different sample times programmable for each channel. for out-of-range values in software. SAR operating range is 1.71 V to 5.5 V. Figure 4. SAR ADC System Diagram
Document Number: 001-87220 Rev. *J Page 7 of 43 PSoC® 4: PSoC 4100 Family Datasheet Two Opamps (CTBm Block) PSoC 4100 has two opamps with Comparator modes which allow most common analog functions to be performed on-chip eliminating external components; PGAs, voltage buffers, filters, trans-impedance amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip opamps are designed with enough bandwidth to drive the S/H circuit of the ADC without requiring external buffering. Temperature Sensor PSoC 4100 has one on-chip temperature sensor This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temper- ature value using Cypress supplied software that includes calibration and linearization. Low-power Comparators PSoC 4100 has a pair of low-power comparators, which can also operate in the Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metasta- bility unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator switch event. Fixed Function Digital Timer/Counter/PWM Block (TCPWM) The TCPWM block consists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with program- mable offset between them to allow use as deadband program- mable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. Serial Communication Blocks (SCB) The PSoC 4100 has two SCBs, which can each implement an I2C, UART, or SPI interface. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I 2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The I2C bus uses open-drain drivers for clock and data with pull-up resistors on the bus for clock and data connected to all nodes. The required Rise and Fall times for different I 2C speeds are guaranteed by using appropriate pull-up resistor values depending on VDD, Bus Capacitance, and resistor tolerance. For detailed information on how to calculate the optimum pull-up resistor value for your design, refer to the UM10204 I2C bus specification and user manual (the latest revision is available at www.nxp.com). PSoC 4100 is not completely compliant with the I 2C spec in the following respects: ■ GPIO cells are not overvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I 2C system. ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the Bus Load. ■ When the SCB is an I2C master, it interposes an IDLE state between NACK and Repeated Start; the I2C spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle. ■ When the SCB is in I2C slave mode, and Address Match on External Clock is enabled (EC_AM = 1) along with operation in the internally clocked mode (EC_OP = 0), then its I2C address must be even. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
Document Number: 001-87220 Rev. *J Page 8 of 43 PSoC® 4: PSoC 4100 Family Datasheet GPIO PSoC 4100 has 36 GPIOs. The GPIO block implements the following: ■ Eight drive strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL). ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes. ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode and Hibernate modes). ■ Selectable slew rates for dV/dt related noise control to improve EMI. The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multi- plexing complexity. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4100 since it has 4.5 ports). Special Function Peripherals LCD Segment Drive PSoC 4100 has an LCD controller which can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as digital corre- lation and PWM. Digital correlation pertains to modulating the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effec- tively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). CapSense CapSense is supported on all pins in the PSoC 4100 through a CapSense Sigma-Delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch. CapSense function can thus be provided on any pin or group of pins in a system under software control. A component is provided for the CapSense block to make it easy for the user. Shield voltage can be driven on another mux bus to provide water tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. The CapSense block has two IDACs which can be used for general purposes if CapSense is not being used.(both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). The WLCSP package is supplied with an I2C Bootloader installed in flash. The bootloader is compatible with PSoC Creator bootloadable project files and has the following default settings: ■ I2C SCL and SDA connected to port pins P4.0 and P4.1 respec- tively (external pull-up resistors required) ■ I2C Slave mode, address 8, data rate = 100 kbps ■ Single application ■ Wait two seconds for bootload command ■ Other bootloader options are as set by the PSoC Creator Bootloader Component default ■ Occupies the bottom 4.5 K of flash For more information on this bootloader, see the following Cypress application notes: AN73854 - Introduction to Bootloaders Note that a PSoC Creator bootloadable project must be associated with .hex and .elf files for a bootloader project that is configured for the target device. Bootloader .hex and .elf files can be found at http://www.cypress.com/?rID=78805. The factory-installed bootloader can be overwritten using JTAG or SWD programming.
Document Number: 001-87220 Rev. *J Page 9 of 43 PSoC® 4: PSoC 4100 Family Datasheet Pinouts The following is the pin-list for PSoC 4100 (44-TQFP, 40-QFN, 28-SSOP, and 48-TQFP). Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the optional external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD CapSense and analog mux bus connections. 44-TQFP 40-QFN 28-SSOP 48-TQFP Alternate Functions for Pins Pin Description Pin Name Pin Name Pin Name Pin Name Analog Alt 1 Alt 2 Alt 3 Alt 4 2 P2.0 1 P2.0 – – 2 P2.0 sarmux.0 – – – – Port 2 Pin 0: gpio, lcd, csd, sarmux 3 P2.1 2 P2.1 – – 3 P2.1 sarmux.1 – – – – Port 2 Pin 1: gpio, lcd, csd, sarmux 11 P3.0 10 P3.0 11 P3.0 12 P3.0 – tcpwm0_p[0] scb1_uart_rx[0] scb1_i2c_scl[0] scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm, scb1 12 P3.1 11 P3.1 12 P3.1 13 P3.1 – tcpwm0_n[0] scb1_uart_tx[0] scb1_i2c_sda[0] scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm, scb1 13 P3.2 12 P3.2 13 P3.2 14 P3.2 – tcpwm1_p[0] – swd_io[0] scb1_spi_clk[0] Port 3 Pin 2: gpio, lcd, csd, pwm, scb1, swd 14 P3.3 13 P3.3 14 P3.3 16 P3.3 – tcpwm1_n[0] – swd_clk[0] scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm, scb1, swd 15 P3.4 14 P3.4 – – 17 P3.4 – tcpwm2_p[0] – – scb1_spi_ssel_1 Port 3 Pin 4: gpio, lcd, csd, pwm, scb1 16 P3.5 15 P3.5 – – 18 P3.5 – tcpwm2_n[0] – – scb1_spi_ssel_2 Port 3 Pin 5: gpio, lcd, csd, pwm, scb1 17 P3.6 16 P3.6 – – 19 P3.6 – tcpwm3_p[0] – – scb1_spi_ssel_3 Port 3 Pin 6: gpio, lcd, csd, pwm, scb1 18 P3.7 17 P3.7 – – 20 P3.7 – tcpwm3_n[0] – – – Port 3 Pin 7: gpio, lcd, csd, pwm 19 VDDD – – – – 21 VDDD – – – – – Digital Supply, 1.8 - 5.5V 20 P4.0 18 P4.0 15 P4.0 22 P4.0 – – scb0_uart_rx scb0_i2c_scl scb0_spi_mosi P ort 4 Pin 0: gpio, lcd, csd, scb0 21 P4.1 19 P4.1 16 P4.1 23 P4.1 – – scb0_uart_tx scb0_i2c_sda scb0_spi_miso P ort 4 Pin 1: gpio, lcd, csd, scb0 22 P4.2 20 P4.2 17 P4.2 24 P4.2 csd_c_mod – – – scb0_sp i_clk Port 4 Pin 2: gpio, lcd, csd, scb0 23 P4.3 21 P4.3 18 P4.3 25 P4.3 csd_c_sh_tank – – – scb0_s pi_ssel_0 Port 4 Pin 3: gpio, lcd, csd, scb0
Document Number: 001-87220 Rev. *J Page 10 of 43 PSoC® 4: PSoC 4100 Family Datasheet Notes: 1. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively. 2. P3.2 and P3.3 are SWD pins after boot (reset). 24 P0.0 22 P0.0 19 P0.0 28 P0.0 comp1_inp – – – scb0_spi_ssel_1 Port 0 Pin 0: gpio, lcd, csd, scb0, comp 25 P0.1 23 P0.1 20 P0.1 29 P0.1 comp1_inn – – – scb0_spi_ssel_2 Port 0 Pin 1: gpio, lcd, csd, scb0, comp 26 P0.2 24 P0.2 21 P0.2 30 P0.2 comp2_inp – – – scb0_spi_ssel_3 Port 0 Pin 2: gpio, lcd, csd, scb0, comp 27 P0.3 25 P0.3 22 P0.3 31 P0.3 comp2_inn – – – – Port 0 Pin 3: gpio, lcd, csd, comp 28 P0.4 26 P0.4 – – 32 P0.4 – – scb1_uart_rx[1] scb1_i2c_scl[1] scb1_spi_mosi[1] Port 0 Pin 4: gpio, lcd, csd, scb1 29 P0.5 27 P0.5 – – 33 P0.5 – – scb1_uart_tx[1] scb1_i2c_sda[1] scb1_spi_miso[ 1] Port 0 Pin 5: gpio, lcd, csd, scb1 30 P0.6 28 P0.6 23 P0.6 34 P0.6 – ext_clk – – scb1_spi_clk[1] Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk 31 P0.7 29 P0.7 24 P0.7 35 P0.7 – – – wakeup scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1, wakeup
32 XRES 30 XRES 25 XRES 36 XRES – – – – – Chip reset, active low
33 VCCD 31 VCCD 26 VCCD 37 VCCD – – – – – Regulated supply, connect to 1µF cap or
1.8V 34 VDDD 32 VDDD 27 VDD 39 VDDD – – – – – Digital Supply, 1.8 - 5.5V 35 VDDA 33 VDDA 27 VDD 40 VDDA – – – – – Analog Supply, 1.8 - 5.5V, equal to VDDD
36 VSSA 34 VSSA 28 VSS 41 VSSA – – – – –
42 P1.5 – – – – 47 P1.5 ctb.oa1.inp – – – – Port 1 Pin 5: gpio, lcd, csd, ctb 43 P1.6 – – – – 48 P1.6 ctb.oa0.inp_alt – – – – Port 1 Pin 6: gpio, lcd, csd ext_vref –– – – Port 1 Pin 7: gpio, lcd, csd, ext_ref 44-TQFP 40-QFN 28-SSOP 48-TQFP Alternate Functions for Pins Pin Description Pin Name Pin Name Pin Name Pin Name Analog Alt 1 Alt 2 Alt 3 Alt 4
Document Number: 001-87220 Rev. *J Page 11 of 43 PSoC® 4: PSoC 4100 Family Datasheet The following is the pin-list for the PSoC 4100 (35-WLCSP). 35-Ball CSP Alternate Functions for Pins Pin Description Pin Name Analog Alt 1 Alt 2 Alt 3 Alt 4 D3 P2.2 sarmux.2 – – – – Port 2 Pin 2: gpio, lcd, csd, sarmux E4 P2.3 sarmux.3 – – – – Port 2 Pin 3: gpio, lcd, csd, sarmux E5 P2.4 sarmux.4 tcpwm0_p[1] – – – Port 2 Pin 4: gpio, lcd, csd, sarmux, pwm E6 P2.5 sarmux.5 tcpwm0_n[1] – – – Port 2 Pin 5: gpio, lcd, csd, sarmux, pwm E3 P2.6 sarmux.6 tcpwm1_p[1] – – – Port 2 Pin 6: gpio, lcd, csd, sarmux, pwm E2 P2.7 sarmux.7 tcpwm1_n[1] – – – Port 2 Pin 7: gpio, lcd, csd, sarmux, pwm E1 P3.0 – tcpwm0_p[0] scb1_uart_rx[0] scb1_i2c_scl[0] scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm, scb1 D2 P3.1 – tcpwm0_n[0] scb1_uart_tx[0] scb1_i2c_sda[0] scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm, scb1 D1 P3.2 – tcpwm1_p[0] – swd_io[0] scb1_spi_clk[0] Port 3 Pin 2: gpio, lcd, csd, pwm, scb1, swd C1 P3.3 – tcpwm1_n[0] – swd_clk[0] scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm, scb1, swd C2 P3.4 – tcpwm2_p[0] - – scb1_spi_ssel_1 Port 3 Pin 4: gpio, lcd, csd, pwm, scb1 B1 P4.0 – – scb0_uart_rx scb0_i2c_scl scb0_spi_mosi Port 4 Pin 0: gpio, lcd, csd, scb0 B2 P4.1 – – scb0_uart_tx scb0_i2c_sda scb0_spi_miso Port 4 Pin 1: gpio, lcd, csd, scb0 A2 P4.2 csd_c_mod – – – scb0_spi_clk Por t 4 Pin 2: gpio, lcd, csd, scb0 A1 P4.3 csd_c_sh_tank – – – scb0_spi_ssel_0 P ort 4 Pin 3: gpio, lcd, csd, scb0 C3 P0.0 comp1_inp – – – scb0_spi_ssel_1 Port 0 Pin 0: gpio, lcd, csd, scb0, comp A5 P0.1 comp1_inn – – – scb0_spi_ssel_2 Port 0 Pin 1: gpio, lcd, csd, scb0, comp A4 P0.2 comp2_inp – – – scb0_spi_ssel_3 Port 0 Pin 2: gpio, lcd, csd, scb0, comp A3 P0.3 comp2_inn – – – – Port 0 Pin 3: gpio, lcd, csd, comp B3 P0.4 – – scb1_uart_rx[1] scb1_i2c_scl[1] scb1_spi_mosi[1] Port 0 Pin 4: gpio, lcd, csd, scb1 A6 P0.5 – – scb1_uart_tx[1] scb1_i2c_sda[1] scb1_spi_miso[1] Port 0 Pin 5: gpio, lcd, csd, scb1 B4 P0.6 – ext_clk – – scb1_spi_clk[1] Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk B5 P0.7 – – – wakeup scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1, wakeup B6 XRES – – – – – Chip reset, active low A7 VCCD – – – – – Regulated supply, connect to 1µF cap or 1.8V C7 VDD – – – – – Supply, 1.8 - 5.5V C4 P1.0 ctb.oa0.inp tcpwm2_p[1] – – – Port 1 Pin 0: gpio, lcd, csd, ctb, pwm C5 P1.1 ctb.oa0.inm tcpwm2_n[1] – – – Port 1 Pin 1: gpio, lcd, csd, ctb, pwm
Document Number: 001-87220 Rev. *J Page 12 of 43 PSoC® 4: PSoC 4100 Family Datasheet Descriptions of the Pin functions are as follows: VDDD: Power supply for both analog and digital sections (where there is no VDDA pin). VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise. VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise VSS: Ground pin. VCCD: Regulated Digital supply (1.8 V ±5%). Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins that can be driven by firmware or DSI signals. The following packages are supported: 48-pin TQFP, 44-pin TQFP, 40-pin QFN, and 28-pin SSOP. C6 P1.2 ctb.oa0.out tcpwm3_p[1] – – – Port 1 Pin 2: gpio, lcd, csd, ctb, pwm D7 P1.3 ctb.oa1.out tcpwm3_n[1] – – – Port 1 Pin 3: gpio, lcd, csd, ctb, pwm D4 P1.4 ctb.oa1.inm – – – – Port 1 Pin 4: gpio, lcd, csd, ctb D5 P1.5 ctb.oa1.inp – – – – Port 1 Pin 5: gpio, lcd, csd, ctb D6 P1.6 ctb.oa0.inp_alt – – – – Port 1 Pin 6: gpio, lcd, csd E7 P1.7/VREF ctb.oa1.inp_alt ext_vref – – – – Port 1 Pin 7: gpio, lcd, csd, ext_ref 35-Ball CSP Alternate Functions for Pins Pin Description Pin Name Analog Alt 1 Alt 2 Alt 3 Alt 4
and Hibernate (lowered power supply and retention) modes. circuits operating over that range. Figure 10. PSoC 4 Power Supply Capacitor (in the range of 1 µF to 1.6 µF; X5R ceramic or better). should be simulated to design and obtain optimal bypassing. Figure 11. 48-TQFP Package Example Figure 12. 44-TQFP Package Example
1.8 Volt
itance may be greater than 10 µF. capacitance may be greater than 10 µF. itance may be greater than 10 µF.
Document Number: 001-87220 Rev. *J Page 17 of 43 PSoC® 4: PSoC 4100 Family Datasheet Development Support The PSoC 4100 family has a rich set of documentation, devel- opment tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4 to find out more. Documentation A suite of documentation supports the PSoC 4100 family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers. The TRM is available in the Documentation section at www.cypress.com/psoc4. Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Tools With industry standard cores, programming, and debugging interfaces, the PSoC 4100 family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits.
- Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Table 1. Absolute Maximum Ratings[1] Table 2. DC Specifications
Table 3. AC Specifications SID50 T DEEPSLEEP Wakeup from Deep Sleep mode – – 25 µs 24-MHz IMO. Table 2. DC Specifications (continued)
- V IH must not exceed VDDD + 0.2 V.
Table 4. GPIO DC Specifications SID67 V HYSTTL Input hysteresis LVTTL 25 40 – mV V DDD 2.7 V.
Table 5. GPIO AC Specifications (Guaranteed by Characterization) Table 6. XRES DC Specifications Table 7. XRES AC Specifications
Table 8. Opamp Specifications (Guaranteed by Characterization) SID290 V OS_DR_TR Offset voltage drift, trimmed –10 ±3 10 µV/°C High mode. SID290Q VOS_DR_TR Offset voltage drift, trimmed 15 ±3 15 µV/°C High mode.
Table 8. Opamp Specifications (Guaranteed by Characterization) (continued) Table 9. Comparator DC Specifications Mode voltage range from 0 to VDD -1. SID88 CMRR Common mode rejection ratio 50 – – dB V DDD 2.7 V.
Table 10. Comparator AC Specifications Table 11. Temperature Sensor Specifications Table 12. SAR ADC DC Specifications
Table 12. SAR ADC DC Specifications (continued) Table 13. SAR ADC AC Specifications (Guaranteed by Characterization) SID108A A_SAMP_2 Sample rate with no bypass cap. SID108B A_SAMP_3 Sample rate with no bypass cap. SID113 A_THD Total harmonic distortion – – –65 dB F IN = 10 kHz.
Table 14. CSD Specifications
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Table 15. TCPWM Specifications Table 16. Fixed I2C DC Specifications (Guaranteed by Characterization) Table 17. Fixed I2C AC Specifications (Guaranteed by Characterization) Table 18. LCD Direct Drive DC Specifications (Guaranteed by Characterization) SID157 I LCDOP1 PWM Mode current. 5-V bias. SID158 I LCDOP2 PWM Mode current. 3.3-V bias.
Table 19. LCD Direct Drive AC Specifications (Guaranteed by Characterization) Table 20. Fixed UART DC Specifications (Guaranteed by Characterization) Table 21. Fixed UART AC Specifications (Guaranteed by Characterization) Table 22. Fixed SPI DC Specifications (Guaranteed by Characterization) Table 23. Fixed SPI AC Specifications (Guaranteed by Characterization) Table 24. Fixed SPI Master Mode AC Specifications (Guaranteed by Characterization) Table 25. Fixed SPI Slave Mode AC Specifications (Guaranteed by Characterization)
Table 26. Flash DC Specifications
- It can take as much as 20 milliseconds to write to Flash. Du ring this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Table 27. Flash AC Specifications Table 28. Imprecise Power On Reset (IPOR) Table 29. Precise Power On Reset (POR)
1.71 V and BOD trip
Table 30. Voltage Monitors DC Specifications Table 31. Voltage Monitors AC Specifications Table 32. SWD Interface Specifications
Table 33. IMO DC Specifications (Guaranteed by Design) Table 34. IMO AC Specifications
48 MHz
Table 35. ILO DC Specifications (Guaranteed by Design) Table 36. ILO AC Specifications Table 37. External Clock Specifications
Table 38. Block Specs
Document Number: 001-87220 Rev. *J Page 33 of 43 PSoC® 4: PSoC 4100 Family Datasheet
Ordering Information
The PSoC 4100 part numbers and features are listed in the following table. Table 39. PSoC 4100 Family Ordering Information
Document Number: 001-87220 Rev. *J Page 34 of 43 PSoC® 4: PSoC 4100 Family Datasheet Part Numbering Conventions PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0, 1, 2, …, 9, A,B, …, Z) unless stated otherwise. The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows. The Field Values are listed in the following table. Architecture Cypress Prefix Family within Architecture Speed Grade Flash Capacity Package Code Temperature Range Attributes Set 4 : PSoC 4 2: 2 4M H z 5: 3 2K B AX: TQFP I : Industrial Example CY8C 4 A E DCBF Y X-Z 1 : 4100Family Field Description Values Meaning CY8C Cypress Prefix
4 Architecture 4 PSoC 4
A Family within architecture 1 4100 Family 2 4200 Family B CPU Speed 22 4 M H z 44 8 M H z C Flash Capacity 41 6 K B 53 2 K B AX, AZ TQFP LQ QFN PV SSOP FN WLCSP F Temperature Range I Industrial Q Extended Industrial XYZ Attributes Code 000-999 Code of feature set in specific family
http://www.cypress.com/cad-resources/psoc-4-cad-libraries?source=search&cat=technical_documents. Table 40. Package Characteristics Table 41. Solder Reflow Peak Temperature Table 42. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Figure 19. 48-Pin TQFP Package Outline
Table 43. Acronyms Used in this Document capabilities, no analog. See GPIO. Table 43. Acronyms Used in this Document (continued)
Table 44. Units of Measure
Document Number: 001-87220 Rev. *J Page 42 of 43 PSoC® 4: PSoC 4100 Family Datasheet
Revision History
Description Title: PSoC® 4: PSoC 4100 Family Datasheet Programmable System-on-Chip (PSoC®) Document Number:001-87220 Revision ECN Orig. of Change Submission Date Description of Change *B 4108562 WKA 08/29/2013 Added clarifying note about the XRES pin in the Reset section. Added a link reference to the PSoC 4 TRM. Updated the footnote in Absolute Maximum Ratings. Updated Sleep Mode IDD specs in DC Specifications. Updated Comparator DC Specifications Updated SAR ADC AC Specifications (Guaranteed by Characterization) Updated LCD Direct Drive DC Specifications (Guaranteed by Characterization) Updated the number of GPIOs in Ordering Information. *C 4568937 WKA 11/19/2014 Added 48-pin TQFP pin and package details. Added SID308A spec details. Updated Ordering Information. *D 4617283 WKA 01/08/2015 Corrected typo in the ordering information table. Updated 28-pin SSOP package diagram. *E 4643655 WKA 04/29/2015 Added 35 WLCSP pinout and package detail information. Updated CSD specifications. *F 5287114 WKA 06/09/2016 Corrected typo in the Features section. Added reference to AN90071 in the More Information section. Updated Flash section with details of flash protection modes. Added notes in the Pinouts section. Updated 40-pin QFN and 28-pin SSOP pin diagrams. Added PSoC 4 Power Supply diagram. Updated the Bypass Capacitors column in the Power Supply table. Updated values for SID32, SID34, SID38, SID269, SID270, SID271. Added SID299A. Updated Comparator Specifications. Updated TCPWM Specifications. Updated values for SID149, SID160, SID171. Updated Conditions for SID190. Added BID55. Removed Conditions for SID237. Added reference to PSoC 4 CAB Libraries with Schematics Symbols and PCB Footprints in the Packaging section. *G 5327384 WKA 06/28/2016 Removed the capacitor connection for Pin 15 in Figure 11. *H 5704046 GNKK 04/26/2017 Updated the Cypress logo and copyright information. *I 5738586 WKA 05/16/2017 Updated max value of SID61. *J 5795966 WKA 07/10/2017 Changed Pin 33 name in 40-pin QFN Pinout from VDDD to VDDA to correct typo; pinout table is correct and not changed. Removed reference to swd_io[1] and swd_clk[1]. Corrected 44-TQFP Package Example.
Document Number: 001-87220 Rev. *J Revised July 10, 2017 Page 43 of 43 © Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. Cypress is not liable, in whol e or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Uninte nded Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. PSoC® 4: PSoC 4100 Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless PSoC® Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support