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■ 48-MHz ARM Cortex-M0+ CPU ■ Up to 32 KB of flash with Read Accelerator ■ Up to 4 KB of SRAM Programmable Analog ■ Single-slope 10-bit ADC function provided by Capacitance sensing block ■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ■ Two low-power comparators that operate in Deep Sleep low-power mode Programmable Digital Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs Low-Power 1.71-V to 5.5-V Operation ■ Deep Sleep mode with operational analog and 2.5 A digital system current Capacitive Sensing ■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance ■ Cypress-supplied software component makes capacitive sensing design easy ■ Automatic hardware tuning (SmartSense™) Serial Communication ■ Two independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality LCD Drive Capability ■ LCD segment drive capability on GPIOs Timing and Pulse-Width Modulation ■ Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks ■ Center-aligned, Edge, and Pseudo-random modes ■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 36 Programmable GPIO Pins ■ 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, and 25-ball WLCSP packages ■ Any GPIO pin can be CapSense, analog, or digital ■ Drive modes, strengths, and slew rates are programmable PSoC Creator Design Environment ■ Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) ■ Applications Programming Interface (API) component for all fixed-function and programmable peripherals Industry-Standard Tool Compatibility ■ After schematic entry, development can be done with ARM-based industry-standard development tools
Figure 1. Block Diagram programming and debug features of the device. connections are required to fully support debug. reprogram the device with new firmware that enables debugging. without erasing the firmware thus providing security.
48 MHz
and the CPU executes a subset of the Thumb-2 instruction set. processor when the chip is in Deep Sleep mode. (address) comparators and two watchpoint (data) comparators. designed to deliver two wait-state (WS) access time at 48 MHz. Active, Sleep, and Deep Sleep low-power modes. remain operational in Deep Sleep mode. clock system ensures that there are no metastable conditions. provided to enable clocking of higher data rates for UARTs. Figure 2. PSoC 4000S MCU Clocking Architecture with Cypress-provided calibration settings is ±2%. counters can be calibrated to the IMO to improve accuracy. for precision timing applications.
PSoC® 4: PSoC 4000S Family Datasheet Document Number: 002-00123 Rev. *I Page 5 of 35 Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause register, which is firmware readable. Reset The PSoC 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled. Voltage Reference The PSoC 4000S reference system generates all internally required references. A 1.2-V voltage reference is provided for the comparator. The IDACs are based on a ±5% reference. Analog Blocks Low-power Comparators (LPC) The PSoC 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event. The LPC outputs can be routed to pins. Current DACs The PSoC 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable current ranges. Analog Multiplexed Buses The PSoC 4000S has two concentric independent buses that go around the periphery of the chip. These buses (called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal resources (IDACs, comparator) to connect to any pin on the I/O Ports. Programmable Digital Blocks The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as outputs. Fixed Function Digital Timer/Counter/PWM (TCPWM) Block The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an I/O event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC 4000S. Serial Communication Block (SCB) The PSoC 4000S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART functionality. I 2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multi-master arbitration). This block is capable of operating at speeds of up to 400 kbps (Fast Mode) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates a mailbox address range in the memory of the PSoC 4000S and effectively reduces I 2C commu- nication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I 2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The PSoC 4000S is not completely compliant with the I2C spec in the following respect: ■ GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
PSoC® 4: PSoC 4000S Family Datasheet Document Number: 002-00123 Rev. *I Page 6 of 35 GPIO The PSoC 4000S has up to 36 GPIOs. The GPIO block imple- ments the following: ■ Eight drive modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL). ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes ■ Selectable slew rates for dV/dt related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 2 and 3). During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4000S). Special Function Peripherals CapSense CapSense is supported in the PSoC 4000S through a CapSense Sigma-Delta (CSD) block that can be connected to any pins through an analog multiplex bus via analog switches. CapSense function can thus be provided on any available pin or group of pins in a system under software control. A PSoC Creator component is provided for the CapSense block to make it easy for the user. Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented. The CapSense block has two IDACs, which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). The CapSense block also provides a 10-bit Slope ADC function, which can be used in conjunction with the CapSense function. The CapSense block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise. LCD Segment Drive The PSoC 4000S has an LCD controller, which can drive up to 8 commons and up to 28 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port).
packages. All port pins support GPIO. Pin 11 is a No-Connect in the 48-TQFP . Table 1. PSoC 4000S Pin List
36 XRES 24 XRES 18 XRES B3 XRES 30 XRES
37 VCCD 25 VCCD 19 VCCD A1 VCCD 31 VCCD
38 VSSD 26 VSSD 20 VSSD A2 VSS
39 VDDD 27 VDD 21 VDD A3 VDD 32 VDDD
40 VDDA 27 VDD 21 VDD A3 VDD 33 VDDA
41 VSSA 28 VSSA 22 VSSA A2 VSS 34 VSSA
10 VSSD A2 VSS 9 VSSD
VDDD: Power supply for the digital section. VDDA: Power supply for the analog section. VSSD, VSSA: Ground pins for the digital and analog sections respectively. pin, or a CapSense pin. The pin assignments are shown in the following table.
21 VDDD
Table 1. PSoC 4000S Pin List (continued)
PSoC® 4: PSoC 4000S Family Datasheet Document Number: 002-00123 Rev. *I Page 9 of 35 P1.6 scb[0].spi_select3:1 P1.7 P2.2 prgio[0].io[2] scb[1].spi_clk:2 P2.3 prgio[0].io[3] scb[1].spi_select0:2 P2.4 prgio[0].io[4] tcpwm.line[0]:1 scb[1].spi_select1:1 P2.5 prgio[0].io[5] tcpwm.line_compl[0]:1 scb[1].spi_select2:1 P2.6 prgio[0].io[6] tcpwm.line[1]:1 scb[1].spi_select3:1 P2.7 prgio[0].io[7] tcpwm.line_compl[1]:1 lpcomp.comp[0]:1 Port/ Pin Analog Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 Deep Sleep 2
Figure 3. Power Supply Connections (externally regulated; 1.71 to 1.89, internal regulator bypassed). ceramic or better) and must not be connected to anything else. bypassed. The internal regulator can be disabled in the firmware. design and obtain optimal bypassing. Figure 4. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
1.8 Volt
PSoC® 4: PSoC 4000S Family Datasheet Document Number: 002-00123 Rev. *I Page 11 of 35 Development Support The PSoC 4000S family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4 to find out more. Documentation A suite of documentation supports the PSoC 4000S family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers. The TRM is available in the Documentation section at www.cypress.com/psoc4. Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Tools With industry standard cores, programming, and debugging interfaces, the PSoC 4000S family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits.
- Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification. Table 2. Absolute Maximum Ratings[1] Table 3. DC Specifications Typical values measured at VDD = 3.3 V and 25 °C.
Table 3. DC Specifications (continued) Typical values measured at VDD = 3.3 V and 25 °C.
- Guaranteed by characterization.
Table 4. AC Specifications
- V IH must not exceed VDDD + 0.2 V.
- Guaranteed by characterization.
Table 5. GPIO DC Specifications Table 6. GPIO AC Specifications
3.3 V VDDD, Cload =
- Guaranteed by characterization.
Table 7. XRES DC Specifications Table 8. XRES AC Specifications
Table 9. Comparator DC Specifications Table 10. Comparator AC Specifications
Table 11. CSD and IDAC Specifications SID313 SNR Ratio of counts of finger to noise.
SID325 CMOD External modulator capacitor. – 2.2 – nF 5-V rating, X7R or NP0 cap. Table 11. CSD and IDAC Specifications (continued) Table 12. 10-bit CapSense ADC Specifications
Table 12. 10-bit CapSense ADC Specifications (continued)
- Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Table 13. TCPWM Specifications
- Guaranteed by characterization.
Table 14. Fixed I2C DC Specifications[7] Table 15. Fixed I2C AC Specifications[7] Table 16. SPI DC Specifications[7] Table 17. SPI AC Specifications[7]
Table 18. UART DC Specifications[8] Table 19. UART AC Specifications[8]
- Guaranteed by characterization.
Table 20. LCD Direct Drive DC Specifications[8] Table 21. LCD Direct Drive AC Specifications[8]
Table 22. Flash DC Specifications
- It can take as much as 20 milliseconds to write to Flash. Du ring this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
- Guaranteed by characterization.
Table 23. Flash AC Specifications Table 24. Power On Reset (PRES) Table 25. Brown-out Detect (BOD) for VCCD
- Guaranteed by characterization.
Table 26. SWD Interface Specifications Table 27. IMO DC Specifications Table 28. IMO AC Specifications
48 MHz (trimmed) ––± 2%
Table 29. ILO DC Specifications Table 30. ILO AC Specifications
Table 31. Watch Crystal Oscillator (WCO) Specifications
- Guaranteed by characterization.
Table 32. External Clock Specifications Table 33. Block Specs Table 34. Smart I/O Pass-through Time (Delay in Bypass Mode)
PSoC® 4: PSoC 4000S Family Datasheet Document Number: 002-00123 Rev. *I Page 25 of 35
Ordering Information
The PSoC 4000S part numbers and features are listed in the following table. The nomenclature used in the preceding table is based on the following part numbering convention: Table 35. PSoC 4000S Ordering Information
4 Architecture 4 PSoC 4
PSoC® 4: PSoC 4000S Family Datasheet Document Number: 002-00123 Rev. *I Page 26 of 35 The following is an example of a part number: C Flash Capacity 41 6 K B 53 2 K B 66 4 K B 7 128 KB AX TQFP (0.8-mm pitch) AZ TQFP (0.5-mm pitch) LQ QFN PV SSOP FN CSP F Temperature Range I Industrial S Silicon Family S PSoC 4A-S1, PSoC 4A-S2 M PSoC 4A-M L PSoC 4A-L BL PSoC 4A-BLE XYZ Attributes Code 000-999 Code of fe ature set in the specific family Field Description Values Meaning CY8C 4 A B C DE F – S XYZ Cypress Prefix Architecture Family within Architecture CPU Speed Temperature Range Package Code Flash Capacity Attributes Code Example 4: PSoC 4 2: 4200 Family 4: 48 MHz I: Industrial AX: TQFP 5: 32 KB Silicon Family 1: 4100 Family AZ: TQFP 0: 4000 Family
The PSoC 4000S will be offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, and 25-ball WLCSP packages. Package dimensions and Cypress drawing numbers are in the following table. Table 36. Package List Table 37. Package Thermal Characteristics Table 38. Solder Reflow Peak Temperature Table 39. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Figure 9. 25-Ball WLCSP
Table 40. Acronyms Used in this Document capabilities, no analog. See GPIO. Table 40. Acronyms Used in this Document (continued)
Table 41. Units of Measure
PSoC® 4: PSoC 4000S Family Datasheet Document Number: 002-00123 Rev. *I Page 34 of 35
Revision History
Description Title: PSoC® 4: PSoC 4000S Family Datasheet Programmable System-on-Chip (PSoC) Document Number: 002-00123 Revision ECN Orig. of Change Submission Date Description of Change ** 4883809 WKA 08/28/2015 New datasheet *A 4992376 WKA 10/30/2015 Updated Pinouts. Added VDDD ≥ 2.2V at –40 °C under Conditions for specs SID247A, SID90, SID92. Updated Table 12. Updated Ordering Information. *B 5037826 SLAN 12/08/2015 Changed datasheet status to Preliminary *C 5104369 WKA 01/27/2016 Added Errata. Added 25 WLCSP package details. Updated theta JA and JC values for all packages. *D 5139206 WKA 02/16/2016 Updated copyright information at the end of the document. *E 5173961 WKA 03/15/2016 Updated Pinouts. Updated values for SID79, BID194. SID175, and SID176. Updated CSD and IDAC Specifications. Updated 10-bit CapSense ADC Specifications. *F 5268662 WKA 05/12/2016 Updated Alternate Pin Functions. Updated the following specs: SID310, SID312, SID313, SID314, SID314C, SID314D, SID314E, SID315, SID315C, SID315D, SID315E, SID322A, SID322B, SIDA109. Removed Errata section. Updated the Cypress logo and copyright information based on the template. *G 5330930 WKA 07/27/2016 Updated LCD Segment Drive. Updated SID60 conditions. Updated IDD specs. Corrected package dimensions for WLCSP package and added WLCSP MSL condition. Moved datasheet status to Final. *H 5415365 WKA 09/14/2016 Added 40-pin QFN pin and package details. Updated IDD spec values in DC Specifications. *I 5561833 WKA 01/09/2017 Changed PRGIO references to Smart I/O.
Document Number: 002-00123 Rev. *I Revised January 9, 2017 Page 35 of 35 PSoC® 4: PSoC 4000S Family Datasheet © Cypress Semiconductor Corporation 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsi diaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. Cypress is not liable, in who le or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Uninte nded Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless PSoC®Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support