39K30 CYPRESS | Alldatasheet
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Technical content
Features
High density — 30K to 200K usable gates — 512 to 3072 macrocells — 136 to 428 maximum I/O pins — Twelve dedicated inputs including four clock pins, four global I/O control signal pins and four JTAG interface pins for boundary scan and reconfig- urability Embedded memory — 80K to 480K bits embedded SRAM 16K to 96K bits of (dual-port) channel memory High speed – 233-MHz in-system operation A n y V o l t ™ interface — 3.3V, 2.5V,1.8V, and 1.5V I/O capability Low-power operation — 0.18-mm six-layer metal SRAM-based logic process — Full-CMOS implementation of product term array — Standby current as low as 5mA Simple timing model — No penalty for using full 16 product terms/macrocell — No delay for single product term steering or sharing Flexible clocking — Spread Aware™ PLL drives all four clock networks Allows 0.6% spread spectrum input clocks Several multiply, divide and phase shift options — Four synchronous clock networks per device — Locally generated product term clock — Clock polarity control at each register Carry-chain logic for fast and efficient arithmetic opera- tions Multiple I/O standards supported (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ Compatible with NOBL™, ZBT™, and QDR™ SRAMs Programmable slew rate control on each I/O pin User-programmable Bus Hold capability on each I/O pin Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec, rev. 2.2) CompactPCI hot swap ready Multiple package/pinout offering across all densities — 208 to 676 pins in PQFP , BGA, and FBGA packages — Simplifies design migration across density — Self-Boot™ solution in BGA and FBGA packages In-System Reprogrammable™ (ISR™) — JTAG-compliant on-board programming — Design changes do not cause pinout changes IEEE1149.1 JTAG boundary scan Development Software Warp ® — IEEE 1076/1164 VHDL or IEEE 1364 Verilog context sensitive editing — Active-HDL FSM graphical finite state machine editor — Active-HDL SIM post-synthesis timing simulator — Architecture Explorer for detailed design analysis — Static Timing Analyzer for critical path analysis — Available on Windows 95/98/2000/XP™ and Windows NT™ for $99 — Supports all Cypress programmable logic products Delta39K™ ISR CPLD Family Members Device Typical Gates[1] Macrocells Cluster memory (Kbits) Channel memory (Kbits) Maximum I/O Pins fMAX2 (MHz) Speed-tPD Pin-to-Pin (ns) Standby ICC [2] TA = 25°C 3.3/2.5V 39K30 16K – 48K 512 64 16 174 233 7.2 5 mA 39K50 23K – 72K 768 96 24 218 233 7.2 5 mA 39K100 46K – 144K 1536 192 48 302 222 7.5 10 mA 39K165 77K – 241K 2560 320 80 386 181 8.5 20 mA 39K200 92K – 288K 3072 384 96 428 181 8.5 20 mA Notes: 1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used. 2. Standby ICC values are with PLL not utilized, no output load and stable inputs.
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 2 of 86 Notes: 3. Speed bins shown here are for commercial operating range. Please refer to Delta39K ordering information on industrial-range speed bins on page 38. 4. Self-boot solution integrates the boot PROM (flash memory) with Delta39K die inside the same package. This flash memory can endure at least 10,000 programming/erase cycles and can retain data for at least 100 years. Delta39K Speed Bins[3] Device VCC 233 200 181 125 83 39K30 3.3/2.5V X X X 39K50 3.3/2.5V X X X 39K100 3.3/2.5V X X X 39K165 3.3/2.5V X X X 39K200 3.3/2.5V X X X Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs Device
208 EQFP
28 × 28 mm 0.5-mm pitch
256 FBGA
17 × 17 mm 1.0-mm pitch 484-FBGA 23 × 23 mm 1.0-mm pitch Self-Boot Solution[4] 256-FBGA 17 × 17 mm 1.0-mm pitch 388-BGA 35 × 35 mm 1.27-mm pitch 484-FBGA 23 × 23 mm 1.0-mm pitch 676-FBGA 27 × 27 mm 1.0-mm pitch 39K30 136 174 174 39K50 136 180 218 218 39K100 136 180 302 294 302 39K165 136 356 294 386 39K200 136 368 294 428
fully synthesizable 64-bit, 66-MHz PCI core. for a block diagram of the Delta39K architecture. Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure
The LB is the basic building block of the Delta39K architecture. allocator, and 16 macrocells. well as cluster memory and channel memory feedbacks. terms in the array can be created from any of the 72 inputs. macrocells within a logic block. mance: product term steering and product term sharing. capability so that the user does not have to intervene. the timing specifications for the Delta39K devices.
64 Inputs From
144 Outputs to
Figure 3. Delta39K Logic Block Cluster Diagram
on an AND expression or an OR expression. macrocell is either registered or combinatorial. macrocell in the logic block. rising or the falling edge (see macrocell diagram in Figure 4). RESET takes priority over PRESET. Figure 4. Delta39K Macrocell
asynchronous or synchronous Single-Port RAM or ROM. in any type of sequential logic circuits (e.g., state machines). design in a macrocell or comes from an I/O pin. ROM applications, the user cannot write to memory blocks. user can choose an inverted clock. primarily with the vertical routing channel. Figure 5. Block Diagram of Cluster Memory Block
when an address collision occurs. are selected from four global clocks and two local clocks. operation is controlled by the clock and the Read enable pin. given set of data when the device is configured at power up. Figure 6. This allows the channel memory blocks to be Table 2. Arbitration Result: Address Match Signal
On each I/O pin, user-programmable-bus-hold is included. frequency modulation (see Figure 9 for details). clocks that go to every macrocell, memory block, and I/O cell. to every cluster, channel memory, and I/O block on the die. minimized while maintaining an acceptable clock delay. supported only with X1, X2, and X4 multiply options. such that this VCO operating frequency requirement is met. This is demonstrated in Table 4 (columns 1, 2, and 3). register (I/O register or a macrocell register). limited multiply, divide and phase shift options can be used. Figure 9. Block Diagram of Spread Aware PLL
used with or without an external feedback. applies to the VCO output and not to the divided output. Table 4. Valid PLL Multiply and Divide Options—without External Feedback Table 5. Valid PLL Multiply and Divide Options—With External Feedback Table 6. Recommended PLL Phase Shift Options Table 7. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 13 of 86 CompactPCI Hot Swap The CompactPCI Hot Swap specification allows the removal and insertion of cards into CompactPCI sockets without switching-off the bus. Delta39K CPLDs can be used as a CompactPCI host or target on these cards. This feature is useful in telecommunication and networking applications as it allows implementation of high availability systems, where repairs and upgrades can be done without downtime. Delta39K CPLDs are CompactPCI Hot Swap Ready per CompactPCI Hot Swap specification R2.0, with the following exception: The I/O cells do not provide bias voltage support. External resistors can be used to achieve this, per section 3.1.3.1 of the CompactPCI Hot Swap specification R2.0. A simple board level solution is provided in the application note titled “Hot-Swapping Delta39K and Quantum38K CPLDs.” Timing Model One important feature of the Delta39K family is the simplicity of its timing. All combinatorial and registered/synchronous delays are worst case and system performance is static (as shown in the AC specs section) as long as data is routed through the same horizontal and vertical channels. Figure 10 illustrates the true timing model for the 200-MHz devices. For synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate Logic Blocks within the same cluster, as well as separate Logic Blocks within different clusters. This is respectively shown as t SCS and tSCS2 in Figure 10. For combinatorial paths, any input to any output (from corner to corner on the device), incurs a worst- case delay in the 39K100 regardless of the amount of logic or which horizontal and vertical channels are used. This is the tPD shown in Figure 10. For synchronous systems, the input set- up time to the output macrocell register and the clock to output time are shown as the parameters tMCS and tMCCO shown in the Figure 10. These measurements are for any output and synchronous clock, regardless of the logic placement. The Delta39K features: no dedicated vs. I/O pin delays no penalty for using 0 – 16 product terms no added delay for steering product terms no added delay for sharing product terms no output bypass delays. The simple timing model of the Delta39K family eliminates unexpected performance penalties. Family, Package, and Density Migration in Delta39K CPLDs The Delta39K CPLDs combine dense logic, embedded mem- ory and configurable I/O standards. Further design flexibility is added by the easy migration options available between differ- ent packages and densities of Delta39K CPLD offerings. This migration flexibility makes changes or additions to designs simple even after PCB layout. It also provides the ability for experimental designs to be used on production PCBs. Please refer to the application note titled “Family, Package, and Density Migration in Delta39K CPLDs.”
both Boundary Scan and ISR operations. tions. The JTAG interface is shown in Figure 11. during debug or field upgrades do not cause board respins. consistent system performance. defined as the loading of a user’s design into the Delta39K die. Figure 10. Timing Model for 39K100 Device
uring Delta39K/Quantum38K” at http://www.cypress.com. see the ISR Programming Kit data sheet (CY3900i). mation on the availability of this option. System General, Hi-Lo) support the Delta39K family. of currently supported third party vendors. Figure 11. JTAG Interface
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 16 of 86 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature Storage Temperature Ambient Temperature with DC Voltage Applied to Outputs [6] Static Discharge Voltage Note: 6. DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV, and 36 mA with GTL+ (with 25W pull-up resistor and VTT = 1.5). 7. Input Leakage current is ±10µA for all the pins on all the Delta39K package except the following pins in Delta39K100 packages: The input leakage current spec for these pins in ±200µA 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester-ground degradation. Tested initially and after any design or process changes that may affect these parameters. Operating Range Range Ambient Temperature Junction Temperature Output Condition VCCIO VCC VCCJTAG / VCCCNFG VCCPLL VCCPRG 2.5V ± 0.2V (39KV) Same as VCCIO Same as VCC 3.3V ± 0.3V2.5V 2.5V ± 0.2V 1.8V 1.8V ± 0.15V Industrial –40°C to +85°C –40°C to +100°C 3.3V 3.3V ± 0.3V 2.5V 2.5V ± 0.2V 1.8V 1.8V ± 0.15V DC Characteristics Parameter Description Test Conditions VCCIO = 3.3VVCCIO = 2.5V VCCIO = 1.8V VDRINT Data Retention VCC Voltage (config data may be lost below this) 1.5 1.5 1.5 V VDRIO Data Retention VCCIO Voltage (config data may be lost below this) 1.2 1.2 1.2 V IIX [7] Input Leakage Current GND ≤ VI ≤ 3.6V –10 10 –10 10 –10 10 µA IOZ Output Leakage Current GND ≤ VO ≤ VCCIO –10 10 –10 10 –10 10 µA IOS [8] Output Short Circuit Current VCCIO = Max. VOUT = 0.5V –160 –160 –160 µA IBHL Input Bus Hold LOW Sustaining CurrentVCC = Min. VPIN = VIL +40 +30 +25 µA IBHH Input Bus Hold HIGH Sustaining CurrentVCC = Min. VPIN = VIH –40 –30 –25 µA IBHLO Input Bus Hold LOW Overdrive CurrentVCC = Max. +250 +200 +150 µA IBHHO Input Bus Hold HIGH Overdrive CurrentVCC = Max. –250 –200 –150 µA ICC0 Standby Current 39K30 39K50 39K100 39K165 39K200 All bins All bins –125 bin –83 bin µA Delta39K100 Package Pins 388-BGA B4, C2 484-FBGA B8, G9 676-FBGA F11, J11
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 17 of 86 Power-up Sequence Requirements Upon power-up, all the outputs remain three-stated until all the VCC pins have powered-up to the nominal voltage and the part has completed configuration. The part will not start configuration until VCC , VCCIO , VCCJTAG , VCCCNFG , VCCPLL and VCCPRG have reached nominal voltage. V CC pins can be powered up in any order. This includes VCC , VCCIO , VCCJTAG , VCCCNFG , VCCPLL and VCCPRG . A l l VCCIO s on a bank should be tied to the same potential and powered up together. A l l VCCIO s (even the unused banks) need to be powered up to at least 1.5V before configuration has completed. Maximum ramp time for all VCC s should be 0V to nominal voltage in 100 ms. Notes: 9. PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf. 10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details. The source current limit per I/O bank per Vccio pin is 165 mA. The sink current limit per I/O bank per GND pin is 230 mA. 11. See “Power-up Sequence Requirements” below for V CCIO requirement. 12. 25W resistor terminated to termination voltage of 1.5V. Capacitance Parameter Description Test Conditions Min. Max. Unit C I/O Input/Output Capacitance Vin = VCCIO @ f = 1 MHz 25°C 10 pF C CLK Clock Signal Capacitance Vin = VCCIO @ f = 1 MHz 25°C 5 12 pF C PCI PCI-compliant[9] Capacitance Vin = VCCIO @ f = 1 MHz 25°C 8 pF DC Characteristics (I/O)[10] I/O Standards VREF (V) VCCIO (V) VOH (V) V OL (V) V IH (V) V IL (V) @ IOH =V OH (min.) @ IOL = VOL LVCMOS2 –1.0 mA 2.0 1.0 mA 0.4 –2.0 mA 1.7 2.0 mA 0.7 GTL+ 1.0 [11] 36 mA[12] 0.6 V REF + 0.2 V REF – 0.2 Configuration Parameters Parameter Description Min. Unit tRECONFIG Reconfig pin LOW time before it goes HIGH 200 ns
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 18 of 86 Switching Characteristics — Parameter Descriptions Over the Operating Range[13] Parameter Description Combinatorial Mode Parameters tPD Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster tEA Global control to output enable tER Global control to output disable tPRR Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in tPRO Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels tPRW Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with Synchronous Clocking Parameters tMCS Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock tMCH Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock tMCCO Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in tIOS Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock tIOH Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock tIOCO Clock to output of an I/O cell register to the output pin associated with that register tSCS Macrocell clock to macrocell clock through array logic within the same cluster tSCS2 Macrocell clock to macrocell clock through array logic in different clusters on the same channel tICS I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with tOCS Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the macrocell is in tCHZ Clock to output disable (high-impedance) tCLZ Clock to output enable (low-impedance) fMAX Maximum frequency with internal feedback—within the same cluster fMAX2 Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or vertical channel Product Term Clock tMCSPT Set-up time for macrocell used as input register, from input to product term clock tMCHPT Hold time of macrocell used as an input register tMCCOPT Product term clock to output delay from input pin tSCS2PT Register to register delay through array logic in different clusters on the same channel using a product term clock Channel Interconnect Parameters tCHSW Adder for a signal to switch from a horizontal to vertical channel and vice-versa tCL2CL Cluster-to-cluster delay adder (through channels and channel PIM) Miscellaneous Delays tCPLD Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter can be added to the t PD and tSCS parameters for each extra pass through the AND/OR array required by a given signal path tMCCD Adder for carry chain logic per macrocell tIOD Delay from the input of the output buffer to the I/O pin tIOIN Delay from the I/O pin to the input of the channel buffer Note: 13. Add tCHSW to signals making a horizontal to vertical channel switch or vice-versa.
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 19 of 86 tCKIN Delay from the clock pin to the input of the clock driver tIOREGPIN Delay from the I/O pin to the input of the I/O register PLL Parameters tMCCJ Maximum cycle to cycle jitter time tDWSA PLL zero phase delay with clock tree deskewed tDWOSA PLL zero phase delay without clock tree deskewed tLOCK Lock time for the PLL tINDUTY Input duty cycle fPLLI Input frequency of the PLL fPLLO Output frequency of the PLL fPLLVCO PLL VCO frequency of operation PSAPLLI Percentage modulation allowed (spread awareness) on the PLL input clock fMPLLI Frequency of modulation allowed on PLL input clock. This specifies how fast the fPLLI sweeps between fPLLI* (1–PSAPLLI/100) and fPLLI* (1+ PSAPLLI/100) JTAG Parameters tJCKH TCLK HIGH time tJCKL TCLK LOW time tJCP TCLK clock period tJSU JTAG port set-up time (TDI/TMS inputs) tJH JTAG port hold time (TDI/TMS inputs) tJCO JTAG port clock to output time (TDO) tJXZ JTAG port valid output to high impedance (TDO) tJZX JTAG port high impedance to valid output (TDO) Switching Characteristics — Parameter Descriptions Over the Operating Range[13] (continued) Parameter Description Cluster Memory Timing Parameter Descriptions Over the Operating Range Parameter Description Asynchronous Mode Parameters tCLMAA Cluster memory access time. Delay from address change to Read data out tCLMPWE Write Enable pulse width tCLMSA Address set-up to the beginning of Write Enable with both signals from the same I/O block tCLMHA Address hold after the end of Write Enable with both signals from the same I/O block tCLMSD Data set-up to the end of Write Enable tCLMHD Data hold after the end of Write Enable Synchronous Mode Parameters tCLMCYC1 Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory back to a macrocell register in the same cluster) tCLMCYC2 Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the memory to cluster memory output register) tCLMS Address, data, and WE set-up time of pin inputs, relative to a global clock tCLMH Address, data, and WE hold time of pin inputs, relative to a global clock tCLMDV1 Global clock to data valid on output pins for flow through data tCLMDV2 Global clock to data valid on output pins for pipelined data tCLMMACS1 Cluster memory input clock to macrocell clock in the same cluster tCLMMACS2 Cluster memory output clock to macrocell clock in the same cluster tMACCLMS1 Macrocell clock to cluster memory input clock in the same cluster
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 20 of 86 tMACCLMS2 Macrocell clock to cluster memory output clock in the same cluster Internal Parameters tCLMCLAA Asynchronous cluster memory access time from input of cluster memory to output of cluster memory Channel Memory Timing Parameter Descriptions Over the Operating Range Parameter Description Dual Port Asynchronous Mode Parameters tCHMAA Channel memory access time. Delay from address change to Read data out tCHMPWE Write enable pulse width tCHMSA Address set-up to the beginning of Write enable with both signals from the same I/O block tCHMHA Address hold after the end of Write enable with both signals from the same I/O block tCHMSD Data set-up to the end of Write enable tCHMHD Data hold after the end of Write enable tCHMBA Channel memory asynchronous dual port address match (busy access time) Dual Port Synchronous Mode Parameters tCHMCYC1 Clock cycle time for flow through Read and Write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) tCHMCYC2 Clock cycle time for pipelined Read and Write operations (from channel memory input register through the memory to channel memory output register) tCHMS Address, data, and WE set-up time of pin inputs, relative to a global clock tCHMH Address, data, and WE hold time of pin inputs, relative to a global clock tCHMDV1 Global clock to data valid on output pins for flow through data tCHMDV2 Global clock to data valid on output pins for pipelined data. tCHMBDV Channel memory synchronous dual-port address match (busy, clock to data valid) tCHMMACS1 Channel memory input clock to macrocell clock in the same cluster tCHMMACS2 Channel memory output clock to macrocell clock in the same cluster tMACCHMS1 Macrocell clock to channel memory input clock in the same cluster tMACCHMS2 Macrocell clock to channel memory output clock in the same cluster Synchronous FIFO Data Parameters t CHMCLK Read and Write minimum clock cycle time tCHMFS Data, Read enable, and Write enable set-up time relative to pin inputs tCHMFH Data, Read enable, and Write enable hold time relative to pin inputs tCHMFRDV Data access time to output pins from rising edge of Read clock (Read clock to data valid) tCHMMACS Channel memory FIFO Read clock to macrocell clock for Read data tMACCHMS Macrocell clock to channel memory FIFO Write clock for Write data Synchronous FIFO Flag Parameters tCHMFO Read or Write clock to respective flag output at output pins tCHMMACF Read or Write clock to macrocell clock with FIFO flag tCHMFRS Master Reset Pulse Width tCHMFRSR Master Reset Recovery Time tCHMFRSF Master Reset to Flag and Data Output Time tCHMSKEW1 Read/Write Clock Skew Time for Full Flag tCHMSKEW2 Read/Write Clock Skew Time for Empty Flag tCHMSKEW3 Read/Write Clock Skew Time for Boundary Flags Cluster Memory Timing Parameter Descriptions Over the Operating Range (continued) Parameter Description
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 21 of 86 Internal Parameters tCHMCHAA Asynchronous channel memory access time from input of channel memory to output of channel memory Channel Memory Timing Parameter Descriptions Over the Operating Range (continued) Parameter Description Switching Characteristics — Parameter Values Over the Operating Range Parameter 233 200 181 125 83 Combinatorial Mode Parameters tPD 7.2 7.5 8.5 10 15 ns tEA 4.5 5.0 5.6 9.0 10 ns tER 4.5 5.0 5.3 9.0 10 ns tPRR 6.0 6.0 6.0 8.0 10 ns tPRO 9.5 10 10.5 13 15 ns Synchronous Clocking Parameters tMCH 00 0 0 0 ns tMCCO 5.8 6.0 7.0 10 12 ns tSCS2 4.3 4.5 5.5 8.0 12 ns tICS 4.5 5.0 5.5 8.0 12 ns tOCS 4.5 5.0 5.5 8.0 12 ns fMAX 294 286 278 156 104 MHz fMAX2 233 222 181 125 83 MHz Product Term Clocking Parameters Channel Interconnect Parameters Miscellaneous Parameters PLL Parameters tMCCJ –150 150 –150 150 –150 150 –180 180 –200 200 ps tDWOSA –150 150 –150 150 –150 150 –180 180 –200 200 ps tLOCK 250 250 250 250 250 ms
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 22 of 86 Input and Output Standard Timing Delay Adjustments All the timing specifications in this data sheet are specified based on LVCMOS compliant inputs and outputs (fast slew rates).[15] Apply following adjustments if the inputs and outputs are configured to operate at other standards. tINDUTY 40 60 40 60 40 60 40 60 40 60 % fPLLO fPLLVCO 100 266 100 266 100 266 100 266 100 266 MHz fMPLLI 50 50 50 50 50 KHz JTAG Parameters tJCKH 25 25 25 25 25 ns tJCKL 25 25 25 25 25 ns tJCP 50 50 50 50 50 ns tJSU 10 10 10 10 10 ns tJH 10 10 10 10 10 ns tJCO 20 20 20 20 20 ns tJXZ 20 20 20 20 20 ns tJZX 20 20 20 20 20 ns Switching Characteristics — Parameter Values Over the Operating Range (continued) Parameter 233 200 181 125 83 I/O Standard Output Delay Adjustments Input Delay AdjustmentsFast Slew Rate Slow Slew Rate (additional delay to fast slew rate) tIOD tEA tER tIODSLOW tEASLOW tERSLOW tIOIN tCKIN tIOREGPIN LVTTL – 2 mA 2.75 0 0 2.6 2.0 2.0 0 0 0 LVTTL – 4 mA 1.8 0 0 2.5 2.0 2.0 0 0 0 LVTTL – 6 mA 1.8 0 0 2.5 2.0 2.0 0 0 0 LVTTL – 8 mA 1.2 0 0 2.4 2.0 2.0 0 0 0 LVTTL – 12 mA 0.6 0 0 2.3 2.0 2.0 0 0 0 LVTTL – 16 mA 0.16 0 0 2.0 2.0 2.0 0 0 0 LVTTL – 24 mA 0 0 0 1.6 2.0 2.0 0 0 0 LVCMOS 0 0 0 2.0 2.0 2.0 0 0 0 GTL+ 0.02 Notes: 14. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation. 15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results. 16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 23 of 86 I/O Standard Output Delay Adjustments Input Delay AdjustmentsFast Slew Rate Slow Slew Rate (additional delay to fast slew rate) tIOD tEA tER tIODSLOW tEASLOW tERSLOW tIOIN tCKIN tIOREGPIN Cluster Memory Timing Parameter Values Over the Operating Range Parameter 233 200 181 125 83 Asynchronous Mode Parameters tCLMAA 10.2 11 12 17 20 ns tCLMPWE 5.5 6 6.5 10 12 ns tCLMSD 5.5 6.0 6.5 10 12 ns Synchronous Mode Parameters tCLMCYC1 9.5 10 10.5 15 20 ns tCLMH 000 0 0 ns tCLMDV1 10 11 12 17 20 ns tCLMDV2 7.0 7.5 8.0 10 15 ns tCLMMACS1 7.7 8.0 8.5 12 15 ns tCLMMACS2 4.5 5.0 5.5 8.0 10 ns tMACCLMS2 6.0 6.5 7.0 10 12 ns Internal Parameters tCLMCLAA 66 6 . 5 10 12 ns Channel Memory Timing Parameter Values Over the Operating Range Parameter 233 200 181 125 83 Dual-Port Asynchronous Mode Parameters tCHMAA 10 11 12 17 20 ns tCHMPWE 5.5 6.0 6.5 10 12 ns tCHMSD 5.5 6.0 6.5 10 12 ns
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 24 of 86 Dual-Port Synchronous Mode Parameters tCHMCYC1 9.5 10 10 15 20 ns tCHMH 000 0 0 ns tCHMDV1 10 11 12 17 20 ns tCHMDV2 7.0 7.5 8.0 10 15 ns tCHMMACS2 4.8 5.0 5.5 8.0 10 ns Synchronous FIFO Data Parameters tCHMFH 000 0 0 ns Synchronous FIFO Flag Parameters tCHMFO 10.5 11 11.5 15 20 ns tCHMMACF 8 . 599 . 5 13 17 ns tCHMFRS 4.5 5.0 5.5 8.0 10 ns Internal Parameters Channel Memory Timing Parameter Values Over the Operating Range (continued) Switching Waveforms tPD INPUT COMBINATORIAL OUTPUT Combinatorial Output
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 25 of 86 Switching Waveforms (continued) Registered Output with Synchronous Clocking (Macrocell) tMCS INPUT SYNCHRONOUS tMCCO REGISTERED OUTPUT tMCH CLOCK Registered Input in I/O Cell tIOS DATA INPUT INPUT REGISTER CLOCK tIOCO REGISTERED OUTPUT tIOH Clock to Clock INPUT REGISTER CLOCK MACROCELL REGISTER CLOCK tSCStICS PT Clock to PT Clock DATA PT CLOCK tSCS2PTtMCSPT INPUT
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 26 of 86 Switching Waveforms (continued) Asynchronous Reset/Preset INPUT tPRO REGISTERED OUTPUT CLOCK tPRR tPRW RESET/PRESET Output Enable/Disable GLOBAL CONTROL tER OUTPUTS tEA INPUT
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 27 of 86 Switching Waveforms (continued) Cluster Memory Asynchronous Timing ADDRESS (AT READWRITEREAD WRITE ENABLE tCLMPWE INPUT OUTPUT tCLMCLAA tCLMCLAA Cluster Memory Asynchronous Timing 2 ADDRESS (AT THE READWRITEREAD WRITE ENABLE tCLMPWE INPUT tCLMSD tCLMHD OUTPUT tCLMSA tCLMHA tCLMAAtCLMAA THE CLUSTER INPUT) I/O PIN)
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 28 of 86 Switching Waveforms (continued) Cluster Memory Synchronous Flow-Through Timing GLOBAL ADDRESS WRITE ENABLE REGISTERED INPUTREGISTERED OUTPUT tCLMS tCLMStCLMS tCLMH tCLMH tCLMH READWRITEREAD tCLMDV1tCLMDV1 tCLMDV1 CLOCK tCLMCYC1 Cluster Memory Internal Clocking MACROCELL CLUSTER MEMORY INPUT CLOCK CLUSTER MEMORY OUTPUT CLOCK tCLMMACS2 tMACCLMS2 tCLMMACS1 tMACCLMS1 INPUT CLOCK
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 29 of 86 Switching Waveforms (continued) Cluster Memory Output Register Timing (Asynchronous Inputs) ADDRESS tCLMCYC2 tCLMDV2 WRITE ENABLE INPUT GLOBAL CLOCK (OUTPUT REGISTER) REGISTERED OUTPUT Cluster Memory Output Register Timing (Synchronous Inputs) ADDRESS tCLMDV2 WRITE ENABLE GLOBAL CLOCK (OUTPUT REGISTER) REGISTERED OUTPUT (INPUT REGISTER) GLOBAL CLOCK tCLMCYC2 tCLMS tCLMH INPUT
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 30 of 86 Switching Waveforms (continued) Channel Memory DP Asynchronous Timing WRITE tCHMPWE tCHMSA tCHMHA tCHMAA tCHMHD ADDRESS DATA OUTPUT tCHMAA An-1 An An+1 An+2 D n D n–1 D n D n+1 tCHMSD ENABLE INPUT Channel Memory Internal Clocking CLOCK INPUT CLOCK OUTPUT CLOCK tCHMMACS1 tMACCHMS2 tCHMMACS2 tMACCHMS1 MACROCELL INPUT CHANNEL MEMORY CHANNEL MEMORY
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 31 of 86 Switching Waveforms (continued) Channel Memory Internal Clocking 2 MACROCELL INPUT CLOCK FIFO READ CLOCK FIFO WRITE CLOCKFIFO READ OR WRITE CLOCK tCHMMACS tCHMMACF tMACCHMS Channel Memory DP SRAM Flow-Through R/W Timing CLOCK tCHMCYC1 tCHMHtCHMS WRITE D n+1 tCHMS tCHMH OUTPUT An+1 An+2 An+3AnADDRESS tCHMDV1 tCHMDV1 tCHMDV1 D n–1 D n+3D n–1 An–1 DATA tCHMDV1 D n+3D n+2D n+1D n ENABLE INPUT
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 32 of 86 Switching Waveforms (continued) Channel Memory DP SRAM Pipeline R/W Timing An+1 An+2 D n+1 tCHMCYC2 tCHMH tCHMS tCHMS tCHMH An tCHMS tCHMH An+3An–1 D n+3D n–1 D n–1 tCHMDV2tCHMDV2 D n D n+1 D n+2 tCHMDV2 CLOCK WRITE OUTPUT ADDRESS DATA ENABLE INPUT Dual-Port Asynchronous Address Match Busy Signal ADDRESS A An An–1 An An+1 ADDRESS tCHMBA tCHMBA Bn ADDRESS B MATCH
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 33 of 86 Switching Waveforms (continued) CLOCK An An Bn–1 Bn+1 tCHMBDV An–1 tCHMBDV tCHMS tCHMS ADDRESS B ADDRESS Dual-Port Synchronous Address Match Busy Signal ADDRESS A MATCH
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 34 of 86 Switching Waveforms (continued) Channel Memory Synchronous FIFO Empty/Write Timing WRITE ENABLE tCHMCLK tCHMFS tCHMFH D n+1REGISTERED INPUT EMPTY FLAG PORT A CLOCK READ ENABLE tCHMSKEW2 tCHMFO tCHMFO tCHMFRDV PORT B CLOCK RE REGISTERED OUTPUT (Active LOW)
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 35 of 86 Switching Waveforms (continued) Channel Memory Synchronous FIFO Full/Read Timing PORT A CLOCK READ ENABLE tCHMCLK tCHMFS REGISTERED OUTPUT FULL FLAG PORT B CLOCK tCHMFH tCHMSKEW1 tCHMFO tCHMFO WRITE ENABLE tCHMS tCHMH tCHMFRDV REGISTERED INPUT (Active LOW)
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 36 of 86 Switching Waveforms (continued) Channel Memory Synchronous FIFO Programmable Flag Timing tCHMCLK tCHMFS tCHMFH PORT B CLOCK PROGRAMMABLE WRITE ENABLE ALMOST EMPTY FLAG PORT A CLOCK tCHMSKEW3 tCHMFO tCHMFO READ ENABLE (active LOW) tCHMFS tCHMFH tCHMCLK PORT B CLOCK PROGRAMMABLE WRITE ENABLE ALMOST FULL FLAG PORT A CLOCK tCHMSKEW3 tCHMFO tCHMFO READ ENABLE (Active LOW)
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 37 of 86 Switching Waveforms (continued) Channel Memory Synchronous FIFO Master Reset Timing MASTER RESET INPUT READ ENABLE / WRITE ENABLE EMPTY/FULL tCHMFRS tCHMFRSR tCHMFRSF tCHMFRSF tCHMFRSF HALF-FULL/ REGISTERED OUTPUT FLAGS PROGRAMMABLE FLAGS ALMOST FULL PROGRAMMABLE ALMOST EMPTY Pin Count 208 = 208 Leads 256 = 256 Balls 388 = 388 Balls 484 = 484 Balls 676 = 676 Balls C Y 3 9 1 0 0 V 6 7 6 - 2 0 0 M B C C ypress Semiconductor ID Family Type 39 = Delta39K Family G ate Density 30=30k Usable Gates 165 = 165k Usable Gates 50=50k Usable Gates 200 = 200k Usable Gates 100=100k Usable Gates Speed 233 = 233 MHz 125 = 125 MHz 200 = 200 MHz 83 = 83 MHz 181 = 181 MHz Package Type N = Plastic Quad Flat Pack (PQFP) NT = Thermally Enhanced Quad Flat Pack (EQFP) BG = Ball Grid Array (BGA) BB = Fine-pitch Ball Grid Array (FBGA) 1.0-mm Lead Pitch MG = Self-Boot Solution -- Ball Grid Array MB = Self-Boot Solution -- Fine Pitch Ball Grid Array 1.0-mm Lead Pitch Operating Conditions Commercial 0°C to +70°C Industrial --40°C to +85°C O perating Reference Voltage V = 3.3V or 2.5V Supply Voltage Z = 1.8V Supply Voltage
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 38 of 86 Delta39K Part Numbers (Ordering Information) Device Speed (MHz) Ordering Code Package Name Package Type Self-Boot Solution Operating Range 39K30 233 CY39030V208-233NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial CY39030V256-233BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39030V256-233MBC MB256 256-Lead Fine Pitch Ball Grid Array ÷
125 CY39030V208-125NTC NT208 208-Lead Enhanced Quad Flat Pack
CY39030V256-125BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39030V256-125MBC MB256 256-Lead Fine Pitch Ball Grid Array ÷ CY39030V208-125NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39030V256-125BBI BB256 256-Lead Fine Pitch Ball Grid Array
83 CY39030V208-83NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial
CY39030V256-83BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39030V256-83MBC MB256 256-Lead Fine Pitch Ball Grid Array ÷ CY39030V208-83NTI NT208 208-Lead Plastic Quad Flat Pack Industrial CY39030V256-83BBI BB256 256-Lead Fine Pitch Ball Grid Array 39K50 233 CY39050V208-233NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial CY39050V256-233BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39050V388-233MGC MG388 388-Lead Ball Grid Array ÷ CY39050V484-233MBC MB484 484-Lead Fine Pitch Ball Grid Array ÷
125 CY39050V208-125NTC NT208 208-Lead Enhanced Quad Flat Pack
CY39050V256-125BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39050V388-125MGC MG388 388-Lead Pitch Ball Grid Array ÷ CY39050V484-125MBC MB484 484-Lead Fine Pitch Ball Grid Array ÷ 39K50 125 CY39050V208-125NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39050V256-125BBI BB256 256-Lead Fine Pitch Ball Grid Array
83 CY39050V208-83NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial
CY39050V256-83BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39050V388-83MGC MG388 388-Lead Ball Grid Array ÷ CY39050V484-83MBC MB484 484-Lead Fine Pitch Ball Grid Array ÷ CY39050V208-83NTI NT208 208-Lead Plastic Quad Flat Pack Industrial CY39050V256-83BBI BB256 256-Lead Fine Pitch Ball Grid Array 39K100 200 CY39100V208B-200NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial CY39100V256B-200BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39100V484B-200BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39100V388B-200MGC MG388 388-Lead Ball Grid Array ÷ CY39100V676B-200MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 39 of 86 39K100 125 CY39100V208B-125NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial CY39100V256B-125BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39100V484B-125BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39100V388B-125MGC MG388 388-Lead Ball Grid Array ÷ CY39100V676B-125MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷ CY39100V208B-125NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39100V256B-125BBI BB256 256-Lead Fine Pitch Ball Grid Array CY39100V484B-125BBI BB484 484-Lead Fine Pitch Ball Grid Array
83 CY39100V208B-83NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial
CY39100V256B-83BBC BB256 256-Lead Fine Pitch Ball Grid Array CY39100V484B-83BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39100V388B-83MGC MG388 388-Lead Ball Grid Array ÷ CY39100V676B-83MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷ CY39100V208B-83NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39100V256B-83BBI BB256 256-Lead Fine Pitch Ball Grid Array CY39100V484B-83BBI BB484 484-Lead Fine Pitch Ball Grid Array 39K165 181 CY39165V208-181NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial CY39165V484-181BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39165V388-181MGC MG388 388-Lead Ball Grid Array ÷ CY39165V676-181MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷
125 CY39165V208-125NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial
CY39165V484-125BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39165V388-125MGC MG388 388-Lead Ball Grid Array ÷ CY39165V676-125MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷ CY39165V208-125NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39165V484-125BBI BB484 484-Lead Fine Pitch Ball Grid Array
83 CY39165V208-83NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial
CY39165V484-83BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39165V388-83MGC MG388 388-Lead Ball Grid Array ÷ CY39165V676-83MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷ CY39165V208-83NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39165V484-83BBI BB484 484-Lead Fine Pitch Ball Grid Array Delta39K Part Numbers (Ordering Information) (continued) Device Speed (MHz) Ordering Code Package Name Package Type Self-Boot Solution Operating Range
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 40 of 86 Note: 17. Refer to the data sheets at www.atmel.com for detailed architectural and timing information. 39K200 181 CY39200V208-181NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial CY39200V484-181BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39200V388-181MGC MG388 388-Lead Ball Grid Array ÷ CY39200V676-181MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷
125 CY39200V208-125NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial
CY39200V484-125BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39200V388-125MGC MG388 388-Lead Ball Grid Array ÷ CY39200V676-125MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷ CY39200V208-125NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39200V484-125BBI BB484 484-Lead Fine Pitch Ball Grid Array
83 CY39200V208-83NTC NT208 208-Lead Enhanced Quad Flat Pack Commercial
CY39200V484-83BBC BB484 484-Lead Fine Pitch Ball Grid Array CY39200V388-83MGC MG388 388-Lead Ball Grid Array ÷ CY39200V676-83MBC MB676 676-Lead Fine Pitch Ball Grid Array ÷ CY39200V208-83NTI NT208 208-Lead Enhanced Quad Flat Pack Industrial CY39200V484-83BBI BB484 484-Lead Fine Pitch Ball Grid Array Delta39K Part Numbers (Ordering Information) (continued) Device Speed (MHz) Ordering Code Package Name Package Type Self-Boot Solution Operating Range CPLD Boot EEPROM [17] Part Numbers (Ordering Information) Device Speed (MHz) Ordering Code Package Name Package Type Operating Range
2 Mbit 15 AT17LV002-10JC 20J 20-Lead Plastic Leaded Chip Carrier Commercial
10 AT17LV002-10JC 20J 20-Lead Plastic Leaded Chip Carrier Industrial
1 Mbit 15 AT17LV010-10JC 20J 20-Lead Plastic Leaded Chip Carrier Commercial
10 AT17LV010-10JI 20J 20-Lead Plastic Leaded Chip Carrier Industrial
512 Kbit 15 AT17LV512-10JC 20J 20-Lead Plastic Leaded Chip Carrier Commercial
10 AT17LV512-10JI 20J 20-Lead Plastic Leaded Chip Carrier Industrial
Recommended ATMEL CPLD Boot EEPROM for corresponding Delta39K CPLDs CPLD Device Recommended boot EEPROM 39K30 AT17LV512 39K50 AT17LV512 39K100 AT17LV010 39K165 AT17LV002 39K200 AT17LV002
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 41 of 86 Package Diagrams 51-85069-*B 208-Lead Enhanced Quad Flat Pack (EQFP) NT208
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 42 of 86 Package Diagrams (continued) 388-Lead Ball Grid Array MG388 51-85103-*C
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 43 of 86 Package Diagrams (continued) BOTTOM VIEWTOP VIEW 1 0 98765432 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø 0 . 2 5MCAB Ø 0 . 0 5MC Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K) 0.25 C 0.70±0.05 C SEATING PLANE 0.15 C 16 15 14 13 12 11 T R P M N L N T R P M L K J F G H E D A C B 161513 141210 11928 765431 A B Ø0.50±0.05(256X)-ALL OTHER DEVICES A1 0.36 0.56 A 1.40 MAX. 1.60 MAX. REFERENCE JEDEC MO-192 15.00 1.00 0.35 A 17.00±0.10 7.50 7.50 15.00 17.00±0.10 1.00 -0.05 +0.10 256-Ball FBGA (17 x 17 mm) BB256 51-85108-*D
Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 44 of 86 Package Diagrams (continued) A 0.10(4X) Ø0.60±0.10(484X) Ø 0 . 2 5MCAB Ø0.05 M C A1 CORNER B C D E F G H J K L M N P R T U V W Y AA AB 2120 19 18 17 16 15 14 13 12 111 0987654321 21.00 Y U V T R M P N L K G J H F E B D C A AA AB W 2215 19 20 2117 181612 141310 11957 864231 1.00 21.00 1.00 A1 CORNER 0.25 C SEATING PLANE C 0.20 C TOP VIEW BOTTOM VIEW 23.00±0.10 23.00±0.10 0.56 0.50±0.10
1.90 MAX
A B 10.50 10.50 0.70±0.05 484-ball FBGA (23 mm x 23 mm x 1.6 mm) BB484 51-85124-*D
Table 8. Pin Definition Table
Table 9. Mode Select (MSEL) Pin Connectivity Table Table 10. I/O Banks for Global Clock and Global Control Table 11. 208 EQFP/PQFP Pin Table
1 GCTL0 GCTL0 GCTL0 GCTL0 GCTL0
2 GND GND GND GND GND
3 GCLK0 GCLK0 GCLK0 GCLK0 GCLK0
4 GND GND GND GND GND
5 IO0 IO0 IO0 IO0 IO0
6 IO0 IO0 IO0 IO0 IO0
7 IO0 IO0 IO0 IO0 IO0
9 IO0 IO0 IO0 IO0 IO0
10 IO0 IO0 IO0 IO0 IO0
11 V CCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0
12 IO0 IO0 IO0 IO0 IO0
13 IO0 IO0 IO0 IO0 IO0
14 IO0 IO0 IO0 IO0 IO0
15 IO0 IO0 IO0 IO0 IO0
16 IO/V
17 IO0 IO0 IO0 IO0 IO0
18 IO0 IO0 IO0 IO0 IO0
19 IO0 IO0 IO0 IO0 IO0
23 V CC VCC VCC VCC VCC
24 GND GND GND GND GND
25 NC NC V CC VCC VCC
26 NC NC GND GND GND
28 V CCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0
29 V CCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1
33 IO1 IO1 IO1 IO1 IO1
34 IO1 IO1 IO1 IO1 IO1
36 GND GND GND GND GND
37 IO1 IO1 IO1 IO1 IO1
38 IO1 IO1 IO1 IO1 IO1
39 IO1 IO1 IO1 IO1 IO1
40 IO/V
41 IO1 IO1 IO1 IO1 IO1
42 IO1 IO1 IO1 IO1 IO1
43 IO1 IO1 IO1 IO1 IO1
44 IO1 IO1 IO1 IO1 IO1
46 V CCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1
47 GND GND GND GND GND
48 IO1 IO1 IO1 IO1 IO1
49 IO/V
50 IO1 IO1 IO1 IO1 IO1
51 IO1 IO1 IO1 IO1 IO1
53 Data Data Data Data Data
54 Config_Done Config_Done Config_Done Config_Done Config_Done
55 Reset Reset Reset Reset Reset
Table 11. 208 EQFP/PQFP Pin Table (continued)
56 Reconfig Reconfig Reconfig Reconfig Reconfig
57 CCE CCE CCE CCE CCE
58 CCLK CCLK CCLK CCLK CCLK
59 V CCCNFG VCCCNFG VCCCNFG VCCCNFG VCCCNFG
60 MSEL MSEL MSEL MSEL MSEL
61 IO2 IO2 IO2 IO2 IO2
62 IO2 IO2 IO2 IO2 IO2
63 IO2 IO2 IO2 IO2 IO2
64 IO/V
65 IO2 IO2 IO2 IO2 IO2
66 V CCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2
67 GND GND GND GND GND
68 IO2 IO2 IO2 IO2 IO2
69 IO2 IO2 IO2 IO2 IO2
70 IO2 IO2 IO2 IO2 IO2
71 IO2 IO2 IO2 IO2 IO2
72 IO/V
73 GND GND GND GND GND
75 V CC VCC VCC VCC VCC
76 GND GND GND GND GND
77 NC NC V
78 NC NC GND GND GND
79 IO2 IO2 IO2 IO2 IO2
80 IO/V REF2 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF2
84 V CCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2
85 V CCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3
89 V CCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3
90 GND GND GND GND GND
91 IO3 IO3 IO3 IO3 IO3
92 IO3 IO3 IO3 IO3 IO3
93 IO3 IO3 IO3 IO3 IO3
94 IO3 IO3 IO3 IO3 IO3
95 IO3 IO3 IO3 IO3 IO3
96 IO/V
97 IO3 IO3 IO3 IO3 IO3
99 IO3 IO3 IO3 IO3 IO3
100 GND GND GND GND GND
101 IO3 IO3 IO3 IO3 IO3
102 IO3 IO3 IO3 IO3 IO3
103 IO3 IO3 IO3 IO3 IO3
104 IO/V
105 IO4 IO4 IO4 IO4 IO4
106 IO4 IO4 IO4 IO4 IO4
107 IO4 IO4 IO4 IO4 IO4
108 IO/V
109 IO4 IO4 IO4 IO4 IO4
110 IO4 IO4 IO4 IO4 IO4
111 V CCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4
112 GND GND GND GND GND
113 IO4 IO4 IO4 IO4 IO4
114 V CCPRG VCCPRG VCCPRG VCCPRG VCCPRG
115 IO4 IO4 IO4 IO4 IO4
116 IO/V REF4 IO/VREF4 IO/VREF4 IO/VREF4 IO/VREF4
117 IO4 IO4 IO4 IO4 IO4
118 IO4 IO4 IO4 IO4 IO4
119 IO4 IO4 IO4 IO4 IO4
120 IO4 IO4 IO4 IO4 IO4
121 IO4 IO4 IO4 IO4 IO4
124 V CCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4
125 GND GND GND GND GND
127 V CC VCC VCC VCC VCC
128 GND GND GND GND GND
129 NC NC V CC VCC VCC
130 NC NC GND GND GND
131 V CCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4
132 V CCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5
136 IO5 IO5 IO5 IO5 IO5
137 IO5 IO5 IO5 IO5 IO5
138 V CCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5
139 IO5 IO5 IO5 IO5 IO5
140 IO5 IO5 IO5 IO5 IO5
141 IO5 IO5 IO5 IO5 IO5
142 IO/V REF5 IO/VREF5 IO/VREF5 IO/VREF5 IO/VREF5
143 IO5 IO5 IO5 IO5 IO5
144 IO5 IO5 IO5 IO5 IO5
145 IO5 IO5 IO5 IO5 IO5
146 IO5 IO5 IO5 IO5 IO5
147 IO5 IO5 IO5 IO5 IO5
149 IO/V REF5 IO/VREF5 IO/VREF5 IO/VREF5 IO/VREF5
150 IO5 IO5 IO5 IO5 IO5
151 IO5 IO5 IO5 IO5 IO5
152 GND GND GND GND GND
153 GCLK1 GCLK1 GCLK1 GCLK1 GCLK1
154 GND GND GND GND GND
155 GCTL1 GCTL1 GCTL1 GCTL1 GCTL1
156 TDO TDO TDO TDO TDO
157 TCLK TCLK TCLK TCLK TCLK
158 TDI TDI TDI TDI TDI
160 GCLK2 GCLK2 GCLK2 GCLK2 GCLK2
161 GND GND GND GND GND
162 TMS TMS TMS TMS TMS
163 GCTL2 GCTL2 GCTL2 GCTL2 GCTL2
164 IO6 IO6 IO6 IO6 IO6
165 IO6 IO6 IO6 IO6 IO6
166 IO6 IO6 IO6 IO6 IO6
167 IO/V
168 IO6 IO6 IO6 IO6 IO6
169 V CCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6
170 IO6 IO6 IO6 IO6 IO6
171 IO6 IO6 IO6 IO6 IO6
172 IO6 IO6 IO6 IO6 IO6
173 IO/V
174 IO6 IO6 IO6 IO6 IO6
175 IO6 IO6 IO6 IO6 IO6
176 IO6 IO6 IO6 IO6 IO6
177 GND GND GND GND GND
179 V CCPLL VCCPLL VCCPLL VCCPLL VCCPLL
180 GND GND GND GND GND
182 GND GND GND GND GND
186 V CCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6
187 V CCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7
191 V CCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7
192 IO7 IO7 IO7 IO7 IO7
193 IO7 IO7 IO7 IO7 IO7
194 IO7 IO7 IO7 IO7 IO7
195 IO7 IO7 IO7 IO7 IO7
196 IO/V
197 IO7 IO7 IO7 IO7 IO7
198 IO7 IO7 IO7 IO7 IO7
199 V CCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7
200 IO7 IO7 IO7 IO7 IO7
201 IO/V REF7 IO/VREF7 IO/VREF7 IO/VREF7 IO/VREF7
202 IO7 IO7 IO7 IO7 IO7
203 IO7 IO7 IO7 IO7 IO7
204 IO7 IO7 IO7 IO7 IO7
205 GND GND GND GND GND
206 GCLK3 GCLK3 GCLK3 GCLK3 GCLK3
207 GND GND GND GND GND
208 GCTL3 GCTL3 GCTL3 GCTL3 GCTL3
Table 12. 388 BGA Pin Table
- Capacitance on these I/O pins meets the PCI spec (rev. 2.2), which requires IDSEL pin in a PCI design to have capacitance less than or equal to 8 pf. In the
document titled “Delta39K CPLD Family data sheet”, this spec is defined as CPCI. All other I/O pins have a capacitance less than or equal to 10 pf.
Table 12. 388 BGA Pin Table (continued)
Table 13. 256 FBGA Pin Table
Table 13. 256 FBGA Pin Table (continued)
Table 14. 484 FBGA Pin Table
Table 14. 484 FBGA Pin Table (continued)
- These I/Os have a slightly higher tPD (propagation delay) than the rest of the pins. The use of these pins on the same packages of different densities or the
packages, the timing-driven routing of Warp 6.2 and later versions will ensure these pins are avoided when routing critical signal.
Table 15. 676 FBGA Pin Table Table 15. 676 FBGA Pin Table (continued)
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Delta39K™ ISR™ CPLD Fami ly Document #: 38-03039 Rev. *H Page 86 of 86 Document History Page Document Title: Delta39K™ ISR™ CPLD Family CPLDs at FPGA Densities™ Document Number: 38-03039 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106503 05/30/01 SZV Change from Spec #: 38-00830 to 38-03039 *A 107625 07/11/01 RN Deleted 39K15 device and the associated -250-MHz bin specs Deleted 144FBGA package and associated part numbers Changed ESD spec from “MIL-STD-883” to “JEDEC EIA/JESD22-A114-A” Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz” Changed the part ordering information accordingly Updated the -233-MHz timing specs to match modified timing specs achieved by design (main affected params: t PD , tMCCO , tIOS, tSCS , tSCS2 , fMAX2 , tCLMAA , tCLMCYC2 , tCHMCYC2 , tCHMCLK ) Updated I/O standard Timing Delay Specs and changed the default I/O standard from 3.3V PCI to LVCMOS Added paragraph about Delta39K being CompactPCI hot swap Ready Added X8 mode in the PLL description Added Standby ICC spec Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead of CY3LV020 *B 109681 11/16/01 RN Updated Delta39K family offering Modified PLL timing parameters t DWSA , tDWOSA , tMCCJ , and tLOCK . Added tINDUTY parameter Deleted exception to CompactPCI Hot Swap compliance regarding “PCI buffers....” Added reference to app note “Hot Socketing Delta39K” Revised CompactPCI Hot Swap Specification R1.0 to be R2.0 *C 112376 12/21/01 RN Combined with spec# 38-03040 *D 112946 04/04/02 RN Updated pin tables for 39K30 (208PQFP, 256FBGA) Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA) Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL Added PLL parameters (f PLLVCO , PSAPLLI, fMPPLI ) Added and updated Storage Temperature for 39K200-208EQFP Changed the Icc0 spec for 39K165 and 39K200 Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin Updated Input and Output Standard Timing Delay Adjustment table Removed Self Boot Industrial parts from the offering Removed Delta39K165Z (1.8V) from the offering Removed 144-FBGA package offering Added self-boot Flash Memory endurance and data retention data Added Family, Package, and Density Migration section Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs *E 117518 10/04/02 OOR Changed data sheet status from Preliminary to Final Added note 7 to DC Characteristics *F 121063 11/06/02 DSG Updated spec 51-85103 (MG388 package drawing) to rev. *C *G 122543 12/10/02 RN Changed the definition of following pins on CY39030 -256FBGA package: Pin A10: From IO/Vref7 to IO/Vref6 Pin B7: From IO/Vref6 to V CC Added Table to identify Bank Location of Global Clock and Global Control Pins *H 128684 08/04/03 OOR Removed all “Z” parts (1.8V) Referenced EEPROM to ATMEL part number