34RC02

34RC02 CATALYST | Alldatasheet

Document overview

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Technical content

2-kb I2C Serial EEPROM, Serial Presence Detect * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. PIN CONFIGURATION FUNCTIONAL SYMBOL

FEATURES

I 400 kHz I2C bus compatible* I 1.7 to 5.5 volt operation I 16-byte page write buffer I Hardware write protection for entire memory I Permanent and reversible software write protection for lower 128 bytes I Schmitt trigger on SCL and SDA inputs I Low power CMOS technology I 1,000,000 program/erase cycles I 100 year data retention I 8-pin DIP, SOIC, TSSOP and TDFNpackages I Industrial and extended temperature ranges

DESCRIPTION

The CAT34RC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT34RC02 features a 16-byte page write buffer. The device operates via the I 2C bus serial interface and is available in 8-pin DIP, SOIC, TSSOP and TDFN packages. © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc No. 1052, Rev. K VSS A0 VCC WP SCL SDA VSS VCC WP SCL SDA VCC WP SCL SDA VSS HALOGEN FREE TM LEAD F REE PIN FUNCTIONS Pin Name Function A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC 1.7 V to 5.5 V Power Supply VSS Ground VSS VCC WP SCL SDA VCC VSS SDA SCL WP CAT34RC02A2, A1, A0

2Doc. No. 1052, Rev. K CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V Symbol Test Conditions Min Typ Max Units CI/O(2) Input/Output Capacitance (SDA) V I/O = 0 V 8 pF CIN(2) Input Capacitance (other pins) V IN = 0 V 6 pF ZWPL WP Input Impedance V IN < 0.5 V 5 70 k Ω ZWPH WP Input Impedance V IN > VCC x 0.7 500 k Ω RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Units NEND(2)(*) Endurance MIL-STD-883, Test Method 1033 1,000,000 Program/ Erase Cycles TDR(2)(*) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(2)(*) ESD Susceptibility MIL-STD-883, Test Method 3015 4000 Volts ILTH(2)(3) Latch-up JEDEC Standard 17 100 mA ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Note: (1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V CC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC voltage on address pin A 0 is +12.0 V. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to V CC + 1.0 V. (4) Standby Current, I SB = 10 µA max at extended temperature range. *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (*) Page Mode, VCC = 5 V, 25°C D.C. OPERATING CHARACTERISTICS VCC = 1.7 V to 5.5 V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units ICC Power Supply Current (Read) f SCL = 100 kHz 1 mA ICC Power Supply Current (Write) f SCL = 100 kHz 3 mA ISB(4) Standby Current (VCC = 5.0 V) V IN = GND or VCC 1 µA ILI Input Leakage Current V IN = GND to VCC 1 µA ILO Output Leakage Current V OUT = GND to VCC 1 µA VIL Input Low Voltage –1V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 1.0 V VOL1 Output Low Voltage (VCC = 3.0 V) I OL = 3 mA 0.4 V VOL2 Output Low Voltage (VCC = 1.7 V) I OL = 1.5 mA 0.5 V VHV RSWP Set/Clear Overdrive V HV - VCC > 4.8 V 7 10 V A0 High Voltage

3 Doc No. 1052, Rev. K Write Cycle Limits Symbol Parameter Min Typ Max Units tWR Write Cycle Time 5 ms A.C. CHARACTERISTICS VCC = 1.7 V to 5.5 V, unless otherwise specified. Read & Write Cycle Limits Symbol Parameter 1.7 V - 5.5 V 2.5 V - 5.5 V Min Max Min Max Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time 100 100 ns Constant at SCL, SDA Inputs tAA SCL Low to SDA Data Out 3.5 0.9 µs and ACK Out tBUF(1) Time the Bus Must be Free Before 4.7 1.3 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4 0.6 µs tLOW Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4 0.6 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 250 100 ns tR(1) SDA and SCL Rise Time 1 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4 0.6 µs tDH Data Out Hold Time 100 100 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Power-Up Timing(1)(2) Symbol Parameter Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal write cycle. During the internal write cycle, SDA is released by the Slave and the device does not acknowledge external commands.

releases it to ‘transmit’ a ‘1’. not busy (see A.C. Characteristics). of a HIGH to LOW transition on SDA while SCL is HIGH. unless the MASTER generates a START condition. of a LOW to HIGH transition on SDA while SCL is HIGH. standby mode, when following a READ command. Read (1) or Write (0) operation is to be performed. transmitting and waits for a STOP condition. Figure 4. Acknowledge Timing Figure 5. Slave Address Bits

010 A 2 A1 A0 R/W

The SWP commands are shown in Table 1. Table 1. SWP Commands address counter will point to the first memory byte, etc. Figure 8. Immediate Address Read Timing

10Doc. No. 1052, Rev. K 8–22-LEAD 300 MIL WIDE PLASTIC DIP (P, L) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. Dimension D Pkg Min Max 0.180 (4.57) MAX 0.015 (0.38) 0.100 (2.54) BSC 0.014 (0.36) 0.022 (0.56) D 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65)

11 Doc No. 1052, Rev. K 8-LEAD 150 MIL WIDE SOIC (J, W) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 3. Lead coplanarity is 0.004" (0.102mm) maximum. 0.149 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0.0099 (0.25) 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0.016 (0.40) 0.050 (1.27) 0˚-8˚ X 45 D Dimension D Pkg Min Max

12Doc. No. 1052, Rev. K 8-PAD TDFN 2X3 PACKAGE (VP2, SP2) 0.08C DAP SIZE 1.7 X 2.1 C0.35 1.50 + 0.10 0.30 + 0.10 (8X) 0.50 TYP. (6X) 1.50 REF. (2X) 0.25 + 0.05 (8X)

0.10 M C AB

1.85 + 0.10 0.0 - 0.05 0.10C C 0.20 REF. 2.00 + 0.10 (S) 0.15C 0.15CPIN 1 INDEX AREA A B 3.00 + 0.10 (S) NOTE: 1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 MM. 3. WARPAGE SHALL NOT EXCEED 0.10 MM. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE NOT CONSIDERED AS SPECIAL CHARACTERISTIC. 0.75 + 0.05 MAX.

13 Doc No. 1052, Rev. K 8-LEAD TSSOP (U, Y)

7.72 TYP

4.16 TYP

(1.78 TYP)

0.42 TYP

0.65 TYP

LAND PATTERN RECOMMENDATION -A- -B- 3.2 6.4 ABC0.2 8 5 3.0 + 0.1 4.4 + 0.1 ALL LEAD TIPS PIN #1 IDENT. 1 4 ALL LEAD TIPS 1.1 MAX TYP 0.1 C (0.9) 0.10 + 0.05 TYP 0.19 - 0.30 TYP

0.3 M A B S C S

0.09 - 0.20 TYP 0.6+0.1 SEATING PLANE GAGE PLANE 0.25 o - 8 o DETAIL A -C- Notes: 1. Lead coplanarity is 0.004" (0.102mm) maximum.

14Doc. No. 1052, Rev. K

ORDERING INFORMATION

Notes: (1) The device used in the above example is a 34RC02JI-TE13 (SOIC, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating Voltage, Tape & Reel) Prefix Device # Suffix 34RC02 J I TE13 Product Number Tape & ReelPackage CAT Temperature Range I = Industri Optional Company ID E = Extended (-40°C to +125°C) REV-E Die Revision SP2: VP2: PDIP SOIC (JEDEC) TSSOP TDFN PDIP (Lead free, Halogen free) SOIC (JEDEC), (Lead free, Halogen free) TSSOP (Lead free, Halogen free) TDFN (Lead free, Halogen free)

15 Doc No. 1052, Rev. K

REVISION HISTORY

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Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: 1052 Revison: K Issue date: 10/18/04 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ DPPs ™ AE 2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.