29F200BB

AM29F200B_06 AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 41

Technical content

Publication Number 21526 Revision D Amendment 4 Issue Date Nobember 1, 2006 Am29F200B Data Sheet The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions.

THIS PAGE LEFT INTENTIONALLY BLANK.

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21526 Rev: D Amendment: 4 Issue Date: November 1, 2006 Am29F200B

2 Megabit (256 K x 8-Bit/128 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ 5.0 V for read and write operations — Minimizes system level power requirements ■ Manufactured on 0.32 µm process technology — Compatible with 0.5 µm Am29F200A device ■ High performance — Access times as fast as 45 ns ■ Low power consumption — 20 mA typical active read current (byte mode) — 28 mA typical active read current for (word mode) — 30 mA typical program/erase current — 1 µA typical standby current ■ Sector erase architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and three 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1,000,000 write/erase cycles guaranteed ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ Package options — 44-pin SO — 48-pin TSOP — Known Good Die (KGD) (see publication number 21257) ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash — Superior inadvertent write protection ■ Data# Polling and Toggle Bit — Detects program or erase cycle completion ■ Ready/Busy# output (RY/BY#) — Hardware method for detection of program or erase cycle completion ■ Erase Suspend/Erase Resume — Supports reading data from a sector not being erased ■ Hardware RESET# pin — Resets internal state machine to the reading array data

2 Am29F200B 21526D4 November 1, 2006

The Am29F200B is a 2 Mbit, 5.0 Volt-only Flash memory organized as 262,144 bytes or 131,072 words. The 8 bits of data appear on DQ0–DQ7; the 16 bits on DQ0–DQ15. The Am29F200B is offered in 44-pin SO and 48-pin TSOP packages. The device is also avail- able in Known Good Die (KGD) form. For more information, refer to publication number 21257. This device is designed to be programmed in-system with the standard system 5.0 volt V CC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and ben- efits of the Am29F200A, which was manufactured using 0.5 µm process technology. The standard device offers access times of 45, 50, 55, 70, 90, and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automati- cally preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6/DQ2 (toggle) status bits . After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

4 Am29F200B 21526D4 November 1, 2006

Family Part Number Am29F200B Speed Option VCC = 5.0 V ± 5% -45 -50 VCC = 5.0 V ± 10% -55 -70 -90 -120 Max access time, ns (tACC) 4 55 05 57 09 0 1 2 0 Max CE# access time, ns (tCE) 4 55 05 57 09 0 1 2 0 Max OE# access time, ns (tOE) 3 03 03 03 03 55 0 Erase Voltage Generator Input/Output Buffers Data Latch Y-Gating Cell MatrixX-Decoder Y-Decoder Address Latch Chip Enable Output Enable Logic PGM Voltage Generator TimerVCC Detector State Control Command Register WE# CE# OE# A0–A16 STB STB DQ0–DQ15 RY/BY# Buffer RY/BY# BYTE# RESET# A-1 VCC VSS

November 1, 2006 21526D4 Am29F200B 5 DATA SHEET CONNECTION DIAGRAMS This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for more information. NC RY/BY# NC CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC SO

6 Am29F200B 21526D4 November 1, 2006

This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for more information. PIN CONFIGURATION A0–A16 = 17 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy output V CC = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) V SS = Device ground NC = Pin not connected internally LOGIC SYMBOL A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 A15 NC A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# NC Standard TSOP 16 or 8 DQ0–DQ15 (A-1) A0–A16 CE# OE# WE# RESET# BYTE# RY/BY#

November 1, 2006 21526D4 Am29F200B 7 DATA SHEET

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29F200B T -45 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-free package E = Extended (–55 °C to +125°C) K = Extended (–55 °C to +125°C) with Pb-free package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) S = 44-Pin Small Outline Package (SO 044 ) This device is also available in Known Good Die (KGD) form. See publication number 21257 for more information. SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29F200B

2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

Valid Combinations V CC Voltage AM29F200BT-45, AM29F200BB-45 EC, EI, SC, SI ED, EF , SD, SF 5.0 V ± 5% AM29F200BT-50, AM29F200BB-50 EC, EI, EE, ED, EF , EK SC, SI, SE, SD, SF , SK AM29F200BT-55, AM29F200BB-55

5.0 V ± 10%

AM29F200BT-70, AM29F200BB-70 AM29F200BT-90, AM29F200BB-90 AM29F200BT-120, AM29F200BB-120

8 Am29F200B 21526D4 November 1, 2006

Table 1. Am29F200B Device Bus Operations Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information. used as an input for the LSB (A-1) address function. array data in words or bytes. register contents are altered. Configuration” for more information.

November 1, 2006 21526D4 Am29F200B 9 DATA SHEET An erase operation can erase one sector, multiple sec- tors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Defini- tions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Charac- teristics section in the appropriate data sheet for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at V CC ± 0.5 V. (Note that this is a more restricted voltage range than V IH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at V IH. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. In the DC Characteristics tables, I CC3 represents the standby current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the system drives the RESET# pin low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be rein itiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V IL, the device enters the TTL standby mode; if RESET# is held at V SS ± 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase oper- ation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state.

10 Am29F200B 21526D4 November 1, 2006

Table 2. Am29F200T Top Boot Block Sector Address Table Table 3. Am29F200B Bottom Boot Block Sector Address Table sectionfor more information. through the command register. shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0.

Table 4. Am29F200B Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. The device is shipped with all sectors unprotected. AMD representative for details. or unprotected. See “Autoselect Mode” for details. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected.
2. All previously protected sectors are protected once

12 Am29F200B 21526D4 November 1, 2006

gramming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When V CC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent uninten- tional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = V IL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more infor- mation on this mode. The system must issue the reset command to re- enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage

mers and requires VID on address bit A9. autoselect mode and return to reading array data. write cycles, followed by the program set-up command. for information on these status bits. reading array data, to ensure data integrity. Figure 2. Program Operation ments for the chip erase command sequence.

14 Am29F200B 21526D4 November 1, 2006

The system can determine the status of the erase oper- ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase opera- tion. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” for infor- mation on these status bits. Figure 3 illustrates the algorithm for the erase opera- tion. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Erase Suspend/Erase Resume Commands The Erase Suspend comma nd allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo- rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-sus- pended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program oper- ation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend

1. See the appropriate Command Definitions table for erase
2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

16 Am29F200B 21526D4 November 1, 2006

Table 5. Am29F200B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A16–A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
4. Data bits DQ15–DQ8 are don’t cares for unlock and
5. Address bits A16–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

1. No unlock or command cycles required when reading array
2. The Reset command is required to return to reading array

high (while the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a
2. The data is 00h for an unprotected sector and 01h for a
3. The system may read and program in non-erasing sectors, or
4. The Erase Resume command is valid only during the Erase

90 X00 01Byte AAA 555 AAA

55 SA 30Byte AAA 555 AAA AAA 555

18 Am29F200B 21526D4 November 1, 2006

RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. The timing dia- grams for read, reset, program, and erase shows the relationship of RY/BY# to other signals. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 μs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is acti vely erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 2 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 5 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the dif- ferences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 5 for the following discussion. When- ever the system initially be gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has com- pleted the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and

determine the status of the operation (top of Figure 5). sector erase commands will always be less than 50 μs. accepted the command sequence, and then read DQ3. pend) are ignored until the erase operation is complete. accepted. Table 6 shows the outputs for DQ3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5

Figure 5. Toggle Bit Algorithm

20 Am29F200B 21526D4 November 1, 2006

Table 6. Write Operation Status

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

22 Am29F200B 21526D4 November 1, 2006

Notes: 1. The I CC current is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Program or Erase Algorithm is in progress. 4. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Max Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCC Max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current VCC = VCC Max, A9, OE#, RESET# = 12.5 V 50 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE # = VIL, OE# = VIH Byte 40 mA Word 50 ICC2 VCC Active Program/Erase Current (Notes 2, 3, 4) CE# = VIL, OE# = VIH 60 mA ICC3 VCC Standby Current (Note 2) V CC = VCC Max, CE# = VIH, OE# = VIH 1.0 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage I OL = 5.8 mA, VCC = VCC Min 0.45 V VOH Output High Voltage I OH = –2.5 mA, VCC = VCC Min 2.4 V VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

November 1, 2006 21526D4 Am29F200B 23 DATA SHEET DC CHARACTERISTICS (Continued) CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Program or Erase Algorithm is in progress. 4. Not 100% tested. 5. I CC3 for extended temperature is 20 µA max (>+85°C). Parameter Symbol Parameter Description Te st Conditions Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCC Max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current VCC = VCC Max; A9, OE#, RESET# = 12.5 V 50 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 20 40 mA Word 28 50 ICC2 VCC Active Program/Erase Current (Notes 2, 3, 4) CE# = VIL, OE# = VIH 30 50 mA ICC3 VCC Standby Current Note (Note 5) CE# = VCC ± 0.5 V, OE# = VIH 15 µ A VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage I OL = 5.8 mA, VCC = VCC Min 0.45 V VOH1 Output Low Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC Min V CC – 0.4 V VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

24 Am29F200B 21526D4 November 1, 2006

Table 7. Test Specifications Figure 8. Test Setup Diodes are IN3064 or equivalents.

November 1, 2006 21526D4 Am29F200B 25 DATA SHEET AC CHARACTERISTICS Read Operations Notes: 1. Not 100% tested. 2. See Figure 8 and Table 7 for test specifications Figure 9. Read Operations Timings

Description

JEDEC Std Test Setup -45 -50 -55 -70 -90 -120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 45 50 55 70 90 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL M a x4 55 05 57 09 0 1 2 0 n s tELQV tCE Chip Enable to Output Delay OE# = V IL M a x4 55 05 57 09 0 1 2 0 n s tGLQV tOE Output Enable to Output Delay (Note 1) M a x3 03 03 03 03 55 0n s tEHQZ tDF Chip Enable to Output High Z (Note 1) M a x2 02 02 02 02 03 0n s tGHQZ tDF Output Enable to Output High Z (Note 1) M a x2 02 02 02 02 03 0n s tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH

26 Am29F200B 21526D4 November 1, 2006

Figure 10. RESET# Timings

28 Am29F200B 21526D4 November 1, 2006

Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -45 -50 -55 -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 45 50 55 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH A d d r e s s H o l d T i m e M i n4 54 54 54 54 55 0n s tDVWH tDS D a t a S e t u p T i m e M i n2 52 52 53 04 55 0n s tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 30 30 35 45 50 ns tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 7 µs Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 30 30 30 30 35 50 ns

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 13. Program Operation Timings

30 Am29F200B 21526D4 November 1, 2006

1. SA = sector address (for Se ctor Erase), VA = Valid Address for reading status data (”see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 14. Chip/Sector Erase Operation Timings

32 Am29F200B 21526D4 November 1, 2006

Figure 17. DQ2 vs. DQ6 Figure 18. Temporary Sector Unprotect Timing Diagram

November 1, 2006 21526D4 Am29F200B 33 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -45 -50 -55 -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 45 50 55 70 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH A d d r e s s H o l d T i m e M i n 4 54 54 54 54 55 0n s tDVEH tDS D a t a S e t u p T i m e M i n 2 52 52 53 04 55 0n s tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 30 30 30 35 45 50 ns tEHEL tCPH CE# Pulse Width High Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 7 µs Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

34 Am29F200B 21526D4 November 1, 2006

1. PA = Program Address, PD = Program Data, SA = Sect or Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 19. Alternate CE# Controlled Write Operation Timings

November 1, 2006 21526D4 Am29F200B 35 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25×C, 5.0 V V CC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 4.5 V (VCC = 4.75 V for ±5% devices), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute th e four-bus-cycle command sequence for programming. See Table 1 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Limits CommentsTyp (Note 1) Max (Note 2) Unit Sector Erase Time 1 8 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 5 sec Byte Programming Time 7 300 µs Excludes system-level overhead (Note 5)Word Programming Time 12 500 µs Chip Programming Time (Note 3) 1.8 5.4 sec Parameter Description Min Max Input Voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance V OUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 8 10 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

36 Am29F200B 21526D4 November 1, 2006

SO 044—44-Pin Smal l Outline Package Dwg rev AC; 10/99

November 1, 2006 21526D4 Am29F200B 37 DATA SHEET PHYSICAL DIMENSIONS TS 048—48-Pin Standard Thin Small Outline Package Dwg rev AA; 10/99

38 Am29F200B 21526D4 November 1, 2006

Revision A (July 1998) Global Made formatting and layout consistent with other data sheets. Used updated common tables and diagrams Revision B (January 1999) Distinctive Characteristics Added bullet for 20-year data retention at 125°C Optional Processing: Deleted “B = Burn-in”. DC Characteristics—TTL/NMOS Compatible ICC1, ICC2, ICC3: Added Note 2 “Maximum I CC specifi- cations are tested with VCC = VCCmax”. DC Characteristics— CMOS Compatible ICC1, ICC2, ICC3: Added Note 2 “Maximum I CC specifi- cations are tested with VCC = VCCmax”. AC Characteristics Figure 15. Data# Polling Timings (During Embedded Algorithms): Added text to note. Figure 16. Toggle Bit Timings (During Embedded Algo- rithms): Added text to note. Replaced figures with more detailed illustrations. Deleted burn-in option. Revision D (November 29, 2000) Added table of contents. Deleted burn-in option. Revision D+1 (June 14, 2004) Added Pb-free OPNs. Revision D+2 (February 16, 2006) Global Deleted TSR048 48-pin Reverse TSOP option. Revision D3 (May 18, 2006) Added “Not recommended for new designs” note. AC Characteristics Changed tBUSY specification to maximium value. Revision D4 (November 1, 2006) Deleted “Not recommended for new designs” note.

November 1, 2006 21526D4 Am29F200B 39 DATA SHEET The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that FASL will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating condi- tions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Ex- change and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2006 Spansion Inc. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof, are trademarks of Spansion Inc. Other company and product names used in this publication are for identification purposes only and may be trade- marks of their respective companies. Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.