AM29F040B_06 AMD | Alldatasheet

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Publication Number 21445 Revision E Amendment 5 Issue Date November 1, 2006 Am29F040B Data Sheet The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21445 Rev: E Amendment: 5 Issue Date: November 1, 2006 Am29F040B

4 Megabit (512 K x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS

  • 5.0 V ± 10% for read and write operations — Minimizes system level power requirements  Manufactured on 0.32 µm process technology — Compatible with 0.5 µm Am29F040 device  High performance — Access times as fast as 55 ns  Low power consumption — 20 mA typical active read current — 30 mA typical program/erase current — 1 µA typical standby current (standard access time to active mode)  Flexible sector architecture — 8 uniform sectors of 64 Kbytes each — Any combination of sectors can be erased — Supports full chip erase — Sector protection: A hardware method of locking sectors to prevent any program or erase operations within that sector  Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies bytes at specified addresses  Minimum 1,000,000 program/erase cycles per sector guaranteed  20-year data retention at 125 °C — Reliable operation for the life of the system  Package options — 32-pin PLCC, TSOP , or PDIP  Compatible with JEDEC standards — Pinout and software compatible with single-power-supply Flash standard — Superior inadvertent write protection  Data# Polling and toggle bits — Provides a software method of detecting program or erase cycle completion  Erase Suspend/Erase Resume — Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation

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The Am29F040B is a 4 Mbit, 5.0 volt-only Flash mem - ory organized as 524,288 Kbytes of 8 bits each. The

512 Kbytes of data are divided into eight sectors of 64

Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0–DQ7. The Am29F040B is offered in 32-pin PLCC, TSOP , and PDIP packages. This device is designed to be programmed in-system with the stan dard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD’s 0.32 µm pro- cess technology, and offers all the features and benefits of the Am29F040, which was manufactured using 0.5 µm process technology. In addtion, the Am29F040B has a second toggle bit, DQ2, and also of fers the ability to program in the Erase Suspend mode. The standard Am29F040B offers access times of 55, 70, 90, and 120 ns, allowing high-speed microproces - sors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Com mands are written to the command register using standard microprocessor write timings. Register con - tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cy cles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com - mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera - tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem - ory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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Note: See the “AC Characteristics” section for more information. BLOCK DIAGRAM Family Part Number Am29F040B Speed Option VCC = 5.0 V ± 5% -55 VCC = 5.0 V ± 10% -70 -90 -120 Max access time, ns (tACC) 55 70 90 120 Max CE# access time, ns (tCE) 55 70 90 120 Max OE# access time, ns (tOE) 25 30 35 50 Erase Voltage Generator Y- G a t i n g Cell MatrixX-Decoder Y -Decoder Address Latch Chip Enable Output Enable Logic PGM Voltage Generator TimerVCC Detector State Control Command Register WE# CE# OE# A0–A18 STB STB DQ0–DQ7 VCC VSS Data Latch Input/Output Buffers

November 1, 2006 21445E5 Am29F040B 5 DATA SHEET CONNECTION DIAGRAMS PIN CONFIGURATION A0–A18 = Address Inputs DQ0–DQ7 = Data Input/Output CE# = Chip Enable WE# = Write Enable OE# = Output Enable VSS = Device Ground VCC =+5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) LOGIC SYMBOL VCC WE# A17 A14 A13 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 A18 A16 A15 A12 DQ0 DQ1 DQ2 V SS PDIP 17 18 19 20161514 13 1 3 02343 2 DQ0 DQ1 DQ2 V SS DQ3 DQ4 DQ5 DQ6 A14 A13 A11 OE# A10 CE# DQ7 A12 A15 A16 A18 V CC WE# A17 PLCC A11 A13 A14 A17 WE# V CC A18 A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 32-Pin Standard TSOP DQ0–DQ7 A0–A18 CE# OE# WE#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi - nation) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29F040B -55 E C TEMPERATURE RANGE C = Commercial (0 °C to +70°C) I = Industrial (–40 °C to +85°C) E = Extended (–55 °C to +125°C) D = Commercial (0 °C to +70°C) for Pb-free Package F = Industrial (-40 °C to +85°C) for Pb-free Package K = Extended (-55 °C to +125°C) for Pb-free Package PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

Valid Combinations VCC Voltage AM29F040B-55 JC, JI, JE, JD, JF , JK EC, ED, EI, EE, EF , EK

5.0 V ± 5%

5.0 V ± 10%AM29F040B-90 PC, PI, PE, PD, PF , PK,

JC, JI, JE, JD, JF , JK EC, EI, EE, ED, EF , EKAM29F040B-120

each of these operations in further detail. Table 1. Am29F040B Device Bus Operations Note: See the “Sector Protection/Unprotection” section. for more information. indicate the address space that each sector occupies. Command Sequence” sections for more information. tables and timing diagrams for write operations. teristics section for timing diagrams.

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standby current specification. Table 2. Sector Addresses Table Note: All sectors are 64 Kbytes in size.

through the command register. Table 3. Am29F040B Autoselect Codes (High Voltage Method) The device is shipped with all sectors unprotected. AMD representative for details. “Autoselect Mode” for details. power-down transitions, or from system noise. tional writes when VCC is greater than VLKO. WE# do not initiate a write cycle. reset to reading array data on power-up.

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Writing specific address and data commands or se - quences into the command re gister initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the im proper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em bedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys tem can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more infor - mation on this mode. The system must issue the reset command to re-en - able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se - quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig nores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read ing array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM program mers and requires VID on address bit A9. The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manu - facturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector ad dress (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro - gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the pro grammed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad dresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for informa tion on these status bits.

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edge of the final WE# pulse in the command sequence. tus of the erase operation by using DQ7, DQ6, or DQ2. read and write timings and command definitions apply. if a sector is actively erasing or is erase-suspended.

  1. See the appropriate Command Definitions table for erase
  2. See “DQ3: Sector Erase Timer” for more information.

Figure 2. Erase Operation

Table 4. Am29F040B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A18–A16 select a unique sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or autoselect data, all bus cycles
  4. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

  1. No unlock or command cycles required when reading array data.
  2. The Reset command is required to return to reading array

high (while the device is providing status data).

  1. The fourth cycle of the autoselect command sequence is a
  2. The data is 00h for an unprotected sector and 01h for a
  3. The system may read and program in non-erasing sectors, or
  4. The Erase Resume command is valid only during the Erase

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completed, or whether the device is in Erase Suspend. Suspend mode, Data# Polling produces a “1” on DQ7. lected sectors that are protected. DQ0–DQ6 while Output Enable (OE#) is asserted low. Table 5 shows the outputs for Data# Polling on DQ7. Figure 3 shows the Data# Polling algorithm.

  1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 3. Data# Polling Algorithm

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“Sector Erase Command Sequence” section. accepted the command sequence, and then read DQ3. pend) are ignored until the erase operation is complete. cepted. Table 5 shows the outputs for DQ3.

  1. Read toggle bit twice to determine whether or not it is
  2. Recheck toggle bit because it may stop toggling as DQ5

Figure 4. Toggle Bit Algorithm

Table 5. Write Operation Status

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

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  1. Minimum DC voltage on input or I/O pins is –0.5 V. During

VCC + 2.0 V for periods up to 20 ns. See Figure 6.

  1. Minimum DC input voltage on A9 pin is –0.5 V. During

overshoot to 13.5 V for periods up to 20 ns.

  1. No more than one output shorted to ground at a time.

extended periods may affect device reliability. functionality of the device is guaranteed. Figure 5. Maximum Negative Figure 6. Maximum Positive

November 1, 2006 21445E5 Am29F040B 19 DATA SHEET DC CHARACTERISTICS TTL/NMOS Compatible CMOS Compatible Notes for DC Characteristics (both tables): 1. The I CC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested. 5. For CMOS mode only, I CC3 = 20 µA max at extended temperatures (> +85°C). Parameter Symbol Parameter Description Test Description Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH 20 30 mA ICC2 VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) CE# = VIL, OE# = VIH 30 40 mA ICC3 VCC Standby Current (Note 2) CE# = VIH 0.4 1.0 mA VIL Input Low Level –0.5 0.8 V VIH Input High Level 2.0 VCC + 0.5 V VID Voltage for Autoselect and Sector Protect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V VLKO Low VCC Lock-Out Voltage 3.2 4.2 V Parameter Symbol Parameter Description Test Description Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH 20 30 mA ICC2 VCC Active Program/Erase Current (Notes 2, 3, 4) CE# = VIL, OE# = VIH 30 40 mA ICC3 VCC Standby Current (Notes 2, 5) CE# = VCC ± 0.5 V 1 5 µA VIL Input Low Level –0.5 0.8 V VIH Input High Level 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Sector Protect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V VOH2 IOH = –100 μA, VCC = VCC Min VCC –0.4 V VLKO Low VCC Lock-out Voltage 3.2 4.2 V

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Table 6. Test Specifications Figure 7. Test Setup

  1. See Figure 7 and Table 6 for test conditions.
  2. Output driver disable time.

Figure 8. Read Operation Timings

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Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Symbols

Description

UnitJEDEC Std -55 -70 -90 -120 tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 40 45 45 50 ns tDVWH tDS Data Setup Time Min 25 30 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recover Time Before Write (OE# high to WE# low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 45 50 ns tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2)) Typ 1 sec tVCS VCC Set Up Time (Note 1)) Min 50 µs

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Figure 11. Data# Polling Timings (During Embedded Algorithms) Figure 12. Toggle Bit Timings (During Embedded Algorithms)

Figure 13. DQ2 vs. DQ6

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Erase and Program Operations Alternate CE# Controlled Writes Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Symbols UnitJEDEC Std -55 -70 -90 -120 tAVAV tWC Write Cycle Time (Note 1)) Min 55 70 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 40 45 45 50 ns tDVEH tDS Data Setup Time Min 25 30 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recover Time Before Write Min 0 ns tWLEL tWS CE# Setup Time Min 0 ns tEHWH tWH CE# Hold Time Min 0 ns tELEH tCP Write Pulse Width Min 30 35 45 50 ns tEHEL tCPH Write Pulse Width High Min 20 20 20 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2)) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2)) Typ 1 sec

  1. PA = Program Address, PD = Program Data, SA = Sect or Address, DQ7# = Complement of Data Input, DOUT = Array Data.
  2. Figure indicates the last two bus cycles of the command sequence.

Figure 14. Alternate CE# Controlled Write Operation Timings

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ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 4.5 V (4.75 V for -55), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execut e the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 1 8 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time 8 64 sec Byte Programming Time 7 300 µs Excludes system-level overhead (Note 5) Chip Programming Time (Note 3) 3.6 10.8 sec Min Max Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

November 1, 2006 21445E5 Am29F040B 29 DATA SHEET PLCC AND PDIP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 4 6 pF COUT Output Capacitance VOUT = 0 8 12 pF CIN2 Control Pin Capacitance VPP = 0 8 12 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Ye a r s 125°C 20 Ye a r s

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PD 032—32-Pin Plastic DIP Dwg rev AD; 10/99

November 1, 2006 21445E5 Am29F040B 31 DATA SHEET PHYSICAL DIMENSIONS (continued) PL 032—32-Pin Plastic Leaded Chip Carrier Dwg rev AH; 10/99

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PHYSICAL DIMENSIONS (continued) TS 032—32-Pin Standard Thin Small Package Dwg rev AA; 10/99

November 1, 2006 21445E5 Am29F040B 33 DATA SHEET REVISION SUMMARY Revision A (May 1997) Initial release. Revision B (January 1998) Global Formatted for consistency with other 5.0 volt-only data sheets. Revision B+1 (January 1998) AC Characteristics, Erase and Program Operations Added Note references to t WHWH1. Corrected the pa- rameter symbol for V CC Set-up Time to t VCS ; the specification is 50 µs minimum. Deleted the last row in table. Revision B+2 (April 1998) Distinctive Characteristics Changed minimum 100K write/erase cycles guaran- teed to 1,000,000. Added extended temperature availability to the -55 and -70 speed options. AC Characteristics Erase and Program Operations; Erase and Program Operations Alternate CE# Controlled Writes: Corrected the notes reference for t WHWH1 and t WHWH2 . These parameters are 100% tested. Corrected the note reference for tVCS. This parameter is not 100% tested. Erase and Programming Performance Changed minimum 100K program and erase cycles guaranteed to 1,000,000. Revision C (January 1999) Global Updated for CS39S process technology. Distinctive Characteristics Added 20-year data retention bullet. DC Characteristics—TTL/NMOS Compatible VOH: Changed the parameter description to “Output High Voltage” from Output High Level”. DC Characteristics—TTL/NMOS Compatible and CMOS Compatible ICC1, ICC2, ICC3: Added Note 2 “Maximum ICC specifi- cations are tested with VCC = VCCmax”. ICC3: Deleted VCC = VCCMax. Revision C+1 (February 1999) Command Definitions Command Definitions table: Deleted “XX” from the fourth cycle data column of the Sector Protect Verify command. Revision C+2 (May 17, 1999) Test Specifications Table Corrected the input and output measurement entries in the “All others” column. Revision D (November 15, 1999) AC Characteristics—Figure 9. Program Operations Timing and Figure 10. Chip/Sector Erase Operations Deleted t GHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision E0 (November 29, 2000) Added table of contents. Deleted burn-in option. Revision E1 (October 4, 2004) Added PB-Free option to Standard Ordering Matrix. Updated Valid Combinations Revision E2 (July 18, 2005) In valid combinations list, added the following: Pb-free options JD, JF , JK to set of -55 and -70 speed options; Pb-free options PD, PF , PK, JD, JF , JK to the set of -90, -120, and -150 speed options. Revision E3 (January 31, 2006) Global Removed 150 speed option from document. Removed 32-pin Reverse TSOP diagrams and all ref- erences from Ordering Information. Revision E4 (May 18, 2006) Added migration and obsolescence information. Revision E5 (November 1, 2006) Deleted migration and obsolescence text.

34 Am29F040B 21445E5 November 1, 2006

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright ©2006 Spansion Inc. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof, are trademarks of Spansion Inc. Other company and product names used in this publication are for identification purposes only and may be trade- marks of their respective companies. Copyright © 1997–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash™ is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.