AM29F040B AMD | Alldatasheet
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Publication# 21445 Rev: B Amendment/ +2 Issue Date: April 1998 Am29F040B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory Distinctive Characteristics ■ 5.0 V ± 10% for read and write operations — Minimizes system level power requirements ■ Manufactured on 0.35 µm process technology — Compatible with 0.5 µm Am29F040 device ■ High performance — Access times as fast as 55 ns ■ Low power consumption — 20 mA typical active read current — 30 mA typical program/erase current — 1 µA typical standby current (standard access time to active mode) ■ Flexible sector architecture — 8 uniform sectors of 64 Kbytes each — Any combination of sectors can be erased — Supports full chip erase — Sector protection: A hardware method of locking sectors to prevent any program or erase operations within that sector ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies bytes at specified addresses ■ Minimum 1,000,000 program/erase cycles per sector guaranteed ■ Package options — 32-pin PLCC, TSOP , or PDIP ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply Flash standard — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
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The Am29F040B is a 4 Mbit, 5.0 volt-only Flash mem- ory organized as 524,288 Kbytes of 8 bits each. The
512 Kbytes of data are divided into eight sectors of 64
Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0–DQ7. The Am29F040B is offered in 32-pin PLCC, TSOP , and PDIP packages. This de- vice is designed to be programmed in-system with the standard system 5.0 volt V CC supply. A 12.0 volt VPP is not required for write or erase operations. The device can also be programmed in standard EPROM pro- grammers. This device is manufactured using AMD’s 0.35 µm process technology, and offers all the features and ben- efits of the Am29F040, which was manufactured using 0.5 µm process technology. In addtion, the Am29F040B has a second toggle bit, DQ2, and also offers the ability to program in the Erase Suspend mode. The standard Am29F040B offers access times of 55, 70, 90, 120, and 150 ns, allowing high-speed micropro- cessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state-machine that con- trols the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The system can place the device into the standby mode . Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnel- ing. The data is programmed using hot electron injec- tion.
Note: See the “AC Characteristics” section for more information. BLOCK DIAGRAM Family Part Number Am29F040B Speed Option VCC = 5.0 V ± 5% -55 VCC = 5.0 V ± 10% -70 -90 -120 -150 Max access time, ns (tACC ) 55 70 90 120 150 Max CE# access time, ns (tCE ) 55 70 90 120 150 Max OE# access time, ns (tOE ) 2 53 03 55 05 5 Erase Voltage Generator Y -Gating Cell MatrixX-Decoder Y-Decoder Address Latch Chip Enable Output Enable Logic PGM Voltage Generator TimerVCC Detector State Control Command Register WE# CE# OE# A0–A18 STB STB DQ0–DQ7 VCC VSS 21445B-1 Data Latch Input/Output Buffers
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WE# A17 A14 A13 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 A18 A16 A15 A12 DQ0 DQ1 DQ2 V SS PDIP 17 18 19 20161514 13 1 3 02343 2 DQ0 DQ1 DQ2 V SS DQ3 DQ4 DQ5 DQ6 A14 A13 A11 OE# A10 CE# DQ7 A12 A15 A16 A18 V CC WE# A17 21445B-3 PLCC A11 A13 A14 A17 WE# V CC A18 A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A11 A13 A14 A17 WE# V CC A18 A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 21445B-4 32-Pin Standard TSOP 32-Pin Reverse TSOP
A0–A18 = Address Inputs DQ0–DQ7 = Data Input/Output CE# = Chip Enable WE# = Write Enable OE# = Output Enable VSS = Device Ground VCC = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) LOGIC SYMBOL
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DQ0–DQ7 A0–A18 CE# OE# WE# 21445B-5 DEVICE NUMBER/DESCRIPTION Am29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0 °C to +70°C) I= Industrial (–40°C to +85°C) E = Extended (–55 °C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations Valid Combinations Am29F040B-55 JC, JI, JE, EC, EI, EE, FC, FI, FE Am29F040B-70 Am29F040B-90 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE Am29F040B-120 Am29F040B-150
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each of these operations in further detail. Table 1. Am29F040B Device Bus Operations Note:See the section on Sector Protection for more information. data upon device power-up, or after a hardware reset. command register contents are altered. tire chip, or suspending/resuming the erase operation. Command Sequence” sections for more information. tables and timing diagrams for write operations. teristics section for timing diagrams.
standby current specification. Table 2. Sector Addresses Table Note:All sectors are 64 Kbytes in size. through the command register.
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Table 3. Am29F040B Autoselect Codes (High Voltage Method) The device is shipped with all sectors unprotected. AMD representative for details. or unprotected. See “Autoselect Mode” for details. power-down transitions, or from system noise. WE# do not initiate a write cycle. reset to reading array data on power-up. “AC Characteristics” section. suspended sectors, the device outputs status data.
data with the same exception. See “Erase Suspend/ Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM program- mers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manu- facturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector ad- dress (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two un- lock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the pro- grammed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.
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Figure 1. Program Operation ments for the chip erase command sequence. ded Erase algorithm are ignored. addresses are no longer latched. Erase Operation Timings for timing waveforms. ings during these operations. and any additional sector addresses and commands. edge of the final WE# pulse in the command sequence. tus of the erase operation by using DQ7, DQ6, or DQ2.
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Table 4. Am29F040B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A18–A16 select a unique sector.
- See Table 1 for description of bus operations.
- All values are in hexadecimal.
- Except when reading array or autoselect data, all bus cycles
- Address bits A18–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
- No unlock or command cycles required when reading array
- The Reset command is required to return to reading array
high (while the device is providing status data).
- The fourth cycle of the autoselect command sequence is a
- The data is 00h for an unprotected sector and 01h for a
- The system may read and program in non-erasing sectors, or
- The Erase Resume command is valid only during the Erase
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 tog- gles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 5 to compare outputs for DQ2 and DQ6. Figure 4 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the dif- ferences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 4 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The sys- tem can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, de- termining the status as described in the previous para- graph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed.
cepted. Table 5 shows the outputs for DQ3.
- Read toggle bit twice to determine whether or not it is
- Recheck toggle bit because it may stop toggling as DQ5
Figure 4. Toggle Bit Algorithm
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Table 5. Write Operation Status
- DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
- DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
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Notes for DC Characteristics (both tables): 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Not 100% tested. 4. For CMOS mode only, ICC3 = 20 µA max at extended temperatures (> +85°C). Parameter Symbol Parameter Description Test Description Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC , VCC = VCC Max ±1.0 µA ILIT A9 Input Load Current V CC = VCC Max, A9 = 12.5 V 50 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Note 1) CE# = VIL, OE# = VIH 20 30 mA ICC2 VCC Active Write (Program/Erase) Current (Notes 2, 3) CE# = VIL, OE# = VIH 30 40 mA ICC3 VCC Standby Current V CC = VCC Max, CE# = VIH 0.4 1.0 mA VIL Input Low Level –0.5 0.8 V VIH Input High Level 2.0 V CC + 0.5 V VID Voltage for Autoselect and Sector Protect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage I OL = 12 mA, VCC = VCC Min 0.45 V VOH Output High Level I OH = –2.5 mA, VCC = VCC Min 2.4 V VLKO Low VCC Lock-Out Voltage 3.2 4.2 V Parameter Symbol Parameter Description Test Description Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC , VCC = VCC Max ±1.0 µA ILIT A9 Input Load Current V CC = VCC Max, A9 = 12.5 V 50 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Note 1) CE# = VIL, OE# = VIH 20 30 mA ICC2 VCC Active Program/Erase Current (Notes 2, 3) CE# = VIL, OE# = VIH 30 40 mA ICC3 VCC Standby Current (Note 4) V CC = VCC Max, CE# = VCC ± 0.5 V 1 5 µA VIL Input Low Level –0.5 0.8 V VIH Input High Level 0.7 x V CC VCC + 0.3 V VID Voltage for Autoselect and Sector Protect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage I OL = 12.0 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage I OH = –2.5 mA, VCC = VCC Min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC Min V CC –0.4 V VLKO Low VCC Lock-out Voltage 3.2 4.2 V
Table 6. Test Specifications Figure 7. Test Setup
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- See Figure 7 and Table 6 for test conditions.
- Output driver disable time.
Figure 8. Read Operation Timings
Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Symbols
Description
UnitJEDEC Std. -55 -70 -90 -120 -150 tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 40 45 45 50 50 ns tDVWH tDS Data Setup Time Min 25 30 45 50 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recover Time Before Write (OE# high to WE# low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 45 50 50 ns tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Ty p 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec tVCS VCC Set Up Time (Note 1) Min 50 µs
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Note:PA = program address, PD = program data, DOUT is the true data at the program address. Figure 9. Program Operation Timings SA = Sector Address. VA = Valid Address for reading status data. Figure 10. Chip/Sector Erase Operation Timings
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Erase and Program Operations Alternate CE# Controlled Writes Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Note: Both DQ6 and DQ2 toggle with OE# or CE#. See the text on DQ6 and DQ2 in the “Write Operation Status” section for more information. 21445B-18 Figure 13. DQ2 vs. DQ6 UnitJEDEC Standard -55 -70 -90 -120 -150 tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 40 45 45 50 50 ns tDVEH tDS Data Setup Time Min 25 30 45 50 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recover Time Before Write Min 0 ns tWLEL tWS CE# Setup Time Min 0 ns tEHWH tWH CE# Hold Time Min 0 ns tELEH tCP Write Pulse Width Min 30 35 45 50 50 ns tEHEL tCPH Write Pulse Width High Min 20 20 20 20 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Ty p 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
- Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC , 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
- Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -55), 1,000,000 cycles.
- The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
does the device set DQ5 = 1. See the section on DQ5 for further information.
- In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
- System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
- The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
- PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
- Figure indicates the last two bus cycles of the command sequence.
Figure 14. Alternate CE# Controlled Write Operation Timings
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Includes all pins except VCC . Test conditions: VCC = 5.0 V, one pin at a time. TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. PLCC AND PDIP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Min Max Input Voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 6 7.5 pF C OUT Output Capacitance V OUT = 0 8.5 12 pF C IN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Symbol Parameter Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 4 6 pF C OUT Output Capacitance V OUT = 0 8 12 pF C IN2 Control Pin Capacitance V PP = 0 8 12 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years
32-Pin Plastic DIP (measured in inches) PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches) Pin 1 I.D. 1.640 1.670 .530 .580 .005 MIN .045 .065 .090 .110 .140 .225 .120 .160 .016 .022 SEATING PLANE .015 .060 16-038-S_AG PD 032 EC75 5-28-97 lv 32 17 16 .630 .700 10° .600 .625 .009 .015 .050 REF..026 .032 TOP VIEW Pin 1 I.D. .485 .495.447 .453 .585 .595 .547 .553 16-038FPO-5 PL 032 DA79 6-28-94 ae SIDE VIEW SEATING PLANE .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 REF. .490 .530
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PHYSICAL DIMENSIONS (continued) TS 032 32-Pin Standard Thin Small Package (measured in millimeters) Pin 1 I.D. 18.30 18.50 7.90 8.10
0.50 BSC
0.05 0.15 0.95 1.05 16-038-TSOP-2 TS 032 DA95 3-25-97 lv 19.80 20.20 1.20 MAX 0.50 0.70 0.10 0.21 0.08 0.20
PHYSICAL DIMENSIONS (continued) TSR032 32-Pin Reversed Thin Small Outline Package (measured in millimeters) 18.30 18.50 19.80 20.20 7.90 8.10 0.05 0.15 0.95 1.05 16-038-TSOP-2 TSR032 DA95 3-25-97 lv Pin 1 I.D. 1.20 MAX 0.50 0.70 0.10 0.21 0.08 0.20
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REVISION SUMMARY FOR AM29F040B Global Formatted for consistency with other 5.0 volt-only data data sheets. Revision B+1 AC Characteristics, Erase and Program Operations Added Note references to tWHWH1 . Corrected the pa- rameter symbol for VCC Set-up Time to tVCS ; the spec- ification is 50 µs minimum. Deleted the last row in table. Revision B+2 Distinctive Characteristics Changed minimum 100K write/erase cycles guaran- teed to 1,000,000. Ordering Infomation Added extended temperature availability to the -55 and -70 speed options. AC Characteristics Erase/Program Operations; Erase and Program Oper- ations Alternate CE# Controlled Writes: Corrected the notes reference for tWHWH1 and tWHWH2 . These param- eters are 100% tested. Corrected the note reference for t VCS . This parameter is not 100% tested. Erase and Programming Performance Changed minimum 100K program and erase cycles guaranteed to 1,000,000. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.