AM29F010 AMD | Alldatasheet
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Publication# 16736 Rev: G Amendment/ +2 Issue Date: March 1998 Am29F010
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation —5 . 0 V ± 10% for read, erase, and program operations — Simplifies system-level power requirements ■ High performance — 45 ns maximum access time ■ Low power consumption — 30 mA max active read current — 50 mA max program/erase current — <25 µA typical standby current ■ Flexible sector architecture — Eight uniform sectors — Any combination of sectors can be erased — Supports full chip erase ■ Sector protection — Hardware-based feature that disables/re- enables program and erase operations in any combination of sectors — Sector protection/unprotection can be implemented using standard PROM programming equipment ■ Embedded Algorithms — Embedded Erase algorithm automatically pre-programs and erases the chip or any combination of designated sector — Embedded Program algorithm automatically programs and verifies data at specified address ■ Minimum 100,000 program/erase cycles guaranteed ■ Package options — 32-pin PLCC — 32-pin TSOP — 32-pin PDIP ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash — Superior inadvertent write protection ■ Data# Polling and Toggle Bits — Provides a software method of detecting program or erase cycle completion
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The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131,072 bytes. The Am29F010 is offered in 32-pin PLCC, TSOP , and PDIP packages. The byte- wide data appears on DQ0-DQ7. The device is de- signed to be programmed in-system with the standard system 5.0 Volt V CC supply. A 12.0 volt VPP is not re- quired for program or erase operations. The device can also be programmed or erased in standard EPROM programmers. The standard device offers access times of 45, 55, 70, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus con- tention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the pro- gramming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com- mand sequence. This invokes the Embedded Erase algorithm—an internal algorithm that automatically pre- programs the array (if it is not already programmed) be- fore executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory. The hardware data protection measures include a low V CC detector automatically inhibits write operations during power transitions. The hardware sector pro- tection feature disables both program and erase oper- ations in any combination of the sectors of memory, and is implemented using standard EPROM program- mers. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
Note:See the AC Characteristics section for full specifications. BLOCK DIAGRAM Family Part Number Am29F010 Speed Option Max Access Time (ns) 45 55 70 90 120 CE# Access (ns) 45 55 70 90 120 OE# Access (ns) 25 30 30 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# CE# OE# STB STB DQ0 –DQ7 Data Latch Y-Gating Cell Matrix 16736G-1 Address LatchA0–A16
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OE# A10 CE# DQ7 VCC WE# DQ6 NC A14 A13 DQ5 DQ4 DQ3 NC PDIP DQ6 NC DQ5 DQ4 DQ3 1 31 30234 17 18 19 20161514 DQ0 A14 A13 A11 OE# A10 CE# DQ7 A12 A15 A16 VCC WE# NC DQ1 DQ2 VSS PLCC 16736G-3 Standard TSOP 16736G-4 A11 A13 A14 NC WE# V CC NC A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A 16736G-5 A11 A13 A14 NC WE# V CC NC A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A Reverse TSOP
A0–A16 = 17 Addresses DQ0–DQ7 = 8 Data Inputs/Outputs CE# = Chip Enable OE# = Output Enable WE# = Write Enable VCC = +5.0 Volt Single Power Supply (See Product Selector Guide for speed options and voltage supply tolerances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL DQ0–DQ7 A0–A16 CE# OE# WE# 16736G-6
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ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DEVICE NUMBER/DESCRIPTION Am29F010
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Blank = Standard Processing B = Burn-In (Contact an AMD representative for more information.) TEMPERATURE RANGE C = Commercial (0 °C to +70°C) I= Industrial (–40°C to +85°C) E = Extended (–55 °C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations B Valid Combinations AM29F010-45 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE AM29F010-55 VCC = 5.0 V ± 5% PC5, PI5, PE5 AM29F010-55 VCC = 5.0 V ± 10% JC, JI, JE, EC, EI, EE, FC, FI, FE AM29F010-70 AM29F010-90 AM29F010-120 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE
does not occupy any addressable memory location. register serve as inputs to the internal state machine. each of these operations in further detail. Table 1. Am29F010 Device Bus Operations
- The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-
tection/Unprotection” section. memory content occurs during the power transition. command register contents are altered. indicate the address space that each sector occupies. Command Sequence” sections for more information. tables and timing diagrams for write operations.
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standby current specification. Table 2. Am29F010 Sector Addresses Table through the command register.
Table 3. Am29F010 Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. The device is shipped with all sectors unprotected. AMD representative for details. or unprotected. See “Autoselect Mode” for details. power-down transitions, or from system noise. WE# do not initiate a write cycle.
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Writing specific address and data commands or se- quences into the command register initiates device op- erations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the im- proper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em- bedded Erase algorithm. The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. This resets the device to reading array data. Once programming begins, how- ever, the device ignores reset commands until the op- eration is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM program- mers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manu- facturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector ad- dress (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two un- lock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the pro- grammed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7or DQ6. See “Write Operation Status” for informa- tion on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.
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- See the appropriate Command Definitions table for erase
- See “DQ3: Sector Erase Timer” for more information.
Figure 2. Erase Operation
Table 4. Am2F010 Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A16–A14 uniquely select any sector.
- See Table 1 for description of bus operations.
- All values are in hexadecimal.
- Except when reading array or autoselect data, all command
bus cycles are write operations.
- No unlock or command cycles required when reading array
- The Reset command is required to return to reading array
high (while the device is providing status data).
- The fourth cycle of the autoselect command sequence is a
- The data is 00h for an unprotected sector and 01h for a
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tus of a write operation: DQ3, DQ5, DQ6, and DQ7. µs, then the device returns to reading array data. lected sectors that are protected. the “AC Characteristics” section illustrates this. Table 5 shows the outputs for Data# Polling on DQ7. Figure 3 shows the Data# Polling algorithm.
- VA = Valid address for programming. During a sector
address is any non-protected sector address.
- DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5. Figure 3. Data# Polling Algorithm
Program or Erase algorithm is in progress or complete. tion), and during the sector erase time-out. complete, DQ6 stops toggling. “AC Characteristics” section for the timing diagram. the status of the operation (top of Figure 4).
- Read toggle bit twice to determine whether or not it is
- Recheck toggle bit because it may stop toggling as DQ5
Figure 4. Toggle Bit Algorithm
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Table 5. Write Operation Status
- DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
- DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
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Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress. 3. Not 100% tested. Parameter Symbol Parameter Description Test Description Min Max Unit ILI Input Load Current V IN = VSS to VCC , VCC = VCC Max ±1.0 µA ILIT A9 Input Load Current V CC = VCC Max, A9 = 12.5 V 50 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC Max ±1.0 µA ICC1 VCC Active Current (Note 1) CE# = VIL, OE# = VIH, VCC = VCC Max 30 mA ICC2 VCC Active Current (Notes 2, 3) CE# = VIL, OE# = VIH, VCC = VCC Max 50 mA ICC3 VCC Standby Current V CC = VCC Max, CE# and OE# = VIH 1.0 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage I OL = 12 mA, VCC = VCC Min 0.45 V VOH Output High Voltage I OH = –2.5 mA, VCC = VCC Min 2.4 V VLKO Low VCC Lock-out Voltage 3.2 4.2 V
DC CHARACTERISTICS (continued) CMOS Compatible Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress. 3. Not 100% tested. Parameter Symbol Parameter Description Test Description Min Max Unit ILI Input Load Current V IN = VSS to VCC , VCC = VCC Max ±1.0 µA ILIT A9 Input Load Current V CC = VCC Max, A9 = 12.5 V 50 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC Max ±1.0 µA ICC1 VCC Active Current (Note 1) CE# = VIL, OE# = VIH, VCC = VCC Max 30 mA ICC2 VCC Active Current (Notes 2, 3) CE# = VIL, OE# = VIH, VCC = VCC Max 50 mA ICC3 VCC Standby Current VCC = VCC Max, CE# = VCC ± 0.5 V, OE# = VIH 100 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage I OL = 12 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC Min V CC –0.4 V VLKO Low VCC Lock-out Voltage 3.2 4.2 V
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Table 6. Test Specifications Figure 7. Test Setup
- Output Driver Disable Time.
- See Figure 7 and Table 6 for test specifications.
Parameter Description Test Setup -45 -55 -70 -90 -120 UnitJEDEC Std. Figure 8. Read Operations Timings
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Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more informaiton. Parameter Symbol Parameter Description -45 -55 -70 -90 -120 UnitJEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 35 45 45 45 50 ns tDVWH tDS Data Setup Time Min 20 20 30 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recover Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 25 30 35 45 50 ns tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 14 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1.0 sec tVCS VCC Set Up Time (Note 1) Min 50 µs
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Figure 11. Data# Polling Timings (During Embedded Algorithms) cycle, and array data read cycle. Figure 12. Toggle Bit Timings (During Embedded Algorithms)
Erase and Program Operations Alternate CE# Controlled Writes Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Symbol Parameter Description -45 -55 -70 -90 -120 UnitJEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 35 45 45 45 50 ns tDVEH tDS Data Setup Time Min 20 20 30 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time (Note 1) Min 0 ns tGHEL tGHEL Read Recover Time Before Write Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 25 30 35 45 50 ns tEHEL tCPH CE# Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 14 µs tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec
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- Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC , 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
- Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -45, -55 PDIP), 100,000 cycles.
- The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
does the device set DQ5 = 1. See the section on DQ5 for further information.
- In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
- System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1
for further information on command definitions.
- The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.
- PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
- Figure indicates the last two bus cycles of the command sequence.
Figure 13. Alternate CE# Controlled Write Operation Timings
Note:Includes all pins except VCC . Test conditions: VCC = 5.0 Volt, one pin at a time. TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. PLCC AND PDIP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Description Min Max Input Voltage with respect to VSS on I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Conditions Typ Max Unit C IN Input Capacitance V IN = 0 6 7.5 pF C OUT Output Capacitance V OUT = 0 8.5 12 pF C IN2 Control Pin Capacitance V IN = 0 8 10 pF Parameter Symbol Parameter Description Test Conditions Typ Max Unit C IN Input Capacitance V IN = 0 4 6 pF C OUT Output Capacitance V OUT = 0 8 12 pF C IN2 Control Pin Capacitance V PP = 0 8 12 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years
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32-Pin Plastic DIP (measured in inches) PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches) Pin 1 I.D. 1.640 1.680 .530 .580 .005 MIN .045 .065 .090 .110 .140 .225 .120 .160 .014 .022 SEATING PLANE .015 .060 16-038-SB_AG PD 032 DG75 2-28-95 ae 32 17 16 .630 .700 10˚ .600 .625 .008 .015 .050 REF..026 .032 TOP VIEW Pin 1 I.D. .485 .495.447 .453 .585 .595 .547 .553 16-038FPO-5 PL 032 DA79 6-28-94 ae SIDE VIEW SEATING PLANE .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 REF. .490 .530
PHYSICAL DIMENSIONS (continued) TS 032 32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 18.30 18.50 7.90 8.10
0.50 BSC
0.05 0.15 0.95 1.05 16-038-TSOP-2 TS 032 DA95 4-4-95 ae 19.80 20.20 1.20 MAX 0.50 0.70 0.10 0.21 0.25MM (0.0098") BSC 0.08 0.20
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PHYSICAL DIMENSIONS (continued) TSR 032 32-Pin Standard Thin Small Outline Package (measured in millimeters) 18.30 18.50 19.80 20.20 7.90 8.10 0.05 0.15 0.95 1.05 16-038-TSOP-2 TSR032 DA95 4-4-95 ae Pin 1 I.D. 1.20 MAX 0.50 0.70 0.10 0.21 0.25MM (0.0098") BSC 0.08 0.20
REVISION SUMMARY FOR AM29F010 Revision F+1 Product Selector Guide There are now two VCC supply operating ranges avail- able for the 55 ns speed option. The PDIP package is only available in the ±5% V CC operating range. The other packages are available in the ±10% operating range. The 45 ns speed grade is now also available in PC con- figuration (PDIP package, commercial temperature.) Operating Ranges VCC Supply Voltages: Changed to reflect the available speed options. AC Characteristics Write/Erase/Program Operations: Corrected to indicate tVLHT , tOESP , tWHWH1 , and tWHWH2 are typical values, not minimum values. Changed value for tWHWH2 . AC Characteristics Write/Erase/Program Operations, Alternate CE# Con- trolled Writes: Corrected to indicate tWHWH1 and tWHWH2 are typical values, not minimum values. Changed value for tWHWH2 . Erase and Programming Performance Combined chip and sector erase specifications; changed typical and maximum values. Added Note 6. Revision G Global Made formatting and layout consistent with other data sheets. Used updated common tables and diagrams. Revision G+1 Table 4, Command Definitions Address bits A0–A14 are required for unlock cycles. Therefore, addresses for second and fifth write cycles are 2AAAh. Addresses for first, third, fourth, and sixth cycles are 5555h. Read cycles are not affected. De- leted Note 4 to reflect the correction. Revision G+2 AC Characteristics Erase/Program Operations; Erase and Program Oper- ations Alternate CE# Controlled Writes: Corrected the notes reference for tWHWH1 and tWHWH2 . These param- eters are 100% tested. Corrected the note reference for t VCS . This parameter is not 100% tested. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.