29F002

AM29F002 AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 37

Technical content

Publication# 20818 Rev: C Amendment/ +2 Issue Date: March 1998 Am29F002/Am29F002N

2 Megabit (256 K x 8-Bit)

CMOS 5.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 5.0 Volt-only operation for read, erase, and program operations — Minimizes system level requirements ■ High performance — Access times as fast as 55 ns ■ Low power consumption (typical values at 5 MHz) — 1 µA standby mode current — 20 mA read current — 30 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 100,000 write cycle guarantee per sector ■ Package option — 32-pin PDIP — 32-pin TSOP — 32-pin PLCC ■ Compatibility with JEDEC standards — Pinout and software compatible with single- power supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data (not available on Am29F002N)

2 Am29F002/Am29F002N

The Am29F002 Family consists of 2 Mbit, 5.0 volt-only Flash memory devices organized as 262,144 bytes. The Am29F002 offers the RESET# function, the Am29F002N does not. The data appears on DQ7– DQ0. The device is offered in 32-pin PLCC, 32-pin TSOP, and 32-pin PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt V CC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM program- mers. The standard device offers access times of 55, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. (This feature is not available on the Am29F002N.) The system can place the device into the standby mode . Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun- neling. The data is programmed using hot electron injection.

Note:See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29F002/Am29F002N Speed Option VCC = 5.0 V ± 5% -55 VCC = 5.0 V ± 10% -70 -90 -120 Max access time, ns (tACC ) 55 70 90 120 Max CE# access time, ns (tCE ) 55 70 90 120 Max OE# access time, ns (tOE ) 30 30 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# CE# OE# STB STB DQ0 –DQ7 Sector Switches RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A17 20818C-1 n/a Am29F00N

4 Am29F002/Am29F002N

OE# A10 CE# DQ7 VCC WE# DQ6 A17 A14 A13 DQ5 DQ4 DQ3 NC A11 A13 A14 A17 WE# V CC RESET# A16 A15 A12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 1 31 30234 17 18 19 20161514 DQ0 A14 A13 A11 OE# A10 CE# DQ7 A12 A15 A16 RESET# VCC WE# A17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 20818C-2 PDIP Standard TSOP PLCC NC on Am29F00N NC on Am29F00N NC on Am29F00N RESET#

A0–A17 = 18 addresses DQ0–DQ7 = 8 data inputs/outputs CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low (not available on Am29F002N) VCC = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) V SS = Device ground NC = Pin not connected internally LOGIC SYMBOL 20818C-3 DQ0–DQ7 A0–A17 CE# OE# WE# RESET# N/C on Am29F002N

6 Am29F002/Am29F002N

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DEVICE NUMBER/DESCRIPTION Am29F002/Am29F002N

2 Megabit (256 K x 8-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0 °C to +70°C) I = Industrial (-40°C to +85°C) E= Extended (–55°C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector B T Valid Combinations Am29F002T -55 Am29F002B-55 Am29F002NT-55 Am29F002NB-55 PC, JC, JI, EC, EI Am29F002T -70 Am29F002B-70 Am29F002NT-70 Am29F002NB-70 PC, PI, JC, JI, EC, EI Am29F002T -90 Am29F002B-90 Am29F002NT-90 Am29F002NB-90 PC, PI, PE, JC, JI, JE, EC, EI, EEAm29F002T -120 Am29F002B-120 Am29F002NT-120 Am29F002NB-120

each of these operations in further detail. Table 1. Am29F002/Am29F002N Device Bus Operations RESET# pin and is therefore not available on the Am29F002N device. data upon device power-up, or after a hardware reset. command register contents are altered. chip, or suspending/resuming the erase operation. Command Sequence sections for more information. tables and timing diagrams for write operations.

8 Am29F002/Am29F002N

teristics section for timing diagrams. modes, before it is ready to read data. standby current specification. standby current specification. 0.5 V, the device enters the CMOS standby mode. rameters and timing diagram. Table 2. Am29F002/Am29F002N Top Boot Block Sector Address Table

Table 3. Am29F002/Am29F002N Bottom Boot Block Sector Address Table through the command register. Table 4. Am29F002/Am29F002N Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. supplements, publication numbers 20819 and 21183.

10 Am29F002/Am29F002N

The device is shipped with all sectors unprotected. AMD representative for details. or unprotected. See “Autoselect Mode” for details. therefore not available on the Am29F002N. ously protected sectors to change data in-system. shows the timing waveforms, for this feature. Figure 1. Temporary Sector Unprotect Operation power-down transitions, or from system noise. WE# do not initiate a write cycle. reset to reading array data on power-up.

1. All protected sectors unprotected.
2. All previously protected sectors are protected once

Writing specific address and data commands or se- quences into the command register initiates device op- erations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the im- proper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em- bedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Sus- pend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM program- mers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manu- facturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector ad- dress (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two un- lock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the pro- grammed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.

12 Am29F002/Am29F002N

array data, to ensure data integrity. Figure 2. Program Operation ments for the chip erase command sequence. erase operation immediately terminates the operation. data, to ensure data integrity. addresses are no longer latched. Erase Operation Timings for timing waveforms. ings during these operations.

14 Am29F002/Am29F002N

Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo- rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Ad- dresses are “don’t-cares” when writing the Erase Sus- pend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sec- tors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program oper- ation. See “Write Operation Status” for more informa- tion. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the de- vice has resumed erasing.

Table 5. Am29F002/Am29F002N Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A17–A13 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
4. Address bits A17–A12 are don’t cares for unlock and

command cycles, except when PA or SA is required.

1. No unlock or command cycles required when reading array
2. The Reset command is required to return to reading array

high (while the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a
2. The data is 00h for an unprotected sector and 01h for a
3. The system may read and program in non-erasing sectors, or
4. The Erase Resume command is valid only during the Erase

16 Am29F002/Am29F002N

Suspend mode, Data# Polling produces a “1” on DQ7. lected sectors that are protected. the “AC Characteristics” section illustrates this. Table 6 shows the outputs for Data# Polling on DQ7. Figure 4 shows the Data# Polling algorithm.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 4. Data# Polling Algorithm

DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 tog- gles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 5 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the dif- ferences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 5 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The sys- tem can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, de- termining the status as described in the previous para- graph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed.

18 Am29F002/Am29F002N

cepted. Table 6 shows the outputs for DQ3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5

Figure 5. Toggle Bit Algorithm

Table 6. Write Operation Status

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

20 Am29F002/Am29F002N

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

to –2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on input or I/O pins is VCC +0.5 V. to VCC +2.0 V for periods up to 20 ns. See Figure 7.

1. Minimum DC input voltage on pins A9, OE#, and RESET#
2. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. Figure 6. Maximum Negative Overshoot Figure 7. Maximum Positive Overshoot tionality of the device is guaranteed.

Notes: 1. RESET# is not available on Am29F002N. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current (Notes 1, 4) VCC = VCC max ; A9, OE#, RESET# = 12.5 V 50 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Note 2) CE# = VIL, OE# = VIH 20 30 mA ICC2 VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH 30 40 mA ICC3 VCC Standby Current V CC = VCC max , CE#, OE# = VIH 0.4 1 mA ICC4 VCC Reset Current (Note 1) V CC = VCC max ; RESET# = VIL 0.4 1 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage I OL = 12 mA, VCC = VCC min 0.45 V VOH Output High Voltage I OH = –2.5 mA, VCC = VCC min 2.4 V VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

22 Am29F002/Am29F002N

Notes: 1. RESET# is not available on Am29F002N. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Not 100% tested. 5. ICC3 and ICC4 = 20 µA max at extended temperature (>+85° C). Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current (Notes 1, 4) VCC = VCC max ; A9, OE#, RESET# = 12.5 V 50 µA ILO Output Leakage Current VOUT = VSS to VCC , VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Note 2) CE# = VIL, OE# = VIH 20 30 mA ICC2 VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH 30 40 mA ICC3 VCC Standby Current (Note 5) VCC = VCC max ; CE# = VCC ±0.5 V 1 5 µA ICC4 VCC Reset Current (Notes 1, 5) VCC = VCC max ; RESET# = VIL 15 µ A VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage I OL = 12 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC –0.4 VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

Table 7. Test Specifications Figure 8. Test Setup

24 Am29F002/Am29F002N

Notes: 1. Not 100% tested. 2. See Figure 8 and Table 7 for test specifications. Parameter

Description

JEDEC Std Test Setup -55 -70 -90 -120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 55 70 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 55 70 90 120 ns tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 15 20 20 30 ns tGHQZ tDF Output Enable to Output High Z (Note 1) M a x 1 52 02 03 0 n s tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE RESET# n/a Am29F002N tDF tOH 20818C-12 Figure 9. Read Operations Timings

25 Am29F002/Am29F002N

Note:Not 100% tested. RESET# is not available on Am29F002N. Figure 10. RESET# Timings

Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter -55 -70 -90 -120JEDEC Std. Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 45 45 45 50 ns tDVWH tDS Data Setup Time Min 25 30 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 45 50 ns tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec tVCS VCC Setup Time (Note 1) Min 50 µs

27 Am29F002/Am29F002N

1. PA = program address, PD = program data, DOUT is the true data at the program address.

Figure 11. Program Operation Timings

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

Figure 12. Chip/Sector Erase Operation Timings

29 Am29F002/Am29F002N

Figure 13. Data# Polling Timings (During Embedded Algorithms) cycle, and array data read cycle. Figure 14. Toggle Bit Timings (During Embedded Algorithms)

31 Am29F002/Am29F002N

Alternate CE# Controlled Erase/Program Operations 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter -55 -70 -90 -120JEDEC Std. Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 45 50 ns tDVEH tDS Data Setup Time Min 25 30 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 30 35 45 50 ns tEHEL tCPH CE# Pulse Width High Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.

Figure 17. Alternate CE# Controlled Write Operation Timings

33 Am29F002/Am29F002N

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC , 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -55), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions. 6. The device has a minimum guaranteed erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Note:Includes all pins except VCC . Test conditions: VCC = 5.0 V, one pin at a time. RESET# not available on Am29F002N. TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 1 8 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 7 s Byte Programming Time 7 300 µs Excludes system level overhead (Note 5)Chip Programming Time (Note 3) 1.8 5.4 s Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 6 7.5 pF C OUT Output Capacitance V OUT = 0 8.5 12 pF C IN2 Control Pin Capacitance V IN = 0 7.5 9 pF

PLCC AND PDIP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Symbol Parameter Description Test Conditions Typ Max Unit C IN Input Capacitance V IN = 0 4 6 pF C OUT Output Capacitance V OUT = 0 8 12 pF C IN2 Control Pin Capacitance V PP = 0 8 12 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years

35 Am29F002/Am29F002N

32-Pin Plastic DIP (measured in inches) PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches) Pin 1 I.D. 1.640 1.670 .530 .580 .005 MIN .045 .065 .090 .110 .140 .225 .120 .160 .016 .022 SEATING PLANE .015 .060 16-038-S_AG PD 032 EC75 5-28-97 lv 32 17 16 .630 .700 10° .600 .625 .009 .015 .050 REF..026 .032 TOP VIEW Pin 1 I.D. .485 .495.447 .453 .585 .595 .547 .553 16-038FPO-5 PL 032 DA79 6-28-94 ae SIDE VIEW SEATING PLANE .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 REF. .490 .530

PHYSICAL DIMENSIONS (continued) TS 032 32-Pin Standard Thin Small Package (measured in millimeters) Pin 1 I.D. 18.30 18.50 7.90 8.10

0.50 BSC

0.05 0.15 0.95 1.05 16-038-TSOP-2 TS 032 DA95 3-25-97 lv 19.80 20.20 1.20 MAX 0.50 0.70 0.10 0.21 0.08 0.20

37 Am29F002/Am29F002N

REVISION SUMMARY FOR AM29F002/AM29F002N Revision C Global Made formatting and layout consistent with other data sheets. Used updated common tables and diagrams. Combined Am29F002 and Am29F002N into a single data sheet. Revision C+1 Figure 17, Alternate CE# Controlled Write Operations Timings Removed the RY/BY# waverform and t BUSY parameter. The RY/BY# pin is not available on this device. Revision C+2 Block Diagram Corrected diagram by adding paths from the timer to the PGM and Erase Voltage Generators. Table 3, Bottom Boot Block Sector Addresses Corrected adddress bit A15 for sector SA2 to “0.” Table 5, Command Definitions Deleted the lower row of addresses in the Sector Pro- tect Verify command definitions. In the legend, corrected the definition for SA to indicate that address bits A17–A13 uniquely select a sector. Deleted Note 4. DC Characteristics Added Note 4 reference to I LIT. Corrected maximum currents for ICC1 and ICC2 , typical currents for ICC3 and ICC4 , test conditions for ICC4 and VOL . In TTL/NMOS table, deleted Note 5. In CMOS table, corrected IOH current for VOH . AC Characteristics Read Operations: Corrected tDF specifications for -55 speed option. Erase/Program Operations: Corrected the notes refer- ence for tWHWH1 and tWHWH2 . These parameters are 100% tested. Corrected the note reference for tVCS . This parameter is not 100% tested. Removed -150 specifications. Corrected t DS and tWP for -55 speed op- tion, tAH for -90 speed option. Alternate CE# Controlled Erase/Program Operations: Corrected the notes reference for tWHWH1 and tWHWH2 . These parameters are 100% tested. This parameter is not 100% tested. Removed -150 specifications. Cor- rected t DS and tCP for -55 speed option. Temporary Sector Unprotect Table Added note reference for tVIDR . This parameter is not 100% tested. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.