29400

A29400 AMICC | Alldatasheet

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Features

n 5.0V ± 10% for read and write operations n Access times: - 55/70/90 (max.) n Current: - 20 mA typical active read current - 30 mA typical program/erase current - 1 µA typical CMOS standby n Flexible sector architecture - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors - 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 s ectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector n Top or bottom boot block configurations availabl e n Embedded Erase Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies bytes at specified add resses n Typical 100,000 program/erase cycles per sector n 20 - year data retention at 125 °C - Reliable operation for the life of the system n Compatible with JEDEC - standards - Pinout and software compatible with single - power - supply Flash memory standard - S uperior inadvertent write protection n Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations n Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or progra m data to, a non - erasing sector, then resumes the erase operation n Hardware reset pin ( RESET ) - Hardware method to reset the device to reading array data n Package options - 44 - pin SOP or 48 - pin TSOP (I) General Description The A29400 is a 5. 0 volt only Flash memory organized as 524,288 bytes of 8 bits or 262,144 words of 16 bits each. The A29400 offers the RESET function. The 512 Kbytes of data are further divided into eleven sectors for flexible sector erase capability. The 8 bits of data appear on I/O 0 - I/O 7 while the addresses are input on A1 to A17; the 16 bits of data appear on I/O 0~I/O 15. The A29400 is offered in 44 - pin SOP and 48 - Pin TSOP packages. This device is designed to be programmed in - system with the standard s ystem 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in - system write or erase operations. However, the A29400 can also be programmed in standard EPROM programmers. The A29400 has the first toggle bit, I/O 6, which indicates whether an Em bedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O 6 toggle bit, the A29400 has a second toggle bit, I/O 2, to indicate whether the addressed sector is being selected for erase. The A29400 also offers the ability to progra m in the Erase Suspend mode. The standard A29400 offers access times of 55, 70 and 90 ns, allowing high - speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write e nable ( WE ) and output enable ( OE ) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29400 is entirely software command set compatible with the JEDEC single - power - supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an in ternal state - machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM de vices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure oc curs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the devi ce automatically times the erase pulse widths and verifies proper erase margin.

PRELIMINARY (February, 2001, Version 0.1) 2 AMIC Technology, Inc. The host system can detect whether a program or erase operation is complete by reading the I/O 7 ( Data Polling) and I/O 6 (toggle) status bits. After a progr am or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29400 is f ully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the Pin Configurations sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when th e device is placed in the standby mode. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. n SOP n TSOP (I) RY/BY A17 CE VSS OE I/O 0 I/O 14I/O 8 I/O 7 I/O 15 (A-1) VSS BYTE A16 A15 A14 A12 A11 A10 WE A13 A29400 16 29 44NC RESET I/O 1 I/O 9 I/O 2 I/O 10 I/O 3 I/O 11 I/O 6 I/O 13 I/O 5 I/O 12 I/O 4 VCC A29400V A14 A13 A12 A11 A10 NC WE RESET NC NC RY/BY NC

33 I/O 2

I/O 15 (A-1) VSS BYTE A16A15 NC 24 25

32 I/O 9

PRELIMINARY (February, 2001, Version 0.1) 3 AMIC Technology, Inc. Block Diagram Pin Descriptions Pin No. Description A0 - A17 Address Inputs I/O 0 - I/O 14 Data Inputs/Outputs I/O 15 Data Input/Output, Word Mode I/O 15 (A - 1) A - 1 LSB Address Input, Byte Mode CE Chip Enable WE Write Enable OE Output Enable RESET Hardware Reset (N/A A294001) BYTE Selects Byte Mode or Word Mode RY/ BY Ready/ BUSY - Output VSS Ground VCC Power Supply State Control Command Register Address Latch X-decoder Y-Decoder Chip Enable Output Enable Logic Cell Matrix Y-Gating VCC Detector PGM Voltage Generator Data Latch Input/Output BuffersErase Voltage Generator VCC VSS WE CE OE A 0 -A 17 I/O 0 - I/O 15 (A-1) Timer STB STB RESET Sector Switches BYTE RY/BY

PRELIMINARY (February, 2001, Version 0.1) 4 AMIC Technology, Inc.

1. Minimum DC voltage on input or I/O pins is - 0.5V.

+2.0V for periods up to 20ns.

1. Minimum DC input voltage on A9 pins is - 0.5V. During

overshoot to 13.5V for periods up to 20ns.

1. No more than one output is shorted at a time. Duration

Ratings" may cause permanent damage to this device. periods may affect device reliability. functionally of the device is guaranteed. Table 1. A29400 Device Bus Operations See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

PRELIMINARY (February, 2001, Version 0.1) 5 AMIC Technology, Inc. Word/Byte Configuration The BYTE pin determines whether the I/O pins I/O 15- I/O 0 operate in the byte or word configuration. If the BYTE pin is set at logic ”1”, the device is in word configuration, I/O 15- I/O 0 are active and controlled by CE and OE . If the BYTE pin is set at logic “0”, the device is in byte configuration, and only I/O 0- I/O 7 are active and controlled by CE and OE . I/O 8- I/O 14 are tri - stated, and I/O 15 pin is used as an input for the LSB(A - 1) address fu nction. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE and OE pins to V IL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at V IH all the time during read operation. The internal state machine is set for reading array data upon device power - up, or after a hardware reset . This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs pro duce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to t he Read Operations Timings diagram for the timing waveforms, l CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which include s programming data to the device and erasing sectors of memory), the system must drive WE and CE to V IL, and OE to V IH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the ent ire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory a rray) on I/O 7 - I/O 0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the w rite mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by readin g the status bits on I/O 7 - I/O 0. Standard read cycle timings and I CC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams. Standby Mode When the system is not readi ng or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE & RESET pins are both held at V CC ± 0.5V. (Note that this is a more restricted voltage range than V IH.) The device enters the TTL standby mode when CE is held at V IH, while RESET is held at VCC ±0.5V. The device requires the standard access time (t CE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is compl eted. ICC3 in the DC Characteristics tables represents the standby current specification. Output Disable Mode When the OE input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. RESET : Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of t RP, the device immedi ately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation th at was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory , enabling the system to read the boot - up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET parameters and diagram.

PRELIMINARY (February, 2001, Version 0.1) 6 AMIC Technology, Inc. Table 2. A29400 Top Boot Block Sector Address Table Table 3. A29400 Bottom Boot Block Sector Address Table

PRELIMINARY (February, 2001, Version 0.1) 7 AMIC Technology, Inc. Table 4. A29400 Autoselect Codes (High Voltage Method) L=Logic Low= V IL , H=Logic High=V IH, SA=Sector Address , X=Don’t Care.

PRELIMINARY (February, 2001, Version 0.1) 8 AMIC Technology, Inc. erase operations in previously protected sectors. voltage (V ID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. unprotected. See "Autoselect Mode" for details. inadvertent writes (refer to the Command De finitions table). do not initiate a write c ycle. WE must be a l ogical zero while OE is a logical one. reading array data on the initial power - up. programmed or erased by selecting the sector addresses. shows the timing waveforms, for this feature.

1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

PRELIMINARY (February, 2001, Version 0.1) 9 AMIC Technology, Inc. Command Definitions Writing specific address and data commands or sequences into the c ommand register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addres ses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the appropri ate timing diagrams in the "AC Characteristics" section. Reading Array Data The device is automatically set to reading array data after device power - up. No commands are required to retrieve data. The device is also ready to read array data after completi ng an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within er ase - suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re - enable the device for reading array data if I/O 5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores r eset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command mus t be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O 5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. T his method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed b y the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read c ycle at XX11h retrieves the continuation code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Se ctor Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE pin. Programming is a four - bus - cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set - up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 5 shows the address and d ata requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system can determine the status of the program operation by using I /O 7, I/O 6, or RY/ BY . See “White Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Not that a hardware reset immediately terminates the programm ing operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” ba ck to a “1”. Attempting to do so may halt the operation and set I/O5 to “1”, or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operat ions can convert a “0” to a “1”.

PRELIMINARY (February, 2001, Version 0.1) 12 AMIC Technology, Inc. Table 5. A29400 Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever h appens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A12 select a unique sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autosele ct data, all bus cycles are write operation.
4. Address bits A17 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading ar ray data when device is in the autoselect mode, or if I/O 5 goes high

(while the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a read cycle.
2. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.
3. The system may read and program in non - erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
4. The Erase Resume command is valid only during the Erase Suspend mode.
5. The ti me between each command cycle has to be less than 50 µs.

PRELIMINARY (February, 2001, Version 0.1) 13 AMIC Technology, Inc. completed, or whether the device is in Erase Suspend. pulse in the program or erase command sequence. program address to read valid status information on I/O 7. device returns to reading array data. for erasure to read valid status information on I/O 7.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. I/O 7 should be rechecked even if I/O 5 = "1" because

I/O 7 may change simultaneously with I/O 5. Figure 4. Data Polling Algorithm

PRELIMINARY (February, 2001, Version 0.1) 14 AMIC Technology, Inc. RY/BY : Read/Busy The RY/ BY is a dedicated, open - drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/ BY is an open - drain output, several RY/ BY pins can be tied together in parallel with a pull - up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/ BY . Refer to “ RESET Timings”, “Timing Waveforms for Program Operation” and “Timing Waveforms fo r Chip/Sector Erase Operation” for more information. I/O6: Toggle Bit I Toggle Bit I on I/O 6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time - out. During an Embedded Program or Erase algorithm oper ation, successive read cycles to any address cause I/O 6 to toggle. (The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O 6 stops toggling. After an erase command seque nce is written, if all sectors selected for erasing are protected, I/O 6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O 6 and I/O 2 together to determine whether a sector is actively erasing or is erase - suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O 6 t oggles. When the device enters the Erase Suspend mode, I/O 6 stops toggling. However, the system must also use I/O 2 to determine which sectors are erasing or erase - suspended. Alternatively, the system can use I/O 7 (see the subsection on " I/O 7 : Data Polling"). If a program address falls within a protected sector, I/O 6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. I/O 6 also toggles during the erase - suspend - program mode, a nd stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O 6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics " section for the timing diagram. The I/O 2 vs. I/O 6 figure shows the differences between I/O 2 and I/O 6 in graphical form. See also the subsection on " I/O 2: Toggle Bit II". I/O2: Toggle Bit II The "Toggle Bit II" on I/O 2, when used with I/O 6, indicates w hether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase - suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequenc e. I/O 2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But I/O 2 cannot distinguish whether the sector is actively erasing or is erase - suspended. I/O 6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O 2 and I/O 6. Figure 5 shows the toggle bit algorithm in flowchart form, and the section " I/O 2: Toggle Bit II" explains the algorithm. See also the " I/O 6: Toggle Bit I" subsection. Refer to t he Toggle Bit Timings figure for the toggle bit timing diagram. The I/O 2 vs. I/O 6 figure shows the differences between I/O 2 and I/O 6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 5 for the following discussion. Whenever the system init ially begins reading toggle bit status, it must read I/O 7 - I/O 0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the sy stem would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O 7 - I/O 0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O 5 is high (see the section on I/O 5). If it is, the system should then determine again whether the toggle bit is toggl ing, since the toggle bit may have stopped toggling just as I/O 5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation su ccessfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O 5 has not gone high. The system may continue to monitor the togg le bit and I/O 5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5).

PRELIMINARY (February, 2001, Version 0.1) 15 AMIC Technology, Inc. reset command to return the device to reading array data. applies after each additional sector erase command. "Sector Erase Command Sequence" section. been accepted. Table 6 shows the outputs for I/O 3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as I/O 5

Figure 5. Toggle Bit Algorithm

PRELIMINARY (February, 2001, Version 0.1) 16 AMIC Technology, Inc. Table 6. Write Operation Status

1. I/O 7 and I/O 2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. I/O 5 switches to “1” when an Embedded Program or Embedded Erase oper ation has exceeded the maximum timing

limits. See “I/O5: Exceeded Timing Limits” for more information.

PRELIMINARY (February, 2001, Version 0.1) 17 AMIC Technology, Inc. DC Characteristics TTL/NMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current V IN = VSS to VCC. VCC = VCC Max ±1.0 µA ILIT A9, OE & RESET Input Load Current VCC = VCC Max, A9, OE & RESET =12.5V 100 µA ILO Output Leakage Current V OUT = VSS to VCC. VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE = V IL, OE = V IH 20 30 mA ICC2 VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) CE = V IL, OE =V IH 30 40 mA ICC3 VCC Standby Current (Note 2) CE = V IH, RESET = VCC ± 0.5V 0.4 1.0 mA V IL Input Low Le vel - 0.5 0.8 V V IH Input High Level 2.0 VCC+0.5 V V ID Voltage for Autoselect and Temporary Unprotect Sector VCC = 5.25 V 10.5 12.5 V V OL Output Low Voltage IOL = 12mA, VCC = VCC Min 0.45 V V OH Output High Voltage IOH = - 2.5 mA, VCC = VCC Min 2.4 V CMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCC Max ±1.0 µA ILIT A9, OE & RESET Input Load Current VCC = VCC Max, A9, OE & RESET = 12.5V 50 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1,2) CE = V IL, OE = V IH 20 30 mA ICC2 VCC Active Program/Erase Current (Notes 2,3,4) CE = V IL, OE = V IH 30 40 mA ICC3 VCC Standby Current (Notes 2, 5) CE = RESET = VCC ± 0.5 V 1 5 µA V IL Input Low Level - 0 .5 0.8 V V IH Input High Level 0.7 x VCC VCC+0.3 V V ID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.25 V 10.5 12.5 V V OL Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V V OH1 IOH = - 2.5 mA, VCC = VCC Min 0.85 x VCC V V OH2 Output High Voltage IOH = - 100 µA. VCC = VCC Min VCC - 0.4 V Notes for DC characteristics (both tables): 1. The I CC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz). The frequency component typically i s less than 2 mA/MHz, with OE at V IH. 2. Maximum I CC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested. 5. For CMOS mode only, I CC3 = 20 µA max at extended tempe ratures (> +85 °C).

PRELIMINARY (February, 2001, Version 0.1) 18 AMIC Technology, Inc. AC Characteristics Read Only Operations Parameter Symbols Speed JEDEC Std Description Test Setup -55 -70 -90 Unit tAVAV tRC Read Cycle Time (Note 2) Min. 55 70 90 ns tAVQV tACC Address to Output Delay CE = V IL OE = V IL Max. 55 70 90 ns tELQV tCE Chip Enable to Output Delay OE = V IL Max. 55 70 90 ns tGLQV tOE Output Enable to Output Delay Max. 30 30 35 ns Read Min. 0 0 0 ns tOEH Output Enable Hold Time (Note 2) Toggle and Data Polling Min. 10 10 10 ns tEHQZ tDF Chip Enable to Output High Z (Notes 1,2) Max. 18 20 20 ns tGHQZ tDF Output Enable to Output High Z (Notes 1,2) 18 20 20 ns tAXQX tOH Output Hold Time from Addresses, CE or OE , Whichever Occurs First Min. 0 0 0 ns Notes: 1. Output driver disable time. 2. Not 100% tested. Timing Waveforms for Read Only Operation ( RESET =VIH on A29400) Addresses Addresses Stable CE OE WE Output Valid High-ZOutput tRC t OEH tOE tCE High-Z tOH tDF tACC RESET RY/BY

PRELIMINARY (February, 2001, Version 0.1) 19 AMIC Technology, Inc. AC Characteristics Hardware Reset (RESET ) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET Pulse Width Min 500 ns tRH RESET High Time Before Read (See Note) Min 50 ns tRB RY/ BY Recovery Time Min 0 ns Note: Not 100% tested. RESET Timings CE, OE RESET tRH tRP tReady Reset Timings NOT during Embedded Algorithms RESET tRP Reset Timings during Embedded Algorithms RY/BY tRB tReady CE, OE RY/BY

PRELIMINARY (February, 2001, Version 0.1) 20 AMIC Technology, Inc. Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR V ID Rise and Fall Time (See Note) Min 500 ns tRSP RESET Setup Time for Temporary Sector U nprotect Min 4 µs Note: Not 100% tested. Temporary Sector Unprotect Timing Diagram Program or Erase Command Sequence RESET 12V 0 or 5V tVIDR tVIDR 0 or 5V tRSP CE WE RY/BY

PRELIMINARY (February, 2001, Version 0.1) 21 AMIC Technology, Inc. AC Characteristics Word/Byte Configuration (BYTE) Parameter All Speed Options JEDEC Std

Description

-55 -70 -90 Unit tELFL/tELFH CE to BYTE Switching Low or High Max 5 ns tFLQZ BYTE Switching Low to Output High - Z Max 15 20 20 ns tHQV BYTE Switching High to Output Active Min 55 70 90 ns BYTE Timings for Read Operations BYTE Timings for Write Operations Note: Refer to the Erase/Program Operations table for t AS and t AH specifications. Data Output (I/O 0-I/O 14) Data Output (I/O 0-I/O 7) I/O 15 Output Address Input Data Output (I/O 0-I/O 14) Data Output (I/O 0-I/O 7) I/O 15 OutputAddress Input tFHQV tFLQZ tELFH tELFL CE OE BYTE I/O 0-I/O 14 I/O 15 (A-1) BYTE I/O 0-I/O 14 I/O 15 (A-1) BYTE Switching from word to byte mode BYTE Switching from byte to word mode The falling edge of the last WE signal tHOLD(t AH) tSET (t AS) CE BYTE WE

PRELIMINARY (February, 2001, Version 0.1) 22 AMIC Technology, Inc. AC Characteristics Erase and Program Operations Parameter Speed JEDEC Std -55 -70 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 55 70 90 ns tAVWL tAS Address Setup Time Min. 0 ns tWLAX tAH Address Hold Time Min. 45 45 45 ns tDVWH tDS Data Setup Time Min. 25 30 45 ns tWHDX tDH Data Hold Time Min. 0 ns tOES Output Enable Setup Time Min. 0 ns tGHWL tGHWL Read Recover Time Before Write ( OE high to WE low) Min. 0 ns tELWL tCS CE Setup Time Min. 0 ns tWHEH tCH CE Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. 30 35 45 ns Min. 20 ns tWHWL tWPH Write Pulse Width High Max. 50 µs Byte Typ. 7 tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Word Typ. 12 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec tvcs VCC Set Up Time (Note 1) Min. 50 µs tRB Recovery Time from RY/ BY Min 0 ns tBUSY Program/Erase Valid to RY/ BY Delay Min 30 30 35 ns Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.

PRELIMINARY (February, 2001, Version 0.1) 23 AMIC Technology, Inc. Timing Waveforms for Program Operation Addresses CE OE WE Data VCC A0h PD tWC PA Program Command Sequence (last two cycles) PA D OUT ~~~~ PA Status tAS tVCS Read Status Data (last two cycles) 555h tAH tWHWH1 tCH tGHWL tWP tWPHtCS tDS tDH Note : 1. PA = program addrss, PD = program data, Dout is the true data at the program address. 2. Illustration shows device in word mode. tRB tBUSY RY/BY

PRELIMINARY (February, 2001, Version 0.1) 24 AMIC Technology, Inc. Addresses CE OE WE Data VCC 55h 30h tWC SA Erase Command Sequence (last two cycles) VA Complete ~~~~ VA In Progress tAS tVCS Read Status Data 2AAh tAH tWHWH2 tCH tGHWL tWP tWPH tCS tDS tDH Note : 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus"). 2. Illustratin shows device in word mode. 555h for chip erase 10h for chip erase tRBtBUSY RY/BY Timing Waveforms for Chip/Sector Erase Operation

PRELIMINARY (February, 2001, Version 0.1) 25 AMIC Technology, Inc. Timing Waveforms for Data Polling (During Embedded Algorithms) Addresses CE OE WE I/O 7 tRC VAVA VA Complement ~~ Complement True Valid Data High-Z Status Data ~~ Status Data True Valid Data High-Z I/O 0 - I/O 6 tACC tCE tCH tOE tOEH tDF tOH Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. tBUSY RY/BY

PRELIMINARY (February, 2001, Version 0.1) 26 AMIC Technology, Inc. Timing Waveforms for Toggle Bit (During Embedded Algorithms) Note: VA = Valid Address; not required for I/O 6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Addresses CE OE WE I/O 6 , I/O 2 tRC VAVA VA Valid Status tACC tCE tCH tOE tOEH tDF tOH VA Valid Status Valid Status Valid Data (first read) (second read) (stop togging) RY/BY tBUSY

PRELIMINARY (February, 2001, Version 0.1) 27 AMIC Technology, Inc. Timing Waveforms for I/O2 vs. I/O6 AC Characteristics Erase and Program Operations Alternate CE Controlled Writes Parameter Speed JEDEC Std -55 -70 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 55 70 90 ns tAVEL tAS Address Setup Time Min. 0 ns tELAX tAH Address Hold Time Min. 40 45 45 ns tDVEH tDS Data Setup Time Min. 25 30 45 ns tEHDX tDH Data Hold Time Min. 0 ns tOES Output Enable Setup Time Min. 0 ns tGHEL tGHEL Read Recover Time Before Write ( OE High to WE Low) Min. 0 ns tWLEL tWS WE Setup Time Min. 0 ns tEHWH tWH WE Hold Time Min. 0 ns tELEH tCP CE Pulse Width Min. 30 35 45 ns tEHEL tCPH CE Pulse Width High Min. 20 20 20 ns Byte Typ. 7 tWHWH1 tWHWH1 P rogramming Operation (Note 2) Word Typ. 12 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec Notes: 3. Not 100% tested. 4. See the "Erase and Programming Performance" section for more information. Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Resume WE I/O 6 I/O 2 Erase Erase Suspend Read Erase Suspend Read Erase Erase Complete I/O 2 and I/O 6 toggle with OE and CE Note : Both I/O 6 and I/O 2 toggle with OE or CE. See the text on I/O 6 and I/O 2 in the section "Write Operation Statue" for more information. ~~Erase Suspend Program ~~~~

PRELIMINARY (February, 2001, Version 0.1) 28 AMIC Technology, Inc. Timing Waveforms for Alternate CE Controlled Write Operation ( RESET =VIH on A29400) Addresses WE OE CE Data 555 for program 2AA for erase PA D OUT ~~~~ I/O 7 Data Polling Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O 7 = Complement of Data Input, D OUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2 tAH tAStWC tWH tGHEL tCP tWS tCPH PA for program SA for sector erase 555 for chip erase A0 for program 55 for erase tRH tDS tDH ~~~~ RESET RY/BY Erase and Programming Performance Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 1.0 8 sec Chip Erase Time 11 sec Excludes 00h programming prior to erasure Byte Programming Time 35 300 µs Word Programming Time 12 500 µs Byte Mode 3.6 10.8 sec Chip Programming Time (Note 3) Word Mode 3.1 9.3 sec Excludes system - level overhead (Note 5) Notes: 1. Typical pr ogram and erase times assume the following conditions: 25 °C, 5.0V VCC, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90 °C, VCC = 4.5V (4.75V for - 55), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O 5 = 1. See the section on I/O 5 for further information. 4. In the pre - programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System - level overhead is the time required to execute the four - bus - cycle command sequence for pr ogramming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.

PRELIMINARY (February, 2001, Version 0.1) 29 AMIC Technology, Inc. Latch-up Characteristics Description Min. Max. Input Voltage with respect to VSS on all I/O pins - 1.0V VCC+1.0V VCC Current - 100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET ) - 1.0V 12.5V Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. TSOP and SOP Pin Capacitance Parameter Symbol Parameter Description Test Setup Typ. Max. Unit C IN Input Capacitance V IN=0 6 7.5 pF C OUT Output Capacitance V OUT=0 8.5 12 pF C IN2 Control Pin Capacitance V IN=0 7.5 9 pF Notes: 1. Sampled, not 1 00% tested. 2. Test conditions T A = 25 °C, f = 1.0MHz Data Retention Parameter Test Conditions Min Unit 150 °C 10 Years Minimum Pattern Data Retention Time 125 °C 20 Years

PRELIMINARY (February, 2001, Version 0.1) 30 AMIC Technology, Inc. Test Conditions Test Specifications Test Condition -55 All others Unit Outp ut Load 1 TTL gate Output Load Capacitance, C L(including jig capacitance) 30 100 pF Input Rise and Fall Times 5 20 ns Input Pulse Levels 0.0 - 3.0 0.45 - 2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement referenc e levels 1.5 0.8, 2.0 V Test Setup

6.2 K Ω

C L Diodes = IN3064 or Equivalent

2.7 K Ω

5.0 V

PRELIMINARY (February, 2001, Version 0.1) 31 AMIC Technology, Inc.

Ordering Information

Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA ) Package A29400TM - 55 44Pin SOP A29400 TV - 55 55 20 30 1 48Pin TSOP A29400TM - 70 44Pin SOP A29400TV - 70 70 20 30 1 48Pin TSOP A29400TM - 90 44Pin SOP A29400TV - 90 90 20 30 1 48Pin TSOP Bottom Boot Sector Flash Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA ) Package A29400UM - 55 44Pin SOP A29400UV - 55 55 20 30 1 48Pin TSOP A29400UM - 70 44Pin SOP A29400UV - 70 70 20 30 1 48Pin TSOP A29400UM - 90 44Pin SOP A29400UV - 90 90 20 30 1 48Pin TSOP

PRELIMINARY (February, 2001, Version 0.1) 32 AMIC Technology, Inc.

Package Information

SOP 44L Outline Dimensions unit: in ches/mm L L 1 C See Detail F Detail F 2344 S D Seating Plane D y E H E A 1 A 2 A e b θ 0.010" Gauge Plane Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max D - 1.122 1.130 - 28.50 28.70 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

PRELIMINARY (February, 2001, Version 0.1) 33 AMIC Technology, Inc. TSOP 48L (Type I) Outline Dimensions unit: inches/mm E c D L θ Detail "A" 0.25 24 25 D 1 D y eS A 1 A 2 A Detail "A" b Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A 1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.12 - 0.20 E - 0.472 0.476 - 12.00 12.10 e 0.020 BASIC 0.50 BASIC S 0.011 Typ. 0.28 Typ. θ 0° - 8° 0° - 8° Notes: 1. The maximum value of dimension D i ncludes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.