28F256

AM28F256 AMD | Alldatasheet

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Technical content

Publication# 11560 Rev: G Amendment/ +2 Issue Date: January 1998 Am28F256

256 Kilobit (32 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory DISTINCTIVE CHARACTERISTICS ■ High performance — 70 ns maximum access time ■ CMOS Low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption ■ Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP ■ 10,000 write/erase cycles minimum ■ Write and erase voltage 12.0 V ±5% ■ Latch-up protected to 100 mA from –1 V to V CC +1 V ■ Flasherase Electrical Bulk Chip-Erase — One second typical chip-erase ■ Flashrite Programming — 10 µs typical byte-program — 0.5 second typical chip program ■ Command register architecture for microprocessor/microcontroller compatible write interface ■ On-chip address and data latches ■ Advanced CMOS flash memory technology — Low cost single transistor memory cell ■ Automatic write/erase pulse stop timer GENERAL DESCRIPTION The Am28F256 is a 256 K Flash memory organized as 32 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. The Am28F256 is packaged in 32-pin PDIP , PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F256 is erased when shipped from the factory. The standard Am28F256 offers access times as fast as 70 ns, allowing operation of high-speed microproces- sors without wait states. To eliminate bus contention, the Am28F256 has separate chip enable (CE#) and output enable (OE#) controls. AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F256 uses a command register to manage this functionality, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming. AMD’s Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combina- tion of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F256 uses a 12.0V± 5% V PP high voltage input to perform the Flasherase and Flashrite algorithms. The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from –1 V to VCC +1 V . The Am28F256 is byte programmable using 10 µs programming pulses in accordance with AMD’s Flashrite programming algorithm. The typical room temperature programming time of the Am28F256 is a half a second. The entire chip is bulk erased using 10 ms erase pulses according to AMD’s Flasherase alrogithm. T ypical erasure at room temperature is accomplished in less than one second. The windowed package and the 15-20 minutes required for EPROM erasure using ultra-violet light are eliminated.

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Commands are written to the command register using standard microprocessor write timings. Register con- tents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches ad- dress and data needed for the programming and erase operations. For system design simplification, the Am28F256 is designed to support either WE# or CE# controlled writes. During a system write cycle, ad- dresses are latched on the falling edge of WE # or CE# whichever occurs last. Data is latched on the rising edge of WE # or CE# whichever occurs first. T o simplify the fol- lowing discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F256 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. BLOCK DIAGRAM PRODUCT SELECTOR GUIDE Family Part Number Am28F256 Speed Options (VCC = 5.0 V ± 10%) -70 -90 -120 -150 -200 Max Access Time (ns) 70 90 120 150 200 CE# (E#) Access (ns) 70 90 120 150 200 OE# (G#) Access (ns) 35 35 50 55 55 Erase Voltage Switch Command Register Program Voltage Switch Chip Enable Output Enable Logic Y-Decoder X-Decoder Y-Gating 262,144 Bit Cell Matrix 11560F-1 A0–A14 OE# CE# WE# VSS VCC To Array DQ0–DQ7 Input/Output Buffers Data Latch VPP Address Latch Low VCC Detector Program/Erase Pulse Timer State Control

WE# (W#) A13 A11 OE# (G#) A10 CE# (E#) DQ7 DQ6 DQ5 DQ4 DQ3 11560F-2 PDIP NC NC Note: Pin 1 is marked for orientation. DQ6 VPP DQ5 DQ4 DQ3 1 31 30234 17 18 19 20161514 DQ0 A14 A13 A11 OE# (G#) A10 CE# (E#) DQ7 A12 NC NC VCC WE# (W#) NC DQ1 DQ2 VSS PLCC 11560F-3

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CONNECTION DIAGRAMS (continued) LOGIC SYMBOL 32-Pin TSOP—Standard Pinout A11 A13 A14 NC WE# V CC VPP NC NC A12 OE# A10 CE# V SS 32-Pin TSOP—Reverse Pinout A11 A13 A14 NC WE# V CC VPP NC NC A12 OE# A10 CE# V SS 11560G-4 DQ0 A0–A14 CE# (E#) OE# (G#) –DQ7 WE# (W#) 11560F-5

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DEVICE NUMBER/DESCRIPTION Am28F256

256 Kilobit (32 K x 8-Bit) CMOS Flash Memory

Blank = Standard Processing B= B u r n - I n Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) P ACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations B Valid Combinations AM28F256-70 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE AM28F256-90 AM28F256-120 AM28F256-150 AM28F256-200

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A0–A14 Address Inputs for memory locations. Internal latches hold addresses during write cycles. CE # (E#) Chip Enable active low input activates the chip’s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode. DQ0–DQ7 Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles. NC No Connect-corresponding pin is not connected internally to the die. OE # (G#) Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high during command sequencing and program/erase operations. VCC Power supply for device operation. (5.0 V ± 5% or 10%) VPP Program voltage input. VPP must be at high voltage in order to write to the command register. The command register controls all functions required to alter the memory array contents. Memory contents cannot be altered when VPP ≤ VCC +2 V . VSS Ground WE # (W#) Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device.

The device uses 100% TTL-level control inputs to manage the command register. Erase and repro- gramming operations use a fixed 12.0 V ± 5% high voltage input. Read Only Memory Without high VPP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes. Command Register The command register is enabled only when high volt- age is applied to the V PP pin. The erase and repro- gramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The tradi- tional read, standby , output disable, and Auto select modes are available via the register. The device’s command register is written using stan- dard microprocessor write timings. The register con- trols an internal state machine that manages all device operations. For system design simplification, the de- vice is designed to support either WE# or CE# con- trolled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# which- ever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. T o simplify the fol- lowing discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# sig- nal. Overview of Erase/Program Operations Flasherase™ Sequence A multiple step command sequence is required to erase the Flash device (a two-cycle Erase command and repeated one cycle verify commands). Note: The Flash memory array must be completely programmed to 0’s prior to erasure. Refer to the Flashrite™ Programming Algorithm. 1. Erase Setup: Write the Setup Erase command to the command register. 2. Erase: Write the Erase command (same as Setup Erase command) to the command register again. The second command initiates the erase operation. The system software routines must now time-out the erase pulse width (10 ms) prior to issuing the Erase-verify command. An integrated stop timer prevents any possibility of overerasure. 3. Erase-Verify: Write the Erase-verify command to the command register. This command terminates the erase operation. After the erase operation, each byte of the array must be verified. Address in- formation must be supplied with the Erase-verify command. This command verifies the margin and outputs the addressed byte in order to compare the array data with FFh data (Byte erased). After successful data verification the Erase-verify command is written again with new address infor- mation. Each byte of the array is sequentially veri- fied in this manner. If data of the addressed location is not verified, the Erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000 times. Flashrite Programming Sequence A three step command sequence (a two-cycle Program command and one cycle Verify command) is required to program a byte of the Flash array. Refer to the Flash- rite Algorithm. 1. Program Setup: Write the Setup Program com- mand to the command register. 2. Program: Write the Program command to the com- mand register with the appropriate Address and Data. The system software routines must now time- out the program pulse width (10 µs) prior to issuing the Program-verify command. An integrated stop timer prevents any possibility of overprogramming. 3. Program-Verify: Write the Program-verify com- mand to the command register. This command ter- minates the programming operation. In addition, this command verifies the margin and outputs the byte just programmed in order to compare the array data with the original data programmed. After suc- cessful data verification, the programming se- quence is initiated again for the next byte address to be programmed. If data is not verified successfully, the Program se- quence is repeated until a successful comparison is verified or the sequence is repeated 25 times. Data Protection The device is designed to offer protection against acci- dental erasure or programming caused by spurious system level signals that may exist during power transi- tions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. The device also incorporates several features to pre- vent inadvertent write cycles resulting fromV CC power- up and power-down transitions or system noise. Low V CC Write Inhibit T o avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for

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state when VCC > VLKO to prevent uninitentional writes. or WE# will not initiate a write cycle. WE# must be a logical zero while OE# is a logical one. ically reset to the read mode on power-up. Table 1. Am28F256 Device Bus Operations (Notes 7 and 8) of VPPH . 0 V < An < VCC + 2 V , (normal TTL or CMOS input levels, where n = 0 or 9).

1. VPPL may be grounded, connected with a resistor to ground, or < VCC + 2.0 V . VPPH is the programming voltage specified for

the device. Refer to the DC characteristics. When VPP = VPPL , memory contents can be read but not written or erased.

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to T able 2.
2. Read operation with VPP = VPPH may access array data or the Auto select codes.
3. With VPP at high voltage, the standby current is ICC + IPP (standby).
4. Refer to Table 3 for valid DIN during a write operation.
5. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In the Auto select mode all

addresses except A9 and A0 must be held at VIL.

1. If VCC ≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP

rise time and fall time specification of 500 ns minimum.

lect data, or be standby mode. dresses have been stable at least tACC –tOE ). draw active current until the operation is terminated. to soldering the device to the board. temperature range of the device. Table 2. Am28F256 Auto Select Code

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by bringing WE# and CE# to VIL, while OE# is at VIH. data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used. command will not be executed. gramming Waveforms for specific timing parameters. fines these register commands. register contents are altered. Waveforms for the specific timing parameters. Table 3. Am28F256 Command Definitions

1. Bus operations are defined in T able 1.
2. RA = Address of the memory location to be read.

EA = Address of the memory location to be read during erase-verify . P A = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# pulse.

1. RD = Data read from location RA during read operation.

EVD = Data read from location EA during erase-verify . PD = Data to be programmed at location P A. Data latched on the rising edge of WE#. PVD = Data read from location P A during program-verify. P A is latched on the Program command.

1. Refer to the appropriate section for algorithms and timing diagrams.

Erase Setup is the first of a two-cycle erase command. It is a command-only operation that stages the device for bulk chip erase. The array contents are not altered with this command. 20h is written to the command reg- ister in order to perform the Erase Setup operation. Erase The second two-cycle erase command initiates the bulk erase operation. Y ou must write the Erase com- mand (20h) again to the register. The erase operation begins with the rising edge of the WE# pulse. The erase operation must be terminated by writing a new command (Erase-verify) to the register. This two step sequence of the Setup and Erase com- mands helps to ensure that memory contents are not accidentally erased. Also, chip erasure can only occur when high voltage is applied to the V PP pin and all con- trol pins are in their proper state. In absence of this high voltage, memory contents cannot be altered. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Note: The Flash memory device must be fully programmed to 00h data prior to erasure. This equalizes the charge on all memory cells ensuring reliable erasure. Erase-Verify Command The erase operation erases all bytes of the array in parallel. After the erase operation, all bytes must be sequentially verified. The Erase-verify operation is initi- ated by writing A0h to the register. The byte address to be verified must be supplied with the command. Ad- dresses are latched on the falling edge of the WE# pulse or CE# pulse, whichever occurs later. The rising edge of the WE# pulse terminates the erase operation. Margin Verify During the Erase-verify operation, the device applies an internally generated margin voltage to the addressed byte. Reading FFh from the addressed byte indicates that all bits in the byte are properly erased. Verify Next Address Y ou must write the Erase-verify command with the ap- propriate address to the register prior to verification of each address. Each new address is latched on the fall- ing edge of WE# or CE# pulse, whichever occurs later. The process continues for each byte in the memory array until a byte does not return FFh data or all the bytes in the array are accessed and verified. If an address is not verified to FFh data, the entire chip is erased again (refer to Erase Setup/Erase). Erase verification then resumes at the address that failed to verify. Erase is complete when all bytes in the array have been verified. The device is now ready to be pro- grammed. At this point, the verification operation is ter- minated by writing a valid command (e.g. Program Setup) to the command register. Figure 1 and T able 4, the Flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to per- form electrical erasure. Refer to AC Erase Characteris- tics and Waveforms for specific timing parameters.

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Figure 1. Flasherase Electrical Erase Algorithm

of erase/program cycles increases. gramming algorithm with the appropriate data pattern. than FFh will be returned from address locations. increasing number of bytes verify to the erased state. Table 4. Flasherase Electrical Erase Algorithm

1. See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V .

1. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written
2. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.

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Figure 2. AC Waveforms For Erase Operations to program the entire array to 00h data prior to erasure. Refer to the Flashrite Programming algorithm. The erase pulse occurs in section C. tiated on the rising edge of the WE# pulse of section B. ation on the rising edge of the WE# pulse (section D). data verification (section F). After each erase operation each byte must be verified.

the Erase-verify command (section D). Addresses are latched on the falling edge of the WE# pulse. Another software timing routine (6 µs duration) must be executed to allow for generation of internal voltages for margin checking and read operation (section E). During Erase-verification (section F) each address that returns FFh data is successfully erased. Each address of the array is sequentially verified in this manner by re- peating sections D thru F until the entire array is veri- fied or an address fails to verify. Should an address location fail to verify to FFh data, erase the device again. Repeat sections A thru F . Resume verification (section D) with the failed address. Each data change sequence allows the device to use up to 1,000 erase pulses to completely erase. Typically 100 erase pulses are required. Note: All address locations must be programmed to 00h prior to erase. This equalizes the charge on all memory cells and ensures reliable erasure. FLASHRITE PROGRAMMING SEQUENCE Program Setup The device is programmed byte by byte. Bytes may be programmed sequentially or at random. Program Setup is the first of a two-cycle program command. It stages the device for byte programming. The Program Setup operation is performed by writing 40h to the command register. Program Only after the program Setup operation is completed will the next WE# pulse initiate the active programming operation. The appropriate address and data for pro- gramming must be available on the second WE# pulse. Addresses and data are internally latched on the falling and rising edge of the WE# pulse respectively. The ris- ing edge of WE# also begins the programming opera- tion. Y ou must write the Program-verify command to terminate the programming operation. This two step sequence of the Setup and Program commands helps to ensure that memory contents are not accidentally written. Also, programming can only occur when high voltage is applied to the V PP pin and all control pins are in their proper state. In absence of this high voltage, memory contents cannot be programmed. Refer to AC Characteristics and Waveforms for specific timing parameters. Program Verify Command Following each programming operation, the byte just programmed must be verified. Write C0h into the command register in order to initiate the Program-verify operation. The rising edge of this WE pulse terminates the programming operation. The Program-verify operation stages the device for verifica- tion of the last byte programmed. Addresses were pre- viously latched. No new information is required. Margin Verify During the Program-verify operation, the device applies an internally generated margin voltage to the ad- dressed byte. A normal microprocessor read cycle out- puts the data. A successful comparison between the programmed byte and the true data indicates that the byte was successfully programmed. The original pro- grammed data should be stored for comparison. Pro- gramming then proceeds to the next desired byte location. Should the byte fail to verify, reprogram (refer to Program Setup/Program). Figure 3 and T able 5 indi- cate how instructions are combined with the bus oper- ations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for spe- cific timing parameters. Flashrite Programming Algorithm The device Flashrite Programming algorithm employs an interactive closed loop flow to program data byte by byte. Bytes may be programmed sequentially or at ran- dom. The Flashrite Programming algorithm uses 10 µs programming pulses. Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. The program al- gorithm allows for up to 25 programming operations per byte per reprogramming cycle. Most bytes verify after the first or second pulse. The entire sequence of pro- gramming and byte verification is performed with high voltage applied to the VPP pin. Figure 3 and T able 5 il- lustrate the programming algorithm.

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Figure 3. Flashrite Programming Algorithm

Table 5. Flashrite Programming Algorithm

1. See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V .

1. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register

is written with the read command. Write Reset Data = FFh, resets the register for read operations.

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Figure 4. AC Waveforms for Programming Operations The program pulse occurs in section C. ated on the rising edge of the WE# pulse of section B. eration on the rising edge of the WE# pulse (section D).

generation of internal voltages for margin checking and read operations (section E). During program-verification (section F) each byte just programmed is read to compare array data with original program data. When successfully verified, the next de- sired address is programmed. Should a byte fail to ver- ify, reprogram the byte (repeat section A thru F). Each data change sequence allows the device to use up to 25 program pulses per byte. T ypically, bytes are verified within one or two pulses. Algorithm Timing Delays There are four different timing delays associated with the Flasherase and Flashrite algorithms: 1. The first delay is associated with the VPP rise-time when VPP first turns on. The capacitors on the VPP bus cause an RC ramp. After switching on the VPP, the delay required is proportional to the number of devices being erased and the 0.1 mF/device. VPP must reach its final value 100 ns before commands are executed. 2. The second delay time is the erase time pulse width (10 ms). A software timing routine should be run by the local microprocessor to time out the delay. The erase operation must be terminated at the conclu- sion of the timing routine or prior to executing any system interrupts that may occur during the erase operation. To ensure proper device operation, write the Erase-verify operation after each pulse. 3. A third delay time is required for each programming pulse width (10 ms). The programming algorithm is interactive and verifies each byte after a program pulse. The program operation must be terminated at the conclusion of the timing routine or prior to exe- cuting any system interrupts that may occur during the programming operation. 4. A fourth timing delay associated with both the Flasherase and Flashrite algorithms is the write re- covery time (6 ms). During this time internal circuitry is changing voltage levels from the erase/ program level to those used for margin verify and read oper- ations. An attempt to read the device during this pe- riod will result in possible false data (it may appear the device is not properly erased or programmed). Note: Software timing routines should be written in machine language for each of the delays. Code written in machine language requires knowledge of the appro- priate microprocessor clock speed in order to accu- rately time each delay. Parallel Device Erasure Many applications will use more than one Flash memory device. T otal erase time may be minimized by implementing a parallel erase algorithm. Flash memories may erase at different rates. Therefore each device must be verified separately. When a device is completely erased and verified use a masking code to prevent further erasure. The other devices will continue to erase until verified. The masking code applied could be the read command (00h). Power-Up/Power-Down Sequence The device powers-up in the Read only mode. Power supply sequencing is not required. Note that if V CC ≤

1.0 Volt, the voltage difference between VPP and VCC

should not exceed 10.0 Volts. Also, the device has VPP rise time and fall time specification of 500 ns minimum. Reset Command The Reset command initializes the Flash memory de- vice to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset command must be written two consecutive times after the setup Program command (40h). This will reset the device to the Read mode. Following any other Flash command write the Reset command once to the device. This will safely abort any previous operation and initialize the device to the Read mode. The Setup Program command (40h) is the only com- mand that requires a two sequence reset cycle. The first Reset command is interpreted as program data. However, FFh data is considered null data during pro- gramming operations (memory cells are only pro- grammed from a logical “1” to “0”). The second Reset command safely aborts the programming operation and resets the device to the Read mode. Memory contents are not altered in any case. This detailed information is for your reference. It may prove easier to always issue the Reset command two consecutive times. This eliminates the need to deter- mine if you are in the setup Program state or not. Programming In-System Flash memories can be programmed in-system or in a standard PROM programmer. The device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board.

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AMD’s Flash memories are designed for use in applica- tions where the local CPU alters memory contents. Ac- cordingly, manufacturer and device codes must be accessible while the device resides in the target sys- tem. PROM programmers typically access the signa- ture codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a generally desired system design practice. The device contains an Auto Select operation to sup- plement traditional PROM programming methodology. The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h. A read cycle from address 0001h returns the device code. To terminate the operation, it is necessary to write another valid command, such as Reset (FFh), into the register.

Voltage with Respect T o Ground All pins except A9 and VPP (Note 1) .–2.0 V to +7.0 V Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V . During voltage transitions, inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 0.5 V . During voltage transitions, input and I/O pins may overshoot to VCC + 2.0V for periods up to 20ns. 2. Minimum DC input voltage on A9 and VPP pins is –0.5 V . During voltage transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 and VPP is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output shorted to ground at a time. Du- ration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Industrial (I) Devices Extended (E) Devices VCC Supply Voltages VPP Voltages Operating ranges define those limits between which the functionality of the device is guaranteed.

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Maximum Negative Input Overshoot Maximum Positive Input Overshoot Maximum V PP Overshoot 11560F-10 20 ns 20 ns +0.8 V –0.5 V 20 ns –2.0 V 11560F-11 20 ns VCC + 0.5 V 2.0 V 20 ns 20 ns VCC + 2.0 V 11560F-12 20 ns 13.5 V VCC + 0.5 V 20 ns 20 ns 14.0 V

DC CHARACTERISTICS over operating range unless otherwise specified TTL/NMOS Compatible Notes: 1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC ≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the Am28F256 has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP.. 4. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V CC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current V CC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current V CC = VCC Max, CE# = VIH 0.2 1.0 mA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 VCC Programming Current CE# = VIL Programming in Progress (Note 4) 20 30 mA ICC3 VCC Erase Current CE# = VIL Erasure in Progress (Note 4) 20 30 mA IPPS VPP Standby Current V PP = VPPL ±1.0 µA IPP1 VPP Read Current VPP = VPPH 70 200 µA VPP = VPPL ±1.0 IPP2 VPP Programming Current VPP = VPPH Programming in Progress (Note 4) 10 30 mA IPP3 VPP Erase Current VPP = VPPH Erasure in Progress (Note 4) 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.5 V VOL Output Low Voltage I OL = 5.8 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage I OH = –2.5 mA, VCC = VCC Min 2.4 V VID A9 Auto Select Voltage A9 = V ID 11.5 13.0 V IID A9 Auto Select Current A9 = V ID Max, VCC = VCC Max 5 50 µA VPPL VPP during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL 0.0 V CC +2.0 V VPPH VPP during Read/Write Operations 11.4 12.6 V VLKO Low VCC Lock-out Voltage 3.2 3.7 V

24 Am28F256

Notes: 1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC ≤ 1.0 volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP. 4. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V CC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current V CC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current V CC = VCC Max, CE# = VCC + 0.5 V 15 100 µA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 VCC Programming Current CE# = VIL Programming in Progress (Note 4) 20 30 mA ICC3 VCC Erase Current CE# = VIL Erasure in Progress (Note 4) 20 30 mA IPPS VPP Standby Current V PP = VPPL ±1.0 µA IPP1 VPP Read Current V PP = VPPH 70 200 µA IPP2 VPP Programming Current VPP = VPPH Programming in Progress (Note 4) 10 30 mA IPP3 VPP Erase Current VPP = VPPH Erasure in Progress (Note 4) 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 V CC VCC + 0.5 V VOL Output Low Voltage I OL = 5.8 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC Min V CC –0.4 VID A9 Auto Select Voltage A9 = V ID 11.5 13.0 V IID A9 Auto Select Current A9 = V ID Max, VCC = VCC Max 5 50 µA VPPL VPPL during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL 0.0 V CC + 2.0 V VPPH VPP during Read/Write Operations 11.4 12.6 V VLKO Low VCC Lock-out Voltage 3.2 3.7 V

26 Am28F256

SWITCHING CHARACTERISTICS over operating range unless otherwise specified AC Characteristics—Read Only Operation Notes: 1. Guaranteed by design not tested. 2. Not 100% tested. Parameter Symbols Parameter Description Am28F256 Speed Options UnitJEDEC Standard -70 -90 -120 -150 -200 tAVAV tRC Read Cycle Time (Note 2) Min 70 90 120 150 200 ns tELQV tCE Chip Enable AccessTime Max 70 90 120 150 200 ns tAVQV tACC Address Access Time Max 70 90 120 150 200 ns tGLQV tOE Output Enable Access Time Max 35 35 50 55 55 ns tELQX tLZ Chip Enable to Output in Low Z (Note 2) M i n 00000 n s tEHQZ tDF Chip Disable to Output in High Z (Note 1) M a x 2 02 03 03 53 5 n s tGLQX tOLZ Output Enable to Output in Low Z (Note 2) M i n 00000 n s tGHQZ tDF Output Disable to Output in High Z (Note 2) M a x 2 02 03 03 53 5 n s tAXQX tOH Output Hold from first of Address, CE#, or OE# Change (Note 2) M i n 00000 n s tWHGL Write Recovery Time before Read Min 6 6 6 6 6 µs tVCS VCC Setup Time to Valid Read (Note 2) M i n 5 05 05 05 05 0 µ s 11560G-15 3 V 0 V Input Output 1.5 V 1.5 VTe s t Poin t s AC T esting for -70 devices: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. 2.4 V 0.45 V Input Output T est Points 2.0 V 2.0 V 0.8 V0.8 V AC T esting (all speed options except -70): Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤10 ns.

AC Characteristics—Write/Erase/Program Operations Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally on the device. 3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and inactive Write-Enable times should be measured relative to the Chip-Enable waveform. 4. Not 100% tested. Parameter Symbols Parameter Description Am28F256 Speed Options UnitJEDEC Standard -70 -90 -120 -150 -200 tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns tAVWL tAS Address Set-up Time Min 0 0 0 0 0 ns tWLAX tAH A d d r e s s H o l d T i m e M i n 4 54 55 06 07 5n s tDVWH tDS Data Setup Time Min 45 45 50 50 50 ns tWHDX tDH Data Hold Time Min 10 10 10 10 10 ns tWHGL tWR Write Recovery Time before Read M i n 66666 µ s tGHWL Read Recovery Time before Write M i n 00000 µ s tELWL tCS Chip Enable Set-up Time Min 0 0 0 0 0 ns tWHEH tCH Chip Enable Hold Time Min 0 0 0 0 0 ns tWLWH tWP Write Pulse Width Min 45 45 50 60 60 ns tWHWL tWPH Write Pulse Width HIGH M i n 2 02 02 02 02 0n s tWHWH1 Duration of Programming Operation (Note 2) M i n 1 01 01 01 01 0µ s tWHWH2 Duration of tVPEL VPP Setup Time to Chip Enable LOW (Note 4) Min 100 100 100 100 100 ns tVCS VCC Set-up Time to Chip Enable LOW (Note 4) M i n 5 05 05 05 05 0µ s tVPPR VPP Rise Time 90% V PPH (Note 4) Min 500 500 500 500 500 ns tVPPF VPP Fall Time 10% V PPL (Note 4) Min 500 500 500 500 500 ns tLKO VCC < VLKO to Reset (Note 4) Min 100 100 100 100 100 ns

28 Am28F256

Figure 7. AC Waveforms for Read Operations

Figure 8. AC Waveforms for Erase Operations

30 Am28F256

Figure 9. AC Waveforms for Programming Operations

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. 25°C, 12 V VPP. 2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count (Flasherase = 1000 max and Flashrite = 25 max). T ypical worst case for program and erase is significantly less than the actual device limit. LATCHUP CHARACTERISTICS PIN CAPACITANCE Note: Sampled, not 100% tested. T est conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Limits CommentsMin Typ (Note 1) Max (Note 2) Unit Chip Erase Time 1 10 sec Excludes 00h programming prior to erasure Chip Programming Time 0.5 3 sec Excludes system-level overhead Write/Erase Cycles 10,000 Cycles Min Max Input Voltage with respect to V SS on all pins except I/O pins (Including A9 and VPP ) –1.0 V 13.5 V Input Voltage with respect to VSS on all pins I/O pins –1.0 V V CC + 1.0 V Current –100 mA +100 mA Includes all pins except VCC . T est conditions: VCC = 5.0 V , one pin at a time. Parameter Symbol Parameter Description Test Conditions Typ Max Unit C IN Input Capacitance V IN = 0 8 10 pF C OUT Output Capacitance V OUT = 0 8 12 pF C IN2 VPP Input Capacitance V PP = 0 8 12 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

32 Am28F256

PD032—32-Pin Plastic DIP (measured in inches) PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches) Pin 1 I.D. 1.640 1.670 .530 .580 .005 MIN .045 .065 .090 .110 .140 .225 .120 .160 .016 .022 SEATING PLANE .015 .060 16-038-S_AG PD 032 EC75 5-28-97 lv 32 17 16 .630 .700 10° .600 .625 .009 .015 .050 REF..026 .032 TOP VIEW Pin 1 I.D. .485 .495.447 .453 .585 .595 .547 .553 16-038FPO-5 PL 032 DA79 6-28-94 ae SIDE VIEW SEATING PLANE .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 REF. .490 .530

TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 18.30 18.50 7.90 8.10 0.50 B 0.05 0.15 0.95 1.05 16-038-TSOP-2 TS 032 DA95 3-25-97 lv 19.80 20.20 1.20 MAX 0.50 0.70 0.10 0.21 0.08 0.20

34 Am28F256

TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) 18.30 18.50 19.80 20.20 7.90 8.10

0.50 BSC

0.05 0.15 0.95 1.05 16-038-TSOP-2 TSR032 DA95 3-25-97 lv Pin 1 I.D. 1.20 MAX 0.50 0.70 0.10 0.21 0.08 0.20

DATA SHEET REVISION SUMMARY FOR AM28F256 Revision G Deleted -75, -95, and -250 speed options. Matched for- matting to other current data sheets. Revision G+1 Figure 3, Flashrite Programming Algorithm: Moved end of arrow originating from Increment Address box so that it points to the PLSCNT = 0 box, not the Write Pro- gram Verify Command box. This is a correction to the diagram on page 6-189 of the 1998 Flash Memory Data Book. Revision G+2 Programming In A PROM Programmer: Deleted the paragraph “(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ MODE section for programming the Flash memory de- vice in-system).” Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. ExpressFlash is a trademark of Advanced Micro Devices, Inc. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.