28C256

CAT28C256 CATALYST | Alldatasheet

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Technical content

FEATURES

n Fast Read Access Times: 120/150ns n Low Power CMOS Dissipation: –Active: 25 mA Max. –Standby: 150 µA Max. n Simple Write Operation: –On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear n Fast Write Cycle Time: –5ms Max n CMOS and TTL Compatible I/O n Hardware and Software Write Protection n Automatic Page Write Operation: –1 to 64 Bytes in 5ms –Page Load Timer n End of Write Detection: –Toggle Bit –DATA Polling n 100,000 Program/Erase Cycles n 100 Year Data Retention n Commerical, Industrial and Automotive Temperature Ranges

DESCRIPTION

The CAT28C256 is a fast, low power, 5V-only CMOS parallel E 2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto- clear and V CC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self- timed write cycle. Additionally, the CAT28C256 features hardware and software write protection. The CAT28C256 is manufactured using Catalyst’s ad- vanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages. BLOCK DIAGRAM

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© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ADDR. BUFFER & LATCHES ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION CONTROL LOGIC TIMER ROW DECODER COLUMN DECODER HIGH VOLTAGE GENERATOR A6–A14 CE OE WE A0–A5 I/O0–I/O7 I/O BUFFERS 32,768 x 8 E2PROM ARRAY

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Doc. No. 25020-0A 2/98

2Doc. No. 25020-0A 2/98

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22 I/O7

A0–A14 Address Inputs I/O0–I/O7 Data Inputs/Outputs CE Chip Enable OE Output Enable Pin Name Function WE Write Enable VCC 5V Supply VSS Ground NC No Connect

3 Doc. No. 25020-0A 2/98 D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC VCC Current (Operating, TTL) 30 mA CE = OE = V IL, f=8MHz All I/O’s Open ICCC (5) VCC Current (Operating, CMOS) 25 mA CE = OE = V ILC, f=8MHz All I/O’s Open ISB VCC Current (Standby, TTL) 1 mA CE = V IH, All I/O’s Open ISBC (6) VCC Current (Standby, CMOS) 150 µA CE = V IHC, All I/O’s Open ILI Input Leakage Current –10 10 µAV IN = GND to VCC ILO Output Leakage Current –10 10 µAV OUT = GND to VCC , CE = VIH VIH(6) High Level Input Voltage 2 V CC +0.3 V VIL(5) Low Level Input Voltage –0.3 0.8 V VOH High Level Output Voltage 2.4 V I OH = –400µA VOL Low Level Output Voltage 0.4 V I OL = 2.1mA VWI Write Inhibit Voltage 3.5 V *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Test Method N END (1) Endurance 10 4 or 105 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (1) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (1)(4) Latch-Up 100 mA JEDEC Standard 17 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V CC +1V. (5) VILC = –0.3V to +0.3V. (6) VIHC = VCC –0.3V to VCC +0.3V.

4Doc. No. 25020-0A 2/98 28C256-12 28C256-15 Symbol Parameter Min. Max. Min. Max. Units tRC Read Cycle Time 120 150 ns tCE CE Access Time 120 150 ns tAA Address Access Time 120 150 ns tOE OE Access Time 50 70 ns tLZ(1) CE Low to Active Output 0 0 ns tOLZ (1) OE Low to Active Output 0 0 ns tHZ (1)(2) CE High to High-Z Output 50 50 ns tOHZ (1)(2) OE High to High-Z Output 50 50 ns tOH (1) Output Hold from Address Change 0 0 ns MODE SELECTION Mode CE WE OE I/O Power Read L H L D OUT ACTIVE Byte Write (WE Controlled) L H D IN ACTIVE Byte Write (CE Controlled) L H D IN ACTIVE Standby, and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions C I/O(1) Input/Output Capacitance 10 pF V I/O = 0V C IN(1) Input Capacitance 6 pF V IN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. A.C. CHARACTERISTICS, Read Cycle VCC =5V + 10%, Unless otherwise specified

(1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) A write pulse of less than 20ns duration will not initiate a write cycle. however a transition from HIGH to LOW within tBLC max. stops the timer.

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Figure 1. A.C. Testing Input/Output Waveform(2) Figure 2. A.C. Testing Load Circuit (example)

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data is written within 5 ms. Figure 3. Read Cycle Figure 4. Byte Write Cycle [WE Controlled]

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limitation as long as WE is pulsed low within tBLC MAX . will not rewrite the entire page. Figure 5. Byte Write Cycle [CE Controlled]

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Figure 6. Page Mode Write Cycle

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tures that are incorporated into the CAT28C256. inputs will not result in a write cycle. in the standard operating mode). Figure 9. Write Sequence for Activating Software Figure 10. Write Sequence for Deactivating

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10Doc. No. 25020-0A 2/98 To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transi- tions. This gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided. To allow the user the ability to program the device with an E 2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing

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Figure 12. Resetting Software Data Protection Timing

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ORDERING INFORMATION

Notes: (1) The device used in the above example is a CAT28C256HNI-15T (100,000 Cycle Endurance, PLCC, Industrial temperature, 150ns Access Time, Tape & Reel). 28C256 F16 Speed 12: 120ns 15: 150ns Prefix Device # Suffix 28C256 Product Number CAT Optional Company ID NI T Tape & Reel T: 500/Reel Package P: PDIP N: PLCC T13: TSOP (8mmx13.4mm) -15 Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* H Endurance Blank = 10,000 Cycle H = 100,000 Cycle * -40˚C to +125˚C is available upon request