CAT25C32 CATALYST | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 9
Technical content
32K/64K-Bit SPI Serial CMOS E2PROM
FEATURES
n 1.8 to 6.0 Volt Operation n Hardware and Software Protection n Zero Standby Current n Low Power CMOS Technology n SPI Modes (0,0 &1,1) n Commercial, Industrial and Automotive Temperature Ranges n 1,000,000 Program/Erase Cycles n 100 Year Data Retention n Self-Timed Write Cycle n 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOPand 20-Pin TSSOP n 64-Byte Page Write Buffer n Block Write Protection – Protect 1/4, 1/2 or all of E 2PROM Array PIN CONFIGURATION PIN FUNCTIONS Pin Name Function SO Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input NC No Connect BLOCK DIAGRAM © 1999 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Advanced Information
DESCRIPTION
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS E 2PROM internally organized as 4Kx8/8Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C32/ 64 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C32/64 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages. Doc No. 25087-00 8/99 SPI-1 SENSE AMPS SHIFT REGISTERS SPI CONTROL LOGIC WORD ADDRESS BUFFERS I/O CONTROL E2PROM ARRAY COLUMN DECODERS XDEC HIGH VOLTAGE/ TIMING CONTROL SO STATUS REGISTER BLOCK PROTECT LOGIC CONTROL LOGIC DATA IN STORAGE SI CS WP HOLD SCK SO WP CS VCC HOLD SCK SI VSS VSS SO WP VCC HOLD SCK SI CS NC NC CS WP HOLD HOLD VCC NC NC NC NC NC NC SO NC NC SO VSS SCK SI 10 11 CS WP HOLD VCC NC NC NC NC SO NC NC VSS SCK SI 7 8
Doc. No. 25087-00 8/99 SPI-1 Advanced Information D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current 10 mA V CC = 5V @ 10MHz (Operating Write) SO=open; CS=Vss ICC2 Power Supply Current 2 mA V CC = 5.0V (Operating Read) F CLK = 10MHz ISB Power Supply Current 0 µA CS = VCC (Standby) V IN = VSS or VCC ILI Input Leakage Current 2 µA ILO Output Leakage Current 3 µAV OUT = 0V to VCC , CS = 0V VIL(3) Input Low Voltage -1 V CC x 0.3 V VIH(3) Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage 0.4 V VOH1 Output High Voltage V CC - 0.8 V VOL2 Output Low Voltage 0.2 V 1.8V ≤VCC <2.7V VOH2 Output High Voltage V CC -0.2 V I OL = 150µA IOH = -100µA ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method N END (3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (3)(4) Latch-Up 100 mA JEDEC Standard 17 Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. 4.5V≤VCC <5.5V IOL = 3.0mA IOH = -1.6mA
(1) This parameter is tested initially and after a design or process change that affects the parameter. Figure 1. Sychronous Data Timing
Doc. No. 25087-00 8/99 SPI-1 Advanced Information FUNCTIONAL DESCRIPTION The CAT25C32/64 supports the SPI bus data transmis- sion protocol. The synchronous Serial Peripheral Inter- face (SPI) helps the CAT25C32/64 to interface directly with many of today’s popular microcontrollers. The CAT25C32/64 contains an 8-bit instruction register. (The instruction set and the operation codes are de- tailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. PIN DESCRIPTION SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C32/64. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C32/64. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchro- nize the communication between the microcontroller and the 25C32/64. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. CSCSCSCSCS: Chip Select CS is the Chip select pin. CS low enables the CAT25C32/ 64 and CS high disables the CAT25C32/64. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway). The CAT25C32/64 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WPWPWPWPWP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. HOLDHOLDHOLDHOLDHOLD: Hold The HOLD pin is used to pause transmission to the CAT25C32/64 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to V cc or tied to Vcc through a resistor. Figure 9 illustrates hold timing sequence. Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory INSTRUCTION SET
Doc No. 25087 -00 8/99 SPI-1 Advanced Information Status Register Bits Array Address Protection BP1 BP0 Protected 0 0 None No Protection 0 1 25C32: 0C00-0FFF Quarter Array Protection 25C64:1800-1FFF 1 0 25C32: 800-0FFF Half Array Protection 25C64:1000-1FFF 1 1 25C32: 0000-0FFF Full Array Protection 25C64:0000-1FFF BLOCK PROTECTION BITS Protected Unprotected Status WPEN WPWPWPWPWP WEL Blocks Blocks Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected X High 1 Protected Writable Writable WRITE PROTECT ENABLE OPERATION 76543210 WPEN X X X BP1 BP0 WEL RDY STATUS REGISTER STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C32/ 64 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect fea- ture. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write pro- tected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero.
Figure 4. Read Instruction Timing 6 illustrates byte write sequence. The CAT25C32/64 powers up in a Write Disable state. selected by the block protection level. Figure 5. RDSR Instruction Timing