CAT24WC01 CATALYST | Alldatasheet
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Technical content
1K/2K/4K/8K/16K-Bit Serial E2PROM * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. PIN CONFIGURATION BLOCK DIAGRAM PIN FUNCTIONS Pin Name Function A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground 24WCXX F03
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FEATURES
I 400 KHZ I2C Bus Compatible* I 1.8 to 6.0Volt Operation I Low Power CMOS Technology I Write Protect Feature — Entire Array Protected When WP at VIH I Page Write Buffer I Self-Timed Write Cycle with Auto-Clear I 1,000,000 Program/Erase Cycles I 100 Year Data Retention I 8-pin DIP, 8-pin SOIC or 8 pin TSSOP I Commercial, Industrial and Automotive Temperature Ranges
DESCRIPTION
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K- bit Serial CMOS E 2PROM internally organized as 128/ 256/512/1024/2048 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces de- vice power requirements. The the CAT24WC01/02/04/ 08/16 feature a 16-byte page write buffer. The device operates via the I 2C bus serial interface, has a special write protection feature, and is available in 8-pin DIP, 8- pin SOIC or 8-pin TSSOP. © 1999 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice VCC WP SCL SDA VSS (* Available for 24WC01 and 24WC02 only) D OUT ACK SENSE AMPS SHIFT REGISTERS CONTROL LOGIC WORD ADDRESS BUFFERS START/STOP LOGIC STATE COUNTERS SLAVE ADDRESS COMPARATORS E2PROM VCC EXTERNAL LOAD COLUMN DECODERS XDEC DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL VSS WP SCL SDA VSS VCC WP SCL SDA A0 VCC WP SCL SDA VSS Doc. No. 25051-00 3/98 S-1
2Doc. No. 25051-00 3/98 S-1 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method N END (3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (3)(4) Latch-up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC Power Supply Current 3 mA f SCL = 100 KHz ISB (5) Standby Current (VCC = 5.0V) 0 µAV IN = GND or VCC ILI Input Leakage Current 10 µAV IN = GND to VCC ILO Output Leakage Current 10 µAV OUT = GND to VCC VIL Input Low Voltage –1 V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage (VCC = 3.0V) 0.4 V I OL = 3 mA VOL2 Output Low Voltage (VCC = 1.8V) 0.5 V I OL = 1.5 mA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. (5) Standby Current (ISB ) = 0µA (<900nA). CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions C I/O(3) Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN(3) Input Capacitance (A0, A1, A2, SCL, WP) 6 pF V IN = 0V
3 Doc. No. 25051-00 3/98 S-1 A.C. CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Read & Write Cycle Limits Symbol Parameter 1.8V, 2.5V 4.5V-5.5V Min. Max. Min. Max. Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time 200 200 ns Constant at SCL, SDA Inputs tAA SCL Low to SDA Data Out 3.5 1 µs and ACK Out tBUF (1) Time the Bus Must be Free Before 4.7 1.2 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4 0.6 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 50 50 ns tR (1) SDA and SCL Rise Time 1 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4 0.6 µs tDH Data Out Hold Time 100 100 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Write Cycle Limits Symbol Parameter Min. Typ. Max Units tWR Write Cycle Time 10 ms Power-Up Timing(1)(2) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms
determined by the device address inputs A0, A1, and A2. used to clock all data transfers into or out of the device. default values are zeros (except for the 24WC01). Figure 2. Write Cycle Timing Figure 1. Bus Timing Figure 3. Start/Stop Timing
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Only two devices can be cascaded when using 24WC08. tions are allowed to the device. interpreted as a START or STOP condition. whether a Read or Write operation is to be performed. and when set to 0, a Write operation is selected. Figure 4. Acknowledge Timing
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cycle, signaling that it received the 8 bits of data. after receiving each 8-bit byte. respond to any request from the Master device. Figure 5. Slave Address Bits
- A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8, a9 and a10 correspond to the address of the memory array address word. *** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
Figure 7. Page Write Timing
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Figure 6. Byte Write Timing the CAT24WC01/02/04/08/16 in a single write cycle. thenext read or write operation. against inadvertent programming of the memory array. edge after the first byte of data is received. with the one exception that the R/W bit is set to a one.
acknowledge but will generate a STOP condition. knowledge but will generate a STOP condition. around” and continue to clock out data bytes.
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Figure 8. Immediate Address Read Timing
9 Doc. No. 25051-00 3/98 S-1 24WCXX F14 Notes: (1) The device used in the above example is a 24WC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel)
ORDERING INFORMATION
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Figure 10. Sequential Read Timing Figure 9. Selective Read Timing