CAT24C321 CATALYST | Alldatasheet
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Technical content
CAT24C321/322(32K), CAT24C641/642(64K) Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
DESCRIPTION
The CAT24CXXX is a single chip solution to three popular functions of EEPROM memory, precision reset controller and watchdog timer. The 24C321/322(32K) and 24C641/642(64K) feature a I 2C Serial CMOS EEPROM. Catalyst's advanced CMOS technology sub- stantially reduces device power requirements. The 24CXXX features a 32-byte page and is available in 8-pin DIP or 8-pin SOIC packages. The reset function of the 24CXXX protects the system during brown out and power up/down conditions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. 24CXXX features active low reset on pin 2 and active high reset on pin 7. 24C321/641 features watchdog timer on the SDA line. 24C322/642 does not feature the watchdog timer func- tion. Pin Name Function SDA Serial Data/Address RESET/ RESET Reset I/O SCL Clock Input Vcc Power Supply DC Do not Connect VSS Ground WP Write Protect PIN FUNCITONS PIN CONFIGURATION 24C321/322* 24C641/642* BLOCK DIAGRAM *All products offered in P and J packages Advanced
FEATURES
© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice n Watchdog Timer on SDA for 24C321/641 n Programmable Reset Threshold n 400 KHz I2C Bus Compatible n 2.7 to 6 Volt Operation n Low Power CMOS Technology n 32 - Byte Page Write Buffer n Built-in inadvertent write protection — VCC Lock Out n Active High or Low Reset Outputs — Precision Power Supply Voltage Monitoring 5V, 3.3V and 3V options n 1,000,000 Program/Erase Cycles n 100 Year Data Retention n 8-Pin DIP or 8-Pin SOIC n Commercial, Industrial and Automotive Temperature Ranges Doc. No. 25083-00 12/98 DC VCC RESET SCL SDA RESET WP VSS D OUT ACK SENSE AMPS SHIFT REGISTERS CONTROL LOGIC WORD ADDRESS BUFFERS START/STOP LOGIC E2PROM VCC EXTERNAL LOAD COLUMN DECODERS XDEC DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL VSS WP SDA RESET Controller High Precision Vcc Monitor STATE COUNTERS SLAVE ADDRESS COMPARATORS SCL Only for 24C321/641 RESET/ RESET WATCHDOG
Doc. No. 25083-00 12/98 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method NEND (3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (3)(4) Latch-up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +2.7V to +6.0V, unless otherwise specified. Symbol Parameter Min. Typ. Max. Units Test Conditions ICC Power Supply Current 3 mA f SCL = 100 KHz Isb Standby Current 40 µA Vcc=3.3V 50 µA Vcc=5 ILI Input Leakage Current 2 µA VIN=G ND or VCC ILO Output Leakage Current 10 µA VIN=G ND or VCC VIL Input Low Voltage –1 VCC x 0.3 V VIH Input High Voltage V CC x 0.7 VCC + 0.5 V VOL Output Low Voltage (SDA) 0.4 V IOL = 3 mA ,VCC =3.0V Limits CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(3) Input/Output Capacitance (SDA) 8 pF V I/O = 0V CIN(3) Input Capacitance (SCL) 6 pF V IN = 0V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.
Doc. No. 25083-00 12/98 A.C. CHARACTERISTICS VCC =2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter V CC =2.7V - 6V V CC =4.5V - 5.5V Min. Max. Min. Max. Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time 200 200 ns Constant at SCL, SDA Inputs tAA SCL Low to SDA Data Out 3.5 1 µs and ACK Out tBUF (1) Time the Bus Must be Free Before 4.7 1.2 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4 0.6 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 50 50 ns tR (1) SDA and SCL Rise Time 1 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4 0.6 µs tDH Data Out Hold Time 100 100 ns Power-Up Timing(1)(2) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Write Cycle Limits Symbol Parameter Min. Typ. Max Units tWR Write Cycle Time 10 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Doc. No. 25083-00 12/98 Symbol Parameter Min. Max. Units tGLITCH Glitch Reject Pulse Width 100 ns VRT Reset Threshold Hystersis 15 mV VOLRS Reset Output Low Voltage (IOLRS =1mA) 0.4 V VOHRS Reset Output High Voltage Vcc-0.75 V Reset Threshold (Vcc=5V) 4.50 4.75 (24CXXX-45) Reset Threshold (Vcc=5V) 4.25 4.50 (24CXXX-42) Reset Threshold (Vcc=3.3V) 3.00 3.15 (24CXXX-30) Reset Threshold (Vcc=3.3V) 2.85 3.00 (24CXXX-28) Reset Threshold (Vcc=3V) 2.55 2.70 (24CXXX-25) tPURST Power-Up Reset Timeout 130 270 ms tRPD VTH to RESET Output Delay 5 µs VRVALID RESET Output Valid 1 V RESET CIRCUIT CHARACTERISTICS V VTH
24CXXX will initiate a reset timeout after detecting a low. time-out interval of 1.6 seconds for lack of activity. dog Timer is cleared by any transition on SDA. does not feature the Watchdog Timer function. Figure 1. RESET Output Timing
Figure 9. Immediate Address Read Timing the next read or write operation. against inadvertent programming of the memory array. after the first byte of data is received. READ, Selective/Random READ and Sequential READ.
Doc. No. 25083-00 12/98
Ordering Information
Note: (1) The device used in the above example is a CAT24C322JI-30TE13 (32K I2C Memory, SOIC, Industrial Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel) 24C322 Temperature Range Blank = Commercial (0˚ to 70˚C) I = Industrial (-40˚ to 85˚C) A = Automotive (-40˚to +105˚C)* * -40˚ to +125˚C is available upon request Prefix Device # Suffix J I TE13 Product Number 24C321: 32K 24C322: 32K 24C641: 64K 24C642: 64K Tape & Reel TE13: 2000/Reel Package P: PDIP J: SOIC (JEDEC) -30CAT Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V Optional Company ID
Doc. No. 25083-00 12/98