24C44

CAT24C44 CATALYST | Alldatasheet

Document overview

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Technical content

256-Bit Serial Nonvolatile CMOS Static RAM

FEATURES

n Infinite E2PROM to RAM Recall n CMOS and TTL Compatible I/O n Low CMOS Power Consumption: –Active: 3 mA Max. –Standby: 30 µA Max. n Power Up/Down Protection n 10 Year Data Retention n JEDEC Standard Pinouts: –8-pin DIP –8-pin SOIC n 100,000 Program/Erase Cycles (E2PROM) n Auto Recall on Power-up n Commercial, Industrial and Automotive Temperature Ranges

DESCRIPTION

The CAT24C44 Serial NVRAM is a 256-bit nonvolatile memory organized as 16 words x 16 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile E 2PROM array which allows for easy trans- fer of data from RAM array to E2PROM (STORE) and from E2PROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typically within 1.5µs. The CAT24C44 features unlimited RAM write operations either through external RAM writes or internal recalls from E 2PROM. Internal false PIN CONFIGURATION store protection circuitry prohibits STORE operations when V CC is less than 3.5V (typical) ensuring E2PROM data integrity. The CAT24C44 is manufactured using Catalyst’s ad- vanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles (E 2PROM) and has a data retention of 10 years. The device is available in JEDEC approved 8-pin plastic DIP and SOIC pack- ages. PIN FUNCTIONS Pin Name Function SK Serial Clock DI Serial Input DO Serial Data Output CE Chip Enable RECALL Recall STORE Store VCC +5V VSS Ground DI DO CE SK RECALL VSS VCC STORE CE SK DI DO VCC RECALL VSS STORE

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© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 25019-0A 2/98 N-1

Doc. No. 25019-0A 2/98 N-1 POWER-UP TIMING (4) Symbol Parameter Min. Max. Units VCCSR V CC Slew Rate 0.5 0.005 V/m tpur Power-Up to Read Operations 200 µs tpuw Power-Up to Write or Store Operation 5 ms MODE SELECTION (1)(2) Software Write Enable Previous Recall Mode STORESTORESTORESTORESTORE RECALLRECALLRECALLRECALLRECALL Instruction Latch Latch Hardware Recall(3) 1 0 NOP X X Software Recall 1 1 RCL X X Hardware Store(3) 0 1 NOP SET TRUE Software Store 1 1 STO SET TRUE X = Don’t Care BLOCK DIAGRAM

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Note: (1) The store operation has priority over all the other operations. (2) The store operation is inhibited when V CC is below ≈ 3.5V. (3) NOP designates that the device is not currently executing an instruction. (4) This parameter is tested initially and after a design or process change that affects the parameter.

3 Doc. No. 25019-0A 2/98 N-1 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method N END (1) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (1) Data Retention 10 Years MIL-STD-883, Test Method 1008 VZAP (1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (1)(4) Latch-Up 100 mA JEDEC Standard 17 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Parameter Max. Unit Conditions C I/O(1) Input/Output Capacitance 10 pF V I/O = 0V C IN(1) Input Capacitance 6 pF V IN = 0V D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Unit Conditions ICCO Current Consumption (Operating) 3 mA Inputs = 5.5V, T A = 0°C All Outputs Unloaded ISB Current Consumption (Standby) 30 µA CE = V IL ILI Input Current 2 µA0 ≤ VIN ≤ 5.5V ILO Output Leakage Current 10 µA0 ≤ VOUT ≤ 5.5V VIH High Level Input Voltage 2 V CC V VIL Low Level Input Voltage 0 0.8 V VOH High Level Output Voltage 2.4 V I OH = –2mA VOL Low Level Output Voltage 0.4 V I OL = 4.2mA

Doc. No. 25019-0A 2/98 N-1 A.C. CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Symbol Parameter Min. Max. Units Conditions FSK SK Frequency DC 1 MHz tSKH SK Positive Pulse Width 400 ns tSKL SK Negative Pulse Width 400 ns C L = 100pF + 1TTL gate tDS Data Setup Time 400 ns V OH = 2.2V, VOL = 0.65V tDH Data Hold Time 80 ns V IH = 2.2V, VIL = 0.65V tPD SK Data Valid Time 375 ns Input rise and fall times = 10ns tZ CE Disable Time 1 µs tCES CE Enable Setup Time 800 ns tCEH CE Enable Hold Time 400 ns tCDS CE De-Select Time 800 ns A.C. CHARACTERISTICS, Store Cycle VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Max. Units Conditions tST Store Time 10 ms C L = 100pF + 1TTL gate tSTP Store Pulse Width 200 ns V OH = 2.2V, VOL = 0.65V tSTZ Store Disable Time 100 ns V IH = 2.2V, VIL = 0.65V A.C. CHARACTERISTICS, Recall Cycle VCC = 5V ±10%, unless otherwise specified. Symbol Parameter Min. Max. Units Conditions tRCC Recall Cycle Time 2.5 µs tRCP Recall Pulse Width 500 ns C L = 100pF + 1TTL gate tRCZ Recall Disable Time 500 ns V OH = 2.2V, VOL = 0.65V tORC Recall Enable Time 10 ns V IH = 2.2V, VIL = 0.65V tARC Recall Data Access Time 1.5 µs INSTRUCTION SET Format Instruction Start Bit Address OP Code Operation WRDS 1 XXXX 0 0 0 Reset Write Enable Latch (Disables, Writes and Stores) STO 1 XXXX 0 0 1 Store RAM Data in E 2PROM WRITE 1 AAAA 0 1 1 Write Data into RAM Address AAAA WREN 1 XXXX 1 0 0 Set Write Enable Latch (Enables, Writes and Stores) RCL 1 XXXX 1 0 1 Recall E 2PROM Data into RAM READ 1 AAAA 1 1 X Read Data From RAM Address AAAA X = Don’t care A = Address bit

pin must remain high during the entire data transfer. in the instructions, will be clocked out of the device. Figure 1. RAM Read Cycle Timing

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(1) Bit 8 of READ instruction is “Don’t Care”. Figure 2. RAM Write Cycle Timing

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1 D 1 D 2 D 3 D 13 D 14 D 15A1 1AAA 0

2PROM store enable) instruction.

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Figure 4. Write Cycle Timing Figure 3. Read Cycle Timing

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less of the “write enable latch” status.

• The “previous recall” latch must be set (either a software or hardware recall operation).
• The “write enable” latch must be set (WREN instruction issued).
• STO instruction issued or STORE input low. During the store operation, all other CAT24C44 func- tions are inhibited. Upon completion of the store opera- tion, the “write enable” latch is reset. The device also provides false store protection whenever V CC falls below a 3.5V level. If VCC falls below this level, the store operation is disabled and the “write enable” latch is reset.

Figure 6. Hardware Store Cycle Timing

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Figure 5. Recall Cycle Timing

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Doc. No. 25019-0A 2/98 N-1 Figure 7. Non-Data Operations

1 XXXX

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ORDERING INFORMATION

Notes: (1) The device used in the above example is a 24C44SI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Prefix Device # Suffix 24C44 S I -TE13 Product Number Tape & Reel TE13: 2000/Reel Package P: PDIP S: SOIC (JEDEC) CAT Temperature Range Blank = Commercial (0˚ - 70˚C) I = Industrial (-40˚ - 85˚C) A = Automotive (-40˚ - 105˚C)* * -40˚ to +125˚C is available upon request Optional Company ID