20V8

PALCE20V8 CYPRESS | Alldatasheet

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Features

• Active pull-up on data input pins  Low power version (20V8L) — 55 mA max. commercial (15, 25 ns) — 65 mA max. military/industrial (15, 25 ns)  Standard version has low power — 90 mA max. commercial (15, 25 ns) — 115 mA max. commercial (10 ns) — 130 mA max. military/industrial (15, 25 ns)  CMOS Flash technology for electrical erasability and reprogrammability  User-programmable macrocell — Output polarity control — Individually selectable for registered or combinato- rial operation  QSOP package available — 10, 15, and 25 ns com’l version — 15, and 25 ns military/industrial versions  High reliability — Proven Flash technology — 100% programming and functional testing Functional Description The Cypress PALCE20V8 is a CMOS Flash Erasable sec- ond-generation programmable array logic device. It is imple- mented with the familiar sum-of-product (AND-OR) logic struc- ture and the programmable macrocell. The PALCE20V8 is executed in a 24-pin 300-mil molded DIP , a 300-mil cerdip, a 28-lead square ceramic leadless chip car- rier, a 28-lead square plastic leaded chip carrier, and a 24-lead quarter size outline. The device provides up to 20 inputs and 8 outputs. The PALCE20V8 can be electrically erased and re- programmed. The programmable macrocell enables the de- vice to function as a superset to the familiar 24-pin PLDs such as 20L8, 20R8, 20R6, 20R4. PAL is a registered trademark of Advanced Micro Devices, Inc. Logic Block Diagram (PDIP/CDIP/QSOP) 20V8–1 88 88 8 88 8 1 098 7 65 432 1 13 15 16 17 18 19 20 21 22 23 PROGRAMMABLE AND ARRAY (64 x40) Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell I9 I8 I7 I6 I5 I4 I3 I2 I1 CLK/I0 OE/I11 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I13 GND I10 MUX VCC MUX I12

Document #: 38-03026 Rev. ** Page 2 of 14 Shaded area contains preliminary information. Functional Description (continued) The PALCE20V8 features 8 product terms per output and 40 input terms into the AND array. The first product term in a mac- rocell can be used either as an internal output enable control or as a data product term. There are a total of 18 architecture bits in the PALCE20V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are select- able from either the input/output pin associated with the mac- rocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself. Power-Up Reset All registers in the PALCE20V8 power-up to a logic LOW for predictable system initialization. For each register, the associ- ated output pin will be HIGH due to active-LOW outputs. Electronic Signature An electronic signature word is provided in the PALCE20V8 that consists of 64 bits of programmable memory that can con- tain user-defined data. Security Bit A security bit is provided that defeats the readback of the in- ternal programmed pattern when the bit is programmed. Low Power The Cypress PALCE20V8 provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each prod- uct term. The PTD fuses allow each product term to be individ- ually disabled. Input and I/O Pin Pull-Ups The PALCE20V8 input and I/O pins have built-in active pull-ups that will float unused inputs and I/Os to an active HIGH state (logical 1). All unused inputs and three-stated I/O pins should be connected to another active input, V CC , or Ground to improve noise immunity and reduce ICC . Pin Configuration PLCC/LCC Top View 20V8–2 DIP/QSOP Top View 11 121314 1516 1718 4 3 2 2827 26 I I CLK/I V I I/O CC

1 NC1

20V8–3 I10 NC I/O2 I/O1 I/O6 I/O5 I/O3 I/O4 NC I GND NC OE/I I I/O Selection Guide Generic Part Number tPD ns tS ns tCO ns ICC mA Com ’l/Ind Mil Com ’l/Ind Mil Com ’l/Ind Mil Com ’l Mil/Ind PALCE20V8 −5 5 3 4 115 PALCE20V8 −7 7.5 7 5 115 PALCE20V8 −10 10 10 10 10 7 10 115 130 PALCE20V8 −15 15 15 12 12 10 12 90 130 PALCE20V8 −25 25 25 15 20 12 20 90 130 PALCE20V8L −15 15 15 12 12 10 12 55 65 PALCE20V8L −25 25 25 15 20 12 20 55 65

Document #: 38-03026 Rev. ** Page 3 of 14 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Ambient Temperature with Supply Voltage to Ground Potential DC Voltage Applied to Outputs Configuration Table CG 0 CG 1 CL0 x Cell Configuration Devices Emulated 0 1 0 Registered Output Registered Med PALs 0 1 1 Combinatorial I/O Registered Med PALs 1 0 0 Combinatorial Output Small PALs 1 0 1 Input Small PALs 1 1 1 Combinatorial I/O 20L8 only Macrocell Q QD CLK 20V8–4 X CL1 x X 1 1 I/Ox From Adjacent PinCL0 xCG 1 for pin 16 to 21 (DIP) CG 0 for pin 15 and 22(DIP) 1 1 0 0 X 1 1 OE VCC To Adjacent Macrocell CL0 x CG 1 VCC Operating Range Range Ambient Temperature VCC Commercial 0°C to +75°C 5V ±5% Industrial −40°C to +85°C 5V ±10% Military[1] −55°C to +125°C 5V ±10% Note: 1. T A is the “instant on” case temperature.

Document #: 38-03026 Rev. ** Page 4 of 14 Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = −3.2 mA Com ’l 2.4 V IOH = −2 mA Mil/Ind VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 24 mA Com ’l 0.5 V IOL = 12 mA Mil/Ind VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[3] 2.0 V VIL[4] Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[3] −0.5 0.8 V IIH Input or I/O HIGH Leakage Current 3.5V < VIN < VCC 10 µA IIL [5] Input or I/O LOW Leakage Current 0V < VIN < VIN (Max.) −100 µA ISC Output Short Circuit CurrentVCC = Max., VOUT = 0.5V[6,7] −30 −150 mA ICC Operating Power Supply Current VCC = Max., VIL = 0V, VIH = 3V, Output Open, f = 15 MHz (counter) 5, 7, 10 ns Com ’l 115 mA 15, 25 ns 90 mA 15L, 25L ns 55 mA 10, 15, 25 ns Mil/Ind 130 mA 15L, 25L ns Mil/Ind 65 mA Capacitance[7] Parameter Description Test Conditions Typ. Unit C IN Input Capacitance VIN = 2.0V @ f = 1 MHz 5 pF C OUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 5 pF Endurance Characteristics[7] Parameter Description Test Conditions Min. Max. Unit N Minimum Reprogramming Cycles Normal Programming Conditions 100 Cycles Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. V IL (Min.) is equal to −3.0V for pulse durations less than 20 ns. 5. The leakage current is due to the internal pull-up resistor on all pins. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-03026 Rev. ** Page 5 of 14 AC Test Loads and Waveforms 90% 10% 3.0V GND 90% 10% ALL INPUT PULSES 2n s ≤ 2n s 20V8–5 OUTPUT C L TEST POINT 20V8–6 Specification S1 C L Commercial Military Measured Output ValueR 1 R 2 R 1 R 2 tPD , tCO Closed 50 pF 200Ω 390Ω 390Ω 750Ω 1.5V tPZX, tEA Z ➧ H: Open Z ➧ L: Closed 1.5V tPXZ, tER H ➧ Z: Open L ➧ Z: Closed 5 pF H ➧ Z: VOH − 0.5V L ➧ Z: VOL + 0.5V

Document #: 38-03026 Rev. ** Page 6 of 14 Commercial and Industrial Switching Characteristics[2] 20V8−52 0 V 8 −7 20V8−10 20V8−15 20V8−25 tPD Input to Output Propagation Delay[8] 1 51 7 . 5 1 10 1 15 1 25 ns tPZX OE to Output Enable 56 10 15 20 ns tPXZ OE to Output Disable 56 10 15 20 ns tEA Input to Output Enable Delay [7] 69 10 15 25 ns tER Input to Output Disable Delay[7,9] 69 10 15 25 ns tCO Clock to Output Delay[8] 1 415 1 7 1 10 1 12 ns tS Input or Feedback Set-Up Time 3 7 10 12 15 ns tH Input Hold Time 0 0 0 0 0 ns tP External Clock Period CO + tS) 7 12 17 22 27 ns tWH Clock Width HIGH[7] 3 5 8 8 12 ns tWL Clock Width LOW[7] 3 5 8 8 12 ns fMAX1 External Maximum Frequency (1/(tCO + tS))[7,10] 143 83 58 45.5 37 MHz fMAX2 Data Path Maximum Frequency (1/(t WH + tWL ))[7, 11] 166. 100 62.5 62.5 41.6 MHz fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[7,12] 166. 100 62.5 50 40 MHz tCF Register Clock to Feedback Input[7, 13] 33 6 8 10 ns tPR Power-Up Reset Time[7] 1 1 1 1 1 µs Shaded area contains preliminary information. Notes: 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. 10. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 11. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 13. This parameter is calculated from the clock period at fMAX internal (1/fMAX3 ) as measured (see Note 7 above) minus tS.

Document #: 38-03026 Rev. ** Page 7 of 14 Shaded area contains preliminary information. Military Switching Characteristics[2] Parameter Description 20V8−10 20V8−15 20V8−25 tPD Input to Output Propagation Delay[8] 11 0 1 15 1 25 ns tPZX OE to Output Enable 10 15 20 ns tPXZ OE to Output Disable 10 15 20 ns tEA Input to Output Enable Delay[7] 10 15 25 ns tER Input to Output Disable Delay[7,9] 10 15 25 ns tCO Clock to Output Delay[8] 11 0 1 12 1 20 ns tS Input or Feedback Set-Up Time 10 12 20 ns tH Input Hold Time 0 0 0 ns tP External Clock Period (tCO + tS)2 0 24 40 ns tWH Clock Width HIGH[7] 8 10 15 ns tWL Clock Width LOW[7] 8 10 15 ns fMAX1 External Maximum Frequency (1/(t CO + tS)[7,10] 50 41.7 25 MHz fMAX2 Data Path Maximum Frequency (1/(tWH + tWL ))[7, 11 ] 62.5 50 33.3 MHz fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[7,12] 62.5 50 33.3 MHz tCF Register Clock to Feedback Input [7, 13] 6 8 10 ns tPR Power-Up Reset Time[7] 1 1 1 µs

Document #: 38-03026 Rev. ** Page 8 of 14 Switching Waveform tS tH tWLtWH tPtCO tPD 20V8–7 tPXZ ,tER INPUTS, I/O, REGISTERED FEEDBACK CP REGISTERED OUTPUTS COMBINATORIAL OUTPUTS tPXZ ,tER tEA ,tPZX tEA ,tPZX [10] [10] [10] [10] Power-Up Reset Waveform tPR POWER CLOCK tS tWL 10% REGISTERED ACTIVE LOW OUTPUTS 20V8–8 SUPPLY VOLTAGE tPR MAX = 1 µs 90% VCC

Document #: 38-03026 Rev. ** Page 9 of 14 Functional Logic Diagram for PALCE20V8 1 (2) 16 20 24 28 1284 3 (4) 22 (26) 13 (16) 20V8–9 MC7 CL1=2560 CL0=2632 4 (5) 21 (25) MC6 CL1=2561 CL0=2633 5 (6) 20 (24) MC5 CL1=2562 CL0=2634 6 (7) 19 (23) MC4 CL1=2563 CL0=2635 7 (9) 18 (21) MC3 CL1=2564 CL0=2636 8 (10) 17 (20) MC2 CL1=2565 CL0=2637 9 (11) 16 (19) MC1 CL1=2566 CL0=2638 10 (12) 15 (18) MC0 CL1=2567 CL0=2639 ELECTRONIC SIGNATURE ROW MSB LSB CG 0=2704 CG 1=2705 23 (27) PIN NUMBERS DIP(PLCC) PACKAGE 280 320 640 960 1280 1600 1920 2240 32 32 PTD 2 (3) CG 0 11 (13) 600 14 (17)0 CG 0 PIN NUMBERS DIP(PLCC)PACKAGE 920 1240 1560 1880 2200 2520

Document #: 38-03026 Rev. ** Page 10 of 14 Shaded area contains preliminary information. ICC (mA) tPD (ns) tS (ns) tCO (ns) Ordering Code Package Name Package Type Operating Range 115 5 3 4 PALCE20V8 −5JC J64 28-Lead Plastic Leaded Chip CarrierCommercial 115 7.5 7 5 PALCE20V8 −7JC J64 28-Lead Plastic Leaded Chip CarrierCommercial PALCE20V8 −7PC P13 24-Lead (300-Mil) Molded DIP 115 10 10 7 PALCE20V8 −10JC J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8 −10PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8 −10QC Q13 24-Lead Quarter-Size Outline 130 10 10 10 PALCE20V8 −10JI J64 28-Lead Plastic Leaded Chip CarrierIndustrial PALCE20V8 −10PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8 −10DMB D14 24-Lead (300-Mil) CerDIP Military PALCE20V8 −10LMB L64 28-Pin Square Leadless Chip Carrier 90 15 12 10 PALCE20V8 −15JC J64 28-Lead Plastic Leaded Chip CarrierCommercial PALCE20V8 −15PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8 −15QC Q13 24-Lead Quarter-Size Outline 130 15 12 12 PALCE20V8 −15JI J64 28-Lead Plastic Leaded Chip CarrierIndustrial PALCE20V8 −15PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8 −15QI Q13 24-Lead Quarter-Size Outline PALCE20V8 −15DMB D14 24-Lead (300-Mil) CerDIP Military PALCE20V8 −15LMB L64 28-Pin Square Leadless Chip Carrier 90 25 15 12 PALCE20V8 −25JC J64 28-Lead Plastic Leaded Chip CarrierCommercial PALCE20V8 −25PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8 −25QC Q13 24-Lead Quarter-Size Outline 130 25 20 20 PALCE20V8 −25JI J64 28-Lead Plastic Leaded Chip CarrierIndustrial PALCE20V8 −25PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8 −25QI Q13 24-Lead Quarter-Size Outline PALCE20V8 −25DMB D14 24-Lead (300-Mil) CerDIP Military PALCE20V8 −25LMB L64 28-Pin Square Leadless Chip Carrier

Document #: 38-03026 Rev. ** Page 11 of 14 MILITARY SPECIFICATIONS Group A Subgroup Testing ICC (mA) tPD (ns) tS (ns) tCO (ns) Ordering Code Package Name Package Type Operating Range 55 15 12 10 PALCE20V8L −15JC J64 28-Lead Plastic Leaded Chip CarrierCommercial PALCE20V8L −15PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8L −15QC Q13 24-Lead Quarter-Size Outline 65 15 12 12 PALCE20V8L −15JI J64 28-Lead Plastic Leaded Chip CarrierIndustrial PALCE20V8L −15PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8L −15QI Q13 24-Lead Quarter-Size Outline PALCE20V8L −15DMB D14 24-Lead (300-Mil) CerDIP Military PALCE20V8L −15LMB L64 28-Pin Square Leadless Chip Carrier 55 25 15 12 PALCE20V8L −25JC J64 28-Lead Plastic Leaded Chip CarrierCommercial PALCE20V8L −25PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8L −25QC Q13 24-Lead Quarter-Size Outline 65 25 20 20 PALCE20V8L −25JI J64 28-Lead Plastic Leaded Chip CarrierIndustrial PALCE20V8L −25PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8L −25QI Q13 24-Lead Quarter-Size Outline PALCE20V8L −25DMB D14 24-Lead (300-Mil) CerDIP Military PALCE20V8L −25LMB L64 28-Pin Square Leadless Chip Carrier DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Switching Characteristics Parameter Subgroups tPD 9, 10, 11 tCO 9, 10, 11 tS 9, 10, 11 tH 9, 10, 11 DC Characteristics Parameter Subgroups

Document #: 38-03026 Rev. ** Page 12 of 14 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL−STD −1835 D −9 Config.A 28-Lead Plastic Leaded Chip CarrierJ64 28-Square Leadless Chip Carrier L64 MIL−STD −1835 C−4

Document #: 38-03026 Rev. ** Page 13 of 14 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagrams (continued) 24-Lead (300-Mil) Molded DIPP13/P13A 24-Lead Quarter Size OutlineQ13

Document #: 38-03026 Rev. Page 14 of 14 Document Title: PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL® Device Document Number: 38-03026 REV. ECN NO. Issue Date Orig. of Change Description of Change 106371 07/11/01 SZV Change from Spec Number: 38-00367 to 38-03026