Z90102 ZILOG | Alldatasheet
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P RODUCT S PECIFICATION Z90102/103/104 40-P IN L OW OST D IGITAL T ELEVISION C ONTROLLER
FEATURES
8-Bit CMOS Microcontroller for Consumer Television, Cable and Satellite Receiver Ap- plications. n Lowest Cost DTC Family Member n Low Power Consumption n Fast Instruction Pointer - 1.5 m s @ 4 MHz n Two Standby Modes - STOP and HALT n Low Voltage Detection/Voltage Sensitive Reset n Port 2 (8-Bit Programmable I/O) and Port 3 (2-Bit Input, 3-Bit Output) Register Mapped Ports n Port 6 (6-Bit Input and Tristate Comparator AFC Input) Memory Mapped I/O Ports n All Digital CMOS Levels Schmitt-Triggered n Two Programmable 8-Bit Counter/Timers each with 6- Bit Programmable Prescaler. n Six Vectored, Priority Interrupts from Six Different Sources n Clock Speed up to 4 MHz n On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC or External Clock Drive n Permanently Enabled Watch-Dog/Power-On Reset Timer n 3K x 6-Bit Character Generator ROM n 120 x 7-Bit Video RAM n Mask Programmable 96-Character Set Display. The 90102 and 90103 6-Row x 20 Column Format, 12x15 Pixel Character Cell. The 90104 8-Row x 20 Column Format 12x15 Pixel Character Cell. The 90102, 90103
90104 Capable of supporting English, Korean, Thai,
Chinese and Japanese High Resolution Characters. n Fully Programmable Color Attributes Including Row Character, Row Background/Fringes, Frame Background/Position, Bar Graph Color Change, and Character Size. n Programmable Display Position and Character Size Control n One Pulse Width Modulator (14-Bit Resolution) for Voltage Synthesis Tuner Control. n Three Pulse Width Modulator (8-Bit Resolution) for Picture Control n Three Pulse Width Modulators (6-Bit Resolution) for Audio Control GENERAL DESCRIPTION The Z90102/3/4 40-pin Low-Cost Digital Television Con- troller are members of the Z8 STOP Mode MCU single- chip family with 4, 6, and 8 KB of ROM and 236 bytes of RAM. The device is offered in a 40-pin package and is CMOS compatible. The DTC offers mask programmed ROM which enables the Z8 MCU to be used in a high vol- ume production application device embedded with a cus- tom program (customer supplied program) and combines Device ROM (KB) RAM* (Bytes) I/O Z90102 4 236 24 Z90103 6 236 24 Z90104 8 236 24 Note: *General-Purpose
40-Pin Low-Cost Digital Television Controller Zilog
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(Continued) together with the Z86C27 and Z86127 to provide support for mid range and low end TV applications. Zilog’s DTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation ca- pabilities, and easy hardware/software system expansion along with low cost and low power consumption. The de- vice provides an ideal performance and reliability solution for consumer and industrial television applications. The Z90102/3/4 architecture is characterized by utilizing Zilog’s advanced Superintegration™ design methodology. The device has an 8-bit internal data path controlled by a Z8 microcontroller and On Screen Display (OSD) logic cir- cuits and Pulse Width Modulators (PWM). On-chip periph- erals include two register mapped I/O ports (Ports 2 and 3), interrupt control logic (one software, two external and three internal interrupts) and a standby mode recovery in- put port (Port 3, P30). The OSD control circuits support 6 rows x 20 columns of characters. The character color is specified by row. One of the six rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5 x 7 dot pattern) or high resolution (11 x 15 dot pattern) characters. A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Three 6-bit PWM ports are used for controlling audio signal levels. Three 8- bit PWM ports used to vary picture levels. For DTC applications demanding powerful I/O capabili- ties, the Z90102/3/4 fulfills this with 24 I/O pins dedicated to input and output. These lines are grouped into three ports, and are configurable under software control to pro- vide timing, status signals, parallel I/O and an address/da- ta bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Video RAM, and Register File. The Register File is composed of 236 bytes of general-purpose registers, two I/O Port regis- ters, 15 control and status registers and three reserved registers. To unburden the program from coping with the real-time problems such as counting/timing and data communica- tion, the DTC offers two on-chip counter/timers with a large number of user selectable modes (Figure 1). Notes: All signals with a preceding front slash, "/", are ac- tive Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions be- low: Connection Circuit Device Power V CC V DD Ground GND V SS
Figure 1. Functional Block Diagram
256 Byte
120 Byte
3 Kbyte
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Figure 2. 40-Pin Mask-ROM Plastic DIP Table 1. 40-Pin Mask-ROM Plastic DIP
1 PWM1 Pulse Width Modulator 1 Output
4 P34 Port 3, Pin 4 Output
5 P31 Port 3, Pin 1 Input
6 P30 Port 3, Pin 0 Input
7 XTAL1 Crystal Oscillator Input
8 XTAL2 Crystal Oscillator Output
10 P60 Port 6, Pin 0 Input
11 GND Ground Input
12 P61 Port 6, Pin 1 Input
13 P62 Port 6, Pin 2 Input
18 AFC
19 OSC
20 OSC
21 HSYNC Horizontal Sync Input
22 VSYNC Vertical Sync Input
23 Vred Video Red Output
24 Vgreen Video Green Output
25 Vblue Video Blue Output
26 Vblank Video Blank Output
35 PWM11 Pulse Width Modulator 11 Output
36 PWM10 Pulse Width Modulator 10 Output
37 PWM9 Pulse Width Modulator 9 Output
38 PWM8 Pulse Width Modulator 8 Output
39 PWM7 Pulse Width Modulator 7 Output
40 PWM6 Pulse Width Modulator 6 Output
40-Pin Low-Cost Digital Television Controller Zilog
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XTAL1, XTAL2. (time-based input, output, respectively). These pins connect to the internal parallel-resonant clock crystal (4 MHz max) oscillator circuit with two capacitors to GND. XTAL1 is also used as an external clock input. SCLK System Clock. SCLK is the internal system clock. It can be used to clock external glue logic. HSYNC (input, Schmitt triggered, CMOS level). Horizontal Sync is an input pin that accepts an externally generated Horizontal Sync signal of either negative or positive polar- ity. VSYNC (input,Schmitt-triggered, CMOS level). Vertical Sync is an input pin that accepts an externally generated Vertical Sync signal of either negative or positive polarity. OSCIN, OSCOUT (Video Oscillator input, output, respec- tively). Oscillator input and output pins for on-screen dis- play circuits. These pins connect to an inductor and two capacitors to generate the character dot clock (typically around 6 MHz). The dot clock frequency determines the character pixel width and phase synchronized to HSYNC. Vblank Video Blank (output). CMOS output, programma- ble polarity. Used as a superimpose control port to display characters from video RAM. The signal controls Y signal output of the CRT and turns off the incoming video display while the characters in video RAM are superimposed on the screen. The red, green, and blue outputs drive the three electron guns on the CRT directly, while the blank output turns off the Y signal. Vblue Video Blue (output). CMOS Output of the Blue vid- eo signal (B-Y) and is programmable for either polarity. Vgreen Video Green (output). CMOS Output of the Green video signal (G-Y) and is programmable for either polarity. Vred Video Red (output). CMOS Output of the Red video signal (R-Y) and is programmable for either polarity. Port 2 (P27-P20). Port 2 is an 8-bit port, CMOS-compati- ble, bit programmable for either input or output. Input buff- ers are Schmitt triggered. Bits programmed as outputs may be globally programmed as either push pull or open- drain (Figure 9). Port 3 (P30, P31, P34-P36). Port 3, P30 input, is read di- rectly. If appropriately enabled, a negative edge event is latched in IRQ3 to initiate an IRQ3 vectored interrupt. An application could place the device in STOP Mode when P30 goes Low (in the IRQ3 interrupt routine). P30 initiates a STOP Mode recovery when it subsequently goes to a High. Port 3, P31 are read directly. If appropriately en- abled, a negative edge event is latched in IRQ2 to initiate an IRQ2 vectored interrupt. P31 High is signified as the TIN signal to Timer1. Port 3, P34 and P35 are general-pur- pose output lines. Port 3, P36 can be used as a general- purpose output or as an output for TOUT (from Timer1 or Timer2) or SCLK (Figure 10). Port 6 (P65-P60). Port 6 is a 6-bit, Schmitt triggered CMOS compatible, input port. The outputs of the AFC comparators internally feed into the Port 6, bit 6 and bit 7 inputs (Figure 11). AFCIN (Comparator input port, memory mapped). The in- put signal is supplied to two comparators with VTH1=2/5 V CC and VTH2=3/5 V CC typical threshold voltage. The comparator outputs are internally connected to Port 6, bit 6 and bit 7. AFCIN is typically used to detect AFC voltage level to accommodate digital automatic fine tuning func- tions (Figure 12). Pulse Width Modulator 1 (PWM). PWM1 is typically used as the D/A converter for Voltage Synthesis Tuning sys- tems. It is a push-pull output with 14-bit resolution. Pulse Width Modulator 6-8 (PWM). PWM8-PWM6 are Pulse Width Modulators with 6-bit resolution. Pulse Width Modulator 9, 10, 11 (PWM). Pulse Width Modulator circuits with 8-bit resolution. These PWMs are 12 volt, open-drain outputs. Pulse Width Modulator 1, 6, 7, 8 (PWM). Can be pro- grammed as general-purpose outputs. PWM 1 is 5 V OH push-pull, and PWMs 6, 7, 8 are 12 volt open-drain out- puts. /RESET System Reset. Code is executed from memory address 000CH after the /RESET pin is set to a high level. The reset function is also carried out by detecting a V CC transition state (automatic Power-On Reset) so that the external reset pin can be permanently tied to V CC . A low level on /RESET forces a restart of the device.
conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 3).
- Absolute maximum operating voltage 13.2V.
Absolute maximum momentary (non-operating) voltage is 16.0V.
- Voltage on all pins with respect to GND.
Figure 3. Test Load Diagram
40-Pin Low-Cost Digital Television Controller Zilog
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TA = 25°C; VCC = GND = 0V; Freq =1.0 MHz; unmeasured pins to GND. DC CHARACTERISTICS TA = 0°C to +70°C; VCC = +4.5V to +5.5V; FOSC = 4 MHz Parameter Max Units Input capacitance 10 pF Output capacitance 20 pF I/O capacitance 25 pF AFCIN input capacitance 10 pF TA = 0°C to +70°C Typical Sym Parameter Min Max @ 25 °C Units Conditions VIL Input Voltage Low 0 0.2 V CC 1.48 V VILC Input XTAL/Osc In Low 0.07 V CC 0.98 V External Clock Generator Driven VIH Input Voltage High 0.7 V CC VCC 3.0 V VIHC Input XTAL/Osc In High 0.8 V CC VCC 3.2 V External Clock Generator Driven VHY Schmitt Hysteresis 0.1 V CC 0.8 V VPU Maximum Pull-Up Voltage
13.2 V 1, 2
VOL Output Voltage Low 0.4 0.4 0.16 0.19 V V IOL =1.00 mA IOL =0.75 mA 1 V00-01 AFC Level 01 In 0.45 V CC 1.9 V V01-11 AFC Level 11 In 0.5 V CC 0.75 VCC 3.12 V VOH Output Voltage High V CC –0.4 4.75 V I OH =–0.75 mA IIR Reset Input Current –80 –46 mAV RL =0V IIL Input Leakage –3.0 3.0 0.01 mA0 V , VCC IOL Tristate Leakage –3.0 3.0 0.02 mA0 V , VCC ICC ICC1 ICC2 Supply Current 20 13.2 3.2 2.0 mA mA mA All inputs at rail & outputs floating Notes: 1. PWM open-drain 2. Recommended operating voltage 12V with maximum positive tolerance 10%, i.e., 13.2V.
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Figure 7. Power-On Reset Figure 8. On-Screen Display
Zilog 40-Pin Low-Cost Digital Television Controller DS97TEL1902 11 AC CHARACTERISTICS TA = 0° C to +70° C; VCC = +4.5V to +5.5V; FOSC = 4 MHz No Symbol Parameter Min Max Unit
1 TpC Input Clock Period 250 1000 ns
2 TrC,TfC Clock Input Rise and Fall 15 ns
3 TwC Input Clock Width 125 ns
4 TwTinL Timer Input Low Width 70 ns
5 TwTinH Timer Input High Width 3TpC
6 TpTin Timer Input Period 8TpC
7 TrTin,TfTin Timer Input Rise and Fall 100 ns
8a TwIL Int Req Input Low 70 ns 8b TwIL 3TpC
9 TwIH Int Request Input High 3TpC
10 TdPOR Power On Reset Delay 25 100 ms
11 TdLVIRES Low Voltage Detect to 200 ns
12 TwRES Reset Minimum Width 5TpC
13 TdHsOI HSYNC Start to VOSC
14 TdHsOh HSYNC End to VOSC
15 TdWDT WDT Refresh Time 12 ms
Notes: Refer to DC Characteristics for details on switching levels.
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cessed through LDE and LDEI instructions. PWM1. It is a push-pull output. mum value for all 0s and minimum value for all 1s. Figure 9. Pulse Width Modulator Block Diagram
Figure 10. On-Screen Display Block Diagram
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horizontal/vertical sync input and RGB outputs. 4HL units and 64 horizontal positions by a 4-dot clock. second color with proper character set. n Fringe Function: Fringe off/on and the color selected. n Number of Display Characters: 6 rows x 20 columns. n Character Set: 96 (11 x 15 dots). cess the Video RAM (Figure 11). Figure 11. Video RAM Configuration
Figure 12. Video RAM Map
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Figure 13. High Resolution Character ROM Configuration
Figure 14. Program Memory
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working register and indirect addressing modes. Figure 15. Register File Configuration Figure 16. Register Pointer the active working-register group.
Figure 17. Z90102/3/4 Register File Reset Condition registers are undefined after reset.
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cascaded by connecting the T0 output to the input of T1. Figure 18. Counter/Timer Block Diagram
Figure 19. Interrupt Block Diagram
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internal CPU clock (SCLK), but not the XTAL oscillation. The counter/timers and external interrupts remain active. high input condition on Port 3 P30 is the second method. on it and OSCOUT has an internal pull-down. less than or equal to 100 Ohms. Figure 20. Oscillator Configuration
instruction WDT 4F (HEX) enables the timer during HALT. the WDT instruction) within 12 ms, a device reset occurs. (Overflow) flags. WDT does not run during STOP Mode. driven if VCC is below the specified voltage (Figure 21). Figure 21. Voltage Sensitive Reset vs Temperature
40-Pin Low-Cost Digital Television Controller Zilog
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Figure 22. Input Only Figure 23. Input Only, Schmitt-Triggered Figure 24. Output Only
20 Ohm
Figure 25. Input/Output Tristate Figure 26. Input/Output, Tristate, Open-Drain Figure 27. Output Only, Tristate
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Figure 28. Output Only, 12-Volt Open-Drain Figure 29. Reset Input Circuit Figure 30. AFC Input Circuit Table 2. Mapping of Symbolic Pad Types to Pin *High gain start, low gain run amplifier circuit.
20 Ohm PAD
Figure 31. Port 2 Register Figure 32. Port 2 Mode Register
0 Logic Level 0
1 Logic Level 1
0 Output Mode
1 Input Mode
Figure 33. Port 3 Register Figure 34. Port 6 Register
00 GND thru V1
11 V2 thru VCC
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Figure 35. PWM 1 High Value Figure 36. PWM 1 Low Value Figure 37. PWM 6 Value Figure 38. PWM 7 Value Figure 39. PWM 8 Value Figure 40. PWM 9 Value Figure 41. PWM 10 Value Figure 42. PWM 11 Value
Figure 43. PWM Mode Register
0 PWM
1 Output Port
Figure 44. PWM Port Output Register
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Figure 45. OSD Control Register Figure 46. OSD Vertical Position Register Figure 47. OSD Horizontal Position Register
0 Positive
1 Negative
Figure 48. OSD Display Attribute Register Figure 49. OSD Row Space Register Figure 50. OSD Fade Position Register
Figure 51. OSD Bar Control Register Figure 52. OSD Bar Position Register Figure 53. Timer Mode Register
00 External Clock Input
01 Gate Input
10 Trigger Input
11 Trigger Input
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out
Figure 54. ROW_ATTR Register Figure 55. Counter Timer 1 Register Figure 56. Prescaler 1 Register
0 Off
0 T1 Single Pass*
1 T1 Modulo N
1 T1 Internal
0 T1 External Timing Input*
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Figure 57. Counter/Timer 0 Register Figure 58. Prescaler 0 Register Figure 59. Port 2 Mode Register
0 T0 Single Pass*
1 T0 Modulo-N
0 Defines Bit as Output
1 Defines Bit as Input
Figure 60. Port 3 Mode Register Figure 61. Interrupt Priority Register
0 P32 - Input P35 - Output
00 P33 - Input P34 - Output
11 Reserved
0 P31 - Input (TIN) P36 - Output (TOUT)
0 P30 - Input
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
40-Pin Low-Cost Digital Television Controller Zilog
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PACKAGE INFORMATION
Figure 68. 40-Pin DIP Package Diagram
Zilog 40-Pin Low-Cost Digital Television Controller DS97TEL1902 35
ORDERING INFORMATION
Z90102, Z90103, Z90104
4 MHz
For fast results, contact your local Zilog sales office for as- sistance in ordering the part desired. CODE Package P = Plastic DIP Temperature S = 0°C to +70°C Speed 04 = 4 MHz Environmental C = Plastic Standard Example: Z 890103 04 P S C is an 86227, 4 MHz, DIP, 0°C to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
40-Pin Low-Cost Digital Television Controller Zilog