Z8523L08VEG ZILOG | Alldatasheet
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Copyright ©2009 by Zilog®, Inc. All rights reserved. www.zilog.com Product Specification PS005308-0609 Z80230/Z85230/L Enhanced Serial Communications Controller
DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FO R USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT TH E EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. A critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2009 by Zilog, Inc. All rights reserved. Information in this pu blication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8 is a registered trademark of Zilog, Inc. All ot her product or service names are the property of their respective owners. Warning:
Revision History
Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Date Revision Level Description Page No June 2009 08 Removed Security Watermark from pages all May 2009 07 Minor update to page 107 107 May 2009 06 system update change only - no technical content revised n/a Mar 2009 05 Updated document to add 3V product information Removed ISO/BSI certification information Figure 1, 7 and 23 changed 5V to Vcc Added Z8523L DC Characteristics Updated Read and Write AC Characteristics Updated System Timing Characteristics Updated General Timing Diagram Ordering Information updated Updated Standard Test Conditions Updatred Table 43 Updated Table 49 - min value Misc ii , 13, 76 107 June 2008 04 Updated as per ne w template and Style Guide. Updated Figure 4. All September 2007 03 Updated Figure 38 and Implemented Style Guide All November 2002 02 Editorial Updates All August 2001 01 Original Issue All
PS005308-0609 Table of Contents Z80230/Z85230/L Product Specification iv Table of Contents
PS005308-0609 Table of Contents Z80230/Z85230/L Product Specification v
PS005308-0609 Pin Descriptions Z80230/Z85230/L Product Specification Pin Descriptions The Enhanced Serial Communication Controller (ESCC) pins are divided into seven func- tional groups: 1. Address/Data 2. Bus Timing and Reset 3. Device Control 4. Interrupt 5. Serial Data (both channels) 6. Peripheral Control (both channels) 7. Clocks (both channels) Figure 1 on page 2 and Figure 2 on page 2 display the pins in each functional group for both the Z80230 and Z85230/L. The pin functions are unique to each bus interface version in the Address/Data group, Bus Timing and Reset group, and Device Control group. The Address/Data group consists of the bidirectional lines used to transfer data between the CPU and the ESCC (addresses in the Z80230 are latched by AS). The direction of these lines depends on whether the operation is a Read or a Write operation. The Timing and Control groups designate the type of transaction to occur and the timing of the occurrence. The interrupt group provides inputs and outputs for handling and prior- itizing interrupts. The remaining groups are divided into Channel A and Channel B groups for:
- Serial Data (Transmit or Receive)
- Peripheral Control (such as DMA or modem)
- Input and Output Line for the Receive and Transmit Clocks
PS005308-0609 Pin Descriptions Z80230/Z85230/L Product Specification Pins Common to Both Z85230/L and Z80230 The pin descriptions for pins common to both Z85230/L and Z80230 are provided below: CTSA, CTSB (Clear To Send (Inputs, Active Low))— These pins function as transmitter enables if they are programmed for AUTO ENABLE (WR3 bit 5 is 1), in which case a Low on each input enables the respective transmitter. If not programmed as AUTO ENABLE, the pins may be used as general-purpose inputs. These pins are Schmitt-trigger buffered to accommodate slow rise-time inputs. The ESCC detects pulses on these pins and may interrupt the CPU on both logic level transitions. DCDA, DCDB (Data Carrier Detect (Inputs, Active Low))— These pins function as receiver enables if they are programmed for AUTO ENABLE (WR3 bit 5 is 1); otherwise, they are used as general-purpose input pins. The pins are Schmitt-trigger buffered to accommodate slow rise-time signals. The ESCC detects pulses on these pins and may interrupt the CPU on both logic level transitions. RTSA, RTSB (Request To Send (Outputs, Active Low))— The RTS pins can be used as general-purpose outputs or with the AUTO ENABLE feature. When AUTO-ENABLE is off, these pins follow the inverse state of WR5 bit 1. When used with the AUTO- ENABLE feature in ASYNCHRONOUS mode, this pin immediately goes Low when WR5 bit 1 is 1. When WR5 bit 0 is 0, this pin remains Low until the transmitter is empty. In Synchronous Data Link Control (SDLC) mode, the RTS pins can be programmed to be deasserted when the closing flag of the message clears the TxD pin, if WR7’ bit 2 is 1, WR10 bit 2 is 0, and WR5 bit 1 is 0. SYNCA, SYNCB (Synchronization (Inputs Or Outputs, Active Low))— These pins can act either as inputs, outputs, or as part of the crystal oscillator circuit. In the ASYNCHRO- NOUS RECEIVE mode (crystal oscillator option not selected), these pins are inputs simi- lar to CTS and DCD. In this mode, transition on these lines affect the state of the SYNC/ HUNT status bits in Read Register 0 but have no other function. In EXTERNAL SYNCHRONIZATION mode, with the crystal oscillator not selected, these lines also act as inputs. In this mode, SYNC is driven Low, two Rx clock cycles after the last bit of the SYNC character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of SYNC. In the INTERNAL SYNCHRONIZATION mode (MONOSYNC and BISYNC) with the crystal oscillator not selected, these pins act as outputs. These outputs go Low each time a SYNC pattern is recognized, regardless of character boundaries. In SDLC mode, pins switch from input to output when MONOSYNC, BISYNC, or SDLC is programmed in WR4 and SYNC modes are enabled. DTR/REQA, DTR/REQB (Data Terminal Ready/Request (Output, Active Low))— These pins can be programmed (WR14 bit 2) to serve either as general-purpose outputs or as DMA Request lines. When programmed for DTR function (WR14 bit 2 is 0), these out- puts follow the inverse of the DTR bit of Write Register 5 (WR5 bit 7). When pro- grammed for REQUEST mode these pins serve as DMA Requests for the transmitter.
PS005308-0609 Pin Descriptions Z80230/Z85230/L Product Specification When used as DMA Request line (WR14 bit 2 is 1), the timing for the deactivation request can be programmed in Write Register 7’ (WR7’) bit 4. If this bit is 1, the DTR/REQ pin is deactivated with the same timing as the W/REQ pin. If 0, the deactivation timing of DTR/ REQ pin is four clock cycles, the same as in the Z80C30/Z85C30. W/REQA, W/REQB (Wait/request (Output, Open-drain When Programmed For WAIT Function, Driven High And Low When Programmed For Request Function))— These dual-purpose outputs may be programmed as REQUEST lines for a DMA controller or as WAIT lines to synchronize the CPU to the ESCC data rate. The reset state is WAIT. RxDA, RxDB (Receive Data (inputs, active High))— These inputs receive serial data at standard Transistor-Transistor Logic (TTL) levels. RTxCA, RTxCB (Receive/Transmit Clocks (Input, Active Low))— These pins can be programmed to several modes of operation. In each channel, RTxC may supply the fol- lowing:
- Receive clock and/or the transmit clock
- Clock for the baud rate generator (BRG)
- Clock for the Digital Phase-Locked Loop These pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in ASYNCHRO- NOUS modes. TxDA, TxDB (Transmit Data (Output, Active High))— These output transmit serial data at standard TTL levels. TRxCA, TRxCB (Transmit/Receive Clocks (Input or Output, Active Low))— These pins can be programmed in several different modes. When configured as an input, the TRxC may supply the receive clock and/or the transmit clock. When configured as an out- put, TRxC can echo the clock output of the Digital Phase-Locked Loop, the crystal oscilla- tor, the BRG or the transmit clock. PCLK (Clock (Input))— This clock is the master ESCC clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship with the master system clock. IEI (Interrupt Enable In (Input, Active High))— IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt-driven device. A High IEI indicates that no higher priority device has an Interrupt Under Service (IUS) or is requesting an interrupt. IEO (Interrupt Enable Out (Output, Active High))— IEO is High only if IEI is High and the CPU is not servicing an ESCC interrupt. During an Interrupt Acknowledge Cycle, IEO is also driven Low if the ESCC is requesting an interrupt. IEO can be connected to the next lower priority device’s IEI input, and in this case inhibits interrupts from lower prior- ity devices.
PS005308-0609 Pin Descriptions Z80230/Z85230/L Product Specification INT (Interrupt (Output, Open-Drain, Active Low))— This pin activates when the ESCC requests an interrupt. The INT is an open-drain output. INTACK (Interrupt Acknowledge (Input, Active Low))— This pin is a strobe which indi- cates that an Interrupt Acknowledge Cycle is in progress. During this cycle, the ESCC interrupt daisy chain is resolved. The device can return an interrupt vector that may be encoded with the type of interrupt pending. During the acknowledge cycle, if IEI is High, the ESCC places the interrupt vector on the data bus when RD goes active for the Z85230/ L, or when DS goes active for the Z80230. INTACK is latched by the rising edge of PCLK. Pin Descriptions Exclusive to the Z85230/L The pin description for pins exclusive to Z85230/L is provided below: Pins D7–D0 (Data Bus (Bidirectional, tristate))— These pins carry data and commands to and from the Z85230/L. CE (Chip Enable (Input, Active Low))— This pin selects the Z85230/L for a Read or Write operation. RD ((Read (input, Active Low))— This pin indicates a Read operation and, when the Z85230/L is selected, enables the Z85230/L’s bus drivers. During the Interrupt Acknowl- edge cycle, RD gates the interrupt vector onto the bus if the Z85230/L is the highest prior- ity device requesting an interrupt. WR (Write (Input, Active Low))— When the Z85230/L is selected, this pin denotes a Write operation, which indicates that the CPU writes command bytes or data to the Z85230/L write registers. WR and RD going Low simultaneously is interpreted as a Reset. A/B (Channel A/Channel B (Input))— This pin selects the channel in which the Read or Write operation occurs. A High selects Channel A and a Low selects Channel B. D/C (Data/Control Select (Input))— This signal defines the type of information trans- ferred to or from the Z85230/L. A High indicates data transfer and a Low indicates a com- mand transfer. Pin Descriptions Exclusive to the Z80230 The pin description for pins exclusive to Z80230 is provided below: AD7–AD0 (Address/Data Bus (Bidirectional, Active High, tristate))— These multi- plexed lines carry register addresses to the Z80230 as well as data or control information to and from the Z80230. R/W (Read/Write (Input, Read Active High))— This pin specifies if the operation to be performed is a Read or Write operation. Note:
PS005308-0609 Pin Descriptions Z80230/Z85230/L Product Specification CS0 (Chip Select 0 (Input, Active Low))— This pin is latched concurrently with the addresses on A7-A0 and must be Low for the intended bus transaction to occur. CS1 (Chip Select 1 (Input, Active High))— This second chip select pin must be High before and during the intended bus transaction. DS (Data Strobe (Input, Active Low))— This pin provides timing for the transfer of data into and out of the Z80230. If AS and DS are both Low, this condition is interpreted as a RESET. AS (Address Strobe (Input, Active Low))— Addresses on A7-A0 are latched by the ris- ing edge of this signal.
- Data communications device, which transmits and receives data in a wide variety of protocols
- Microprocessor peripheral, in which the ESCC offers valuable features such as vectored interrupts and DMA support The details of the communication between the receive and transmit logic of the system bus are displayed in Figure 5 and Figure 6 on page 9. The features and data path for each of the ESCC A and B channels are identical. For more information on SCC/ESCC and ISCC Family of Products, refer to the respective User Manuals available for download from www.zilog.com.
Figure 5. ESCC Transmit Data Path
2 Bit Delay
4 Bytes
Figure 6. ESCC Receive Data Path 11 lists the Read Registers.
16 Bit Down Counter Div 2 BRG
8 Bytes Deep
14 Bit Counter
Table 1. ESCC Write Registers
- INTERRUPT (vectored and non-vectored)
The BLOCK TRANSFER mode can be implemented under CPU or DMA control. Table 2. ESCC Read Registers
PS005308-0609 Functional Description Z80230/Z85230/L Product Specification Pending register. Status information for both channels resides in one register. Only one register may be read. Depending on its contents, the CPU performs one of the three opera- tions listed below: 1. Write data 2. Read data 3. Continues processing Two bits in the register indicate the requirement for data transfer. INTERRUPT The ESCC INTERRUPT mode supports vectored and nested interrupts. The fill levels at which the transmit and receive FIFOs interrupt the CPU are programmable, allowing the ESCC requests for data transfer to be tuned to the system interrupt response time. Nested interrupts are supported with the interrupt acknowledge (INTACK) feature of the ESCC. It allows the CPU to acknowledge the occurrence of an interrupt, and re-enable higher priority interrupts. Since an INTACK cycle releases the INT pin from the active state, a higher priority ESCC interrupt or another higher priority device can interrupt the CPU. When an ESCC responds to INTACK signal from the CPU, it can place an interrupt vector on the data bus. This vector is written in WR2 and may be read in RR2. To increase the interrupt response time, the ESCC can modify 3 bits in this vector to indicate status. If the vector is read in Channel A, status is not included. If it is read in Channel B, status is included. Each of the six sources of interrupts in the ESCC (Transmit, Receive, and External/Status interrupts in both channels) has 3 bits associated with the interrupt source as listed below: 1. Interrupt Pending (IP) 2. Interrupt Under Service (IUS) 3. Interrupt Enable (IE) If the IE bit is set for a given interrupt source, then that source can request interrupts. However, when the Master Interrupt Enable (MIE) bit in WR9 is reset, no interrupts can be requested. The IE bits are write-only. The other two bits are related to the interrupt pri- ority chain (see Figure 7 on page 13). The ESCC can request an interrupt only when no higher priority device is requesting an interrupt (that is, when IEI is High). If the device in question requests an interrupt, it pulls down INT. The CPU then responds with INTACK, and the interrupting device places a vector on the data bus.
Figure 7. ESCC Interrupt Priority Schedule IE bit is not set, then the IP for that source is never set. The IP bits are read in RR3A. there are no higher priority devices requesting interrupt. to the Tx FIFO for it to become empty.
PS005308-0609 Functional Description Z80230/Z85230/L Product Specification When the receiver is enabled, the CPU is interrupted in one of the following three meth- ods: 1. Interrupt on First Receive Character or Special Receive Condition 2. Interrupt on All Receive Charact ers or Special Receive Conditions 3. Interrupt on Special Receive Conditions Only If WR7’ bit 3 is 1, and the Special Receive Condition is selected, the Receive character occurs when there are four bytes available in the Receive FIFO. This is most useful in syn- chronous applications as the data is in consecutive bytes. Interrupt on First Character or Special Condition and Interrupt on Special Condition Only are typically used with the BLOCK TRANSFER mode. A special Receive Condition consists of one of the follow- ing:
- Receiver Overrun
- Framing error in ASYNCHRONOUS mode
- EOF in SDLC mode
- Parity error (optional) The Special Receive Condition interrupt is different from an ordinary receive character available interrupt only by the status placed in the vector during the Interrupt Acknowl- edge cycle. In Receive Interrupt on First Character or Special Condition mode, an inter- rupt occurs from Special Receive Conditions any time after the first receive character interrupt. The primary function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD, and SYNC pins. However, an External/Status interrupt is also caused by any of the following:
- A Transmit Underrun condition
- A zero count in the BRG
- A detection of a Break (ASYNCHRONOUS mode)
- An ABORT (SDLC mode)
- An End Of Poll (EOP) sequence in the data stream (SDLC LOOP mode) The interrupt caused by the ABORT or EOP sequence has a special feature that allows the ESCC to interrupt when the ABORT or EOP sequence is detected or terminated. This fea- ture facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the ABORT condition by external logic in SDLC mode. SDLC LOOP mode allows secondary stations to recognize the primary station and regain control of the loop during a poll sequence.
ing sync characters are removed without interrupting the CPU. ping the larger pattern across multiple incoming sync characters as displayed in Figure 9. Figure 9. Detecting 5- or 7-Bit Synchronous Characters
5 Bits
PS005308-0609 Functional Description Z80230/Z85230/L Product Specification CRC checking for SYNCHRONOUS BYTE-ORIENTED mode is delayed by one charac- ter time so that the CPU may disable CRC checking on specific characters. This action permits the implementation of protocols such as IBM BISYNC. Both CRC-16 (X16 + X15 + X2 + 1) and CRC-CCITT (X16 + X12 + X5 + 1) error checking polynomials are supported. Either polynomial may be selected in all synchronous modes. You can preset the CRC generator and checker to all 1s or all 0s. The ESCC also provides a feature that automatically transmits CRC data when no other data is available for trans- mission. This feature enables high-speed transmissions under DMA control, with no need for CPU intervention at the end of a message. When there is no data or CRC to send in the SYNCHRONOUS mode, the transmitter inserts 6-, 8-, 12-, or 16-bit SYNC characters, regardless of the programmed character length. SDLC Mode The ESCC supports SYNCHRONOUS bit-oriented protocols, such as SDLC and High-Level Data Link Control (HDLC), by performing automatic flag sending, zero inser- tion, and CRC generation. A special command is used to abort a frame which is in transmission. At the end of a mes- sage, the ESCC automatically transmits the CRC and trailing flag when the transmitter underruns. The transmitter may also be programmed to send an idle line consisting of con- tinuous flag characters or a steady marking condition. If a transmit underrun occurs in the middle of a message, an External/Status interrupt warns the CPU of this status change so that an Abort command can be issued. The ESCC may also be programmed to send an Abort command by itself, in the event of an underrun, relieving the CPU of the task. The last character of a frame may consist of 1- to 8-bits, allowing reception of frames of any length. The receiver automatically synchronizes on the leading flag of a frame in SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt may also be pro- grammed). The receiver may search for frames addressed by 1-byte or 4-bits within a byte of a user-specified address or for a global broadcast address. Frames not matching either the user-selected address or broadcast address are ignored. The number of address bytes are extended under software control. To receive data, an interrupt can be selected on the first received character, or on every character, or On Spe- cial Condition Only (EOF). The receiver automatically deletes all zeros inserted by the transmitter during character assembly. CRC is also calculated and is automatically checked to validate frame transmission. At the end of transmission, the status of a received frame is available in the status registers. In SDLC mode, the ESCC must be programmed to use the CRC-CCITT polynomial, but the generator and checker may be pre-set to all 1s or all 0s. The CRC data is inverted before transmission and the receiver checks against the bit pattern 0001110100001111.
PS005308-0609 Functional Description Z80230/Z85230/L Product Specification SDLC Status FIFO The ESCC’s ability to receive high speed back-to-back SDLC frames is maximized by a 10-bit deep by 19-bit wide status FIFO buffer. When enabled (through WR15 bit 2 is 1), the storage area enables DMA to continue data transfer into the memory, so that the CPU examines the message later. For each SDLC frame, 14 counter bits and 5 Status/Error bits are stored. The byte count and status bits are accessed through Read Registers, RR6, and RR7. RR6 and RR7 are only used when the SDLC FIFO buffer is enabled. The 10 x 19 status FIFO buffer is separate from the 8-byte receive data FIFO buffer. Baud Rate Generator Each channel in the ESCC contains a programmable BRG. Each generator consists of two 8-bit registers that form a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output, producing a square wave. At start-up, the flip-flop at the output is set High, the value in the time constant register is loaded into the counter, and the count down begins. When the BRG reaches zero, the output toggles, the counter is reloaded with the time con- stant, and the process repeats. The time constant can be changed at any time, but the new value does not take effect until the counter is loaded again. The output of the BRG may be used as the Transmit clock, the Receive clock, or both. The output can also drive the DPLL. For more information, see Digital Phase-Locked Loop. If the receive clock or the transmit clock is not programmed to come from the TRxC pin, the output of the BRG may be echoed out by the TRxC pin. The following formula relates the time constant to the baud rate. PCLK or RTxC is the clock input to the BRG . The clock mode is 1, 16, 32, or 64, as selected in WR 4 bits 6 and Digital Phase-Locked Loop The ESCC contains a DPLL to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream, to construct a clock for the data. This clock is then used as the ESCC receive clock, the transmit clock, or both. When the DPLL is selected as the transmit clock source, it provides a jitter-free clock output. The clock output is the DPLL input frequency divided by the appropriate divisor for the selected encoding technique. For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the 32x clock is counted, the DPLL searches the incoming data stream for edges (either 1 to 0 or 0 to 1). When a transition is detected the DPLL makes a count adjustment (during the next counting cycle), producing a terminal count closer to the center of the bit cell. PCLK or RTxC FrequencyTime Constant =2(Baud Rate) (Clock Mode) -2
time centered on the 15 to 16 counting transition. TRxC pin (if this pin is not being used as an input). the transmitter or receiver is idling or disabled. Figure 11. Data Encoding Methods Table 3 lists the four encoding methods, their levels, and values. Table 3. Data Encoding Descriptions
is 0 to 1, the bit is a 0. If the transition is 1 to 0, the bit is a 1. interrupts and Wait/Request on transmit. NOUS, and SDLC modes with NRZ, NRZI, or FM coding of the data stream. at the center of the bit cell. Table 3. Data Encoding Descriptions (Continued)
PS005308-0609 Z80230/Z85230/L Enhancements Z80230/Z85230/L Product Specification Z80230/Z85230/L Enhancements A detailed description of the enhancements to the Z80230/Z85230/L ESCC that differenti- ate it from the standard SCC is provided below: 4-Byte Transmit FIFO Buffer The ESCC has a 4-byte transmit buffer with programmable interrupt and DMA request levels. It is not necessary to enable the FIFO buffer as it is always available. You can set the Transmit Buffer Empty (TBE) interrupt and DMA Request on Transmit command to be generated either when the top byte of transmit FIFO is empty or only when the FIFO is completely empty. A hardware or channel reset clears the transmit shift register, flushes the transmit FIFO, and sets WR7’ bit 5 to 1. If the transmitter generates the interrupt or DMA request for data when the top byte of the FIFO is empty (WR7’ bit 5 is 0), the system allows for a long response time to the data request without underflowing. The interrupt service routine (ISR) writes 1byte and then tests RR0 bit 2. The DMA Request on Transmit in this mode is set to 0 after each data Write (that is, TBE), RR0 bit 2, is set to 1 when the top byte of the FIFO is empty. WR7’ bit 5 resets to 1. In applications for which the interrupt frequency is important, the transmit ISR can be optimized by programming the ESCC to generate the TBE interrupt only when the FIFO is completely empty (WR7’ bit 5 is 1) and, writing 4 bytes to fill the FIFO. When WR7’ bit 5 is 1, only one DMA request is generated, filling the bottom of the FIFO. However, this may be advantageous for applications where the possible reassertion of the DMA request is not required. The TBE status bit, RR0 bit 2, is set to 1 when the top byte of the FIFO is empty. WR7’ bit 5 is set to1 after a hardware or channel reset. 8-Byte Receive FIFO The ESCC has an 8-byte receive FIFO with programmable interrupt levels. It is not neces- sary to enable the 8-byte FIFO as it is always available. A hardware or channel reset clears the Receive Shift register and flushes the Receive FIFO. The Receive Character Available interrupt is generated as selected by WR7’ bit 3. The Receive Character Available bit, RR0 bit 0 is set to 1 when at least one byte is available at the top of the FIFO (independent of WR7’ bit 3). A DMA Request on Receive, if enabled, is generated whenever 1 byte is available in the receive FIFO independent of WR7’ bit 3. If more than 1 byte is available in the FIFO, the Wait/Request pin becomes inactive and becomes active when the FIFO is emptied.
can then test the Receive Character Available bit to determine if more data is available. 1, the Receive Character Available interrupt is generated when there are 4 bytes available. If the ISR reads 4 bytes during each routine, the frequency of interrupts is reduced. Table 4. Write Register 7 Prime (WR7’)
7 W 0 Reserved, must be 0
6 W Extended Read Enable
5 W Transmit FIFO Int Level
4 W DTR/REQ Timing Mode
3 W Receive FIFO Int Level
2 W Auto RTS Deactivation
1 W Auto EOM Reset
0 W Auto Transmit Flag
PS005308-0609 Z80230/Z85230/L Enhancements Z80230/Z85230/L Product Specification 1. WR15 bit 0 must be reset to 0 to address the SYNC character in register WR7. If bit 6 of WR7’ is set to 1, then WR7’ can be read by performing a read cycle to RR14. The WR7’ features remain enabled until specifically disabled or by a hardware or software reset. Bit 5 is set to 1 and all other bits are reset to 0 after a reset. For applications which use either the Zilog Z8X30SCC or Z80230, these two device types can be identified in software with the following test: 1. Write 01H to Write Register 15 2. Read Register 15 If bit 0 is set to 0, the device is Z8X30SCC. If bit 0 is set to 1, it is a Z80C30. If the device is Z8XC30, a write to WR15 is required before proceeding. If the device is Z80230, all writes to address 7 are to WR7’ until WR15 is set to 0. The WR7 register bits are described below: Bit 7 (Not used) This bit must always be 0. Bit 6 (Extended Read Enable) Setting this bit to 1 enables WR3, WR4, WR5, WR7’ and WR10 to be read by issuing a READ command for RR9 (WR3) RR4, RR5, RR14 (WR7’) and RR11 (WR10), respec- tively. Bit 5 (Transmit FIFO Interrupt Level) If this bit is set to 1, the TBE interrupt is generated when the transmit FIFO is completely empty. If this bit is set to 0, the TBE interrupt is generated when the top byte of the trans- mit FIFO is empty. This bit is set following a hardware or channel reset. In DMA REQUEST ON TRANSMIT mode, when using either the W/REQ or DTR/REQ pins, the request is asserted when the Tx FIFO is completely empty if WR7’ bit 5 is set to 1. The request is asserted when the top byte of the FIFO is empty if bit 5 is reset. Bit 4 (DTR/REQ Timing) If this bit is set to 1 and the DTR/REQ pin is used for REQUEST mode (WR14 bit 2 is 1), the deactivation of the DTR/REQ pin is identical to the W/REQ pin as displayed in Figure 12 on page 25. If this bit is reset, the deactivation time is 4TcPc.
Figure 12. DMA Request on Transmit Deactivation Timing more information, see 8-Byte Receive FIFO on page 22. WR7’ bit 2 is set to 0, the RTS follows the state of WR5 bit 1. command when this feature is enabled. If this bit is 1, the ESCC automatically transmits an SDLC flag before transmitting data.
PS005308-0609 Z80230/Z85230/L Enhancements Z80230/Z85230/L Product Specification Historically, the SCC latched the databus on the falling edge of WR. However, as many CPUs do not guarantee that the databus is valid when the WR pin goes Low, Zilog modi- fied the databus timing to allow a maximum delay of 20 nS from the WR signal going active Low to the latching of the databus. CRC Reception in SDLC Mode In SDLC mode, the entire CRC is clocked into the receive FIFO. The ESCC completes clocking in the CRC to allow it to be retransmitted or manipulated software. In the SCC, when the closing flag is recognized, the contents of the receive shift register are immedi- ately transferred to the receive FIFO, resulting in the loss of the last two bits of the CRC. In the ESCC, it is not necessary to program this feature. When the closing flag is detected, the last 2 bits of the CRC are transferred into the receive FIFO. In all other SYNCHRONOUS mode, the ESCC does not clock in the last 2 CRC bits (same as the SCC). TxD Forced High in SDLC with NRZI Encoding When Marking Idle When the ESCC is programmed for SDLC mode with NRZI data encoding and Mark Idle (WR10 bit 6 is 0, bit 5 is 1, bit 3 is 1), the TxD pin is automatically forced High when the transmitter enters the Mark Idle state. There are several different ways for the transmitter to enter the Idle state. In each of the following cases the TxD pin is forced High when the Mark Idle condition is reached:
- Data, CRC, flag, and Idle
- Data, flag, and Idle
- Data, abort (on underrun), and Idle
- Data, abort (command), and Idle
- Idle flag and command to Idle Mark The Force High feature is disabled when the Mark Idle bit is set to 0. This feature is used in combination with the automatic SDLC opening flag transmission feature, WR7’ bit 0 is 1, to assure that data packets are formatted correctly. In this case, the CPU is not required to issue any commands. If WR7’ bit 0 is 0, as on the SCC, the Mark Idle bit (WR10 bit 3), is set to 1, to enable flag transmission before an SDLC packet trans- mits. Improved Transmit Interrupt Handling The ESCC latches the TBE interrupt because the CRC is loaded into the Transmit Shift register even if the TBE interrupt, due at the last data byte, has not been reset. The end of a
PS005308-0609 Z80230/Z85230/L Enhancements Z80230/Z85230/L Product Specification Software Interrupt Acknowledge The Z80230/Z85230/L interrupt acknowledge cycle can be initiated using software. If Write Register 9 (WR9 bit 5 is 1), Read Register 2 (RR2) results in an interrupt INTACK cycle, a software acknowledgment causes the INT pin to go High. The IEO pin goes Low. The Interrupt Under Service (IUS) latch is set to the highest priority pending interrupt. When a hardware INTACK signal is desired, a software acknowledge cycle requires that a Reset Highest IUS command be issued in the ISR. If RR2 is read from Channel A, the unmodified vector is returned. If RR2 is read from Channel B, then the vector is modified to indicate the source of the interrupt. The Vector Includes Status (VIS) and No Vector (NV) bits in WR9 are ignored when WR9 bit 5 is set to 1. If the INTACK and IEI pins are not used, they are pulled up to VCC through a resistor (2.2 k?, typical). Fast SDLC Transmit Data Interrupt Response To facilitate the transmission of back-to-back SDLC frames with a single shared flag between frames, the ESCC allows data for a second frame to be written to the transmit FIFO after the Tx Underrun/EOM interrupt occurs. This feature allows application soft- ware more time to write the data to the transmitter while allowing the current frame to conclude with CRC and flag. The SCC required that data not be written to the transmitter until a TBE interrupt is generated after the CRC completed transmission. If data is written to the transmit FIFO after the Transmit Underrun/EOM interrupt is issued but before the TBE interrupt is issued, the Automatic EOM Reset function is enabled (WR7’ bit 1 is 1). Consequently, the commands Reset Tx/Underrun EOM Latch and Reset Tx CRC Generator must never be used. SDLC FIFO Frame Status Enhancement When used with a DMA controller, the ESCC SDLC Frame Status FIFO enhancement maximizes the ESCC’s ability to receive high-speed, back-to-back SDLC messages. It minimizes frame overruns due to CPU latencies in responding to interrupts. The feature (displayed in Figure 15 on page 29) includes:
- 10-bit deep by 19-bit wide status FIFO
- 14-bit receive byte counter
- Control logic The 10 x 19 bits status FIFO is separate from the 8-byte receive data FIFO. When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for the SDLC frame are stored in the 10- x 19-bit status FIFO. This action allows the DMA
Figure 15. SDLC Frame Status FIFO
- All Sent bypasses MUX and equals contents of SCC Status Register.
- Parity bits bypass MUX and equals contents of SCC Status Register.
- EOF is set to 1 whenever reading from the FIFO.
before transferring to memory by the DMA controller.
2 Bits 6 Bits
5 Bits EOF=1 6 Bits
5 Bits 14 Bits
8 Bits
PS005308-0609 Z80230/Z85230/L Enhancements Z80230/Z85230/L Product Specification When a flag is received at the end of an SDLC frame, the frame byte count from the 14-bit counter and 5 status bits are loaded into the status FIFO for verification by the CPU. The CRC checker is automatically reset in preparation for the next frame, which starts immedi- ately. Because the byte count and status are saved for each frame, the message integrity can be verified at a later time. Status information for up to ten frames is stored before a status FIFO overrun occurs. If a frame is terminated with an Abort command, the byte count and status is loaded to the status FIFO and the counter is reset for the next frame. FIFO Enable/Disable This FIFO buffer is enabled when WR15 bit 2 is 1 and the ESCC is in the SDLC/HDLC mode. Otherwise, the status register contents bypass the FIFO and transfer directly to the bus interface (the FIFO pointer logic is reset either when disabled or by a channel or power-on reset). When the FIFO mode is disabled, the ESCC is downward-compatible with the NMOS Z8030/Z8530. The FIFO mode is disabled on power-up (WR15 bit 2 set to 0 on reset). The effects of backward compatibility on the register set are that RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2, and RR7 is an image of RR3. For information on the added registers, see Read Registers on page 53. The status of the FIFO Enable signal is read at RR15 bit 2. If the FIFO is enabled, the bit is set to 1; oth- erwise it is reset to 0. FIFO Read Operation When WR15 bit 2 is 1 and the FIFO is not empty, the next read status register RR1 or the additional registers RR7 and RR6, reads the FIFO. Reading status register RR1 causes one location of the FIFO to empty, so status is read after reading the byte count; otherwise the count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer is switched to allow status to read directly from the status register. In this state, reads from RR7 and RR6 are undefined bit 6 of RR7 (FIFO data available) status data is coming from the FIFO or directly from the status register, because it is set to 1 whenever the FIFO is not empty. Since all status bits are not stored in the FIFO, the All Sent, Parity, and EOF bits bypass the FIFO. The status bits sent through the FIFO are the three Residue Bits, Overrun, and CRC Error. The correct sequence for polling the byte count and FIFO logic is RR7, RR6, then RR1 (reading RR6 is optional). Additional logic prevents the FIFO from emptying by multiple reads from RR1. The read from RR7 latches the FIFO empty/full status bit (bit 6) and steers the status multiplexer to read the ESCC megacell instead of the status FIFO
The ESCC contains write registers in each channel that are programmed by the system separately to configure the function of each channel. In the Z85230/L ESCC, the data FIFOs are directly accessible by selecting a High on the D/C pin. Except WR0 and RR0, programming the write registers requires two write oper- ations and reading a read register requires a write and a read operation. The first Write is to WR0 which contains bits that point to the selected register. If the next operation is a Write the selected write register is written. If the next operation is a read, the selected read regis- ter is read. The pointer bits are automatically cleared after the second operation so the next read or write comes from RR0 or goes to WR0. It is not necessary to write 00 to WR0 to access WR0 or RR0. For the Z80230 ESCC, the registers are directly addressable. A command issued to WR0B determines how the ESCC decodes the address placed on the address/data bus at the beginning of a Read or Write cycle. In Shift Right mode the channel select A/B is taken from AD0 and the state of AD5 is ignored. In Shift Left mode, the channel select A/B is taken from AD5 and the state of AD0 is ignored. AD7 and AD6 are always ignored as address bits and the register address itself occupies AD4–AD1. Initializing The software first issues a series of commands to initialize the basic mode of operation. These commands are followed by other commands to qualify conditions within the selected mode. For example, in the ASYNCHRONOUS mode, character length, clock rate, number of stop bits, and even and odd parity is set first. Next, the INTERRUPT mode is set. Finally, the receiver and transmitter are enabled. Write Registers The ESCC contains 16 write registers (17 counting the transmit buffer) in each channel. These write registers are programmed to configure the function of the channel. There are two registers (WR2 and WR9) shared by the two channels, which can be accessed through either of them. WR2 contains the interrupt vector for both channels. WR9 contains the interrupt control bits and reset commands. Register WR7’ can be written to if WR15 bit 0 is 1. Z80X20 Register Access The Z80230 registers are addressed using the address on AD7–AD0 which are latched by the rising edge of AS. The Shift Right/Shift Left bit in the Channel B WR0 controls which
programming when the current state of the Shift right/Shift Left bit is not known. pendent of the state of the Shift Right/Shift Left bit. address is again placed on AD4–AD1 but the Channel Select A/B is decoded from AD0. contains only one WR2 and WR9; these registers may be written from either channel. at a time. The SHIFT RIGHT mode is used when the channels are programmed the same. Table 5 lists details of the Z80X30 Register Map in SHIFT LEFT Mode. Table 5. Z80230 Register Map (Shift Left Mode)
- The register names in ( ) are the values read out from that register location.
- WR15 bit D2 enables status FIFO function (not available on NMOS).
- WR7’ bit D6 enables extend read function (only on ESCC).
Table 5. Z80230 Register Map (Shift Left Mode) (Continued)
Table 6 lists details of the Z80X30 Register Map in SHIFT RIGHT mode. Table 6. Z80X30 Register Map (Shift Right Mode)
- The register names in ( ) are the values read out from that register location.
- WR15 bit D2 enables status FIFO function (not available on NMOS).
- WR7’ bit D6 enables extend read function (only on ESCC).
selected. Table 7 lists details of the Z8530 Register Map. Table 7. Z85230/L Register Map
- The register names in ( ) are the values read out from that register location.
- WR15 bit D2 enables status FIFO function (not available on NMOS).
- WR7’ bit D6 enables extend read function (only on ESCC).
Table 8 through Table 24 on page 53 list the format of each write register. Table 8. Write Register 0 For the 80230, bits 1 and 0 are accessible only through Channel B.
Table 9. Write Register 1
2 Parity is Special condition
0 Ext Int Enable
Table 10. Write Register 2
7 V7–Interrupt Vector
6 V6–Interrupt Vector
5 V5–Interrupt Vector
4 V4–Interrupt Vector
3 V3–Interrupt Vector
2 V2–Interrupt Vector
1 V1–Interrupt Vector
0 V0–Interrupt Vector
Table 11. Write Register 3
5 Auto Enable
4 Enter HUNT Mode
3 Rx CRC Enable
2 Address Search Mode (SDLC)
1 Sync Character Load Inhibit
0 Rx Enable
Table 12. Write Register 4
1 Stop Bit/Character
1.5 Stop Bits/Character
2 Stop Bits/Character
0 Parity Enable
Table 13. Write Register 5
4 Send Break
3 Tx Enable
0 Tx CRC Enable
Table 14. Write Register 6
Description
Bisync
16 Bits
Bisync
12 Bits SDLC
(Address Range)
7 Sync7 Sync1 Sync7 Sync3 ADR7 ADR7
6 Sync6 Sync0 Sync6 Sync2 ADR6 ADR6
5 Sync5 Sync5 Sync5 Sync1 ADR5 ADR5
4 Sync4 Sync4 Sync4 Sync0 ADR4 ADR4
3 Sync3 Sync3 Sync3 1 ADR3 X
2 Sync2 Sync2 Sync2 1 ADR2 X
1 Sync1 Sync1 Sync1 1 ADR1 X
0 Sync0 Sync0 Sync0 1 ADR0 X
Table 15. Write Register 7
7 Sync7 Sync5 Sync15 Sync11 0
6 Sync6 Sync4 Sync14 Sync10 1
5 Sync5 Sync3 Sync13 Sync9 1
4 Sync4 Sync2 Sync12 Sync8 1
3 Sync3 Sync1 Sync11 Sync7 1
2 Sync2 Sync0 Sync10 Sync6 1
1 Sync1 X Sync9 Sync5 1
0 Sync0 X Sync8 Sync4 0
Table 16. Write Register 7’
6 Extended Read Enable
5 Tx FIFO Int Level
3 Rx FIFO Int Level
2 Auto RTS Deactivation
1 Auto EOM Reset
0 Auto Tx Flag
Table 17. Write Register 8
Table 18. Write Register 9
5 Software INTACK
3 Master Interrupt Enable
2 Disable Lower Chain
1 No Vector
0 Vector Includes Status
Table 19. Write Register 10
7 CRC Preset I/O
4 Go Active on Poll
1 Loop Mode
Table 20. Write Register 11
Table 21. Write Register 12
Table 22. Write Register 13
Table 23. Write Register 14
4 Local Loopback
3 Auto Echo
2 DTR/Request Generator Source
0 BRG Enable
RR3 contains the Interrupt Pending (IP) bits for Channel A. Table 40 on page 69 list the format of the read registers. Table 24. Write Register 15
7 Break/Abort Interrupt Enable
6 Tx Underrun/EOM Interrupt Enable
4 Sync /Hunt
3 DCD Interrupt Enable
2 SDLC FIFO Enable
1 Zero Count Interrupt Enable
0 WR7’ SDLC Feature Enable
Table 25. Read Register 0
7 Break/Abort
6 Tx Underrun/EOM
2 Tx Buffer Empty
1 Zero Count
0 Rx Character Available
Table 26. Read Register 1
7 EOF (SDLC)
6 CRC/Framing Error
5 Rx Overrun Error
3 Residue Code 0
2 Residue Code 1
1 Residue Code 2
0 All Sent
Table 27. Read Register 2 These bits include status information when read from Channel B.
Table 28. Read Register 3
5 Channel A Rx IP
4 Channel A Tx IP
3 Channel A Ext/Status IP
2 Channel B Rx IP
1 Channel B Tx IP
0 Channel B Ext/Status IP
Bits 5, 4, 3, 2, 1 and 0 are always 0 when read from Channel B.
Table 29. Read Register 4 This register reflects the contents of RR0 if WR7’ bit 6 is enabled.
Table 30. Read Register 5 This register reflects the contents of RR1 if WR7’ bit 6 is enabled.
Table 31. Read Register 6
Table 32. Read Register 7
Table 33. Read Register 8
Table 34. Read Register 9
5 Software INTACK Enable
To access this register WR7’ bit 6 must be enabled.
Table 35. Read Register 10
7 One Clock Missing
6 Two Clocks Missing
4 Loop Sending
1 On Loop
Table 36. Read Register 11
Table 37. Read Register 12
Table 38. Read Register 13
Table 39. Read Register 14
Table 40. Read Register 15
register address on the Address/Data bus and the state of INTACK and CS0. (IP) bits. Therefore, AS must be kept cycling for the interrupt section to function. results in a recovery time related to PCLK. access. Figure 17 displays the Write cycle timing. Figure 17. Z80230 Write Cycle Timing
are enabled while CS1 is High and DS is Low. Figure 18. Z80230 Read Cycle Timing
- The address on A7-A0 and the state of CS0 and INTACK are latched by the rising -
are ignored for the duration of the interrupt acknowledge cycle. The Z80230 samples the state of INTACK on the rising edge of AS, and AC parameters. Parameters 7 and 8 of Table 45 on page 83, specify the setup and hold time requirements. Note 5 of Table 45, for the time required to settle the daisy chain.
sor does not supply AS strobes during the time in between accesses of the Z80230. Figure 19. Z80230 Interrupt Acknowledge Cycle Timing The ESCC generates internal control signals from WR and RD that relate to PCLK.
Electrical Characteristics
Stresses greater than those listed in this section can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition above those indicated in the operational section of this specification is not implied. Exposure to abso- lute maximum rating conditions for extended periods can affect reliability. Standard Test Conditions The DC Characteristics and capacitance sections apply for the following standard test conditions, unless otherwise noted. All voltages reference GND. Positive current flows into the referenced pin. Standard conditions are as follows:
- GND = 0 V
- T as specified in Ordering Information
- +4.5V VCC +5.5V" or +3.0 V VCC +3.6V (Z8523L only) VCC Supply Voltage Range –0.3 V to +7.0 V Voltages on All Pins with Respect to GND –0.3 V to VCC +0.3 V Operating Ambient Temperature See Ordering Information on page 107 Storage Temperatures –65º C to +150º C
Table 42 lists the DC characteristics for the Z80230/Z85230 device. Table 42. Z80230/Z85230 DC Characteristics
- Vcc=5 V ± 10% unless otherwise specifi ed, over specified temperature range.
- Typical Icc was measured with oscillator off.
- No Icc(osc) max is specified becaus e of dependency on the external circuit.
Table 43 lists the DC characteristics for the Z8523L device. Figure 24 on page 79 displays the Z80230 Read/Write timing diagram. Table 43. Z8523L DC Characteristics
- Vcc=3.3 V ± 10% unless otherwise specif ied, over specified temperature range.
- Typical Icc was measured with oscillator off.
- No Icc(osc) max is specified becaus e of dependency on the external circuit.
- I/O pins are NOT 5V tolerant
Figure 24. Z80230 Read/Write Timing Diagram
Table 44 lists the Z80230 general timing characteristics details. Table 44. Z80230 General Timing Characteristics
10 MHz 16 MHz
1 TdPC (REQ) PCLK Low to W /REQ Valid 200 110 9
2 TsPC (W) PCLK Low to Wait Inactive 300 180 9
3 TsRXC (PC) RxC High to PCLK High Setup
4 TsRXD (RXCr) RxD to RxC High Setup Time 0 0 1,9
5 ThRXD (RxCr) RxD to RxC High Hold Time 125 60 1,9
6 TsRXD (RXCf) RxD to RxC Low Setup Time 0 0 1, 5, 9
7 ThRXD (RXCf) RxD to RxC Low Hold Time 125 60 1, 5, 9
8 TsSY (RXC) SYNC
9 ThSY (RXC) SYNC to RxC High Hold Time 5 5 1, 10
10 TsTXC (PC) TxC Low to PCLK High Setup
11 TdTXCf (TXD) TxC Low to TxD Delay 150 85 2, 9
12 TdTxCr (TXD) TxC High to TxD Delay 150 85 2, 5, 9
13 TdTXD (TRX) TxD to TRxC
14 TwRTXh RTxC High Width 120 80 6, 9
15 TwRTXI TRxC Low Width 120 80 6, 9
17 TcRTXX Crystal Oscillator Period 100 1000 100 1000 3, 9
18 TwTRXh TRxC
19 TwTRXI TRxC Low Width 120 80 6, 9
20 TcTRX TRxC Cycle Time 400 244 6, 7, 9
21 TwEXT DCD or CTS Pulse Width 120 70 9
22 TwSY SYNC Pulse Width 120 70 9
Table 45 lists the Z80230 Read and Write AC characteristics.
- RxC is RTxC or TRxC, whichever is supplying the receive clock.
- TxC is TRxC or RTxC, whichever is supplying the transmit clock.
- Both RTxC and SYNC have 30 pf capacitors to ground connected to them.
- Synchronization of RxC to PCLK is eliminated in divide by four operation.
- Parameter applies only to FM encoding/decoding.
- Parameter applies only for transmitter and receiver; DPLL and BRG timing requirements are identical to PCLK
- The maximum transmit or receive data rate is 1/4 PCLK.
- Applies to the DPLL clock source only. Maximum data ra te of 1/4 PCLK still applies. DPLL clock must have a
Table 45. Z80230 AC Characteristics
2 TdDS (AS) DS Rise to AS Fall Delay 10 10 1, 8
3 TsCS0 (AS) CS0 to AS Rise Setup Time 0 0 1, 8
4 ThCS0 (AS) CS0 to AS Rise Hold Time 20 15 1, 8
5 TsCS1 (DS) CS1 to DS Fall Setup Time 50 35 1, 8
6 ThCS1 (DS) CS1 to DS Rise Hold Time 20 10 1, 8
7 TsIA (AS) INTACK to AS Rise Setup Time 10 10 8
8 ThIA (AS) INTACK to AS Rise Hold Time 125 100 8
9 TsRWR
10 ThRW (DS) R/W to DS Rise Hold Time 0 0 8
11 TsRWW
12 TdAS (DS) AS Rise to DS Fall Delay 20 15 8
Table 44. Z80230 General Timing Characteristics (Continued)
13 TwDSI DS Low Width 125 80 8
14 TrC Valid Access Recovery Time 4 4 2, 9
15 TsA (AS) Address to AS Rise Setup Time 10 10 1, 8
16 ThA (AS) Address to AS Rise Hold Time 20 10 1, 8
17 TsDW (DS) Write Data to DS Fall Setup Time 10 10 8
18 ThDW (DS) Write Data to DS Rise Hold Time 0 0 8
19 TdDS (DA) DS Fall to Data Active Delay 0 0 8
20 TdDSr (DR) DS Rise to Read Data Not Valid
21 TdDSf (DR) DS Fall to Da ta Active Delay 120 70 8
22 TdAS (DR) AS Rise to Read Data Valid Delay 190 110 8
23 TdDS (DRz) DS Rise to Read Data Float
24 TdA (DR) Address Required Valid to Read
25 TdDS (W) DS Fall to Wait Valid Delay 160 60 4, 8
26 TdDSf
27 TdDSr
28 TdAS (INT) AS Rise to INT Valid Delay 500 175
29 TdAS (DSA) AS Rise to DS Fall
30 TsDSA DS (Acknowledge) Low Width 125 75 8
31 TdDSA (DR) DS Fall (Acknowledge) to Read
32 TsIEI (DSA) IEI to DS Fall (Acknowledge)
33 ThIEI (DSA) IEI to DS Rise (Acknowledge)
Table 45. Z80230 AC Characteristics (Continued)
34 TdIEI (IEO) IEI to IEO Delay 90 45 8
35 TdAS (IEO) AS Rise to IEO Delay 175 80 6
36 TdDSA (INT) DS Fall (Acknowledge) to INT
37 TdDS (ASQ) DS Rise to AS Fall Delay for No
38 TdASQ (DS) AS Rise to DS Fall Delay for No
39 TwRES AS and DS Coincident Low for
40 TwPCl PCLK Low Width 40 100 26 1000 8
41 TwPCh PCLK High Width 40 1000 26 1000 8
42 TcPc PCLK Cycle Time 100 2000 61 2000 8
43 TrPC PCLK Rise Time 10 5 8
44 TfPC PCLK Fall Time 10 5 8
- Parameter does not apply to Interrupt Acknowledge transactions.
- Parameter applies only between transactions involving the ESCC.
- Float delay is defined as the time required for a ±0.5 V change in the output with a maximum DC load and a min-
- Open-drain output, measured with open-drain test load.
- Parameter is system-dependent. For any Zilog ESCC in the daisy chain. TdAS (DSA) must be greater than the
(IEO) for each device separating them in the daisy chain.
- Parameter applies only to a Zilog ESCC pulling INT Low at the beginning of the Interrupt Acknowledge transac-
- Internal circuitry allows for the reset provided by the Z8
references assume 2.0 V for a 1 and 0.8 V for a logic 0.
Table 46 lists the Z80230 system timing parameter details. Z85230/L Cycle Timing Diagram. Table 46. Z80230 System Timing Table
1 TdRXC (REQ) RxC High to W/REQ Valid 13 17 13 17 2, 5
2 TdRXC (W) RxC High to Wait Inactive 13 19 13 19 1, 2, 5
3 TdRXC (SY) RxC High to SYNC Valid 9 12 9 12 2, 5
4 TdRXC (INT),
5 TdTXC (REQ) TxC Low to W/REQ Valid 11 14 11 14 3, 5
6 TdTXC (W) TxC Low to Wait Inactive 8 14 8 14 1, 3, 5
7 TdTXC (DRQ) TxC Low to DTR/REQ Valid 3, 5
8 TdTXC (INT),
9 TdSY (INT) SYNC to INT Valid 2
10 TdEXT (INT),
- Open-drain output, measured with open-drain test load.
- RxC is RTxC or TRxC, whichever is supplying the receive clock.
- TxC is TRxC or RTxC, whichever is supplying the transmit clock.
Figure 29. Z85230/L Read/Write Timing Diagram
Table 47 lists the Z85230/L Read and Write AC characteristics details. Table 47. Z85230/L AC Characteristics (20MHz applies only to Z85230)
8.5 MHz 10 MHz 16 MHz 20 MHz
1 TwPCl PCLK Low Width 45 1000 40 1000 26 1000 22 1000 6
2 TxPCh PCLK High Width 45 1000 40 1000 26 1000 22 1000 6
3 TfPC PCLK Fall Time 10 10 5 5 6
4 TrPC PCLK Rise Time 10 10 5 5 6
5 TcPc PCLK Cycle Time 118 2000 100 2000 61 2000 50 2000 6
6 TsA Address to WR fall
7 ThA (WR) Address to WR
8 TsA (RD) Address to RD Fall
9 ThA (RD) Address to RD
10 TsIA (PC) INTACK to PCLK
11 TsIAi (WR) INTACK to WR
12 ThIA (WR) INTACK to WR
13 TsIAi (RD) INTACK to RD Fall
14 ThIA (RD) INTACK to RD
15 ThIA (PC) INTACK to PCLK
16 TsCEI (WR) CE Low to WR Fall
17 ThCE (WR) CE to WR Rise
18 TsCEh (WR) CE High to WR
19 TsCEI (RD) CE Low to RD Fall
20 ThCE ((RD) CE to RD Rise
21 TsCEh (RD) CE High to RD Fall
22 TwRDI RD Low Width 145 125 70 65 1, 6
23 TdRD (DRA) RD Fall to Read
24 TdRDr (DR) RD Rise to Data
25 TdRDI RD Fall to Read
26 TdRD (DRz) RD Rise to Read
27 TdA (DR) Addr to Read Data
28 TwWRI WR Low Width 145 125 75 65 6
29 TdWR (DW) WR Fall to Write
30 ThDW (WR) Write Data to WR
31 TdWR (W) WR Fall to Wait
32 TdRD (W) RD Fall to Wait
33 TdWRf
34 TdRDf
Table 47. Z85230/L AC Characteristics (20MHz applies only to Z85230) (Continued)
36 TdRDr
37 TdPC (INT) PCLK Fall to INT
38 TdIAi (RD) INTACK to RD Fall
39 TwRDA RD (Acknowledge)
40 TdRDA (DR) RD Fall (ACK) to
41 TsIEI (RDA) IEI to RD Fall
42 ThIEI (RDA) IEI to RD Rise
43 TdIEI (IEO) IEI to IEO Delay
44 TdPC (IEO) PCLK Rise to IEO
45 TdRDA
46 TdRD
47 TdWRQ
48 TwRES WR and RD Low
49 Trc Valid Access
- Parameter does not apply to Interrupt Acknowledge transactions.
- Parameter applies only between transactions involving the ESCC.
- Open-drain output, measured with open-drain test load.
- Parameter is system-dependent. For any ESCC in the daisy chain, TdIAi (RD) must be greater than the sum of
device separating them in the daisy chain.
- Parameter applies to enhanced Request mode only (WR7’ bit 4=1)
- Applies to 8523L (3V version) only
the Z85230/L Read/Write Timing characteristics details. Table 48. Z85230/L General Timing Table (20MHz applies only to Z85230)
1 TdPC (REQ) PCLK to W /REQ
2 TdPC (W) PCLK to Wait
3 TsRXC (PC) RxC to PCLK
4 TsRXD
6 TsRXD
8 TsSY (RXC) SYNC to RXC
9 ThSY (RXC) SYNC to RXC
10 TsTXC (PC) TxC to PCLK
11 TdTXCf
12 TdTxCr
14 TwRTXh RTxC High
15 TwRTXI RTxC Low Width 130 120 80 70 6, 9
18 TwRTXh TRxC High
19 TwTRXI TRxC Low Width 130 120 80 70 6, 9
20 TcTRX TRxC Cycle
21 TwEXT DCD or CTS
22 TwSY SYNC Pulse
- RxC is RTxC or TRxC, whichever is supplying the receive clock.
- TxC is TRxC or RTxC, whichever is supplying the transmit clock.
- Both RTxC and SYNC have 30 pF capacitors to ground connected to them.
- Synchronization of RxC to PCLK is eliminated in divide by four operation.
- Parameter applies only to FM encoding/decoding.
- Parameter applies only for transmitter and receiver; DPLL and
- The maximum receive or transmit data rate is 1/4 PCLK.
- Applies to the DPLL clock source only. Maximum data ra te of 1/4 PCLK still applies. DPLL clock must have a
Table 48. Z85230/L General Timing Table (20MHz applies only to Z85230) (Continued)
Table 49. Z85230/L System Timing Characteristics (20MHz applies only to Z85230)
2 TdRXC (W) RxC to Wait
3 TdRXC (SY) RxC to SYNC
4 TdRXC (INT) RxC to INT Valid 15 21 15 21 15 21 15 22 1, 2, 4
6 TdTXC (W) TxC to Wait
8 TdTXC (INT) TxC to INT Valid 7 13 7 13 7 13 7 14 1, 3, 4
9 TsSY (INT) SYNC to INT V a l i d 27 27 27 27 1 , 4
10 TdEXT (INT) DCD or CTS to
- Open-drain output, measured with open-drain test load.
- RxC is RTxC or TRxC, whichever is supplying the receive clock.
- TxC is TRxC or RTxC, whichever is supplying the transmit clock.
PS005308-0609 Z80230/Z85230/L Errata Z80230/Z85230/L Product Specification Z80230/Z85230/L Errata The current revision of Zilog’s ESCC has six known bugs. This section identifies these bugs and provides workarounds. IUS Problem Description The IUS problem occurs under the following conditions:
- SDLC 10x19 Status FIFO is enabled
- Interrupts on Receive Special Conditions only This mode is intended for an application where received characters are read by a DMA controller. EOF is treated differently from other special conditions (for example, parity error, overrun error, and CRC error). When EOF is detected, the following conditions occur:
- A Receive Character Available (RCA) interrupt is generated, rather than the Special Conditions interrupt, as in other operating modes.
- The data FIFO is not locked, as in other operating modes, and is known as the Anti- Lock feature. This feature allows the processor to service the EOF interrupt with more latency. Immedi- ate attention from the processor is not necessary because the data FIFO is not locked. Incoming data can still be delivered to the Receive FIFO and not get lost. It also allows for operation with no servicing of the interrupt. When the EOF interrupt (RCA interrupt) is serviced, the processor must use the Reset Highest IUS command to clear the EOF. If an EOF interrupt occurs when another lower priority interrupt is enabled (for example, Ext/Status interrupt is serviced) the Reset Highest IUS command issued by the lower priority ISR (to clear out the pending interrupt) can accidentally clear the pending EOF interrupt. The Reset Highest IUS command clears the IP bit related to the EOF (in this mode, the RCA IP bit) regardless of the priorities of the pending interrupts. This action causes errors under the following circumstances:
- Another ESCC interrupt is being serviced (for example, an Ext/Status interrupt for Transmitter Underrun in Full Duplex operation)
- The DMA reads a byte marked with EOF. The corresponding IP bit is set to 1 and the INT line goes Low (highest priority interrupt in the daisy chain).
PS005308-0609 Z80230/Z85230/L Errata Z80230/Z85230/L Product Specification 100
- The processor does not acknowledge this interrupt because it is servicing another interrupt.
- The processor finishes servicing the other interrupt and uses the Reset Highest IUS command.
- The IP bit reset corresponding to the EOF, and the EOF interrupt is lost. IUS Problem Solutions The following methods can be used to work around the previously described problems.
- Alternate Operating Mode–A similar operating mode can be used to achieve the same functionality with minimum code modifications. The ESCC must operate in Receive Interrupts on First Character and Special Condition, instead of Receive Interrupt on Special Condition Only. In this mode, the Anti-Lock feature is not enabled. The FIFO is locked after the last character of a frame has been transferred, and the interrupt condition does not disappear until after an Error Reset command is issued to the ESCC. No Reset Highest IUS command can clear any IP bit.
- Daisy Chain– This workaround uses the following two conditions: – The EOF interrupt is the highest priority interrupt if only one channel is used. – Channel A is the only channel issuing interrupts. If both conditions are satisfied, allowing nested interrupts can solve the problem. The processor servicing an interrupt on the daisy chain must be interruptible again from another interrupt of higher priority on that same daisy chain.
- RR7 Register–This workaround is applicable if the EOF interrupt is used only to notify another part of the software that there has been another frame received: – Read RR7 after issuing the Reset IUS command. – Check bit 6 of RR7. This bit, when set, indicates that the SDLC frame FIFO con- tains a valid frame. Although one interrupt might have been lost (IP reset) by the Reset IUS command, bit 6 of RR7 always indicates that at least one frame is available in the frame FIFO. If bit 6 of RR7 is 1, notify the concerned part of the software that at least one frame is available in the frame FIFO. When the SDLC FIFO is enabled and Receive Interrupts on Special Conditions Only is selected, software checks that there is a Receive Character Available interrupt, which is generated by DMA reading an EOF character, and before issuing the Reset Highest IUS command. Otherwise, the EOF interrupt conditions are cleared by that command.
PS005308-0609 Z80230/Z85230/L Errata Z80230/Z85230/L Product Specification 103 back frames are sent. The TxD output is automatically forced High for eight bit-times and the first byte of the second frame is corrupted. In a multiple-frame transmission, a zero (0) bit is inserted before the opening flag of the second frame. Automatic TxD Forced High Problem Solutions Send back-to-back frames in FLAG IDLE mode, because the Automatic TxD Forced High feature creates problems only if all the following conditions are true:
- Back-to-back frame transmission
- NRZI
- Mark Idle Setting the system in Flag Idle mode (WR10 bit 3 equals 0) in frame transmission allows back-to-back frames to be sent without any data corruption. SDLC FIFO Overflow Problem Description In SDLC mode, bit 7 of RR7 (FIFO Overflow status bit) is set if an 11th frame ends while the FIFO is full (that is, ten frames have accumulated in the Status FIFO and have not yet been read by the processor). Under this circumstance, the status FIFO is locked and no data can be written to the Status FIFO until bit 7 of RR7 is reset. If the ESCC is set up in ANTI-LOCK mode (that is, the SDKC FIFO is used when Receive Interrupts on Special Condition Only is enabled), the only method of resetting bit 7 of RR7(the FIFO Overflow bit) is to reset and set WR15 bit 2 (SDLC FIFO Enable Bit). This action causes the SDLC FIFO to reset and all the SDLC frame information is lost. With no Anti-Lock feature, the FIFO Overflow status bit is reset if the SDLC FIFO is read. If the ESCC is in NRZI and Mark Idle in back-to-back frame transmission, (one the FIFO Overflow bit RR7 bit 7) is set, the only method of resetting the status is to reset and set WR15 bit 2. This action causes the SDLC FIFO to reset and the unprocessed frame infor- mation stored in the SDLC FIFO is lost. SDLC FIFO Overflow Problem Solution Do not use Receive Interrupts on Special Conditions Only and Mark Idle if there is a pos- sibility of Status FIFO Overflow. Default RR0 Value Problem Description RR7 bit 7, the Break/Abort status bit, does not always clear after reset. Default RR0 Value Problem Solution Ignore the first bit 7 value read from RR0 after reset.
PS005308-0609 Z80230/Z85230/L Errata Z80230/Z85230/L Product Specification 104 Default RR10 Value Problem Description RR10 bit 6, the 2 clock missing bit, is sometimes erroneously set to indicate that the DPLL detects a clock edge in two successive tries after hardware reset. Default RR10 Value Problem Solution Ignore the first bit 7 value Read from RR10 after reset. CRC Problem Description The CRC cannot be interpreted from the Receive FIFO when one or two residue bits are sent. The CRC value is received and checked correctly but is not loaded to the Receive FIFO. The two types of CRC problems are described below:
- Two Residue bits (Residue code is 000) The last three bytes of the Receive FIFO read: Bits 6 and 7 of the CRC are lost.
- One Residue Bit (Residue code is 111) The last three bytes of the Receive FIFO read: Bit 7 of the CRC is lost. The CRC is received and loaded into the Receive FIFO in other situations (that is, the 0, 3, 4, 5, 6, and 7 residue bits). The Residue code, RR1 bits 3, 2, and 1, is reported independently of the number of residue bits sent. CRC Problem Solution Ignore the CRC value read from the Receive FIFO if one or two residue bits are sent. D7 D6 D5 D4 D3 D2 D1 D0 C5 C4 C3 C2 C1 C0 D9 D8 C15 C14 C13 C12 C11 C10 C9 C8 D7 D6 D5 D4 D3 D2 D1 D0 C6 C5 C4 C3 C2 C1 C0 D8 C15 C14 C13 C12 C11 C10 C9 C8
Figure 38 displays the 44-pin Plastic Leaded Chip Carrier (PLCC) package. Figure 38. 44-Pin PLCC Package Diagram
- LEADS ARE COPLANAR WITHIN 0.004".
- CONTROLLING DIMENSION : INCH
1.27 BSC
0.050 BSC
Ordering Information
Order the required ESCC from Zilog using the following part details. For more informa- tion on ordering, consult your local Zilog sales offices. The Zilog website (www.zilog.com) lists all the regional offices and provides additional product information. Z8523L (3.3V) Z85230 (5V) Z8523L Available Packages
8 MHz Z8523L Z8523L08VSG
10 MHz Z8523L Z8523L10VSG
16 MHz Z8523L Z8523L16VSG
8 MHz Z85230 Z8523008PSG
10 MHz Z85230 Z8523010PSG
16 MHz Z85230 Z8523016PSG
20 MHz Z85230 Z8523020PSG
Part Number Suffix Designation Z80230 Available Packages
10 MHz Z80230 Z8023010PSG
16 MHz Z80230 Z8023016PSG
G = Green Plastic Packaging Compound Temperature E = -40C to +100C S = 0C to +70C Package P = Plastic DIP (PDIP) V = Plastic LCC (PLCC) Speed 8 = 8.0 MHz 10 = 10.0 MHz 16 = 16.384 MHz 20 = 20 MHz Product Number Zilog Prefix
PS005308-0609 Customer Support Z80230/Z85230/L Product Specification 112 Customer Support For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com.
PS005308-0609 P R E L I M I N A R Y Index 108 Index A abort character 18 absolute maximum ratings 75 AC characteristics 78 AC characteristics table, Z85230 90 AC characteristics, Z85230 87 asynchronous receive mode 4 auto echo and logical loopback 21 auto enable 4 automatic EOM reset 28 B baud rate generator 19 bisync 4, 16 block transfer, CPU/DMA 15 C capacitance 76 character abort 18 EOP 18 code NRZ 18 NRZI 18 command reset highest IUS 28 reset Tx CRC generator 28 reset Tx/underrun latch 28 counter transmit clock 5 CRC problem description 104 solution 104 CRC reception in SDLC mode 26 Customer Feedback Form 112 D data communications capabilities 15 data encoding 20 DC characteristics 77 default RR0 value problem description 103 solution 103 default RR10 value problem description 104 solution 104 device type identification 24 diagram 40-pin DIP package 105 44-pin PLCC package 106 automatic RTS deactivation 102 cycle timing, Z85230 89 data encoding methods 20 detecting 5-or 7-bit characters 16 DPLL Outputs 27 ESCC protocols 15 general timing, Z80230 81 general timing, Z85230 94 interrupt acknowledge cycle timing, Z80230 interrupt acknowledge cycle timing, Z85230 interrupt acknowledge timing, Z80230 80 interrupt acknowledge timing, Z85230 89 interrupt priority schedule 13 read cycle timing, Z80230 71 read cycle timing, Z85230 73 read/write timing, Z80230 79 read/write timing, Z85230 88 receive data path 9 reset timing, Z80230 80 reset timing, Z85230 89 resetting highest IUS from lower priority 101 SDLC frame status FIFO 29 SDLC loop 18 standard and open-drain test conditions 76 system timing, Z80230 86 system timing, Z85230 98 transmit data path 8 TxIP latching 27
PS005308-0609 P R E L I M I N A R Y Index 109 write cycle timing,Z85230 74 Z80230 pin assignments 3 Z80230 pin functions 2 Z85230 pin assignments 3 Z85230 pin functions 2 digital phase-locked loop 5, 19 DPLL counter Tx clock source 27 E encoding, data 20 end of poll (EOP) character 18 enhancements receive FIFO, 8 bytes 22 transmit FIFO, 4 bytes 22 Z80230 and Z85230 22 EOP 18 errata 99 ESCC programming 32 read registers 53 write registers 32 external synchronization 4 F FIFO anti-lock feature 31 enable/disable 30 read operation 30 write operation 31 functional description 8 G general timing characteristics table, Z80230 82 general timing table, Z85230 95 I identification, device types 24 IE 12 input/output capabilities 9 INTACK 13 interface timing, Z80230 70 internal synchronization 4 interrupt acknowledge cycle timing Z80230 71 Z85230 74 interrupts 12 external/status 13, 14 interrupt cknowledge (INTACK) 13 interrupt enable (IE) 12 interrupt on all receive characters or special re- ceive conditions 14 interrupt on first receive character or special re- ceive condition 14 interrupt on special receive conditions only 14 interrupt pending (IP) 12, 13 interrupt under service (IUS) 12, 13 receive 13 receive character available 22 transmit 13 transmit buffer empty 22, 24 Tx underrun/EOM 28 IUS latch 28 IUS problem description 99 solutions 100 L latch ISU 28 RR0 27 TxIP 26 local loopback 21 M mark idle 26 mode 1x 18 asynchronous receive 4 auto echo 21 request on transmit 24 SDLC 17
PS005308-0609 P R E L I M I N A R Y Index 110 SDLC loop 18 SDLC status FIFO 19 synchronous 16 monosync 4, 16 N no vector (NV) 28 NV 28 O ordering information 107 P package information 105 part number descriiption 108 pin assignments Z80230 3 Z85230 3 pin descriptions 1 pin functions Z80230 2 Z85230 2 pins, common CTSA 4 CTSB 4 DCDA 4 DCDB 4 DTR/REQA 4 DTR/REQB 4 IEI 5 IEO 5 INT 6 INTACK 6 PCLK 5 RTSA 4 RTSB 4 RTxCA 5 RTxCB 5 RxDA 5, 16 RxDB 5, 16 SYNCA 4 SYNCB 4 TRxCA 5 TRxCB 5 TxDA 5 TxDB 5 W/REQA 5 W/REQB 5 pins, Z80230 exclusive A7-A0 6 AS 7 CS0 7 CS1 7 DS 7 R/W 6 pins, Z85230 exclusive CE 6 Channels A/B 6 D/C 6 D7-D0 6 RD 6 WR 6 polynomial, SDLC CRC 17 R ratings, absolute maximum 75 read cycle timing Z80230 71 Z85230 73 read register (RR) 10 read registers 53 receive conditions 14 request on receive 22 request on transmit 22 request on transmit mode 24 reset highest IUS command 28 reset Tx CRC generator command 28 reset Tx/underrun EOM latch 28 RR 10 RR0 latch 27 RTS problem description 101 solutions 102
PS005308-0609 P R E L I M I N A R Y Index 111 S SDLC CRC polynomial 17 FIFO frame status enhancement 28 loop mode 18 mode, CRC reception 26 mode, TxD forced high 26 status FIFO 19 status FIFO anti-lock feature 31 transmit data interrupt response 28 SDLC FIFO overflow problem description 103 solutions 103 SDLC mode 17 software interrupt acknowledge 28 standard test conditions 75 synchronization external 4 internal 4 synchronous modes 16 system timing characteristics table, Z85230 98 T timing, Z85230 72 transmit buffer empty interrupt 22 transmit clock counter 5 Tx underrun/EOM interrupt 28 TxD forced high in SDLC mode 26 TxD forced high problem description 102 solutions 103 TxIP latch 26 V vector includes status (VIS) 28 VIS 28 W WR 10 WR7’ 9, 23 write cycle timing Z80230 70 Z85230 73 write register (WR) 10 write register 7 prime (WR&’) 23 write register 7 prime (WR7’) 9 bit 0 25 bit 1 25 bit 2 25 bit 3 25 bit 4 24 bit 5 24 bit 6 24 bit 7 24 write registers 32