Z8018006FSC

Z8S18020FSC ZILOG | Alldatasheet

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P RELIMINARY P RODUCT S PECIFICATION Z80180/Z8S180/ Z8L180 SL1919 E NHANCED Z180 M ICROPROCESSOR

FEATURES

n Code Compatible with Zilog Z80 CPU n Extended Instructions n Two Chain-Linked DMA Channels n Low Power-Down Modes n On-Chip Interrupt Controllers n Three On-Chip Wait-State Generators n On-Chip Oscillator/Generator n Expanded MMU Addressing (up to 1 MB) n Clocked Serial I/O Port n Two 16-Bit Counter/Timers n Two Enhanced UARTs (up to 512 Kbps) n Clock Speeds: 6, 8, 10, 20, 33 MHz n Operating Range: 5V (3.3V@ 20 MHz) n Operating Temperature Range: 0 C to +70 C n -40 C to +85 C Extended Temperature Range n Three Packaging Styles – 68-Pin PLCC – 64-Pin DIP – 80-Pin QFP GENERAL DESCRIPTION The enhanced Z80180/Z8S180/Z8L180 significantly im- proves on the previous Z80180 models while still providing full backward compatibility with existing Zilog Z80 devices. The Z80180/Z8S180/Z8L180 now offers faster execution speeds, power saving modes, and EMI noise reduction. This enhanced Z180 design also incorporates additional feature enhancements to the ASCIs, DMAs, and I cc STANDBY Mode power consumption. With the addition of “ESCC-like” Baud Rate Generators (BRGs), the two ASCIs now have the flexibility and capability to transfer data asyn- chronously at rates of up to 512 Kbps. In addition, the ASCI receiver has added a 4-byte First In First Out (FIFO) which can be used to buffer incoming data to reduce the inci- dence of overrun errors. The DMAs have been modified to allow for a “chain-linking” of the two DMA channels when set to take their DMA requests from the same peripherals device. This feature allows for non-stop DMA operation be- tween the two DMA channels, reducing the amount of CPU intervention (Figure 1). Not only does the Z80180/Z8S180/Z8L180 consume less power during normal operations than the previous model, it has also been designed with three modes intended to fur- ther reduce the power consumption. Zilog reduced I cc pow- er consumption during STANDBY Mode to a minimum of m A by stopping the external oscillators and internal clock. The SLEEP mode reduces power by placing the CPU into a “stopped” state, thereby consuming less cur- rent while the on-chip I/O device is still operating. The SYSTEM STOP mode places both the CPU and the on- chip peripherals into a “stopped” mode, thereby reducing power consumption even further. A new clock doubler feature has been implemented in the Z80180/Z8S180/Z8L180 device that allows the program- mer to double the internal clock from that of the external clock. This provides a systems cost savings by allowing the use of lower cost, lower frequency crystals instead of the higher cost, and higher speed oscillators. The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages.

Figure 1. Z80180/Z8S180/Z8L180 Functional Block Diagram

Figure 2. Z80180 64-Pin DIP Pin Configuration

Figure 3. Z80180/Z8S180/Z8L180 68-Pin PLCC Pin Configuration

Figure 4. Z80180/Z8S180/Z8L180 80-Pin QFP Pin Configuration

Table 1. Z80180/Z8S180/Z8L180 Pin Identification

Table 2. Pin Status During RESET BUSACK and SLEEP

Enhanced Z180 Microprocessor Zilog 1-10 P R E L I M I N A R Y DS971800401 PIN DESCRIPTIONS A0-A19. Address Bus (Output, active High, tri-state). A0- A19 form a 20-bit address bus. The Address Bus provides the address for memory data bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64K. The address bus enters a high-impedance state during reset and external bus acknowledge cycles. Address line A18 is multiplexed with the output of PRT channel 1 (T OUT , selected as ad- dress output on reset) and address line A19 is not avail- able in DIP versions of the Z80180. BUSACK. Bus Acknowledge (Output, active Low). /BUSACK indicated the requesting device, the MPU ad- dress and data bus, and some control signals, have en- tered their high-impedance state. /BUSREQ. Bus Request (Input, active Low). This input is used by external devices (such as DMA controllers) to re- quest access to the system bus. This request has a higher priority than /NMI and is always recognized at the end of the current machine cycle. This signal will stop the CPU from executing further instructions and places address and data buses, and other control signals, into the high-imped- ance state. CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional, active High). When in output mode, these pins are the transmit and receive clock outputs from the ASCI baud rate generators. When in input mode, these pins serve as the external clock inputs for the ASCI baud rate genera- tors. CKA0 is multiplexed with /DREQ0, and CKA1 is mul- tiplexed with /TEND0. CKS. Serial Clock (Bidirectional, active High). This line is clock for the CSIO channel. PHI CLOCK. System Clock (Output, active High). The out- put is used as a reference clock for the MPU and the ex- ternal system. The frequency of this output is equal to one- half that of the crystal or input clock frequency. /CTS0 - /CTS1. Clear to send 0 and 1 (Inputs, active Low). These lines are modem control signals for the ASCI chan- nels. /CTS1 is multiplexed with RXS. D0 - D7. Data Bus = (Bidirectional, active High, tri-state). D0 - D7 constitute an 8-bit bi-directional data bus, used for the transfer of information to and from I/O and memory de- vices. The data bus enters the high-impedance state dur- ing reset and external bus acknowledge cycles. DCD0. Data Carrier Detect 0 (Input, active Low). This is a programmable modem control signal for ASCI channel 0. /DREQ0, /DREQ1. DMA Request 0 and 1 (Input, active Low). /DREQ is used to request a DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these inputs to determine when an external device is ready for a read or write operation. These inputs can be pro- grammed to be either level or edge sensed. /DREQ0 is multiplexed with CKA0. E. Enable Clock (Output, active High). Synchronous ma- chine cycle clock output during bus transactions. EXTAL. External Clock Crystal (Input, active High). Crys- tal oscillator connections. An external clock can be input to the Z80180/Z8S180/Z8L180 on this pin when a crystal is not used. This input is Schmitt triggered. /HALT. Halt/SLEEP (Output, active Low). This output is asserted after the CPU has executed either the HALT or SLP instruction, and is waiting for either non-maskable or maskable interrupt before operation can resume. It is also used with the /M1 and ST signals to decode status of the CPU machine cycle. /INT0. Maskable Interrupt Request 0 (Input, active Low). This signal is generated by external I/O devices. The CPU will honor these requests at the end of the current instruc- tion cycle as long as the /NMI and /BUSREQ signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the /M1 and /IORQ signals will become active. /INT1, /INT2. Maskable Interrupt Request 1 and 2 (Inputs, active Low). This signal is generated by external I/O devic- es. The CPU will honor these requests at the end of the current instruction cycle as long as the /NMI, /BUSREQ, and /INT0 signals are inactive. The CPU will acknowledge these requests with an interrupt acknowledge cycle. Unlike the acknowledgment for /INT0, during this cycle neither the /M1 or /IORQ signals will become active. /IORQ. I/O Request (Output, active Low, tri-state). /IORQ indicates that the address bus contains a valid I/O address for an I/O read or I/O write operation. /IORQ is also gener- ated, along with /M1, during the acknowledgment of the /INT0 input signal to indicate that an interrupt response vector can be place onto the data bus. This signal is anal- ogous to the /IOE signal of the Z64180. /M1. Machine Cycle 1 (Output, active Low). Together with /MREQ, /M1 indicates that the current cycle is the Opcode fetch cycle of and instruction execution. Together with /IORQ, /M1 indicates that the current cycle is for an inter- rupt acknowledge. It is also used with the /HALT and ST signal to decode status of the CPU machine cycle. This signal is analogous to the /LIR signal of the Z64180. /MREQ. Memory Request (Output, active Low, tri-state). /MREQ indicates that the address bus holds a valid ad- dress for a memory read or memory write operation. This signal is analogous to the /ME signal of Z64180.

CPU execution to continue at location 0066H. use this signal to gate data onto the CPU data bus. the address bus (A7 - A10) contain the refresh address. programmable modem control signal for ASCI channel 0. RXA0, RXA1. Receive Data 0 and 1 (Input, active High). These signals are the receive data to the ASCI channels. RXS. Clocked Serial Receive Data (Input, active High). multiplexed with the /CTS1 signal for ASCI channel 1. the block transfer. /TEND0 is multiplexed with CKA1. spect to the falling edge of the transmit clock. TXS. Clocked Serial Transmit Data (Output, active High). This line is the transmitted data from the CSIO channel. /WR. Write (Output, active Low, tri-state). addressed I/O or memory location. XTAL. Crystal (Input, active High). level (reference DC characteristics). Table 3. Status Summary

0 X 1 DMA Operation

1, /DREQ0 function is always selected. to 0, RXS function is selected.

Enhanced Z180 Microprocessor Zilog 1-12 P R E L I M I N A R Y DS971800401 ARCHITECTURE The Z180® combines a high-performance CPU core with a variety of system and I/O resources useful in a broad range of applications. The CPU core consists of five func- tional blocks: clock generator, bus state controller, Inter- rupt controller, memory management unit (MMU), and the central processing unit (CPU). The integrated I/O resourc- es make up the remaining four function blocks: direct memory access (DMA) control (2 channels), asynchro- nous serial communication interface (ASCI, 2 channels) programmable reload timers (PRT, 2 channels), and a clock serial I/O (CSIO) channel. Clock Generator. Generates system clock from an exter- nal crystal or clock input. The external clock is divided by two or one and provided to both internal and external de- vices. Bus State Controller. This logic performs all of the status and bus control activity associated with both the CPU and some on-chip peripherals. This includes wait-state timing, reset cycles, DRAM refresh, and DMA bus exchanges. Interrupt Controller. This logic monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the CPU. To maintain compatibility with the Z80 ® CPU, three different interrupts modes are supported. Memory Management Unit. The MMU allows the user to “map” the memory used by the CPU (logically only 64KB) into the 1 MB addressing range supported by the Z80180/Z8S180/Z8L180. The organization of the MMU object code maintains compatibility with the Z80 CPU, while offering access to an extended memory space. This is accomplished by using an effective “common area- banked area” scheme. Central Processing Unit. The CPU is microcoded to pro- vide a core that is object-code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply. The core has been modified to al- low many of the instructions to execute in fewer clock cy- cles. DMA Controller. The DMA controller provides high speed transfers between memory and I/O devices. Transfer op- erations supported are memory-to-memory, memory to/from I/O, and I/O-to-I/O. Transfer modes supported are request, burst, and cycle steal. DMA transfers can access the full 1 MB address range with a block length up to 64 KB, and can cross over 64K boundaries. Asynchronous Serial Communication Interface (AS- CI). The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels can also support a multiprocessor communication format as well as break detection and generation. Programmable Reload Timers (PRT). This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow for waveform generation.

as a 1 and is set to 1 during reset. complete the function being programmed. disable the function (see Figure10). Figure 9. RETI Instruction Sequence with MIE=0 Table 4. RETI Control Signal States with MIE=0

1 T1-T3 1st Opcode EDH 0 1 0 1 0 1 1 0

2 T1-T3 2nd Opcode 4DH 0 1 0 1 0 1 1 0

3 T1-T3 1st Opcode EDH 0 1 0 1 0 0 1 1

4 T1-T3 2nd Opcode 4DH 0 1 0 1 0 1 1 1

5 T1-T3 SP Data 0 1 0 1 1 1 1 1

6 T1-T3 SP+1 Data 0 1 0 1 1 1 1 1

tem/application and respond appropriately. all control signals except /HALT are maintained High. instruction, except for the DMA channels. Figure 13. HALT Timing

about 1.5 clocks to restart. case, on-chip I/O (ASCI, CSI/O, PRT) stops operating. IOSTOP mode is by resetting the IOSTOP bit in ICR to 0. abled by IOSTOP) cannot generate a recovery interrupt. (CCR5) was set to 1 before IDLE mode was entered. the instruction after the SLP instruction. executing the instructions following the SLP instruction. Figure 14. SLEEP Timing

Z80180/Z8S180/Z8L180 takes about 9.5 clocks to restart. (CCR5) is 1. Figure 16 shows the timing for this sequence. the Bus Request than in normal operation. Figure 15. Z80180/Z8S180/Z8L180 IDLE Mode Exit due to External Interrupt

9.5 Cycle Delay from INTi Asserted

STANDBY Mode (With or Without QUICK RECOVERY). bilized to square-wave operation. Figure 16. Bus Granting to External Master in IDLE Mode

9.5 Cycle Delay until BUSACK Asserted

Figure 18. Bus Granting to External Master During STANDBY Mode

erwise noted. All voltages are referenced to GND (0V). Positive current flows in to the referenced pin. All AC parameters assume a load capacitance of 100 pF. are exceeded, it could affect reliability of LSI. Figure 19. AC Load Capacitance Parameters

Enhanced Z180 Microprocessor Zilog 1-24 P R E L I M I N A R Y DS971800401 DC CHARACTERISTICS Note: Vcc = 5V + 10%, Vss = 0V over specified temperature range unless otherwise noted. Symbol Item Condition Min. Typ. Max. Unit VIH1 Input “H” Voltage /RESET, EXTAL, /NMI Vcc -0.6 – V cc +0.3 V VIH2 Input “H” Voltage Except /RESET, EXTAL, /NMI 2.0 – V cc +0.3 V VIH3 Input “H” Voltage Except CKS, CKA0, CKA1 2.4 – V cc +0.3 V VIL1 Input “L ” Voltage /RESET, EXTAL, /NMI -0.3 – 0.6 V VIL2 Input “L ” Voltage Except /RESET, EXTAL, /NMI -0.3 – 0.8 V VOH Outputs “H” Voltage All outputs IOH = -200 mA 2.4 – – V IOH = -20 mAV cc -1.2 – – VOL Outputs “L ” Voltage All outputs IOL = -2.2 mA – – 0.45 V IIL Input Leakage Current All Inputs Except XTAL, EXTAL V ITL Three State Leakage Current VIN = 0.5 ~ Vcc -0.5 – – 1.0 mA ICC * Power Dissipation* (Normal Operation) F = 6 MHz – 15 40 MA F = 8 MHz – 20 50 F = 10 MHz** – 25 60 Power Dissipation* (SYSTEM STOP mode) F = 6 MHz – 3.8 12.5 F = 8 MHz – 5 15 C P Pin Capacitance V IN = 0V, f = 1 MHz Ta = 25° C – – 12 pF Note: ** VIHmin = VCC -1.0V, VILmax = 0.8V (all output terminals are at no load.) VCC = 5.0V

Zilog Enhanced Z180 Microprocessor DS971800401 P R E L I M I N A R Y 1-25 AC CHARACTERISTICS Vcc = 5V + 10%, Vss = 0V, TA - 0 to +70° C, unless otherwise noted. No. Symbol Item Z80180-6 Z80180-8 Z80180-10 1. t cyc Clock Cycle Time 162 2000 125 2000 100 2000 ns 2. t CHW Clock “H” Pulse Width 65 – 50 – 40 – ns 3. t CLW Clock “L ” Pulse Width 65 – 50 – 40 – ns 4. t cf Clock Fall Time – 15 – 15 – 10 ns 5. t cr Clock Rise Time – 15 – 15 – 10 ns 6. t AD ØRise to Address Valid Delay – 90 – 80 – 70 ns 7. t AS Address Valid to /MREQ Fall or /IORQ Fall) 3 0–2 0–1 0– n s 8. t MED1 Ø Fall to /MREQ Fall Delay –6 0–5 0–5 0 n s 9. t RDD1 Ø Fall to /RD Fall Delay /IOC = 1 –6 0–5 0–5 0 n s Ø Rise to /RD Rise Delay /IOC = 0 –6 5–6 0–5 5 10. t M1D1 Ø Rise to /M1 Fall Delay –8 0–7 0–6 0 n s 11. t AH Address Hold Time from (/MREQ, /IOREQ, /RD, /WR) 3 5–2 0–1 0– n s 12. t MED2 Ø Fall to /MREQ Rise Delay –6 0–5 0–5 0 n s 13. t RDD2 Ø Fall to /RD Rise Delay –6 0–5 0–5 0 n s 14. t M1D2 Ø Rise to /M1 Rise Delay –8 0– 7 0 * –6 0 n s 15. t DRS Data Read Set-up Time 40 – 30 – 25 – ns 16. t DRH Data Read Hold Time 0–0–0– n s 17. t STD1 Ø Fall to ST Fall Delay –9 0–7 0–6 0 n s 18. t STD2 Ø Fall to ST Rise Delay –9 0–7 0–6 0 n s 19. t WS /WAIT Set-up Time to Ø Fall 40 – 40 – 30 – ns 20. t WH /WAIT Hold Time from Ø Fall 40 – 40 – 30 – ns 21. t WDZ Ø Rise to Data Float Delay – 95 – 70 – 60 ns 22. t WRD1 Ø Rise to /WR Fall Delay –6 5–6 0–5 0 n s 23. t WDD Ø Fall to Write Data Delay Time – 90 – 80 – 60 ns 24. t WDS Write Data Set-up Time to /WR Fall 40 – 20 – 15 – ns 25. t WRD2 Ø Fall to /WR Rise Delay –8 0–6 0–5 0 n s 26. t WRP /WR Pulse Width 170 – 130 – 110 – ns 26a. /WR Pulse Width (I/O Write Cycle) 332 – 255 – 210 – ns 27. t WDH Write Data Hold Time from (/WR Rise) 4 0–1 5–1 0– 28. t IOD1 Ø Fall to /IORQ Fall Delay /IOC = 1 –6 0–5 0–5 0 n s Ø Rise to /IORQ Fall Delay /IOC = 1 –6 5–6 0–5 5 29. t IOD2 Ø Fall to /IORQ Rise Delay –6 0–5 0–5 0 n s 30. t IOD3 /M1 Fall to /IORQ Fall Delay 340 – 250 – 200 – ns 31. t INTS /INT Set-up Time to Ø Fall 40 – 40 – 30 – ns 32. t INTS /INT Hold Time from Ø Fall 40 – 40 – 30 – ns 33. t NMIW /NMI Pulse Width 120 – 100 – 80 – ns 34. t BRS /BUSREQ Set-up Time to Ø Fall 40 – 40 – 30 – ns 35. t BRH /BUSREQ Hold Time from Ø Fall 40 – 40 30 ns 36. t BAD1 Ø Rise to /BUSACK Fall Delay –9 5–7 0–6 0 n s 37. t BAD2 Ø Fall to /BUSACK Rise Delay –9 0–7 0–6 0 n s 38. t BZD Ø Rise to Bus Floating Delay Time – 125 – 90 – 80 ns 39. t MEWH /MREQ Pulse Width (HIGH) 110 – 90 – 70 – ns

Enhanced Z180 Microprocessor Zilog 1-26 P R E L I M I N A R Y DS971800401 40. t MEWL /MREQ Pulse Width (LOW) 125 – 100 – 80 – ns 41. t RFD1 Ø Rise to /RFSH Fall Delay – 90 – 80 – 60 ns 42. t RFD2 Ø Rise to /RFSH Rise Delay – 90 – 80 – 60 ns 43. t HAD1 Ø Rise to /HALT Fall Delay – 90 – 80 – 50 ns 44. t HAD2 Ø Rise to /HALT Rise Delay – 90 – 80 – 50 ns 45. t DRQS /DREQi Set-up Time to Ø Rise 40 – 40 – 30 – ns 46. t DRQH /DREQi Hold Time from Ø Rise 40 – 40 – 30 – ns 47. t TED1 Ø Fall to /TENDi Fall Delay – 70 – 60 – 50 ns 48. t TED2 Ø Fall to /TENDI Rise Delay – 70 – 60 – 50 ns 49. t ED1 Ø Rise to E Rise Delay – 95 – 70 – 60 ns 50. t ED2 Ø Fall or Rise to E Fall Delay – 95 – 70 – 60 ns 51. P WEH E Pulse Width (HIGH) 75 – 65 – 55 – ns 52. P WEL E Pulse Width (LOW) 180 – 130 – 110 – ns 53. t Er Enable Rise Time – 20 – 20 – 20 ns 54. t Ef Enable Fall Time – 20 – 20 – 20 ns 55. t TOD Ø Fall to Timer Output Delay – 300 – 200 – 150 ns 56. t STDI CSI/O Transmit Data Delay Time (Internal Clock Operation) – 200 – 200 – 150 ns 57. t STDE CSI/O Transmit Data Delay Time (External Clock Operation) – 7.5tcyc +300 – 7.5tcyc +200 – 7.5tcyc +150 ns 58. t SRSI CSI/O Receive Data Set-up Time (Internal Clock Operation) 1–1–1– tcyc 59. t SRHI CSI/O Receive Data Hold Time (Internal Clock Operation) 1–1–1– tcyc 60. t SRSE CSI/O Receive Data Set-up Time (External Clock Operation) 1–1–1– tcyc 61. t SRHE CSI/O Receive Data Hold Time (External Clock Operation) 1–1–1– tcyc 62. t RES /RESET Set-up Time to Ø Fall 120 – 100 – 80 – ns 63. t REH /RESET Hold Time from Ø Fall 80 – 70 – 50 – ns 64. t OSC Oscillator Stabilization Time – 20 – 20 – TBD ns 65. t EXr External Clock Rise Time (EXTAL) – 25 – 25 – 25 ns 66. t EXf External Clock Fall Time (EXTAL) – 25 – 25 – 25 ns 67. t Rr /RESET Rise Time – 50 – 50 – 50 ns 68. t Rf /RESET Fall Time – 50 – 50 – 50 ns 69. t Ir Input Rise Time (except EXTAL, /RESET) – 100 – 100 – 100 ns 70. t If Input Fall Time (except EXTAL, /RESET) – 100 – 100 – 100 ns No. Symbol Item Z80180-6 Z80180-8 Z80180-10

Zilog Enhanced Z180 Microprocessor DS971800401 P R E L I M I N A R Y 1-27 AC CHARACTERISTICS (VCC = 5V –10% or VCC = 3.3V –10% over specified temperature range, unless otherwise noted, 33 MHZ characteristics apply only to 5V operation.) No. Symbol Item Z80180-20 Z80180-33 UnitMin. Max. Min. Max. 1. t cyc Clock Cycle Time 50 2000 33 2000 ns 2. t CHW Clock “H” Pulse Width 15 – 10 – ns 3. t CLW Clock “L ” Pulse Width 15 – 10 – ns 4. t cf Clock Fall Time – 10 – 5 ns 5. t cr Clock Rise Time – 10 – 5 ns 6. t AD ØRise to Address Valid Delay – 15 – 15 ns 7. t AS Address Valid to /MREQ Fall or /IORQ Fall) 20 – 5 – ns 8. t MED1 Ø Fall to /MREQ Fall Delay –1 5–1 5 n s 9. t RDD1 Ø Fall to /RD Fall Delay /IOC = 1 –1 5–1 5 n s Ø Rise to /RD Rise Delay /IOC = 0 –1 5–1 5 10. t M1D1 Ø Rise to /M1 Fall Delay –1 5–1 5 n s 11. t AH Address Hold Time from (/MREQ, /IOREQ, /RD, /WR) –2 05 – n s 12. t MED2 Ø Fall to /MREQ Rise Delay –1 5–1 5 n s 13. t RDD2 Ø Fall to /RD Rise Delay –1 5–1 5 n s 14. t M1D2 Ø Rise to /M1 Rise Delay – 15 – 15* ns 15. t DRS Data Read Set-up Time 15 – 15 – ns 16. t DRH Data Read Hold Time 0–0– n s 17. t STD1 Ø Fall to ST Fall Delay –1 5–1 5 n s 18. t STD2 Ø Fall to ST Rise Delay –1 5–1 5 n s 19. t WS /WAIT Set-up Time to Ø Fall 15 – 15 – ns 20. t WH /WAIT Hold Time from Ø Fall 5–5– n s 21. t WDZ Ø Rise to Data Float Delay – 10 – 10 ns 22. t WRD1 Ø Rise to /WR Fall Delay –1 5–1 5 n s 23. t WDD Ø Fall to Write Data Delay Time – 20 – 20 ns 24. t WDS Write Data Set-up Time to /WR Fall 10 – 0 – ns 25. t WRD2 Ø Fall to /WR Rise Delay –1 5–1 5 n s 26. t WRP /WR Pulse Width 70 – 40 – ns 26a. /WR Pulse Width (I/O Write Cycle) 120 – 70 – ns 27. t WDH Write Data Hold Time from (/WR Rise) 5–5– 28. t IOD1 Ø Fall to /IORQ Fall Delay /IOC = 1 –1 5–1 5 n s Ø Rise to /IORQ Fall Delay /IOC = 1 –1 5–1 5 29. t IOD2 Ø Fall to /IORQ Rise Delay –1 5–1 5 n s 30. t IOD3 /M1 Fall to /IORQ Fall Delay 120 – 70 – ns 31. t INTS /INT Set-up Time to Ø Fall 15 – 15 – ns 32. t INTS /INT Hold Time from Ø Fall 10 – 10 – ns 33. t NMIW /NMI Pulse Width 35 – 25 – ns 34. t BRS /BUSREQ Set-up Time to Ø Fall 10 – 10 – ns 35. t BRH /BUSREQ Hold Time from Ø Fall 10 – 10 ns 36. t BAD1 Ø Rise to /BUSACK Fall Delay –1 5–1 5 n s 37. t BAD2 Ø Fall to /BUSACK Rise Delay –1 5–1 5 n s

Enhanced Z180 Microprocessor Zilog 1-28 P R E L I M I N A R Y DS971800401 38. t BZD Ø Rise to Bus Floating Delay Time – 10 – 25 ns 39. t MEWH /MREQ Pulse Width (HIGH) 45 – 25 – ns 40. t MEWL /MREQ Pulse Width (LOW) 45 – 25 – ns 41. t RFD1 Ø Rise to /RFSH Fall Delay – 15 – 15 ns 42. t RFD2 Ø Rise to /RFSH Rise Delay – 15 – 15 ns 43. t HAD1 Ø Rise to /HALT Fall Delay – 15 – 15 ns 44. t HAD2 Ø Rise to /HALT Rise Delay – 15 – 15 ns 45. t DRQS /DREQi Set-up Time to Ø Rise 20 – 20 – ns 46. t DRQH /DREQi Hold Time from Ø Rise 15 – 15 – ns 47. t TED1 Ø Fall to /TENDi Fall Delay – 15 – 15 ns 48. t TED2 Ø Fall to /TENDI Rise Delay – 15 – 15 ns 49. t ED1 Ø Rise to E Rise Delay – 15 – 15 ns 50. t ED2 Ø Fall or Rise to E Fall Delay – 15 – 15 ns 51. P WEH E Pulse Width (HIGH) 45 – 20 – ns 52. P WEL E Pulse Width (LOW) 70 – 20 – ns 53. t Er Enable Rise Time – 10 – 10 ns 54. t Ef Enable Fall Time – 10 – 10 ns 55. t TOD Ø Fall to Timer Output Delay – 50 – 50 ns 56. t STDI CSI/O Transmit Data Delay Time (Internal Clock Operation) –2–2 n s 57. t STDE CSI/O Transmit Data Delay Time (External Clock Operation) – 7.5tcyc +75 – 7.5tcyc +60 ns 58. t SRSI CSI/O Receive Data Set-up Time (Internal Clock Operation) 1–1– tcyc 59. t SRHI CSI/O Receive Data Hold Time (Internal Clock Operation) 1–1– tcyc 60. t SRSE CSI/O Receive Data Set-up Time (External Clock Operation) 1–1– tcyc 61. t SRHE CSI/O Receive Data Hold Time (External Clock Operation) 1–1– tcyc 62. t RES /RESET Set-up Time to Ø Fall 25 – 25 – ns 63. t REH /RESET Hold Time from Ø Fall 15 – 15 – ns 64. t OSC Oscillator Stabilization Time – 20 – 20 ns 65. t EXr External Clock Rise Time (EXTAL) – 10 – 5 ns 66. t EXf External Clock Fall Time (EXTAL) – 10 – 5 ns 67. t Rr /RESET Rise Time – 50 – 50 ns 68. t Rf /RESET Fall Time – 50 – 50 ns 69. t Ir Input Rise Time (except EXTAL, /RESET) – 50 – 50 ns 70. t If Input Fall Time (except EXTAL, /RESET) – 50 – 50 ns No. Symbol Item Z80180-20 Z80180-33 UnitMin. Max. Min. Max.

*1. Output buffer is off at this point. there are no automatic wait states (TW ), and /MREQ is active instead of /IORQ. Figure 20. CPU Timing

1. During /INT0 acknowledge cycle.
2. Output buffer is off at this point.

Figure 21. CPU Timing

and output drive/low noise options (Figure 31). teristics must be satisfied. mode, depending on the IOSTOP bit (ICR5). of the part, including PHI out. oscillator to stabilize when it's restarted. scribes the subject more fully. will be reduced to 33 percent of its drive capability. Figure 31. CPU Control Register (CCR) Address 1FH

Enhanced Z180 Microprocessor Zilog 1-36 P R E L I M I N A R Y DS971800401 Bit 2 LNIO. This bit controls the drive capability of certain external I/O pins of the Z8S180/Z8L180. When this bit is set to 1, the output drive capability of the following pins is reduced to 33percent of the original drive capability: – /RTSO/TxS – CKA1 – CKAO – TXAO – TXAI – TOUT Bit 1 LNCPUCTL. This bit controls the drive capability of the CPU Control pins. When this bit is set to 1, the output drive capability of the following pins is reduced to 33percent the original drive capability: – /BUSACK – /RD – /WR – /M1 – /MREQ – /IORQ – /RFSH – /HALT Bit 0 LNAD/DATA. This bit controls the drive capability of the Address/Data bus output drivers. If this bit is set to 1, the output drive capability of the Address and Data bus output is reduced to 33percent of its original drive capability.

Figure 32. ASCI Block Diagram

Enhanced Z180 Microprocessor Zilog 1-38 P R E L I M I N A R Y DS971800401 The following paragraphs explain the various functions of the ASCI registers. ASCI Transmit Register 0. When the ASCI Transmit Register receives data from the ASCI Transmit Data Reg- ister (TDR), the data is shifted out to the TxA pin. When transmission is completed, the next byte (if available) is automatically loaded from TDR into TSR and the next transmission starts. If no data is available for transmission, TSR IDLEs by outputting a continuous High level. This reg- ister is not program accessible ASCI Transmit Data Register 0,1 (TDR0, 1: I/O address = 06H, 07H). Data written to the ASCI Transmit Data Reg- ister is transferred to the TSR as soon as TSR is empty. Data can be written while TSR is shifting out the previous byte of data. Thus, the ASCI transmitter is double buffered. Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation will not be af- fected by this read operation ASCI Receive Shift Register 0,1 (RSR0,1). This register receives data shifted in on the RxA pin. When full, data is automatically transferred to the ASCI Receive Data Regis- ter (RDR) if it is empty. If RSR is not empty when the next incoming data byte is shifted in, an overrun error occurs. This register is not program accessible. ASCI Receive Data FIFO 0,1 (RDR0, 1:I/O Address = 08H, 09H). The ASCI Receive Data Register is a read-only reg- ister. When a complete incoming data byte is assembled in RSR, it is automatically transferred to the 4 character Receive Data First-In First-Out (FIFO) memory. The oldest character in the FIFO (if any) can be read from the Receive Data Register (RDR). The next incoming data byte can be shifted into RSR while the FIFO is full. Thus, the ASCI re- ceiver is well buffered. ASCI STATUS FIFO This 4 entry FIFO contains Parity Error, Framing Error, Rx Overrun, and Break status bits associated with each char- acter in the receive data FIFO. The status of the oldest character (if any) can be read from the ASCI status regis- ters as described below

1. If multiprocessor mode is not selected (MP bit in CNTLB

error flags. MPE is cleared to 0 during RESET. cleared to 0 in IOSTOP mode during RESET. having no side effects on other ASCI registers or flags. Figure 33. ASCI Channel Control Register A

MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2-0). These bits program the ASCI data format as follows. MOD2, MOD1, and MOD0 are shown in Table 5-6. MPBT is used to specify the MPB data bit for transmission. tiplexed with RXS pin (Clocked Serial Receive Data). CTS1E bit = 1 and the /CTS input pin function is selected. The read data of /CTS/PS is not affected by RESET. divide by 30. The bit resets to 0. is cleared to 0 during RESET. used. DR is cleared to 0 during RESET. Table 5. Data Formats Figure 34. ASCI Channel Control Register B

pending on the DR bit and the X1 bit in the ASEXT register. PHI clock as shown in Table 9. and enabling or disabling of ASCI interrupts. abled and is negated (High). the Rx FIFO is full so there is no room for the character. abled and is negated (High). software then writes a 1 to EFR to clear it. Table 6. Divide Ratio Figure 35. ASCI Status Registers

and TMDRn will not decrement until TDEn is set to 1. added to the ASCIs in the Z80180/Z8S180/Z8L180 family. Note: All bits in this register reset to zero. the receiver will interrupt on a rising edge of DCD0. ter will send Breaks under the control of bit 0. pin is auto-enabled and is negated (high). mitter holds the TXA pin low to send a Bread condition. Figure 47. ASCI Extension Control Registers, Channel 0 and 1

Figure 53. ASCI Time Constant Registers

mode. Upon powerup, this feature is disabled. enable the low noise option for the EXTAL and XTAL pins. output drive capability to 30% of its original drive capability. select for normal operation of the EXTAL and XTAL pins. The default for this bit is 0. operation is needed, use the clock multiplier feature. Figure 54. Clock Multiplier Register Table 9. Low Noise Option

transfer status, in other words, completed or in progress. fer terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC. 1), a DMA interrupt request is made to the CPU. DE1 to 0 disables channel 1 DMA, but DMA is restartable. fer terminates (BCR0 = 0), DE0 is reset to 0 by the DMAC. 1), a DMA interrupt request is made to the CPU. Main Enable) to 1. DE0 is cleared to 0 during RESET. during the same access. DWE1 always reads as 1. during the same access. DWE0 always reads as 1. nel 1) and the DME bit is set to 1. Figure 72. DMA Status Register (DSTAT: I/O Address = 30H)

and DM0 are cleared to 0 during RESET. decremented for each byte transferred. Figure 73. DMA Mode Register (DMODE: I/O Address = 31H) Table 10. Channel 0 Destination Table 11. Channel 0 Source

are not implemented, 12 combinations are available. lectable: burst (MMOD = 1) and cycle steal (MMOD = 0). byte transfer cycle until the transfer is completed. is ignored. MMOD is cleared to 0 during RESET. Table 12. Transfer Mode Combinations

0000 Memory fi Memory SAR0+1, DAR0+1

0001 Memory fi Memory SAR0–1, DAR0+1

0010 Memory*fi Memory SAR0 fixed, DAR0+1

0011 I / O fi Memory SAR0 fixed, DAR0+1

0100 Memory fi Memory SAR0+1, DAR0–1

0101 Memory fi Memory SAR0–1, DAR0–1

0110 Memory*fi Memory SAR0 fixed, DAR0–1

0111 I / O fi Memory SAR0 fixed, DAR0–1

1000 Memory fi Memory* SAR0+1, DAR0 fixed

1001 Memory fi Memory* SAR0–1, DAR0 fixed

1010 Reserved

1011 Reserved

1100 Memory fi I/O SAR0+1, DAR0 fixed

1101 Memory I/O SAR0–1, DAR0 fixed

1110 Reserved

Note: * Includes memory mapped I/O.

Request signal for each channel as level or edge sense. which is limited to memory to/from I/O transfers. access cycles. IWI1 and IWI0 are set to 1 during RESET. See the section on Wait-State Generation for details. and DMS0 are cleared to 0 during RESET. of the two machine cycles involved in transferring a byte. Figure 74. DMA/WAIT Control Register (DCNTL: I/O Address = 32H)

1 Edge Sense

0 Level Sense

modifier for channel 1 memory to/from I/O transfer modes. DIM1 and DIM0 are cleared to 0 during RESET. bits are cleared to 0 during Reset (Figure 75). INT/TRAP Control Register (ITC, I/O Address 34H). under program control. TRAP is reset to 0 during RESET. first Opcode address is stacked PC-2. UFO is Read-Only. Table 13. Channel 1 Transfer Mode Figure 75. Interrupt Vector Low Register (IL: I/O Address = 33H)

for INT0 when Mode 0 is used.

1. The TRAP bit in the Interrupt TRAP/Control (ITC)
2. The current PC (Program Counter) value, reflecting
3. The Z80180/Z8S180/Z8L180 vectors to logical

address 00000H was caused by RESET or TRAP. Figure 76. TRAP Timing-2

1. Refresh Cycle insertion is stopped when the CPU is in
2. Refresh cycles are suppressed when the bus is
3. Refresh cycles are suppressed during SLEEP mode.

with the exit from SLEEP mode.

1. The refresh address is incremented by one for each

of CBR are reset to 0 during RESET. Table 14. DRAM Refresh Intervals Figure 79. MMU Common Base Register (BBR: I/O Address = 38H)

ways 0. IOA7 and IOA6 are cleared to 0 during Reset. Figure 85. I/O Address Relocation

Enhanced Z180 Microprocessor Zilog 1-66 P R E L I M I N A R Y DS971800401

PACKAGE INFORMATION

Figure 86. 80-Pin QFP Package Diagram

Enhanced Z180 Microprocessor Zilog 1-68 P R E L I M I N A R Y DS971800401

ORDERING INFORMATION

Z80180 6, 8, 10MHz Z8S180 20, 33MHz Z8L180 20MHz Please check availability before placing order. CODES Package F = Plastic Quad Flatpack P = Plastic Dual In Line V = Plastic Leaded Chip Carrier Temperature S = 0°C to +70°C E = -40C to +85C Speeds 06 = 6 MHz 08 = 8 MHz 10 = 10 MHz 20 = 20 MHz 33 = 33 MHz Environmental C = Plastic Standard Example: Z 80180 08 P S C is a Z80180, 08 MHz, Plastic DIP , 0° to +70°C, Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix

Zilog Enhanced Z180 Microprocessor DS971800401 P R E L I M I N A R Y 1-69 © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com

Enhanced Z180 Microprocessor Zilog 1-70 P R E L I M I N A R Y DS971800401