Z8018010PSC

Z8018010VSG ZILOG | Alldatasheet

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Revision History

Each instance in the following table reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table below. Date Revision Level Description Page No November 2006

04 Updated DC Characteristics table and minor edits done

throughout the document. All

v Table of Contents

Features

The key features of Z80180™ microprocessor unit (MPU) include:

• Code compatible with ZiLOG Z80® CPU
• Extended instructions
• Two DMA channels
• Low power-down modes
• On-chip interrupt controllers
• Three on-chip wait-state generators
• On-chip oscillator/generator
• Expanded MMU addressing (up to 1 MB)
• Clocked serial I/O port
• Two 16-Bit counter/timers
• Two UARTs
• Clock Speeds: 6 MHz, 8 MHz, and 10 MHz
• 6 MHz version supports 6.144 MHz CPU clock operation
• Operating range: 5 V
• Operating temperature range: 0 ºC to +70 ºC
• Three packaging styles – 68-Pin PLCC – 64-Pin DIP – 80-Pin QFP General Description The Z80180™ is an 8-bit MPU which provides the benefits of reduced system costs and also provides full backward compatibility with existing ZiLOG Z80 devices. Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer

The Z80180™ is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages. active Low); and B/W, in which BYTE is active Low. Power connections follow conventional descriptions as listed in Table 1. Table 1. Power Connection Conventions Figure 1. Z80180 Functional Block Diagram

Figure 2. Z80180 64-Pin Dip Configuration

Figure 3. Z80180 68-Pin PLCC Configuration NMI

Figure 4. Z80180 80-Pin QFP Configuration Table 2. Pin Status During RESET BUSACK and SLEEP

Table 2. Pin Status During RESET BUSACK and SLEEP(continued) (continued)

A0–A19. Address Bus (output, active High, 3-state)— A0–A19 form a 20-bit address bus. address line A19 is not available in DIP versions of the Z80180.

BUSACK— Bus Acknowledge (output, active Low). BUSACK indicates the requesting device, the MPU address and data bus, and some control signals that enter their high-imped- ance state. BUSREQ— Bus Request (input, active Low). This input is used by external devices (such as DMA controllers) to request access to the system bus. This request demands a higher priority than NMI and is always recognized at the end of the current machine cycle. This signal stops the CPU from executing further instruc- tions and places address and data buses, and other control signals, into the high-impedance state. CKA0, CKA1— Asynchronous Clock 0 and 1 (bidirectional, active High). When in output mode, these pins are the transmit and receive clock outputs from the ASCI baud rate generators. When in input mode, these pins serve as the external clock inputs for the ASCI baud rate generators. CKA0 is multiplexed with DREQ0, and CKA1 is multiplexed with TEND0. CKS— Serial Clock (bidirectional, active High). This line is the clock for the CSIO channel. CLOCK— System Clock (output, active High). The output is used as a reference clock for the MPU and the external system. The frequency of this output is equal to one-half that of the crystal or input clock frequency. CTS0–CTS1— Clear to send 0 and 1 (inputs, active Low). These lines are modem control signals for the ASCI channels. CTS1 is multiplexed with RXS. D0–D7— Data Bus (bidirectional, active High, 3-state). D0–D7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high-impedance state during reset and external bus acknowledge cycles. DCD0— Data Carrier Detect 0 (input, active Low). A programmable modem control signal for ASCI channel 0. DREQ0, DREQ1. DMA Request 0 and 1 (input, active Low). DREQ is used to request a DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these inputs to determine when an external device is ready for a READ or WRITE operation. These inputs can be programmed to be either level or edge sensed. DREQ0 is multiplexed with CKA0. E— Enable Clock (output, active High). Synchronous machine cycle clock output during bus transactions. EXTAL— External Clock Crystal (input, active High). Crystal oscillator connections. An external clock can be input to the Z80180 on this pin when a crystal is not used. This input is Schmitt-triggered. HALT— HALT/SLEEP (output, active Low). This output is asserted after the CPU executes either the HALT or SLEEP instruction, and is waiting for either nonmaskable or maskable

interrupt before operation resumes. It is also used with the M1 and ST signals to decode status of the CPU machine cycle. INT0— Maskable Interrupt Request 0 (input, active Low). This signal is generated by exter- nal I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the NMI and BUSREQ signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the M1 and IORQ signals become active. INT1, INT2— Maskable Interrupt Request 1 and 2 (inputs, active Low). This signal is gener- ated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the NMI, BUSREQ, and INT0 signals are inactive. The CPU acknowledges these requests with an interrupt acknowledge cycle. Unlike the acknowledg- ment for INT0, during this cycle neither the M1 or IORQ signals become active. IORQ— I/O Request (output, active Low, 3-state). IORQ indicates that the address bus con- tains a valid I/O address for an I/O READ or I/O WRITE operation. IORQ is also generated, along with M1, during the acknowledgment of the INT0 input signal to indicate that an inter- rupt response vector can be placed onto the data bus. This signal is analogous to the IOE sig- nal of the Z64180. M1— Machine Cycle 1 (output, active Low). Together with MREQ, M1 indicates that the cur- rent cycle is the opcode fetch cycle of and instruction execution. Together with IORQ, M1 indicates that the current cycle is for an interrupt acknowledge. It is also used with the HALT and ST signal to decode status of the CPU machine cycle. This signal is analogous to the LIR signal of the Z64180. MREQ— Memory Request (output, active Low, 3-state). MREQ indicates that the address bus holds a valid address for a memory READ or memory WRITE operation. This signal is analogous to the ME signal of Z64180. NMI— Nonmaskable Interrupt (input, negative edge triggered). NMI demands a higher prior- ity than INT and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. This signal forces CPU execution to continue at location 0066h. RD— Opcode Reinitialized (output, active Low, 3-state). RD indicated that the CPU wants to read data from memory or an I/O device. The addressed I/O or memory device must use this signal to gate data onto the CPU data bus. RFSH— Refresh (output, active Low). Together with MREQ, RFSH indicates that the current CPU machine cycle and the contents of the address bus must be used for refresh of dynamic memories. The low order 8 bits of the address bus (A7–A10) contain the refresh address. This signal is analogous to the REF signal of the Z64180. RTS0— Request to Send 0 (output, active Low). A programmable modem control signal for ASCI channel 0. RXA0, RXA1— Receive Data 0 and 1 (input, active High). These signals are the receive data to the ASCI channels.

CSIO channel. RXS is multiplexed with the CTS1 signal for ASCI channel 1. decode the status of the CPU machine cycle. TEST— Test (output, not in DIP version). This pin is for test and must be left open. line is multiplexed with A18 of the address bus. inserted until the WAIT input is sampled high, at which time execution continues. data to be stored at the addressed I/O or memory location. Table 3. Status Summary

depending on the circumstance. Table 4. Multiplexed Pin Descriptions selected. If TOC1 and TOC0 are cleared to 0, A18 function is selected. CKA1D bit is set to 0, CKA1 function is selected. CTS1E bit is set to 0, RXS function is selected.

PS014004-1106 Architecture Architecture The Z180® combines a high-performance CPU core with a variety of system and I/O resources useful in a broad range of applications. The CPU core consists of five functional blocks: clock generator, bus state controller, interrupt controller, memory management unit (MMU), and the central processing unit (CPU). The integrated I/O resources make up the remaining four function blocks: direct memory access (DMA) control (2 channels), asynchronous serial communication interface (ASCI) 2 channels, programma- ble reload timers (PRT) 2 channels, and a clock serial I/O (CSIO) channel. Clock Generator— Generates system clock from an external crystal or clock input. The external clock is divided by two or one and provided to both internal and external devices. Bus State Controller— This logic performs all of the status and bus control activity associated with both the CPU and some on-chip peripherals. Included are wait-state timing, reset cycles, DRAM refresh, and DMA bus exchanges. Interrupt Controller— This logic monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the CPU. To maintain compatibility with the Z80® CPU, three different interrupts modes are supported. Memory Management Unit— The MMU allows you to map the memory used by the CPU (logically only 64 KB) into the 1-MB addressing range supported by the Z80180. The orga- nization of the MMU object code allows maintenance compatibility with the Z80 CPU, while offering access to an extended memory space. This organization is achieved by using an effective common area-banked area scheme. Central Processing Unit— The CPU is microcoded to provide a core that is object-code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, includ- ing 8-bit multiply. The core is modified to allow many of the instructions to execute in fewer clock cycles. DMA Controller— The DMA controller provides high speed transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O, and I/O-to-I/O. Transfer modes supported are request, burst, and cycle steal. DMA transfers can access the full 1 MB address range with a block length up to 64 KB, and can cross over 64K boundaries. Asynchronous Serial Communication Interface (ASC)— The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels also support a multiprocessor communication format as well as break detection and generation. Programmable Reload Timers (PRT)— This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow for waveform generation.

are not fully Z80-timing compatible but are compatible with the on-chip CTCs. refetches the instruction using fully Z80-compatible cycles that include driving M1 Low. illustrates the RETI sequence when M1E = 0. Figure 9. RETI Instruction Sequence with MIE = 0 assertion of the M1 signal. It is always read back as a 1 and is set to 1 during RESET. the function being programmed. not required to preprogram a 1 to disable the function (see Figure 10).

• Normal Operation
• HALT mode
• IOSTOP mode
• SLEEP mode
• SYSTEM STOP mode Normal Operation— The Z80180 processor is fetching and running a program. All enabled functions and portions of the device are active, and the HALT pin is High. HALT Mode— This mode is entered by the HALT instruction. Thereafter, the Z80180 processor continually fetches the following opcode but does not execute it, and drives the HALT, ST and M1 pins all Low. The oscillator and PHI pin remain active, interrupts and bus granting to external masters, and DRAM refresh can occur and all on-chip I/O devices continue to operate including the DMA channels. The Z80180 leaves HALT mode in response to a Low on RESET, on to an interrupt from an enabled on-chip source, an external request on NMI, or an enabled external request on INT0, INT1, or INT2. In case of an interrupt, the return address is the instruction following the HALT instruction; at that point the program can either branch back to the HALT instruction to wait for another interrupt, or can examine the new state of the system/application and respond appropriately.

Figure 13. HALT Timing

tions continue as before the SLEEP instruction, except for the DMA channels. tion), the Z80180 leaves SLEEP mode by simply executing the following instruction(s). timing for exiting SLEEP mode due to an interrupt request. The Z80180 takes about 1.5 clocks to restart. Figure 14. SLEEP Timing

(disabled by IOSTOP) cannot generate a recovery interrupt. GND (0 V). Positive current flows in to the referenced pin. Package Information section (see Figure 15). Figure 15. AC Load Capacitance Parameters Permanent LSI damage occurs if maximum ratings listed in Table 5 are exceeded. Table 5. Absolute Maximum Ratings

conditions are exceeded, it affects reliability of LSI. Table 6 lists the DC characteristics of Z80180™ MPU. Table 6. DC Characteristics Table 5. Absolute Maximum Ratings(continued)

VSS = 0 V , TA – 0 °C to +70 °C, unless otherwise noted.

1 MHz TA = 25°

Note: *V IHmin = VCC –1.0 V, VILmax = 0.8 V (all output terminals are at no load); VCC = 5.0 V. Table 7. Z80180-6 AC Characteristics Table 6. DC Characteristics (continued)

51 P WEH E Pulse Width (High) 75 – ns

52 P WEL E Pulse Width (Low) 180 – ns

Table 7. Z80180-6 AC Characteristics (continued)

Table 8. Z80180-8 AC Characteristics

Table 8. Z80180-8 AC Characteristics (continued)

51 P WEH E Pulse Width (High) 65 – ns

52 P WEL E Pulse Width (Low) 130 – ns

Table 9. Z80180-10 AC Characteristics

Table 9. Z80180-10 AC Characteristics (continued)

51 P WEH E Pulse Width (High) 55 – ns

52 P WEL E Pulse Width (Low) 110 – ns

Z80180 Timing signals are displayed in Figure 16 through Figure 27.

Figure 16. CPU Timing (Opcode Fetch, I/O WRITE, and I/O READ Cycles)

Figure 17. CPU Timing (INT0 Acknowledge Cycle, Refresh Cycle)

Figure 18. CPU Timing (IOC = 0) (I/O READ Cycle, I/O WRITE Cycle)

Figure 19. DMA Control Signals

1. t DRQS and tDHQH are specified for the rising edge of clock followed by T3.
2. t DRQS and tDHQH are specified for the rising edge of clock.

Figure 27. ASCI Block Diagram register is not program accessible. the previous byte of data. The ASCI transmitter is double buffered.

overrun error occurs. This register is not program accessible. Register (RDR). The next incoming data byte can be shifted into RSR while the FIFO is full. The ASCI receiver is well buffered. Figure 28. ASCI Register Channel 0

error flags. MPE is cleared to 0 during RESET. interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode during RESET. interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode during RESET. side effects on other ASCI registers or flags. Bit 4 in CNTLA1 is not used. data format as listed in Table 10. Table 10. ASCI Data Formats Mode 2, 1, 0

Figure 33. ASCI Channel Control Register B undefined during and after RESET. bits) bits in CNTLA. The format is as follows. MP=1) format does not feature any provision for parity. bit is cleared to 0 during RESET. Table 11. Data Formats

is inhibited (forced to 0). Bit 5 of CNTLB1 reads back as 0. cates a divide-by-10 prescale function, while a 1 indicates divide-by-30. The bit resets to 0. selected. If PEO is set to 1, odd parity is selected. PEO is cleared to 0 during RESET. 16 is used, while if DR is set to 1, divide-by-64 is used. DR is cleared to 0 during RESET. DR bit and the X1 bit in the ASEXT register. two divider for the PHI clock as indicated in Table 12. the Interrupt Edge register is 1. Table 12. Divide Ratio

control signal status, and enabling or disabling of ASCI interrupts. Figure 34. ASCI Status Registers byte is loaded into an empty RxFIFO. generated the error) is still loaded into the FIFO. mode, during RESET and for ASCI0 if the DCD0 input is auto-enabled and is negated (High). assembling a character, but the RxFIFO is full so that there is no room for the character. pin is auto enabled and is negated (High). FIFO so that OVRN is set, and software then writes a 1 to EFR to clear it. mode, and for ASCI0 if the DCD0 pin is auto-enabled and is negated (High).

pin is auto-enabled and is negated (High). DCD0 goes High. RIE is cleared to 0 by RESET. auto-enabling, and the pin is negated (High), the bit 2 of STAT1 is not used. pin is auto-enabled in the ASEXT0 registers and the pin is High, TDRE is reset to 0. CSIO, enable and disable interrupt generation, and select the data clock speed and source. Figure 35. CSIO Control Register

EIE: End Interrupt Enable (bit 6)— EIE is set to 1 to generate a CPU interrupt request. The interrupt request is inhibited if EIE is reset to 0. EIE is cleared to 0 during RESET. RE: Receive Enable (bit 5)— A CSIO receive operation is started by setting RE to 1. same time. RE is cleared to 0 during RESET and ISTOP mode. same time. TE is cleared to 0 during RESET and IOSTOP mode. the CSIO Baud Rate selection. After RESET, the CKS pin is configured as an external clock input (SS2, SS1, SS0 = 1). when transmit or receive operations are enabled. Table 13. CSIO Baud Rate Selection

is read and the higher or lower byte of TMDR1 is read. During RESET, TIF1 is cleared to 0. is read and the higher or lower byte of TMDR0 is read. During RESET, TIF0 is cleared to 0. RESET, TIE0 is cleared to 0. during RESET and TMDRn do not decrement until TDEn is set to 1. All bits in this register reset to 0. Table 14. Timer Output Control

Figure 42. ASCI Extension Control Registers, Channel 0 and 1 of the IER is 0 and this bit is 1, the state of the DCD-pin has no effect on receiver operation. and the receiver interrupts on a rising edge of DCD0. this bit, software can read the state of the CTS0 pin the CNTLB0 register. mode, receive data on the RXA pin is not required to be synchronized to a clock. them in bit 1, and the transmitter sends breaks under the control of bit 0.

All DMA Count Register channels are undefined during RESET. Figure 54. DMA Byte Count Register 0L Table 15. DMA Transfer Requests

PS014004-1106 Architecture When DE0 = 0 and the DMA interrupt is enabled (DIE0 = 1), a DMA interrupt request is made to the CPU. To perform a software WRITE to DE0, DWE0 must be written with 0 during the same register WRITE access. Writing DE0 to 0 disables channel 0 DMA. Writing DE0 to 1 enables channel 0 DMA and automatically sets DME (DMA Main Enable) to 1. DE0 is cleared to 0 during RESET. DWE1: DE1 Bit WRITE Enable (bit 5)— When performing any software WRITE to DE1, DWE1 must be written with 0 during the same access. DWE1 always reads as 1. DWE0: DE0 Bit WRITE Enable (bit 4)— When performing any software WRITE to DE0, DWE0 must be written with 0 during the same access. DWE0 always reads as 1. DIE1: DMA Interrupt Enable Channel 1 (bit 3)— When DIE0 is set to 1, the termination channel 1 DMA transfer (indicated when DE1 = 0) causes a CPU interrupt request to be generated. When DIE0 = 0, the channel 0 DMA termination interrupt is disabled. DIE0 is cleared to 0 during RESET. DIE0: DMA Interrupt Enable Channel 0 (bit 2)— When DIE0 is set to 1, the termination channel 0 of DMA transfer (indicated when DE0 = 0) causes a CPU interrupt request to be generated. When DIE0 = 0, the channel 0 DMA termination interrupt is dis- abled. DIE0 is cleared to 0 during RESET. DME: DMA Main Enable (bit 0)— A DMA operation is only enabled when its DE bit (DE0 for channel 0, DE1 for channel 1) and the DME bit is set to 1. When NMI occurs, DME is reset to 0, disabling DMA activity during the NMI interrupt service routine. To restart DMA, DE– and/or DE1 must be written with a 1 (even if the contents are already 1). This WRITE automatically sets DME to 1, allowing DMA operations to continue. DME cannot be directly written. It is cleared to 0 by NMI or indirectly set to 1 by setting DE0 and/or DE1 to 1. DME is cleared to 0 during RESET. DMA Mode Register (DMODE) DMODE is used to set the addressing and transfer mode for channel 0. Note:

Figure 66. DMA Mode Register (DMODE: I/O Address = 31h) decremented for each byte transferred (see Table 17). I/O to/from I/O transfers are not implemented, 12 combinations are available. Table 16. Channel 0 Destination Table 17. Channel 0 Source

until the transfer is completed. signal times the transfer and MMOD is ignored. MMOD is cleared to 0 during RESET. Figure 67. DMA/WAIT Control Register (DCNTL: I/O Address = 32h introduced into CPU or DMAC I/O access cycles. IWI1 and IWI0 are set to 1 during RESET. machine cycles involved in transferring a byte.

REQUEST signal in time, and edge sensing must be used. devices connected to TOUT/DREQ. output on the ESCC and bidirectional Centronics controller. source/destination and address modifier for channel 1 memory to/from I/O transfer modes. DIM1 and DIM0 are cleared to 0 during RESET. to 0 during RESET (Figure 68). Figure 68. Interrupt Vector Low Register (IL: I/O Address = 33h) Table 18. Channel 1 Transfer Mode

Level 0 and the INT1 and INT2 pins. Figure 69. Int/TRAP Control Register gram control. TRAP is reset to 0 during RESET. it. A RESET clears ITE0 to 1 and clears ITE1 and ITE2 to 0.

1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1.
2. The current Program Counter ( PC) value, reflecting the location of the undefined

opcode, is saved on the stack.

1. The Z80180 vectors to logical address 0.

restart at physical address 00000h was caused by RESET or TRAP. following one of the double-prefix opcodes DDCBh or FDCBh. Figure 70. TRAP Timing—2 nd Opcode Undefined

frequency. CYC0 and CYC1 are cleared to 0 during RESET (see Table 19). 10 clock cycles and be 3 clock cycles in duration.

1. REFRESH CYCLE insertion is stopped when the CPU is in the following states:
2. Refresh cycles are suppressed when the bus is released in response to BUSREQ.

no timing relationship with the bus exchange.

1. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is requested during

Table 19. DRAM Refresh Intervals

Figure 75. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH of the Bank Area. All bits of CA are set to 1 during RESET. BA are set to 1 during RESET.

Package Information

Figure 80. 80-Pin QFP Package Diagram

Figure 81. 64-Pin DIP Package Diagram

Figure 82. 68-Pin PLCC Package Diagram

Ordering Information

For fast results, contact your local ZiLOG sales office for assistance in ordering the part required. Codes Example: The Z80180 is a 10-MHz DIP, 0 ºC to 70 ºC, with Plastic Standard Flow. Table 20. Ordering Information

80180 Product Number

10 Speed

PS014004-1106 Customer Support Z80180 Microprocessor Unit Customer Support If you experience any problems while operating this product, please check the ZiLOG Knowledge Base: http://kb.zilog.com/kb/oKBmain.asp If you cannot find an answer or have further questions, please see the ZiLOG Technical Support web page: http://support.zilog.com