Z8X1621

Z8X1621 ZILOG | Alldatasheet

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High Performance 8-Bit Microcontrollers Z8 Encore!® 64K Series Preliminary ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 PS019910-0504

PS019910-0504 P r e l i m i n a r y This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters

532 Race Street

San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

PS019910-0504 P r e l i m i n a r y Table of Contents Z8 Encore!® 64K Series Product Specification iii Table of Contents I

PS019910-0504 P r e l i m i n a r y Table of Contents Z8 Encore!® 64K Series Product Specification iv

PS019910-0504 P r e l i m i n a r y Table of Contents Z8 Encore!® 64K Series Product Specification v

PS019910-0504 P r e l i m i n a r y Table of Contents Z8 Encore!® 64K Series Product Specification vi I

PS019910-0504 P r e l i m i n a r y Table of Contents Z8 Encore!® 64K Series Product Specification vii

PS019910-0504 P r e l i m i n a r y Table of Contents Z8 Encore!® 64K Series Product Specification viii

PS019910-0504 P r e l i m i n a r y Table of Contents Z8 Encore!® 64K Series Product Specification ix

Table 62. SPI Clock Phase (PHASE) and Cloc k Polarity (CLKPOL) Operation . . . 127

Table 108. Recommended Crystal Oscillator Sp ecifications (20MHz Operation) . . . 208 Table 111. Power-On Reset and Voltage Br own-Out Electrical Characteristics

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Manual Objectives xviii Manual Objectives This Product Specification provides detailed operating information for the Flash and ROM devices within the Z8 Encore!® 64K Series Microcontroller (MCU) products. Within this document, the Z8F642x, Z8F482x, Z8F322x, Z8F242x, Z8F162x, Z8R642x, Z8R482x, Z8R322x, Z8R242x, and Z8R162x devices are referred to collectively as the Z8 Encore! 64K Series unless specifically stated otherwise. About This Manual ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that there are different styles of learning. Therefore, we have designed this Product Specification to be used either as a how to procedural manual or a reference guide to important data. Intended Audience This document is written for ZiLOG customers who are experienced at working with microcontrollers, integrated circuits, or printed circuit assemblies. Manual Conventions The following assumptions and conventions are adopted to provide clarity and ease of use: Courier Typeface Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the Courier typeface. Where the use of the font is not indicated, as in the Index, the name of the entity is pre- sented in upper case.

• Example: FLAGS[1] is smrf. Hexadecimal Values Hexadecimal values are designated by uppercase H suffix and appear in the Courier typeface.
• Example: R1 is set to F8H. Brackets The square brackets, [ ], indicate a register or bus.

PS019910-0504 P r e l i m i n a r y Manual Objectives Z8 Encore!® 64K Series Product Specification xix

• Example: for the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant bit, and R1[0] is the least significant bit. Braces The curly braces, { }, indicate a single register or bus created by concatenating some com- bination of smaller registers, buses, or individual bits.
• Example: the 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer (RP) and Working Register R1. 0H is the most significant nibble (4-bit value) of the 12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register. Parentheses The parentheses, ( ), indicate an indirect register address lookup.
• Example: (R1) is the memory location referenced by the address contained in the Working Register R1. Parentheses/Bracket Combinations The parentheses, ( ), indicate an indirect register address lookup and the square brackets, [ ], indicate a register or bus.
• Example: assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the contents of the memory location at address 1234h. Use of the Words Set, Reset and Clear The word set implies that a register bit or a condition contains a logical 1. The words reset or clear imply that a register bit or a condition contains a logical 0. When either of these terms is followed by a number, the word logical may not be included; however, it is implied. Notation for Bits and Similar Registers A field of bits within a register is designated as: Register[n:n].
• Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address. Use of the Terms LSB, MSB, lsb, and msb In this document, the terms LSB and MSB, when appearing in upper case, mean least sig- nificant byte and most significant byte, respectively. The lowercase forms, lsb and msb, mean least significant bit and most significant bit, respectively. Use of Initial Uppercase Letters Initial uppercase letters designate settings and conditions in general text.
• Example 1: The receiver forces the SCL line to Low.

PS019910-0504 P r e l i m i n a r y Manual Objectives Z8 Encore!® 64K Series Product Specification xx

• Example 2: The Master can generate a Stop condition to abort the transfer. Use of All Uppercase Letters The use of all uppercase letters designates the names of states, modes, and commands.
• Example 1: The bus is considered BUSY after the Start condition.
• Example 2: A START command triggers the processing of the initialization sequence.
• Example 3: STOP mode Bit Numbering Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example, the 8 bits of a register are numbered from 0 to 7. Safeguards It is important that all users understand the following safety terms, which are defined here. Indicates a procedure or file may become corrupted if the user does not fol- low directions. Trademarks ZiLOG®, eZ8, Z8 Encore!®, and Z8® are trademarks of ZiLOG , Inc. in the U.S.A. and other countries. All other trademarks are the property of their respective corporations. Caution:

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Introduction Introduction The Z8 Encore!® MCU family of products are a line of ZiLOG microcontroller products based upon the 8-bit eZ8 CPU. The Z8 Encore!® 64K Series, hereafter referred to collec- tively as the Z8 Encore!® or the 64K Series adds Flash memory to ZiLOG’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The Z8 Encore!® 64K Series also includes ROM devices that are pin- and function-compatible with the Flash products. The ROM devices provide a low-cost alternative for customers who do not require the repro- grammability of the Flash devices. The new eZ8 CPU is upward compatible with existing Z8® instructions. The rich peripheral set of the Z8 Encore!® makes it suitable for a variety of applications including motor control, security systems, home appliances, personal elec- tronic devices, and sensors.

Features

• 20MHz eZ8 CPU
• Up to 64KB Flash (or optional ROM) with in-circuit programming capability (Flash only)
• Up to 4KB register RAM
• 12-channel, 10-bit analog-to-digital converter (ADC)
• Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control
• I2C
• Serial Peripheral Interface
• Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders
• Up to four 16-bit timers with capture, compare, and PWM capability
• Watch-Dog Timer (WDT) with internal RC oscillator
• 3-channel DMA
• Up to 60 I/O pins
• 24 interrupts with configurable priority
• On-Chip Debugger

• V oltage Brown-out Protection (VBO)
• Power-On Reset (POR)
• 3.0-3.6V operating voltage with 5V-tolerant inputs
• 0° to +70°C and -40° to +105°C operating temperature ranges Part Selection Guide Table 1 identifies the basic features and package styles available for each device within the Z8 Encore!® Z8 Encore!® product line.

Table 1. Z8 Encore!® 64K Series Part Selection Guide

PS019910-0504 P r e l i m i n a r y Introduction Z8 Encore!® 64K Series Product Specification

• Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks
• Compatible with existing Z8® code
• Expanded internal Register File allows access of up to 4KB
• New instructions improve execution efficiency for code developed using higher-level programming languages, including C
• Pipelined instruction fetch and execution
• New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL
• New instructions support 12-bit linear addressing of the Register File
• Up to 10 MIPS operation
• C-Compiler friendly
• 2-9 clock cycles per instruction For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail- able for download at www.zilog.com. General Purpose I/O The 64K Series features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for gen- eral purpose I/O (GPIO). Each pin is individually programmable. All ports (except B and H) support 5V-tolerant inputs. Flash Controller The Flash Controller programs and erases the Flash memory. 10-Bit Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from up to 12 different analog input sources. UARTs Each UART is full-duplex and capable of handling asynchronous data transfers. The UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.

PS019910-0504 P r e l i m i n a r y Introduction Z8 Encore!® 64K Series Product Specification I2C The inter-integrated circuit (I2C®) controller makes the Z8 Encore!® compatible with the I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL) line. Serial Peripheral Interface The serial peripheral interface (SPI) allows the Z8 Encore!® to exchange data between other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface. Timers Up to four 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and oper- ate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages. Interrupt Controller The 64K Series products support up to 24 interrupts. These interrupts consist of 12 inter- nal and 12 general-purpose I/O pins. The interrupts have 3 levels of programmable inter- rupt priority. Reset Controller The Z8 Encore!® can be reset using the RESET pin, power-on reset, Watch-Dog Timer (WDT), STOP mode exit, or V oltage Brown-Out (VBO) warning signal. On-Chip Debugger The Z8 Encore!® features an integrated On-Chip Debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing registers, programming the Flash, setting breakpoints and executing code. A single-pin interface provides communi- cation to the OCD. DMA Controller The 64K Series features three channels of DMA. Two of the channels are for register RAM to and from I/O operations. The third channel automatically controls the transfer of data from the ADC to the memory.

please refer to the chapter Packaging on page 260. Encore!® 64K Series product line. Table 2. Z8 Encore!® 64K Series Package Options

Figure 2. 64K Series in 40-Pin Dual Inline Package (PDIP)

• T2OUT is not supported.Note: Timer 3 is not supported.

Figure 3. 64K Series in 44-Pin Plastic Leaded Chip Carrier (PLCC)

Figure 4. 64K Series in 44-Pin Low-Profile Quad Flat Package (LQFP)

Figure 5. 64K Series in 64-Pin Low-Profile Quad Flat Package (LQFP)

Figure 6. 64K Series in 68-Pin Plastic Leaded Chip Carrier (PLCC)

Figure 7. 64K Series in 80-Pin Quad Flat Package (QFP)

page 7 to determine the signals available for the specific package styles. Table 3. Signal Descriptions PB[7:0] I/O Port B[7:0]. These pins are used for general-purpose I/O. general-purpose I/O and support 5V-tolerant inputs. general-purpose I/O and support 5V-tolerant inputs. general-purpose I/O and support 5V-tolerant inputs. PH[3:0] I/O Port H[3:0]. These pins are used for general-purpose I/O. alternate function to enable the SCL function, this pin is open-drain. configured for alternate function to enable the SDA function, this pin is open-drain. multiplexed with a general-purpose I/O pin. this pin is an input. It is multiplexed with a general-purpose I/O pin.

output from the SPI slave device. It is multiplexed with a general-purpose I/O pin. signals are multiplexed with general-purpose I/O pins. RXD signals are multiplexed with general-purpose I/O pins. multiplexed with general-purpose I/O pins. enabled when data is transmitted by the UART. I Timer Input 0-3. These signals are used as the capture, gating and counter inputs. available in 44-pin package devices. ADC analog inputs are multiplexed with general-purpose I/O pins. reference is selected as the ADC reference voltage. with external RC networks and an external clock driver. Table 3. Signal Descriptions (Continued)

clock is referred to in this manual, it refers to the frequency of the signal at this pin. This pin must be left unconnected when not using a crystal. Debugger. This pin is open-drain. supplied with power and all ground pins (VSS and A VSS) must be properly grounded. RESET I RESET. Generates a Reset when asserted (driven Low). A VDD I Analog Power Supply.

Table 4. Pin Characteristics of the 64K Series

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Address Space Address Space Overview The eZ8 CPU can access three distinct address spaces:

• The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral, and general-purpose I/O port control registers.
• The Program Memory contains addresses for all memory locations having executable code and/or data.
• The Data Memory contains addresses for all memory locations that hold data only. These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU User Manual available for download at www.zilog.com. Register File The Register File address space in the 64K Series is 4KB (4096 bytes). The Register File is composed of two sections—control regist ers and general-purpose registers. When instructions are executed, registers are read from when defined as sources and written to when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256-byte control register section are reserved (unavailable). Reading from an reserved Register File addresses returns an undefined value. Writing to reserved Register File addresses is not recom- mended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. The 64K Series provide 2KB to 4KB of on-chip RAM depending upon the device. Reading from Register File addresses outside the available RAM addresses (and not within the con- trol register address space) returns an undefined value. Writing to these Register File addresses produces no effect. Refer to the Part Selection Guide on page 2 to determine the amount of RAM available for the specific 64K Series device.

the Program Memory Maps for the 64K Series products. Table 5. Z8 Encore® 64K Series Program Memory Maps

• See Table 23 on page 63 for a list of the interrupt vectors.

Table 5. Z8 Encore

• See Table 23 on page 63 for a list of the interrupt vectors.

Table 6. Z8 Encore!® 64K Series Information Area Map

devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports. Consider registers for unimplemented peripherals as Reserved. Table 7. 64K Series Register File Address Map

Table 7. 64K Series Register File Address Map (Continued)

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Control Register Summary Timer 0 High Byte T0H (F00H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [15:8] Timer 0 Low Byte T0L (F01H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [7:0] Timer 0 Reload High Byte T0RH (F02H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [15:8] Timer 0 Reload Low Byte T0RL (HF03 - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [7:0] Timer 0 PWM High Byte T0PWMH (F04H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 PWM value [15:8] Timer 0 Control 0 T0CTL0 (F06H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 0 Input signal is GPIO pin 1 = Timer 0 Input signal is Timer 3 out Reserved Timer 0 Control 1 T0CTL1 (F07H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled Timer 1 High Byte T1H (F08H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [15:8] Timer 1 Low Byte T1L (F09H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [7:0] Timer 1 Reload High Byte T1RH (F0AH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [15:8] Timer 1 Reload Low Byte T1RL (F0BH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [7:0]

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Timer 1 PWM High Byte T1PWMH (F0CH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [15:8] Timer 1 PWM Low Byte T1PWML (F0DH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [7:0] Timer 1 Control 0 T1CTL0 (F0EH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 1 Input signal is GPIO pin 1 = Timer 1 Input signal is Timer 0 out Reserved Timer 1 Control 1 T1CTL1 (F0FH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled Timer 2 High Byte T2H (F10H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 current count value [15:8] Timer 2 Low Byte T2L (F11H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 current count value [7:0] Timer 2 Reload High Byte T2RH (F12H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 reload value [15:8] Timer 2 Reload Low Byte T2RL (F13H- Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 reload value [7:0] Timer 2 PWM High Byte T2PWMH (F14H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 PWM value [15:8] Timer 2 PWM Low Byte T2PWML (F15H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 PWM value [7:0] Timer 2 Control 0 T2CTL0 (F16H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 2 Input signal is GPIO pin 1 = Timer 2 Input signal is Timer 1 out Reserved

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Timer 2 Control 1 T2CTL1 (F17H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = CAPTURE/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled Timer 3 High Byte T3H (F18H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 current count value [15:8] Timer 3 Low Byte T3L (F19H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 current count value [7:0] Timer 3 Reload High Byte T3RH (F1AH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 reload value [15:8] Timer 3 Reload Low Byte T3RL (F1BH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 reload value [7:0] Timer 3 PWM High Byte T3PWMH (F1CH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 PWM value [15:8] Timer 3 PWM Low Byte T3PWML (F1DH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 PWM value [7:0] Timer 3 Control 0 T3CTL0 (F1EH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 3 Input signal is GPIO pin 1 = Timer 3 Input signal is Timer 2 out Reserved Timer 3 Control 1 T3CTL1 (F1FH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! UART0 Transmit Data U0TXD (F40H - Write Only) D7 D6 D5 D4 D3 D2 D1 D0 UART0 transmitter data byte [7:0] UART0 Receive Data U0RXD (F40H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 UART0 receiver data byte [7:0] UART0 Status 0 U0STAT0 (F41H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data Register Empty 0 = Transmit Data Register is full 1 = Transmit Data register is empty Break Detect 0 = No break occurred 1 = A break occurred Framing Error 0 = No framing error occurred 1 = A framing occurred Overrun Error 0 = No overrun error occurred 1 = An overrun error occurred Parity Error 0 = No parity error occurred 1 = A parity error occurred Receive Data Available 0 = Receive Data Register is empty 1 = A byte is available in the Receive Data Register UART0 Control 0 U0CTL0 (F42H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Loop Back Enable 0 = Normal operation 1 = Transmit data is looped back to the receiver Stop Bit Select 0 = Transmitter sends 1 Stop bit 1 = Transmitter sends 2 Stop bits Send Break 0 = No break is sent 1 = Output of the transmitter is zero Parity Select 0 = Even parity 1 = Odd parity Parity Enable 0 = Parity is disabled 1 = Parity is enabled CTS Enable 0 = CTS signal has no effect on the transmitter 1 = UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 = Receiver disabled 1 = Receiver enabled Transmit Enable 0 = Transmitter disabled 1 = Transmitter enabled

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! UART0 Control 1 U0CTL1 (F43H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors generate interrupt requests 1 = Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 = DE signal is active High 1 = DE signal is active Low Multiprocessor Bit Transmit 0 = Send a 0 as the multiprocessor bit 1 = Send a 1 as the multiprocessor bit Multiprocessor Mode [0] See Multiprocessor Mode [1] below Multiprocessor (9-bit) Enable 0 = Multiprocessor mode is disabled 1 = Multiprocessor mode is enabled Multiprocessor Mode [1] with Multiprocess Mode bit 0: 00 = Interrupt on all received bytes 01 = Interrupt only on address bytes 10 = Interrupt on address match and following data 11 = Interrupt on data following an address match UART0 Status 1 U0STAT1 (F44H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Mulitprocessor Receive Returns value of last multiprocessor bit New Frame 0 = Current byte is not start of frame 1 = Current byte is start of new frame Reserved UART0 Address Compare U0ADDR (F45H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART0 Address Compare [7:0] UART0 Baud Rate Generator High Byte U0BRH (F46H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [15:8] UART0 Baud Rate Generator Low Byte U0BRL (F47H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [7:0] UART1 Transmit Data U1TXD (F48H - Write Only) D7 D6 D5 D4 D3 D2 D1 D0 UART1 transmitter data byte[7:0] UART1 Receive Data U1RXD (F48H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 UART receiver data byte [7:0]

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! UART1 Status 0 U1STAT0 (F49H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data Register Empty 0 = Transmit Data Register is full 1 = Transmit Data register is empty Break Detect 0 = No break occurred 1 = A break occurred Framing Error 0 = No framing error occurred 1 = A framing occurred Overrun Error 0 = No overrun error occurred 1 = An overrun error occurred Parity Error 0 = No parity error occurred 1 = A parity error occurred Receive Data Available 0 = Receive Data Register is empty 1 = A byte is available in the Receive Data Register UART1 Control 0 U1CTL0 (F4AH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Loop Back Enable 0 = Normal operation 1 = Transmit data is looped back to the receiver Stop Bit Select 0 = Transmitter sends 1 Stop bit 1 = Transmitter sends 2 Stop bits Send Break 0 = No break is sent 1 = Output of the transmitter is zero Parity Select 0 = Even parity 1 = Odd parity Parity Enable 0 = Parity is disabled 1 = Parity is enabled CTS Enable 0 = CTS signal has no effect on the transmitter 1 = UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 = Receiver disabled 1 = Receiver enabled Transmit Enable 0 = Transmitter disabled 1 = Transmitter enabled

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! UART1 Control 1 U0CTL1 (F4BH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors generate interrupt requests 1 = Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 = DE signal is active High 1 = DE signal is active Low Multiprocessor Bit Transmit 0 = Send a 0 as the multiprocessor bit 1 = Send a 1 as the multiprocessor bit Multiprocessor Mode [0] See Multiprocessor Mode [1] below Multiprocessor (9-bit) Enable 0 = Multiprocessor mode is disabled 1 = Multiprocessor mode is enabled Multiprocessor Mode [1] with Multiprocess Mode bit 0: 00 = Interrupt on all received bytes 01 = Interrupt only on address bytes 10 = Interrupt on address match and following data 11 = Interrupt on data following an address match UART1 Status 1 U0STAT1 (F4CH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Mulitprocessor Receive Returns value of last multiprocessor bit New Frame 0 = Current byte is not start of frame 1 = Current byte is start of new frame Reserved UART1 Address Compare U0ADDR (F4DH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART1 Address Compare [7:0] UART1 Baud Rate Generator High Byte U0BRH (F4EH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART1 Baud Rate divisor [15:8] UART1 Baud Rate Generator Low Byte U1BRL (F4FH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART1 Baud Rate divisor [7:0] I2C Data I2CDATA (F50H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C data [7:0] I2C Status I2CSTAT (F51H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 NACK Interrupt 0 = No action required to service NAK 1 = START/STOP not set after NAK Data Shift State 0 = Data is not being transferred 1 = Data is being transferred Transmit Address State 0 = Address is not being transferred 1 = Address is being transferred Read 0 = Write operation 1 = Read operation 10-Bit Address 0 = 7-bit address being transmitted 1 = 10-bit address being transmitted Acknowledge 0 = Acknowledge not transmitted/received 1 = For last byte, Acknowledge was transmitted/received Receive Data Register Full 0 = I2C has not received data 1 = Data register contains received data Transmit Data Register Empty 0 = Data register is full 1 = Data register is empty

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! I2C Control I2CCTL (F52H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C Signal Filter Enable 0 = Digital filtering disabled 1 = Low-pass digital filters enabled on SDA and SCL input signals Flush Data 0 = No effect 1 = Clears I2C Data register Send NAK 0 = Do not send NAK 1 = Send NAK after next byte received from slave Enable TDRE Interrupts 0 = Do not generate an interrupt when the I2C Data register is empty 1 = Generate an interrupt when the I2C Transmit Data register is empty Baud Rate Generator Interrupt Request 0 = Interrupts behave as set by I2C control 1 = BRG generates an interrupt when it counts down to zero Send Stop Condition 0 = Do not issue Stop condition after data transmission is complete 1 = Issue Stop condition after data transmission is complete Send Start Condition 0 = Do not send Start Condition 1 = Send Start Condition I2C Enable 0 = I2C is disabled 1 = I2C is enabled I2C Baud Rate Generator High Byte I2CBRH (F53H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [15:8] I2C Baud Rate Generator Low Byte I2CBRL (F54H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [7:0] SPI Data SPIDATA (F60H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Data [7:0] SPI Control SPICTL (F61H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Enable 0 = SPI disabled 1 = SPI enabled Master Mode Enabled 0 = SPI configured in Slave mode 1 = SPI configured in Master mode Wire-OR (open-drain) Mode Enabled 0 = SPI signals not configured for open-drain 1 = SPI signals (SCK, SS, MISO, and MOSI) configured for open-drain Clock Polarity 0 = SCK idles Low 1 = SPI idles High Phase Select Sets the phase relationship of the data to the clock. BRG Timer Interrupt Request 0 = BRG timer function is disabled 1 = BRG time-out interrupt is enabled Start an SPI Interrupt Request 0 = No effect 1 = Generate an SPI interrupt request Interrupt Request Enable 0 = SPI interrupt requests are disabled 1 = SPI interrupt requests are enabled

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! SPI Status SPISTAT (F62H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Slave Select 0 = If Slave, SS pin is asserted 1 = If Slave, SS pin is not asserted Transmit Status 0 = No data transmission in progress 1 = Data transmission now in progress Reserved Slave Mode Transaction Abort 0 = No slave mode transaction abort detected 1 = Slave mode transaction abort was detected Collision 0 = No multi-master collision detected 1 = Multi-master collision was detected Overrun 0 = No overrun error detected 1 = Overrun error was detected Interrupt Request 0 = No SPI interrupt request pending 1 = SPI interrupt request is pending SPI Mode SPIMODE (F63H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Slave Select Value If Master and SPIMODE[1] = 1: 0 = SS pin driven Low 1 = SS pin driven High Slave Select I/O 0 = SS pin configured as an input 1 = SS pin configured as an output (Master mode only) Number of Data Bits Per Character 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bit 110 = 6 bits 111 = 7 bits Diagnostic Mode Control 0 = Reading from SPIBRH, SPIBRL returns reload values 1 = Reading from SPIBRH, SPIBRL returns current BRG count value Reserved SPI Diagnostic State SPIDST (F64H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 SPI State Transmit Clock Enable 0 = Internal transmit clock enable signal is deasserted 1 = Internal transmit clock enable signal is asserted Shift Clock Enable 0 = Internal shift clock enable signal is deasserted 1 = Internal shift clock enable signal is asserted SPI Baud Rate Generator High Byte SPIBRH (F66H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [15:8] SPI Baud Rate Generator Low Byte SPIBRL (F67H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [7:0] ADC Control ADCCTL (F70H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Analog Input Select 0000 = ANA0 0001 = ANA1 0010 = ANA2 0011 = ANA3 0100 = ANA4 0101 = ANA5 0110 = ANA6 0111 = ANA7 1000 = ANA8 1001 = ANA9 1010 = ANA10 1011 = ANA11 11xx = Reserved Continuous Mode Select 0 = Single-shot conversion 1 = Continuous conversion External VREF select 0 = Internal voltage reference selected 1 = External voltage reference selected Reserved Conversion Enable 0 = Conversion is complete 1 = Begin conversion

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! ADC Data High Byte ADCD_H (F72H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 ADC Data [9:2] ADC Data Low Bits ADCD_L (F73H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Reserved ADC Data [1:0] DMA0 Control DMA0CTL (FB0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Received Data register contains valid data 101 = UART1 Received Data register contains valid data 110 = I2C receiver contains valid data 111 = Reserved Word Select 0 = DMA transfers 1 byte per request 1 = DMA transfers 2 bytes per request DMA0 Interrupt Enable 0 = DMA0 does not generate interrupts 1 = DMA0 generates an interrupt when End Address data is transferred DMA0 Data Transfer Direction 0 = Register File to peripheral registers 1 = Peripheral registers to Register File DMA0 Loop Enable 0 = DMA disables after End Address 1 = DMA reloads Start Address after End Address and continues to run DMA0 Enable 0 = DMA0 is disabled 1 = DMA0 is enabled DMA0 I/O Address DMA0IO (FB1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Peripheral Register Address Low byte of on-chip peripheral control registers on Register File page FH DMA0 Address High Nibble DMA0H (FB2H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Start Address [11:8] DMA0 End Address [11:8] DMA0 Start/Current Address Low Byte DMA0START (FB3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Start Address [7:0] DMA0 End Address Low Byte DMA0END (FB4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 End Address [7:0] DMA1 Control DMA1CTL (FB8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Transmit Data register is empty 101 = UART1 Transmit Data register is empty 110 = I2C Transmit Data register is empty 111 = Reserved Word Select 0 = DMA transfers 1 byte per request 1 = DMA transfers 2 bytes per request DMA1 Interrupt Enable 0 = DMA1 does not generate interrupts 1 = DMA1 generates an interrupt when End Address data is transferred DMA1 Data Transfer Direction 0 = Register File to peripheral registers 1 = Peripheral registers to Register File DMA1 Loop Enable 0 = DMA disables after End Address 1 = DMA reloads Start Address after End Address and continues to run DMA1 Enable 0 = DMA1 is disabled 1 = DMA1 is enabled

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! DMA1 I/O Address DMA1IO (FB9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Peripheral Register Address Low byte of on-chip peripheral control registers on Register File page FH DMA1 Address High Nibble DMA1H (FBAH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Start Address [11:8] DMA1 End Address [11:8] DMA1 Start/Current Address Low Byte DMA1START (FBBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Start Address [7:0] DMA1 End Address Low Byte DMA1END (FBCH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 End Address [7:0] DMA_ADC Address DMAA_ADDR (FBDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved DMA_ADC Address DMA_ADC Control DMAACTL (FBEH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC Analog Input Number 0000 = Analog input 0 updated 0001 = Analog input 0-1 updated 0010 = Analog input 0-2 updated 0011 = Analog input 0-3 updated 0100 = Analog input 0-4 updated 0101 = Analog input 0-5 updated 0100 = Analog input 0-6 updated 0101 = Analog input 0-7 updated 1000 = Analog input 0-8 updated 1001 = Analog input 0-9 updated 1010 = Analog input 0-10 updated 1011 = Analog inputs 0-11 updated 11xx = Reserved Reserved Interrupt request enable 0 = DMA_ADC does not generate interrupt requests 1 = DMA_ADC generates interrupt requests after last analog input DMA_ADC Enable 0 = DMA_ADC is disabled 1 = DMA_ADC is enabled DMA Status DMAA_STAT (FBFH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Interrupt Request Indicator 0 = DMA0 is not the source of the IRQ 1 = DMA0 is the source of the IRQ DMA1 Interrupt Request Indicator 0 = DMA1 is not the source of the IRQ 1 = DMA1 is the source of the IRQ DMA_ADC Interrupt Request Indicator 0 = DMA_ADC is not the source of the IRQ 1 = DMA_ADC is the source of the IRQ Reserved Current ADC analog input Identifies the analog input the ADC is currently converting

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Interrupt Request 0 IRQ0 (FC0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC Interrupt Request SPI Interrupt Request I2C Interrupt Request UART 0 Transmitter Interrupt Request UART 0 Receiver Interrupt Request Timer 0 Interrupt Request Timer 1 Interrupt Request Timer 2 Interrupt Request For all of the above peripherals: 0 = Peripheral IRQ is not pending 1 = Peripheral IRQ is awaiting service IRQ0 Enable High Bit IRQ0ENH (FC1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable High Bit I2C IRQ Enable High Bit UART 0 Transmitter IRQ Enable High UART 0 Receiver IRQ Enable High Bit Timer 0 IRQ Enable High Bit Timer 1 IRQ Enable High Bit Timer 2 IRQ Enable High Bit IRQ0 Enable Low Bit IRQ0ENL (FC2H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable Low Bit I2C IRQ Enable Low Bit UART 0 Transmitter IRQ Enable Low UART 0 Receiver IRQ Enable Low Bit Timer 0 IRQ Enable Low Bit Timer 1 IRQ Enable Low Bit Timer 2 IRQ Enable Low Bit Interrupt Request 1 IRQ1 (FC3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin Interrupt Request 0 = IRQ from corresponding pin [7:0] is not pending 1 = IRQ from corresponding pin [7:0] is awaiting service IRQ1 Enable High Bit IRQ1ENH (FC4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin IRQ Enable High Bit IRQ1 Enable Low Bit IRQ1ENL (FC5H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin IRQ Enable Low Bit

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Interrupt Request 2 IRQ2 (FC6H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin Interrupt Request 0 = IRQ from corresponding pin [3:0] is not pending 1 = IRQ from corresponding pin [3:0] is awaiting service DMA Interrupt Request UART 1 Transmitter Interrupt Request UART 1 Receiver Interrupt Request Timer 3 Interrupt Request For all of the above peripherals: 0 = Peripheral IRQ is not pending 1 = Peripheral IRQ is awaiting service IRQ2 Enable High Bit IRQ2ENH (FC7H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable High Bit DMA IRQ Enable High Bit UART 1 Transmitter IRQ Enable High UART 1 Receiver IRQ Enable High Bit Timer 3 IRQ Enable High Bit IRQ2 Enable Low Bit IRQ2ENL (FC8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable Low Bit DMA IRQ Enable Low Bit UART 1 Transmitter IRQ Enable Low UART 1 Receiver IRQ Enable Low Bit Timer 3 IRQ Enable Low Bit Interrupt Edge Select IRQES (FCDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Interrupt Edge Select [7:0] 0 = Falling edge 1 = Rising edge Interrupt Port Select IRQPS (FCEH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Port Pin Select [7:0] 0 = Port A pin is the interrupt source 1 = Port D pin is the interrupt source Interrupt Control IRQCTL (FCFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Interrupt Request Enable 0 = Interrupts are disabled 1 = Interrupts are enabled Port A Address PAADDR (FD0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port A Control PACTL (FD1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A Control[7:0] Provides Access to Port Sub-Registers Port A Input Data PAIN (FD2H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port A Input Data [7:0] Port A Output Data PAOUT (FD3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A Output Data [7:0]

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Port B Address PBADDR (FD4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port B Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port B Control PBCTL (FD5H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port B Control[7:0] Provides Access to Port Sub-Registers Port B Input Data PBIN (FD6H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port B Input Data [7:0] Port B Output Data PBOUT (FD7H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port B Output Data [7:0] Port C Address PCADDR (FD8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port C Control PCCTL (FD9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Control[7:0] Provides Access to Port Sub-Registers Port C Input Data PCIN (FDAH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port C Input Data [7:0] Port C Output Data PCOUT (FDBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Output Data [7:0] Port D Address PDADDR (FDCH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port D Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port D Control PDCTL (FDDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port D Control[7:0] Provides Access to Port Sub-Registers Port D Input Data PDIN (FDE H- Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port D Input Data [7:0] Port D Output Data PDOUT (FDFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port D Output Data [7:0]

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Port E Address PEADDR (FE0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port E Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port E Control PECTL (FE1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port E Control[7:0] Provides Access to Port Sub-Registers Port E Input Data PEIN (FE2H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port E Input Data [7:0] Port E Output Data PEOUT (FE3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port E Output Data [7:0] Port F Address PFADDR (FE4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port F Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port F Control PFCTL (FE5H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port F Control[7:0] Provides Access to Port Sub-Registers Port F Input Data PFIN (FE6H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port F Input Data [7:0] Port F Output Data PFOUT (FE7H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port F Output Data [7:0] Port G Address PGADDR (FE8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port G Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port G Control PGCTL (FE9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port G Control[7:0] Provides Access to Port Sub-Registers Port G Input Data PGIN (FEAH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port G Input Data [7:0] Port G Output Data PGOUT (FEBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port G Output Data [7:0]

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Port H Address PHADDR (FECH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port H Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port H Control PHCTL (FEDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port H Control [3:0] Provides Access to Port Sub-Registers Reserved Port H Input Data PHIN (FEEH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port H Input Data [3:0] Reserved Port H Output Data PHOUT (FEFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port H Output Data [3:0] Reserved Watch-Dog Timer Control WDTCTL (FF0H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 SM Configuration Indicator Reserved EXT 0 = Reset not generated by RESET pin 1 = Reset generated by RESET pin WDT 0 = WDT timeout has not occurred 1 = WDT timeout occurred STOP 0 = SMR has not occurred 1 = SMR has occurred POR 0 = POR has not occurred 1 = POR has occurred Watch-Dog Timer Reload Upper Byte WDTU (FF1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [23:16] Watch-Dog Timer Reload Middle Byte WDTH (FF2 H- Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [15:8] Watch-Dog Timer Reload Low Byte WDTL (FF3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [7:0] Flash Control FCTL (FF8H - Write Only) D7 D6 D5 D4 D3 D2 D1 D0 Flash Command 73H = First unlock command 8CH = Second unlock command 95H = Page erase command 63H = Mass erase command 5EH = Flash Sector Protect reg select

PS019910-0504 P r e l i m i n a r y Control Register Summary Z8 Encore!® 64K Series Z8 Encore! Flash Status FSTAT (FF8H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Flash Controller Status 00_0000 = Flash controller locked 00_0001 = First unlock received 00_0010 = Second unlock received 00_0011 = Flash controller unlocked 00_0100 = Flash Sector Protect register selected 00_1xxx = Programming in progress 01_0xxx = Page erase in progress 10_0xxx = Mass erase in progress Reserved Page Select FPS (FF9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Page Select [6:0] Identifies the Flash memory page for Page Erase operation. Information Area Enable 0 = Information Area access is disabled 1 = Information Area access is enabled Flash Sector Protect FPROT (FF9H - Read/Write to 1’s) D7 D6 D5 D4 D3 D2 D1 D0 Flash Sector Protect [7:0] 0 = Sector can be programmed or erased from user code 1 = Sector is protected and cannot be programmed or erased from user code Flash Frequency High Byte FFREQH (FFAH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [15:8] Flash Frequency Low Byte FFREQL (FFBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [7:0] Flags FLAGS (FFC - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 F1 - User Flag 1 F2 - User Flag 2 H - Half Carry D - Decimal Adjust V - Overflow Flag S - Sign Flag Z - Zero Flag C - Carry Flag Register Pointer RP (FFDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Working Register Page Address [11:8] Working Register Group Address [7:4] Stack Pointer High Byte SPH (FFEH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [15:8] Stack Pointer Low Byte SPL (FFFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [7:0]

• Power-On Reset (POR)
• V oltage Brown-Out (VBO)
• Watch-Dog Timer time-out (when configured via the WDT_RES Option Bit to initiate a Reset)
• External RESET pin assertion
• On-Chip Debugger initiated Reset (OCDCTL[0] set to 1) When the 64K Series devices are in STOP mode, a STOP Mode Recovery is initiated by either of the following:
• Watch-Dog Timer time-out
• GPIO Port input pin transition on an enabled STOP Mode Recovery source
• DBG pin driven Low Reset Types The 64K Series provides two different types of reset operation (System Reset and STOP Mode Recovery). The type of Reset is a function of both the current operating mode of the 64K Series devices and the source of the Reset. Table 8 lists the types of Reset and their operating characteristics.

Table 8. Reset and STOP Mode Recovery Characteristics and Latency

of Reset, all GPIO pins are configured as inputs. peripherals remain idle through the 16 cycles of the system clock. Table 9. Reset Sources and Resulting Reset Type

The V oltage Brown-Out circuit can be either enabled or disabled during STOP mode. chapter for information on configuring VBO_AO. Figure 9. Voltage Brown-Out Reset Operation trol register is set to signify that the reset was initiated by the Watch-Dog Timer.

reset. Following the system reset the POR bit in the WDT Control register is set. control registers, and general-purpose RAM. Table 10. STOP Mode Recovery Sources and Resulting Action

PS019910-0504 P r e l i m i n a r y Reset and STOP Mode Recovery Z8 Encore!® 64K Series Product Specification STOP Mode Recovery Using Watch-Dog Timer Time-Out If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP Mode Recovery sequence. In the Watch-Dog Timer Control register, the WDT and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon time- out and the 64K Series devices are configured to respond to interrupts, the eZ8 CPU ser- vices the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery sequence. STOP Mode Recovery Using a GPIO Port Pin Transition HALT Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source. On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin value (from High to Low or from Low to High) initiates STOP Mode Recovery. The GPIO STOP Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in dura- tion. In the Watch-Dog Timer Control register, the STOP bit is set to 1. In STOP mode, the GPIO Port Input Data registers (P xIN) are disabled. The Port Input Data registers record the Port transition only if the signal stays on the Port pin through the end of the STOP Mode Recovery delay. Thus, short pulses on the Port pin can initiate STOP Mode Recovery with- out being written to the Port Input Data register or without initiating an in- terrupt (if enabled for that pin). Caution:

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Low-Power Modes Low-Power Modes Overview The 64K Series products contain power-saving features. The highest level of power reduc- tion is provided by STOP mode. The next level of power reduction is provided by the HALT mode. STOP Mode Execution of the eZ8 CPU’s STOP instruction places the device into STOP mode. In STOP mode, the operating characteristics are:

• Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is driven Low.
• System clock is stopped
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• The Watch-Dog Timer and its internal RC oscillator continue to operate, if enabled for operation during STOP mode.
• The V oltage Brown-Out protection circuit continues to operate, if enabled for operation in STOP mode using the associated Option Bit.
• All other on-chip peripherals are idle. To minimize current in STOP mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (VCC or GND), the V oltage Brown-Out protection must be disabled, and the Watch-Dog Timer must be disabled. The devices can be brought out of STOP mode using STOP Mode Recovery. For more information on STOP Mode Recovery refer to the Reset and STOP Mode Recovery chapter beginning on page 43. STOP Mode must not be used when driving the 64K Series devices with an external clock driver source. Caution:

PS019910-0504 P r e l i m i n a r y Low-Power Modes Z8 Encore!® 64K Series Product Specification HALT Mode Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are:

• Primary crystal oscillator is enabled and continues to operate
• System clock is enabled and continues to operate
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• Watch-Dog Timer’s internal RC oscillator continues to operate
• The Watch-Dog Timer continues to operate, if enabled
• All other on-chip peripherals continue to operate The eZ8 CPU can be brought out of HALT mode by any of the following operations:
• Interrupt
• Watch-Dog Timer time-out (interrupt or reset)
• Power-on reset
• V oltage-brown out reset
• External RESET pin assertion To minimize current in HALT mode, all GPIO pins which are configured as inputs must be driven to one of the supply rails (VCC or GND).

programmable. All ports (except B and H) support 5V-tolerant inputs. Table 11 lists the port pins available with each device and package type. Table 11. Port Availability by Device and Package Type

associated with each port pin. Table 12. Port Alternate Function Mapping

interrupts using the GPIO pins. Four registers for each Port provide access to GPIO control, input data, and output data. together to provide access to sub-registers for Port configuration and control. Table 12. Port Alternate Function Mapping (Continued)

vide access to all GPIO Port control (Table 14). Table 13. GPIO Port Registers and Sub-Registers Table 14. Port A-H GPIO Address Registers (PxADDR)

Port A–H Control register (Table 15). 00H No function. Provides some protection against accidental Port reconfiguration. 05H STOP Mode Recovery Source Enable. Table 15. Port A

ter by writing 01H to the Port A–H Address register (Table 16). tion overrides the Data Direction register setting. 0 = Output. Data in the Port A–H Output Data register is driven onto the port pin. ister. The output driver is tri-stated. Table 16. Port A-H Data Direction Sub-Registers Table 17. Port A-H Alternate Function Sub-Registers

register determines the direction of the pin. 0 = The drains are enabled for any output mode. 1 = The drain of the associated pin is disabled (open-drain mode). Table 18. Port A-H Output Control Sub-Registers

pins directly and, as a result, alternate functions are also affected. 0 = The Port pin is configured for standard output current drive. 1 = The Port pin is configured for high output current drive. through the Port A–H Control register by writing 05H to the Port A–H Address register. Table 19. Port A–H High Drive Enable Sub-Registers

pin during STOP mode do not initiate STOP Mode Recovery. this pin during STOP mode initiates STOP Mode Recovery. from the corresponding port pins. The Port A–H Input Data registers are Read-only. Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High). Table 20. Port A-H STOP Mode Recovery Source Enable Sub-Registers Table 21. Port A–H Input Data Registers (PxIN)

The Port A–H Output Data register (Table 22) writes output data to the pins. 0 = Drive a logical 0 (Low). ting the corresponding Port Output Control register bit to 1. Table 22. Port A-H Output Data Register (PxOUT)

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Interrupt Controller Interrupt Controller Overview The interrupt controller on the 64K Series products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt controller include the following:

• 24 unique interrupt vectors: – 12 GPIO port pin interrupt sources – 12 on-chip peripheral interrupt sources
• Flexible GPIO interrupts – 8 selectable rising and falling edge GPIO interrupts – 4 dual-edge interrupts
• 3 levels of individually programmable interrupt priority
• Watch-Dog Timer can be configured to generate an interrupt Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the CPU and the interrupting peripheral. When the service routine is com- pleted, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt control has no effect on operation. Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man- ual is available for download at www.zilog.com. Interrupt Vector Listing Table 23 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even Program Memory address and the least significant byte (LSB) at the following odd Program Memory address.

Table 23. Interrupt Vectors in Order of Priority

• Executing a Trap instruction
• Illegal Instruction trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for example), then interrupt priority would be assigned from highest to lowest as specified in

Table 23. Level 3 interrupts always have higher priority than Level 2 interrupts which, in execution of the first LDX command and the last LDX command are lost.

and the last LDX command are lost. enable individual interrupts, set interrupt priorities, and indicate interrupt requests. Table 24. Interrupt Request 0 Register (IRQ0)

PS019910-0504 P r e l i m i n a r y Interrupt Controller Z8 Encore!® 64K Series Product Specification T2I—Timer 2 Interrupt Request 0 = No interrupt request is pending for Timer 2. 1 = An interrupt request from Timer 2 is awaiting service. T1I—Timer 1 Interrupt Request 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. T0I—Timer 0 Interrupt Request 0 = No interrupt request is pending for Timer 0. 1 = An interrupt request from Timer 0 is awaiting service. U0RXI—UART 0 Receiver Interrupt Request 0 = No interrupt request is pending for the UART 0 receiver. 1 = An interrupt request from the UART 0 receiver is awaiting service. U0TXI—UART 0 Transmitter Interrupt Request 0 = No interrupt request is pending for the UART 0 transmitter. 1 = An interrupt request from the UART 0 transmitter is awaiting service. I 2CI— I 2C Interrupt Request 0 = No interrupt request is pending for the I2C. 1 = An interrupt request from the I2C is awaiting service. SPII—SPI Interrupt Request 0 = No interrupt request is pending for the SPI. 1 = An interrupt request from the SPI is awaiting service. ADCI—ADC Interrupt Request 0 = No interrupt request is pending for the Analog-to-Digital Converter. 1 = An interrupt request from the Analog-to-Digital Converter is awaiting service. Interrupt Request 1 Register The Interrupt Request 1 (IRQ1) register (Table 25) stores interrupt requests for both vec- tored and polled interrupts. When a request is presented to the interrupt controller, the cor- responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending.

0 = No interrupt request is pending for GPIO Port A or Port D pin x. 1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service. D) is determined by the values in the Interrupt Port Select Register. register to determine if any interrupt requests are pending. 0 = No interrupt request is pending for Timer 3. 1 = An interrupt request from Timer 3 is awaiting service. Table 25. Interrupt Request 1 Register (IRQ1) Table 26. Interrupt Request 2 Register (IRQ2)

0 = No interrupt request is pending for the UART1 receiver. 1 = An interrupt request from UART1 receiver is awaiting service. 0 = No interrupt request is pending for the UART 1 transmitter. 1 = An interrupt request from the UART 1 transmitter is awaiting service. 0 = No interrupt request is pending for the DMA. 1 = An interrupt request from the DMA is awaiting service. 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. where x indicates the specific GPIO Port C pin number (0 through 3). bits in each register. Table 27 describes the priority control for IRQ0. Table 27. IRQ0 Enable and Priority Encoding

01 L e v e l 1 L o w

11 L e v e l 3 H i g h

where x indicates the register bits from 0 through 7. Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)

bits in each register. Table 30 describes the priority control for IRQ1. Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL) Table 30. IRQ1 Enable and Priority Encoding where x indicates the register bits from 0 through 7.

bits in each register. Table 33 describes the priority control for IRQ2. Table 31. IRQ1 Enable High Bit Register (IRQ1ENH) Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL) Table 33. IRQ2 Enable and Priority Encoding where x indicates the register bits from 0 through 7.

Table 34. IRQ2 Enable High Bit Register (IRQ2ENH) Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)

the edge triggered interrupt. Shorter pulses may be captured but not guaranteed. 0 = An interrupt request is generated on the falling edge of the PAx/PDx input. 1 = An interrupt request is generated on the rising edge of the PAx/PDx input. rupts. The Interrupt Edge Select register controls the active interrupt edge. 0 = PAx is used for the interrupt for PAx/PDx interrupt request. 1 = PDx is used for the interrupt for PAx/PDx interrupt request. Table 36. Interrupt Edge Select Register (IRQES) Table 37. Interrupt Port Select Register (IRQPS)

instruction, eZ8 CPU acknowledgement of an interrupt request, or Reset. Table 38. Interrupt Control Register (IRQCTL)

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Timers Timers Overview The 64K Series products contain up to four 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) signals. The tim- ers’ features include:

• 16-bit reload counter
• Programmable prescaler with prescale values from 1 to 128
• PWM output generation
• Capture and compare capability
• External input pin for timer input, clock gating, or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency.
• Timer output pin
• Timer interrupt In addition to the timers described in this chapter, the Baud Rate Generators for any unused UART, SPI, or I2C peripherals may also be used to provide basic timing function- ality. Refer to the respective serial communication peripheral chapters for information on using the Baud Rate Generators as timers. Timer 3 is unavailable in the 44-pin package devices. Architecture Figure 12 illustrates the architecture of the timers.

Figure 12. Timer Block Diagram FFFFH, the timer rolls over to 0000H and continues counting.

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification out, first set the TPOL bit in the Timer Control 1 Register to the start value before begin- ning ONE-SHOT mode. Then, after starting the timer, set TPOL to the opposite bit value. The steps for configuring a timer for ONE-SHOT mode and initiating the count are as fol- lows: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for ONE-SHOT mode – Set the prescale value – If using the Timer Output alternate functio n, set the initial output level (High or Low) 2. Write to the Timer High and Low Byte registers to set the starting count value 3. Write to the Timer Reload High and Low Byte registers to set the Reload value 4. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function 6. Write to the Timer Control 1 register to enable the timer and initiate counting In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon timer Reload. The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for CONTINUOUS mode – Set the prescale value One-Shot Mode Time-Out Period (s) Reload Value Start Value–() Prescale×

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification – If using the Timer Output alternate functio n, set the initial output level (High or Low) 2. Write to the Timer High and Low Byte regist ers to set the starting count value (usually 0001H), affecting only the first pass in CONTINUOUS mode. After the first timer Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control 1 register to enable the timer and initiate counting. In CONTINUOUS mode, the system clock always provides the timer input. The timer period is given by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT mode equation must be used to determine the first time-out period. COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer Control 1 Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled. The input frequency of the Timer Input signal must not exceed one-fourth the system clock frequency. Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COUNTER mode and initiating the count are as fol- lows: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for COUNTER mode Continuous Mode Time-Out Period (s) Reload Value Prescale× Caution:

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification – Select either the rising edge or falling edge of the Timer Input signal for the count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function does not have to be enabled 2. Write to the Timer High and Low Byte regi sters to set the starting count value. This only affects the first pass in COUNTER mode. After the first timer Reload in COUNTER mode, counting always begins at the reset value of 0001H. Generally, in COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control 1 register to enable the timer. In COUNTER mode, the number of Timer Input transitions since the timer start is given by the following equation: PWM Mode In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16- bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control 1 register is set to 1, the Timer Output signal begins as a High (1) and then transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control 1 register is set to 0, the Timer Output signal begins as a Low (0) and then transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H. The steps for configuring a timer for PWM mode and initiating the PWM operation are as follows: Counter Mode Timer Input Transitions Current Count Value Start Value–=

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for PWM mode – Set the prescale value – Set the initial logic level (High or Lo w) and PWM High/Low transition for the Timer Output alternate function 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the Timer Reload High and Low By te registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. 5. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control 1 register to enable the timer and initiate counting. The PWM period is given by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the One-Shot mode equation must be used to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by: If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by: Capture Mode In CAPTURE mode, the current timer count value is recorded when the desired external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control 1 register determines if the Capture occurs on a rising edge or a falling edge of the PWM Period (s) Reload Value Prescale× PWM Output High Time Ratio (%) Reload Value PWM Value– PWM Output High Time Ratio (%) PWM Value

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt and continues counting. The steps for configuring a timer for CAPTURE mode and initiating the count are as fol- lows: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for CAPTURE mode. – Set the prescale value. – Set the Capture edge (rising or falling) for the Timer Input. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, then the interrupt was generated by a Reload. 5. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pi n for the Timer Input alternate function. 7. Write to the Timer Control 1 register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: Compare Mode In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon Com- pare. Capture Elapsed Time (s) Capture Value Start Value–() Prescale×

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. The steps for configuring a timer for COMPARE mode and initiating the count are as fol- lows: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for COMPARE mode – Set the prescale value – Set the initial logic level (High or Low) fo r the Timer Output alternate function, if desired 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control 1 register to enable the timer and initiate counting. In COMPARE mode, the system clock always provides the timer input. The Compare time is given by the following equation: GATED Mode In GATED mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control 1 register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset. Compare Mode Time (s) Compare Value Start Value–() Prescale×

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification The steps for configuring a timer for GATED mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for GATED mode – Set the prescale value 2. Write to the Timer High and Low Byte regi sters to set the starting count value. This only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. Write to the Timer Control 1 register to enable the timer. 7. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer Input transition. The desired transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control 1 Register. The timer input is the system clock. Every subsequent desired transition (after the first) of the Timer Input signal captures the current count value. The Capture value is written to the Timer PWM High and Low Byte Registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: – Disable the timer – Configure the timer for CAPTURE/COMPARE mode – Set the prescale value – Set the Capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H).

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. If desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. Write to the Timer Control 1 register to enable the timer. 7. Counting begins on the first appropriate transition of the Timer Input signal. No interrupt is generated by this first edge. In m/COMPARE mode, the elapsed time from timer start to Capture event can be calcu- lated using the following equation: Reading the Timer Count Values The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte reg- ister is read, the contents of the Timer Low Byte register are placed in a holding register. A subsequent read from the Timer Low Byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte register returns the actual value in the counter. Timer Output Signal Operation Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled every time the counter is reloaded. Timer Control Register Definitions Timers 0-2 are available in all packages. Timer 3 is only available in the 64-, 68-, and 80- pin packages. Timer 0-3 High and Low Byte Registers The Timer 0-3 High and Low Byte (TxH and TxL) registers (Tables 38 and 39) contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TMRL always returns this temporary register when the timers are enabled. When the timer is disabled, reads from the TMRL reads the register directly. Writing to the Timer High and Low Byte registers while the timer is enabled is not recom- mended. There are no temporary holding registers available for write operations, so simul- taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are Capture Elapsed Time (s) Capture Value Start Value–() Prescale×

Byte) at the next clock edge. The counter continues counting from the new value. Timer 3 is unavailable in the 40- and 44-pin packages. These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value. Table 38. Timer 0-3 High Byte Register (TxH)

two byte form the 16-bit Compare value. Table 40. Timer 0-3 Reload High Byte Register (TxRH) Table 41. Timer 0-3 Reload Low Byte Register (TxRL)

the Capture values for the Capture and Capture/COMPARE modes. operating in Capture or Capture/COMPARE modes. Table 42. Timer 0-3 PWM High Byte Register (TxPWMH) Table 43. Timer 0-3 PWM Low Byte Register (TxPWML)

0 = Timer Input signal comes from the pin. 1 = For Timer 0, Input signal is connected to Timer 3 output. For Timer 1, Input signal is connected to Timer 0 output. For Timer 2, Input signal is connected to Timer 1 output. For Timer 3, Input signal is connected to Timer 2 output. value, and determine the timer operating mode. Operation of this bit is a function of the current operating mode of the timer. Table 44. Timer 0-3 Control 0 Register (TxCTL0) Table 45. Timer 0-3 Control 1 Register (TxCTL1)

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification ONE-SHOT mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. PWM mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. CAPTURE mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. GATED mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal.

PS019910-0504 P r e l i m i n a r y Timers Z8 Encore!® 64K Series Product Specification PRES—Prescale value. The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the Timer is disabled. This insures proper clock division each time the Timer is restarted. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 TMODE—TIMER mode 000 = ONE-SHOT mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = CAPTURE/COMPARe mode

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Watch-Dog Timer Watch-Dog Timer Overview The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore!® into unsuitable operating states. The Watch-Dog Timer includes the following features:

• On-chip RC oscillator
• A selectable time-out response:
• WDT Time-out response: Reset or interrupt
• 24-bit programmable time-out value Operation The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the 64K Series devices when the WDT reaches its terminal count. The Watch-Dog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer has only two modes of operation—ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. An enable can be performed by executing the WDT instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the Watch-Dog Timer to operate all the time, even if a WDT instruction has not been executed. The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is given by the following equation: where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator frequency is 10kHz. The Watch-Dog Timer cannot be refreshed once it reaches 000002H. The WDT Reload Value must not be set to values below 000004H. Table 46 provides information on approximate time-out delays for the minimum and maximum WDT reload values. WDT Time-out Period (ms) WDT Reload Value

Timer Reload registers. Counting resumes following the reload operation. ter for information regarding programming of the WDT_RES Option Bit. Timer counter is not automatically returned to its Reload Value. Table 46. Watch-Dog Timer Approximate Time-Out Delays

PS019910-0504 P r e l i m i n a r y Watch-Dog Timer Z8 Encore!® 64K Series Product Specification the Reset and STOP Mode Recovery chapter for more information on STOP Mode Recovery. If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. WDT Reset in Normal Operation If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the device into the Reset state. The WDT status bit in the Watch-Dog Timer Control register is set to 1. Refer to the Reset and STOP Mode Recovery chapter for more information on Reset. WDT Reset in STOP Mode If enabled in STOP mode and configured to generate a Reset when a time-out occurs and the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the STOP bit in the Watch-Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to the Reset and STOP Mode Recovery chapter for more information. Default operation is for the WDT and its RC oscillator to be enabled during STOP mode. WDT RC Disable in STOP Mode To minimize power consumption in STOP Mode, the WDT and its RC oscillator can be disabled in STOP mode. The following sequence configures the WDT to be disabled when the 64K Series devices enter STOP Mode following execution of a STOP instruction: 1. Write 55H to the Watch-Dog Timer Control register (WDTCTL). 2. Write AAH to the Watch-Dog Timer Control register (WDTCTL). 3. Write 81H to the Watch-Dog Timer Control register (WDTCTL) to configure the WDT and its oscillator to be disabled during STOP Mode. Alternatively, write 00H to the Watch-Dog Timer Control register (WDTCTL) as the third step in this sequence to reconfigure the WDT and its oscillator to be enabled during STOP Mode. This sequence only affects WDT operation in STOP mode. Watch-Dog Timer Reload Unlock Sequence Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers. The follow sequence is required to unlock the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access.

1. Write 55H to the Watch-Dog Timer Control register (WDTCTL).
2. Write AAH to the Watch-Dog Timer Control register (WDTCTL).
3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU).
4. Write the Watch-Dog Timer Reload High Byte register (WDTH).
5. Write the Watch-Dog Timer Relo ad Low Byte register (WDTL).

locking mechanism prevents spurious writes to the Reload registers. Table 47. Watch-Dog Timer Control Register (WDTCTL)

PS019910-0504 P r e l i m i n a r y Watch-Dog Timer Z8 Encore!® 64K Series Product Specification POR—Power-On Reset Indicator If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time- out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read. STOP—STOP Mode Recovery Indicator If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP mode. Reading this register also resets this bit. WDT—Watch-Dog Timer Time-Out Indicator If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. EXT—External Reset Indicator If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this register resets this bit. Reserved These bits are reserved and must be 0. SM—STOP Mode Configuration Indicator 0 = Watch-Dog Timer and its internal RC oscillator will continue to operate in STOP Mode. 1 = Watch-Dog Timer and its internal RC oscillator will be disabled in STOP Mode. Watch-Dog Timer Reload Upper, High and Low Byte Registers The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg- isters (Tables 48 through 50) form the 24-bit reload value that is loaded into the Watch- Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the desired Reload Value. Read- ing from these registers returns the current Watch-Dog Timer count value. Reset or STOP Mode Recovery Event POR STOP WDT EXT Power-On Reset 1 0 0 0 Reset using RESET pin assertion 0 0 0 1 Reset using Watch-Dog Timer time-out 0 0 1 0 Reset using the On-Chip Debugger (OCDCTL[1] set to 1) 1 0 0 0 Reset from STOP Mode using DBG Pin driven Low 1 0 0 0 STOP Mode Recovery using GPIO pin transition 0 1 0 0 STOP Mode Recovery using Watch-Dog Timer time-out 0 1 1 0

Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value. Middle byte, Bits[15:8], of the 24-bit WDT reload value. Table 48. Watch-Dog Timer Reload Upper Byte Register (WDTU) R/W* - Read returns the current WDT count value. Write sets the desired Reload Value. Table 49. Watch-Dog Timer Reload High Byte Register (WDTH) R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.

Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value. Table 50. Watch-Dog Timer Reload Low Byte Register (WDTL) R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification UART Overview The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communica- tion channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include:

• 8-bit asynchronous data transfer
• Selectable even- and odd-parity generation and checking
• Option of one or two Stop bits
• Separate transmit and receive interrupts
• Framing, parity, overrun and break detection
• Separate transmit and receive enables
• 16-bit Baud Rate Generator (BRG)
• Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes
• Baud Rate Generator timer mode
• Driver Enable output for external bus transceivers Architecture The UART consists of three primary functional blocks: transmitter, receiver, and baud rate generator. The UART’s transmitter and receiver function independently, but employ the same baud rate and data format. Figure 13 illustrates the UART architecture.

begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits. out parity and with parity, respectively. Figure 13. UART Block Diagram

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification 101 – Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin. 5. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data. 6. Write the UART Control 1 register to select the outgoing address bit. 7. Set the MULTIPROCESSOR Bit Transmitter ( MPBT) if sending an address byte, clear it if sending a data byte. 8. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 9. If desired and MULTIPROCESSOR mode is enabled, make any changes to the MULTIPROCESSOR Bit Transmitter (MPBT) value. 10. To transmit additional bytes, return to Step 5. Transmitting Data using the Interrupt-Driven Method The UART transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow these steps to configure the UART for interrupt- driven data transmission: 1. Write to the UART Baud Rate High and Lo w Byte registers to set the desired baud rate. 2. Enable the UART pin functions by config uring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the desired priority. 5. If MULTIPROCESSOR mode is desired, wr ite to the UART Control 1 register to enable MULTIPROCESSOR (9-bit) mode functions. 6. Set the MULTIPROCESSOR Mode Select ( MPEN) to Enable MULTIPROCESSOR mode 7. Write to the UART Control 0 register to: – Set the transmit enable bit ( TEN) to enable the UART for data transmission – Enable parity, if desired and if multipro cessor mode is not enabled, and select either even or odd parity – Set or clear the CTSE bit to enable or disable control from the remote receiver via the CTS pin

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification 102 8. Execute an EI instruc tion to enable interrupts. The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write the UART Control 1 register to select the outgoing address bit: – Set the MULTIPROCESSOR Bit Transmitter ( MPBT) if sending an address byte, clear it if sending a data byte. 2. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 3. Clear the UART Transmit interrupt bit in th e applicable Interrupt Request register. 4. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data register to again become empty. Receiving Data using the Polled Method Follow these steps to configure the UART for polled data reception: 1. Write to the UART Baud Rate High and Lo w Byte registers to set the desired baud rate. 2. Enable the UART pin functions by config uring the associated GPIO Port pins for alternate function operation. 3. Write to the UART Control 1 register to enable Multiprocessor mode functions, if desired. 4. Write to the UART Control 0 register to: – Set the receive enable bit ( REN) to enable the UART for data reception – Enable parity, if desired and if multipro cessor mode is not enabled, and select either even or odd parity 5. Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 6. If the Receive Data register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data. 6. Read data from the UART Receive Data re gister. If operating in Multiprocessor (9-bit) mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0]. 7. Return to Step 5 to receive additional data.

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification 103 Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error con- ditions). Follow these steps to configure the UART receiver for interrupt-driven operation: 1. Write to the UART Baud Rate High and Lo w Byte registers to set the desired baud rate. 2. Enable the UART pin functions by config uring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the desired priority. 5. Clear the UART Receiver interrupt in th e applicable Interrupt Request register. 6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode functions, if desired. – Set the MULTIPROCESSOR Mode Select ( MPEN) to Enable Multiprocessor mode – Set the MULTIPROCESSOR Mode Bits, MPMD[1:0], to select the desired address matching scheme – Configure the UART to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a DMA block) 7. Write the device address to the Address Compare Register (automatic multiprocessor modes only). 8. Write to the UART Control 0 register to: – Set the receive enable bit ( REN) to enable the UART for data reception – Enable parity, if desired and if multipro cessor mode is not enabled, and select either even or odd parity 9. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Check the UART Status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. If the interrupt was caused by data ava ilable, read the data from the UART Receive Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0]. 3. Clear the UART Receiver interrupt in th e applicable Interrupt Request register.

1. Execute the IRET instruction to return fro m the interrupt-service routine and await

the middle of a character transmission, the current character is sent completely. Figure 16. UART Asynchronous MULTIPROCESSOR Mode Data Format

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification 105 on the multi-node network. The following three MULTIPROCESSOR modes are avail- able in hardware:

• Interrupt on all address bytes
• Interrupt on matched address bytes and correctly framed data bytes
• Interrupt only on correctly framed data bytes These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all MULTIPROCESSOR modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software clears MPMD[0]. At this point, each new incoming byte interrupts the CPU. The software is then responsible for determining the end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame is different from the UART’s address, then set MPMD[0] to 1 causing the UART interrupts to go inactive until the next address byte. If the new frame’s address matches the UART’s, the data in the new frame is processed as well. The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART’s address into the UART Address Compare Register. This mode introduces more hardware control, interrupting only on frames that match the UART’s address. When an incoming address byte does not match the UART’s address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an interrupt is issued and further interrupts now occur on each succesive data byte. The first data byte in the frame contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts continue sand the NEWFRM bit is set for the first byte of the new frame. If there is no match, then the UART ignores all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s address into the UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame is still accompanied by a NEWFRM assertion. External Driver Enable The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi-transceiver bus, such as RS-485. Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 17. The Driver Enable signal asserts when a byte is written to the UART Transmit Data register. The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the

polarity of the Driver Enable signal. Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) tion as a basic timer with interrupt capability. Transmit Data register clears the TDRE bit to 0.

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification 107 Receiver Interrupts The receiver generates an interrupt when any of the following occurs:

• A data byte has been received and is available in the UART Receive Data register. This interrupt can be disabled independent of the other receiver interrupt sources. The received data interrupt occurs once the receive character has been received and placed in the Receive Data register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error. Note that in multiprocessor mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte.
• A break is received
• An overrun is detected
• A data framing error is detected UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and should be ignored. The BRKD bit indi- cates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received. UART Data and Error Handling Procedure Figure 18 illustrates the recommended procedure for use in UART receiver interrupt ser- vice routines.

Figure 18. UART Receiver Interrupt Service Routine Flow Generator to function as an additional counter if the UART functionality is not employed.

1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
2. Load the desired 16-bit co unt value into the UART Baud Rate High and Low Byte
3. Enable the Baud Rate Generator timer fu nction and associated interrupt by setting the

BRGCTL bit in the UART Control 1 register to 1. Decoder chapter on page 119. with the Read-only UART Receive Data register. UART transmitter data byte to be shifted out through the TXDx pin. Table 51. UART Transmit Data Register (UxTXD)

with the Write-only UART Transmit Data register. operating configuration and status. UART Receive Data register clears this bit. 0 = The UART Receive Data register is empty. 1 = There is a byte in the UART Receive Data register. Table 52. UART Receive Data Register (UxRXD) Table 53. UART Status 0 Register (UxSTAT0)

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification 111 0 = No parity error occurred. 1 = A parity error occurred. OE—Overrun Error This bit indicates that an overrun error has occurred. An overrun occurs when new data is received and the UART Receive Data register has not been read. If the RDA bit is reset to 0, then reading the UART Receive Data register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. FE—Framing Error This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data register clears this bit. 0 = No framing error occurred. 1 = A framing error occurred. BRKD—Break Detect This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data register clears this bit. 0 = No break occurred. 1 = A break occurred. TDRE—Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data. Writing to the UART Transmit Data register resets this bit. 0 = Do not write to the UART Transmit Data register. 1 = The UART Transmit Data register is ready to receive an additional byte to be transmit- ted. TXE—Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is fin- ished. 0 = Data is currently transmitting. 1 = Transmission is complete. CTS—CTS signal When this bit is read it returns the level of the CTS signal.

Data register resets this bit to 0. 0 = The current byte is not the first data byte of a new frame. 1 = The current byte is the first data byte of a new frame. Data register resets this bit to 0. been written while the UART is enabled. This register contains multiprocessor control and status bits. Table 54. UART Status 1 Register (UxSTAT1) Table 55. UART Control 0 Register (UxCTL0)

This bit enables or disables the receiver. 0 = The CTS signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. progress, so ensure that the transmitter has finished sending data before setting this bit. 1 = The output of the transmitter is zero. 0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits. 1 = All transmitted data is looped back to the receiver. Table 56. UART Control 1 Register (UxCTL1)

PS019910-0504 P r e l i m i n a r y UART Z8 Encore!® 64K Series Product Specification 114 MPMD[1:0]—MULTIPROCESSOR Mode If MULTIPROCESSOR (9-bit) mode is enabled, 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. 10 = The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an address mismatch occurs. 11 = The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register. MPEN—MULTIPROCESSOR (9-bit) Enable This bit is used to enable MULTIPROCESSOR (9-bit) mode. 0 = Disable MULTIPROCESSOR (9-bit) mode. 1 = Enable MULTIPROCESSOR (9-bit) mode. MPBT—MULTIPROCESSOR Bit Transmit This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. 0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit). 1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit). DEPOL—Driver Enable Polarity 0 = DE signal is Active High. 1 = DE signal is Active Low. BRGCTL—Baud Rate Control This bit causes different UART behavior depending on whether the UART receiver is enabled (REN = 1 in the UART Control 0 Register). When the UART receiver is not enabled, this bit determines whether the Baud Rate Gener- ator issues interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low Byte is read. RDAIRQ—Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Con- troller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request.

0 = Infrared Encoder/Decoder is disabled. UART operates normally operation. the Infrared Encoder/Decoder. interrupts and RDA assertions only occur in the event of a match. This 8-bit value is compared to the incoming address bytes. Table 57. UART Address Compare Register (UxADDR) Table 58. UART Baud Rate High Byte Register (UxBRH)

For reliable communication, the UART baud rate error must never exceed 5 percent. used crystal oscillator frequencies. Table 59. UART Baud Rate Low Byte Register (UxBRL) Table 60. UART Baud Rates

Table 60. UART Baud Rates (Continued)

PS019910-0504 P r e l i m i n a r y Infrared Encoder/Decoder Z8 Encore!® 64K Series Product Specification 120 Operation When the Infrared Endec is enabled, the transmit data from the associated on-chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infra- red transceiver via the TXD pin. Likewise, data received from the infrared transceiver is passed to the Infrared Endec via the RXD pin, decoded by the Infrared Endec, and then passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared Endec data rate is calculated using the following equation: Transmitting IrDA Data The data to be transmitted using the infrared transceiver is first sent to the UART. The UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is output to complete the full 16-clock data period. Figure 20 illustrates IrDA data transmis- sion. When the Infrared Endec is enabled, the UART’s TXD signal is internal to the 64K Series products while the IR_TXD signal is output through the TXD pin. Infrared Data Rate (bits/s) System Clock Frequency (Hz)

Figure 20. Infrared Data Transmission Series products while the IR_RXD signal is received through the RXD pin.

Figure 21. Infrared Data Reception ception of the 1.6µs minimum width pulses allowed by the IrDA standard. reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the Endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchronized to the incoming data stream when a Start bit is received.

PS019910-0504 P r e l i m i n a r y Infrared Encoder/Decoder Z8 Encore!® 64K Series Product Specification 123 Infrared Encoder/Decoder Control Register Definitions All Infrared Endec configuration and status information is set by the UART control regis- ters as defined beginning on page 109. To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART x Control 1 register to 1 to enable the Infrared Encoder/ Decoder before enabling the GPIO Port alte rnate function for the corre- sponding pin. Caution:

• Full-duplex, synchronous, character-oriented communication
• Four-wire interface
• Data transfers rates up to a maximum of one-half the system clock frequency
• Error detection
• Dedicated Baud Rate Generator Architecture The SPI may be configured as either a Master (in single or multi-master systems) or a Slave as illustrated in Figures 22 through 24.

Figure 22. SPI Configured as a Master in a Single Master, Single Slave System

PS019910-0504 P r e l i m i n a r y Serial Peripheral Interface Z8 Encore!® 64K Series Product Specification 126 During an SPI transfer, data is sent and received simultaneously by both the Master and the Slave SPI devices. Separate signals are required for data and the serial clock. When an SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register in the Master and another 8-bit shift register in the Slave are connected as a circular buffer. The SPI shift register is single-buffered in the transmit and receive directions. New data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read. SPI Signals The four basic SPI signals are:

• MISO (Master-In, Slave-Out)
• MOSI (Master-Out, Slave-In)
• SCK (SPI Serial Clock)
• SS (Slave Select) The following paragraphs discuss these SPI signals. Each signal is described in both Mas- ter and Slave modes. Master-In, Slave-Out The Master-In, Slave-Out (MISO) pin is configured as an input in a Master device and as an output in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance state if the Slave is not selected. When the SPI is not enabled, this signal is in a high- impedance state. Master-Out, Slave-In The Master-Out, Slave-In (MOSI) pin is configured as an output in a Master device and as an input in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance state. Serial Clock The Serial Clock (SCK) synchronizes data movement both in and out of the device through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator cre- ates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave’s SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock sig- nal from the Master synchronizes the data transfer between the Master and Slave devices. Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times the system (XIN) clock period.

sequence of NUMBITS clock cycles (refer to NUMBITS field in the SPIMODE register). of multiple characters or may deassert between each character. employed to select external SPI Slave devices. Table 61. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation

Figure 26. SPI Timing When PHASE is 1

PS019910-0504 P r e l i m i n a r y Serial Peripheral Interface Z8 Encore!® 64K Series Product Specification 130 ister. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUMBITS field in the SPIMODE register must be set to be consistent with the other SPI devices. The STR bit in the SPICTL register may be used if desired to force a “startup” interrupt. The BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register are not used in slave mode. The SPI baud rate generator is not used in slave mode so the SPIBRH and SPIBRL registers need not be initialized. If the slave has data to send to the master, the data must be written to the SPIDAT register before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT regis- ter is not written prior to the slave transaction, the MISO pin outputs whatever value is currently in the SPIDAT register. Due to the delay resulting from synchronization of the SPI input signals to the internal sys- tem clock, the maximum SPICLK baud rate that can be supported in slave mode is the sys- tem clock frequency (XIN) divided by 8. This rate is controlled by the SPI master. Error Detection The SPI contains error detection logic to support SPI communication protocols and recog- nize when communication errors have occurred. The SPI Status register indicates when a data transmission error has been detected. Overrun (Write Collision) An overrun error (write collision) indicates a write to the SPI Data register was attempted while a data transfer is in progress (in either master or slave modes). An overrun sets the OVR bit in the SPI Status register to 1. Writing a 1 to OVR clears this error flag. The data register is not altered when a write occurs while data transfer is in progress. Mode Fault (Multi-Master Collision) A mode fault indicates when more than one Master is trying to communicate at the same time (a multi-master collision). The mode fault is detected when the enabled Master’s SS pin is asserted. A mode fault sets the COL bit in the SPI Status register to 1. Writing a 1 to COL clears this error flag. Slave Mode Abort In slave mode of operation if the SS pin deasserts before all bits in a character have been transferred, the transaction is aborted. When this condition occurs the ABT bit is set in the SPISTAT register as well as the IRQ bit (indicating the transaction is complete). The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous trans- action left off. Writing a 1 to ABT clears this error flag. SPI Interrupts When SPI interrupts are enabled, the SPI generates an interrupt after character transmis- sion/reception completes in both master and slave modes. A character can be defined to be

PS019910-0504 P r e l i m i n a r y Serial Peripheral Interface Z8 Encore!® 64K Series Product Specification 131 1 through 8 bits by the NUMBITS field in the SPI Mode register. In slave mode it is not necessary for SS to deassert between characters to generate the interrupt. The SPI in Slave mode can also generate an interrupt if the SS signal deasserts prior to transfer of all the bits in a character (see description of slave abort error above). Writing a 1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts. To start the transfer pro- cess, an SPI interrupt may be forced by software writing a 1 to the STR bit in the SPICTL register. If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator time- out. This timer function must be enabled by setting the BIRQ bit in the SPICTL register. This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT register, just the SPI interrupt bit in the interrupt controller. SPI Baud Rate Generator In SPI Master mode, the Baud Rate Generator creates a lower frequency serial clock (SCK) for data transmission synchronization between the Master and the external Slave. The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud rate is calculated using the following equation: Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value of (2 X 65536 = 131072). When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0. 2. Load the desired 16-bit co unt value into the SPI Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer fu nction and associated interrupt by setting the BIRQ bit in the SPI Control register to 1. SPI Control Register Definitions SPI Data Register The SPI Data register (Table 62) stores both the outgoing (transmit) data and the incoming (receive) data. Reads from the SPI Data register always return the current contents of the SPI Baud Rate (bits/s) System Clock Frequency (Hz)

are ignored and the Overrun error flag, OVR, is set in the SPI Status register. ten to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0]. Transmit and/or receive data. The SPI Control register (Table 63) configures the SPI for transmit and receive operations. Table 62. SPI Data Register (SPIDATA)

0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller. 1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller. IRQ bit in the SPI Status register clears this bit to 0. 0 = The Baud Rate Generator timer function is disabled. 1 = The Baud Rate Generator timer function and time-out interrupt are enabled. Polarity Control section for more information on operation of the PHASE bit. 0 = SPI signal pins not configured for open-drain. , MISO, MOSI) configured for open-drain function. This setting is typically used for multi-master and/or multi-slave configurations. 0 = SPI configured in Slave mode. 1 = SPI configured in Master mode. Table 63. SPI Control Register (SPICTL)

their reset state if the SPIEN bit in the SPICTL register = 0. Rate Generator is used as a timer to generate the SPI interrupt. 0 = No SPI interrupt request pending. 1 = SPI interrupt request is pending. 0 = An overrun error has not occurred. 1 = An overrun error has been detected. 0 = A multi-master collision (mode fault) has not occurred. 1 = A multi-master collision (mode fault) has been detected. 0 = A slave mode transaction abort has not occurred. 1 = A slave mode transaction abort has been detected. 0 = No data transmission currently in progress. 1 = Data transmission currently in progress. Table 64. SPI Status Register (SPISTAT) R/W* = Read access. Write a 1 to clear the bit to 0.

1 = SS input is not asserted (High). If SPI enabled as a Master, this bit is not applicable. read using the SPIBRH and SPIBRL register locations. Low byte values are not buffered. Exercise caution if reading the values while the BRG is counting. Table 65. SPI Mode Register (SPIMODE)

0 = SS pin configured as an input. 1 = SS pin configured as an output (Master mode only). This bit has no effect if SSIO = 0 or SPI configured as a Slave. is a read only register used for SPI diagnostics. 0 = The internal Transmit Clock Enable signal is deasserted. data out is updated on the next system clock (MOSI or MISO). Defines the current state of the internal SPI State Machine. Table 66. SPI Diagnostic State Register (SPIDST)

Most significant byte, BRG[15:8], of the SPI Baud Rate Generator’s reload value. Least significant byte, BRG[7:0], of the SPI Baud Rate Generator’s reload value. Table 67. SPI Baud Rate High Byte Register (SPIBRH) Table 68. SPI Baud Rate Low Byte Register (SPIBRL)

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y I2C Controller 138 I2C Controller Overview The I2C Controller makes the 64K Series products bus-compatible with the I2CTM proto- col. The I2C Controller consists of two bidirectional bus lines—a serial data signal (SDA) and a serial clock signal (SCL). Features of the I2C Controller include:

• Transmit and Receive Operation in MASTER mode
• Maximum data rate of 400kbit/sec
• 7- and 10-bit addressing modes for Slaves
• Unrestricted number of data bytes transmitted per transfer The I2C Controller in the 64K Series products does not operate in Slave mode.

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 140

• Master receives from a 7-bit slave
• Master receives from a 10-bit slave SDA and SCL Signals I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin alternate functions are selected for their respective GPIO ports, the pins are automatically configured for open-drain operation. The master (I2C) is responsible for driving the SCL clock signal, although the clock signal can become skewed by a slow slave device. During the low period of the clock, the slave pulls the SCL signal Low to suspend the transaction. The master releases the clock at the end of the low period and notices that the clock remains low instead of returning to a high level. When the slave releases the clock, the I2C Controller continues the transaction. All data is transferred in bytes and there is no limit to the amount of data transferred in one operation. When transmitting data or acknowledging read data from the slave, the SDA signal changes in the middle of the low period of SCL and is sampled in the middle of the high period of SCL. I2C Interrupts The I2C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowl- edge and baud rate generator. These four interrupt sources are combined into a single interrupt request signal to the Interrupt Controller. The Transmit interrupt is enabled by the IEN and TXI bits of the Control register. The Receive and Not Acknowledge interrupts are enabled by the IEN bit of the Control register. The baud rate generator interrupt is enabled by the BIRQ and IEN bits of the Control register. Not Acknowledge interrupts occur when a Not Acknowledge condition is received from the slave or sent by the I2C Controller and neither the START or STOP bit is set. The Not Acknowledge event sets the NCKI bit of the I2C Status register and can only be cleared by setting the START or STOP bit in the I2C Control register. When this interrupt occurs, the I2C Controller waits until either the STOP or START bit is set before performing any action. In an interrupt service routine, the NCKI bit should always be checked prior to ser- vicing transmit or receive interrupt conditions because it indicates the transaction is being terminated. Receive interrupts occur when a byte of data has been received by the I2C Controller (master reading data from slave). This procedure sets the RDRF bit of the I2C Status regis- ter. The RDRF bit is cleared by reading the I2C Data register. The RDRF bit is set during the acknowledge phase. The I2C Controller pauses after the acknowledge phase until the receive interrupt is cleared before performing any other action.

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 141 Transmit interrupts occur when the TDRE bit of the I2C Status register sets and the TXI bit in the I2C Control register is set. Transmit interrupts occur under the following condi- tions when the transmit data register is empty:

• The I2C Controller is enabled
• The first bit of the byte of an address is shifting out and the RD bit of the I2C Status register is deasserted.
• The first bit of a 10-bit address shifts out.
• The first bit of write data shifts out. Writing to the I2C Data register always clears the TRDE bit to 0. When TDRE is asserted, the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently shifting out until the Data register is written with the next value to send or the STOP or START bits are set indicating the current byte is the last one to send. The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled (IEN bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an inter- rupt is generated when the baud rate generator counts down to 1. This allows the I2C baud rate generator to be used by software as a general purpose timer when IEN = 0. Software Control of I2C Transactions Software can control I2C transactions by using the I2C Controller interrupt, by polling the I2C Status register or by DMA. Note that not all products include a DMA Controller. To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller. The TXI bit in the I2C Control register must be set to enable transmit interrupts. To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I2C Status register should be polled. The TDRE bit asserts regardless of the state of the TXI bit. Either or both transmit and receive data movement can be controlled by the DMA Control- ler. The DMA Controller channel(s) must be initialized to select the I2C transmit and receive requests. Transmit DMA requests require that the TXI bit in the I2C Control regis- ter be set. A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge before the last byte h as been sent. After receiving the Not Acknowledge, the I2C Controller sets the NCKI bit in the Status register and pauses until either the STOP or START bits in the Control register are set. Note: Caution:

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 142 In order for a receive (read) DMA transaction to send a Not Acknowledge on the last byte, the receive DMA must be set up to receive n-1 bytes, then software must set the NAK bit and receive the last (nth) byte directly. Start and Stop Conditions The master (I2C) drives all Start and Stop signals and initiates all transactions. To start a transaction, the I2C Controller generates a START condition by pulling the SDA signal Low while SCL is High. To complete a transaction, the I2C Controller generates a Stop condition by creating a low-to-high transition of the SDA signal while the SCL signal is high. The START and STOP bits in the I2C Control register control the sending of the Start and Stop conditions. A master is also allowed to end one transaction and begin a new one by issuing a Restart. This is accomplished by setting the START bit at the end of a transaction, rather than the STOP bit. Note that the Start condition not sent until the START bit is set and data has been written to the I2C Data register. Master Write and Read Transactions The following sections provide a recommended procedure for performing I2C write and read transactions from the I2C Controller (master) to slave I2C devices. In general soft- ware should rely on the TDRE, RDRF and NCKI bits of the status register (these bits gen- erate interrupts) to initiate software actions. When using interrupts or DMA, the TXI bit is set to start each transaction and cleared at the end of each transaction to eliminate a “trail- ing” Transmit interrupt. Caution should be used in using the ACK status bit within a transaction because it is diffi- cult for software to tell when it is updated by hardware. When writing data to a slave, the I2C pauses at the beginning of the Acknowledge cycle if the data register has not been written with the next value to be sent (TDRE bit in the I2C Status register = 1). In this scenario where software is not keeping up with the I2C bus (TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is delayed until the Data register is written with byte n + 1, and appears to be grouped with the data clock cycles for byte n+1. If either the START or STOP bit is set, the I2C does not pause prior to the Acknowledge cycle because no additional data is sent. When a Not Acknowledge condition is received during a write (either during the address or data phases), the I2C Controller generates the Not Acknowledge interrupt (NCKI = 1) and pause until either the STOP or START bit is set. Unless the Not Acknowledge was received on the last byte, the Data register will already have been written with the next address or data byte to send. In this case the FLUSH bit of the Control register should be set at the same time the STOP or START bit is set to remove the stale transmit data and enable subsequent Transmit interrupts. When reading data from the slave, the I2C pauses after the data Acknowledge cycle until the receive interrupt is serviced and the RDRF bit of the status register is cleared by read-

Acknowledge, the transaction can be repeated until the slave does Acknowledge. Figure 28. 7-Bit Address Only Transaction Format

1. Software asserts the IEN bit in the I2C Control register.
2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts.
3. The I 2C interrupt asserts, because the I2C Data register is empty (TDRE = 1)
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
5. Software sets the START and STOP bits of the I 2C Control register and clears the TXI
6. The I 2C Controller sends the START condition to the I2C slave.
7. The I 2C Controller loads the I2C Shift register with the contents of the I2C Data
8. Software polls the STOP bit of the I2C Co ntrol register. Hardware deasserts the STOP

bit when the address only transaction is completed.

1. Software checks the ACK bit of the I2C Status register. If the slave acknowledged,

interrupt does not occur in the not acknowledge case because the STOP bit was set.

1. The I 2C Controller shifts the data out of using the SDA signal. After the first bit is

sent, the Transmit interrupt is asserted.

1. If more bytes remain to be sent, return to step 9.
2. Software responds by setting the STOP bit of the I2C Control register (or START bit

Control register at the same time.

1. The I 2C Controller completes transmission of the data on the SDA signal.
2. The slave may either Acknowledge or Not Acknowledge the last byte. Because either

the STOP or START bit is already set, the NCKI interrupt does not occur.

1. The I 2C Controller sends the STOP (or RESTART) condition to the I2C bus. The

STOP or START bit is cleared. Figure 30. 10-Bit Address Only Transaction Format

1. Software asserts the IEN bit in the I2C Control register.
2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts.
3. The I 2C interrupt asserts, because the I2C Data register is empty (TDRE = 1)
4. Software responds to the TDRE interrupt by writing the first slave address byte. The

least-significant bit must be 0 for the write operation.

1. Software asserts the START bit of the I 2C Control register.
2. The I 2C Controller sends the START condition to the I2C slave.

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 147 The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the read/write control bit (=0). The transmit operation is carried out in the same manner as 7- bit addressing. The procedure for a transmit operation on a 10-bit addressed slave is as follows: 1. Software asserts the IEN bit in the I2C Control register. 2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. 3. The I 2C interrupt asserts because the I2C Data register is empty. 4. Software responds to the TDRE interrupt by writing the first slave address byte to the I2C Data register. The least-significant bit must be 0 for the write operation. 5. Software asserts the START bit of the I 2C Control register. 6. The I 2C Controller sends the START condition to the I2C slave. 7. The I 2C Controller loads the I2C Shift register with the contents of the I2C Data register. 8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is asserted. 9. Software responds by writing the second byte of address into the contents of the I2C Data register. 10. The I 2C Controller shifts the rest of the first byte of address and write bit out the SDA signal. 11. If the I 2C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 12. If the slave does not acknowledge the first address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 12. The I 2C Controller loads the I2C Shift register with the contents of the I2C Data register. 13. The I 2C Controller shifts the second address byte out the SDA signal. After the first bit has been sent, the Transmit interrupt is asserted. 14. Software responds by writing a data byte to the I 2C Data register. 15. The I 2C Controller completes shifting the contents of the shift register on the SDA signal.

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 150 1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C Data register. 2. Software asserts the START and TXI bits of the I2C Control register. 3. The I 2C Controller sends the Start condition. 4. The I 2C Controller loads the I2C Shift register with the contents of the I2C Data register. 5. After the first bit has been shifted out, a Transmit interrupt is asserted. 6. Software responds by writing the lowe r eight bits of address to the I2C Data register. 7. The I 2C Controller completes shifting of the two address bits and a 0 (write). 8. If the I 2C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 9. If the slave does not acknowledge the first address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore following steps). 9. The I 2C Controller loads the I2C Shift register with the contents of the I2C Data register (second address byte). 10. The I 2C Controller shifts out the second address byte. After the first bit is shifted, the I2C Controller generates a Transmit interrupt. 11. Software responds by setting the START bit of the I2C Control register to generate a repeated START and by clearing the TXI bit. 12. Software responds by writing 11110B followed by the 2-bit slave address and a 1 (read) to the I2C Data register. 13. If only one byte is to be read , software sets the NAK bit of the I2C Control register. 14. After the I 2C Controller shifts out the 2nd address byte, the I2C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL, the I 2C Controller sets the ACK bit in the I2C Status register. Continue with step 15. If the slave does not acknowledge the second address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 15. The I 2C Controller sends the repeated START condition.

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 151 16. The I 2C Controller loads the I2C Shift register with the contents of the I2C Data register (third address transfer). 17. The I 2C Controller sends 11110B followed by the two most significant bits of the slave read address and a 1 (read). 18. The I 2C slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL If the slave were to Not Acknowledge at this point (this should not happen because the slave did acknowledge the first two address bytes), software would respond by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 19. The I 2C Controller shifts in a byte of data from the I2C slave on the SDA signal. The I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last byte), else it sends an Acknowledge. 20. The I 2C Controller asserts the Receive interrupt (RDRF bit set in the Status register). 21. Software responds by reading the I2C Data register which clears the RDRF bit. If there is only one more byte to receive, set the NAK bit of the I2C Control register. 22. If there are one or more bytes to transfer, return to step 19. 23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C Controller. 24. Software responds by setting the STOP bit of the I2C Control register. 25. A STOP condition is sent to the I 2C slave and the STOP and NCKI bits are cleared. I2C Control Register Definitions I2C Data Register The I2C Data register (Table 69) holds the data that is to be loaded into the I2C Shift regis- ter during a write to a slave. This register also holds data that is loaded from the I2C Shift

File address space, but is used only to buffer incoming and outgoing data. The Read-only I2C Status register (Table 70) indicates the status of the I2C Controller. When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty. the RD bit is set. This bit is cleared by writing to the I2CDATA register. byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt. cution of the On-Chip Debugger’s Read Register command). This bit indicates the status of the Acknowledge for the last byte transmitted or received. Table 69. I2C Data Register (I2CDATA) Table 70. I2C Status Register (I2CSTAT)

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 153 last byte transmitted or received. It is not reset at the beginning of each transaction and is not reset when this register is read. Software must be cautious in making de cisions based on this bit within a transaction because software cannot te ll when the bit is updated by hard- ware. In the case of write transactions, the I2C pauses at the beginning of the Acknowledge cycle if the next tr ansmit data or address byte has not been written (TDRE = 1) and STOP and START = 0. In this case the ACK bit is not updated until the transmit interrupt is serviced and the Acknowl- edge cycle for the previous byte completes. Refer to Address Only Trans- action with a 7-bit Address on page 143 and Address Only Transaction with a 10-bit Address on page 145 for examples of how the ACK bit can be used. 10B—10-Bit Address This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit is set, if the five most-significant bits of the address are 11110B, this bit is set. When set, it is reset once the first byte of the address has been sent. RD—Read This bit indicates the direction of transfer of the data. It is active high during a read. The status of this bit is determined by the least-significant bit of the I 2C Shift register after the START bit is set. TAS—Transmit Address State This bit is active high while the address is being shifted out of the I2C Shift register. DSS—Data Shift State This bit is active high while data is being shifted to or from the I2C Shift register. NCKI—NACK Interrupt This bit is set high when a Not Acknowledge condition is received or sent and neither the START nor the STOP bit is active. When set, this bit generates an interrupt that can only be cleared by setting the START or STOP bit, allowing the user to specify whether he wants to perform a STOP or a repeated START. Caution:

The I2C Control register (Table 71) enables the I2C operation. 1 = The I2C transmitter and receiver are enabled. 0 = The I2C transmitter and receiver are disabled. dition is sent before the sending the START condition. ler is disabled. This bit is ignored when the I2C Controller is enabled. 1 = An interrupt occurs every time the baud rate generator counts down to one. 0 = No baud rate generator interrupt occurs. This bit enables the transmit interrupt when the I2C Data register is empty (TDRE = 1). 1 = Transmit interrupt (and DMA transmit request) is enabled. 0 = Transmit interrupt (and DMA transmit request) is disabled. Table 71. I2C Control Register (I2CCTL)

bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register. data has been sent to the I2C Data register. Reading this bit always returns 0. a 3-system clock cycle latency on the inputs. 1 = low-pass filters are enabled. 0 = low-pass filters are disabled. Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value. Table 72. I2C Baud Rate High Byte Register (I2CBRH)

register returns the current value of the I2C Baud Rate Counter[15:8]. Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value. register returns the current value of the I2C Baud Rate Counter[7:0]. Table 73. I2C Baud Rate Low Byte Register (I2CBRL)

is a read only register used for I2C diagnostics and manufacturing test. Table 74. I2C Diagnostic State Register (I2CDST)

PS019910-0504 P r e l i m i n a r y I2C Controller Z8 Encore!® 64K Series Product Specification 158 0_1111 10-bit address: Bit 0 (Least significant bit) of 2nd address byte 7-bit address: Bit 0 (Least significant bit) (R/W) of address byte 1_0000 10-bit addressing: Bit 7 (Most si gnificant bit) of 1st address byte 1_0001 10-bit addressing: Bit 6 of 1st address byte 1_0010 10-bit addressing: Bit 5 of 1st address byte 1_0011 10-bit addressing: Bit 4 of 1st address byte 1_0100 10-bit addressing: Bit 3 of 1st address byte 1_0101 10-bit addressing: Bit 2 of 1st address byte 1_0110 10-bit addressing: Bit 1 of 1st address byte 1_0111 10-bit addressing: Bit 0 (R/W) of 1st address byte 1_1000 10-bit addressing: Acknowle dge state for 1st address byte 1_1001 10-bit addressing: Bit 7 of 2nd address byte 7-bit addressing: Bit 7 of address byte 1_1010 10-bit addressing: Bit 6 of 2nd address byte 7-bit addressing: Bit 6 of address byte 1_1011 10-bit addressing: Bit 5 of 2nd address byte 7-bit addressing: Bit 5 of address byte 1_1100 10-bit addressing: Bit 4 of 2nd address byte 7-bit addressing: Bit 4 of address byte 1_1101 10-bit addressing: Bit 3 of 2nd address byte 7-bit addressing: Bit 3 of address byte 1_1110 10-bit addressing: Bit 2 of 2nd address byte 7-bit addressing: Bit 2 of address byte 1_1111 10-bit addressing: Bit 1 of 2nd address byte 7-bit addressing: Bit 1 of address byte TXRXSTATE State Description

ter is a read/write register used for I2C diagnostics. Table 75. I2C Diagnostic Control Register (I2CDIAG)

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Direct Memory Access Controller 160 Direct Memory Access Controller Overview The 64K Series Direct Memory Access (DMA) Controller provides three independent Direct Memory Access channels. Two of the channels (DMA0 and DMA1) transfer data between the on-chip peripherals and the Register File. The third channel (DMA_ADC) controls the Analog-to-Digital Converter (ADC) operation and transfers SINGLE-SHOT mode ADC output data to the Register File. Operation DMA0 and DMA1 Operation DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip peripheral control registers to the Register File, or from the Register File to the on-chip peripheral control registers. The sequence of operations in a DMAx data transfer is: 1. DMA x trigger source requests a DMA data transfer. 2. DMA x requests control of the system bus (address and data) from the eZ8 CPU. 3. After the eZ8 CPU acknowled ges the bus request, DMAx transfers either a single byte or a two-byte word (depending upon configuration) and then returns system bus control back to the eZ8 CPU. 4. If Current Address equals End Address: –D M A x reloads the original Start Address – If configured to gene rate an interrupt, DMAx sends an interrupt request to the Interrupt Controller – If configured for single-pass operation, DMA x resets the DEN bit in the DMAx Control register to 0 and the DMA is disabled. If Current Address does not equal End Address, the Current Address increments by 1 (single-byte transfer) or 2 (two-byte word transfer).

PS019910-0504 P r e l i m i n a r y Direct Memory Access Controller Z8 Encore!® 64K Series Product Specification 161 Configuring DMA0 and DMA1 for Data Transfer Follow these steps to configure and enable DMA0 or DMA1: 1. Write to the DMA x I/O Address register to set the Register File address identifying the on-chip peripheral control register. The upper nibble of the 12-bit address for on-chip peripheral control registers is always FH. The full address is {FH, DMAx_IO[7:0]} 2. Determine the 12-bit Start and End Register File addresses. The 12-bit Start Address is given by {DMAx_H[3:0], DMA_START[7:0]}. The 12-bit End Address is given by {DMAx_H[7:4], DMA_END[7:0]}. 3. Write the Start and End Register F ile address high nibbles to the DMAx End/Start Address High Nibble register. 4. Write the lower byte of the Start Address to the DMA x Start/Current Address register. 5. Write the lower byte of the End Address to the DMA x End Address register. 6. Write to the DMA x Control register to complete the following: – Select loop or single-pass mode operation – Select the data transfer direction (eithe r from the Register File RAM to the on- chip peripheral control register; or from the on-chip peripheral control register to the Register File RAM) – Enable the DMA x interrupt request, if desired – Select Word or Byte mode – Select the DMA x request trigger – Enable the DMA x channel DMA_ADC Operation DMA_ADC transfers data from the ADC to the Register File. The sequence of operations in a DMA_ADC data transfer is: 1. ADC completes conversion on the current ADC input channel and signals the DMA controller that two-bytes of ADC data are ready for transfer. 2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU. 3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte ADC output value to the Register File and then returns system bus control back to the eZ8 CPU. 4. If the current ADC Analog Input is the highest numbered input to be converted: – DMA_ADC resets the ADC Analog Input number to 0 and initiates data conversion on ADC Analog Input 0. – If configured to genera te an interrupt, DMA_ADC sends an interrupt request to the Interrupt Controller

PS019910-0504 P r e l i m i n a r y Direct Memory Access Controller Z8 Encore!® 64K Series Product Specification 162 If the current ADC Analog Input is not the highest numbered input to be converted, DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input. Configuring DMA_ADC for Data Transfer Follow these steps to configure and enable DMA_ADC: 1. Write the DMA_ADC Address register with th e 7 most-significant bits of the Register File address for data transfers. 2. Write to the DMA_ADC Control register to complete the following: – Enable the DMA_ADC interrupt request, if desired – Select the number of ADC Analog Inputs to convert – Enable the DMA_ADC channel When using the DMA_ADC to perform conversions on multiple ADC in- puts, the Analog-to-Dig ital Converter must be configured for SINGLE- SHOT mode. If the ADC_IN field in the DMA_ADC Control Register is greater than 000b, the ADC must be in SINGLE-SHOT mode. CONTINUOUS mode operation of the ADC can only be used in conjunc- tion with DMA_ADC if the ADC_IN field in the DMA_ADC Control Register is reset to 000b to enable conversion on ADC Analog Input 0 only. DMA Control Register Definitions DMAx Control Register The DMAx Control register (Table 76) enables and selects the mode of operation for DMAx. Caution:

0 = DMAx is disabled and data transfer requests are disregarded. 0 = Register File → on-chip peripheral control register. 1 = on-chip peripheral control register → Register File. 0 = DMAx does not generate any interrupts. 1 = DMAx generates an interrupt when the End Address data is transferred. 0 = DMAx transfers a single byte per request. control register must be an even address. enabled within the Request Trigger Source block. Control register: UART0 Transmit Data register empty. Table 76. DMAx Control Register (DMAxCTL)

Control register: UART1 Transmit Data register empty. mitter Interrupt register empty. O Address register must contain an even numbered address. File Page FH (addresses F00H to FFFH). the Start/Current and End Addresses of DMAx. Table 77. DMAx I/O Address Register (DMAxIO) Table 78. DMAx Address High Nibble Register (DMAxH)

These bits, used with the DMAx End Address Low register, form a 12-bit End Address. The full 12-bit address is given by {DMA_END_H[3:0], DMA_END[7:0]}. address. The full 12-bit address is given by {DMA_START_H[3:0], DMA_START[7:0]}. register (Table 80), forms a 12-bit End Address. Table 79. DMAx Start/Current Address Low Byte Register (DMAxSTART)

most significant byte of the ADC data stored at the even numbered Register File address. register contains the value 72H. Table 80. DMAx End Address Low Byte Register (DMAxEND) Table 81. DMA_ADC Register File Address Example

{DMAA_ADDR[7:1], 4-bit ADC Analog Input Number, 0}. This bit is reserved and must be 0. interrupt enable) for ADC operation. Table 82. DMA_ADC Address Register (DMAA_ADDR)

0 = DMA_ADC is disabled and the ADC Analog Input Number (ADC_IN) is reset to 0. 0 = DMA_ADC does not generate any interrupts. Input specified by the ADC_IN field. These bits are reserved and must be 0. 0000 = ADC Analog Input 0 updated. 0001 = ADC Analog Inputs 0-1 updated. 0010 = ADC Analog Inputs 0-2 updated. 0011 = ADC Analog Inputs 0-3 updated. 0100 = ADC Analog Inputs 0-4 updated. 0101 = ADC Analog Inputs 0-5 updated. 0110 = ADC Analog Inputs 0-6 updated. 0111 = ADC Analog Inputs 0-7 updated. 1000 = ADC Analog Inputs 0-8 updated. 1001 = ADC Analog Inputs 0-9 updated. 1010 = ADC Analog Inputs 0-10 updated. 1011 = ADC Analog Inputs 0-11 updated. Table 83. DMA_ADC Control Register (DMAACTL)

This field identifies the Analog Input that the ADC is currently converting. This bit is reserved and must be 0. This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA_ADC is not the source of the interrupt from the DMA Controller. This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA1 is not the source of the interrupt from the DMA Controller. 1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt. This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA0 is not the source of the interrupt from the DMA Controller. 1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt. Table 84. DMA_ADC Status Register (DMAA_STAT)

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Analog-to-Digital Converter 170 Analog-to-Digital Converter Overview The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The features of the sigma-delta ADC include:

• 12 analog input sources are multiplexed with general-purpose I/O ports
• Interrupt upon conversion complete
• Internal voltage reference generator
• Direct Memory Access (DMA) controller can automatically initiate data conversion and transfer of the data from 1 to 12 of the analog inputs Architecture Figure 34 illustrates the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the ADC. The ADC converts an analog input signal to its digital representation. The 12-input analog multiplexer selects one of the 12 analog input sources. The ADC requires an input reference voltage for the conversion. The voltage ref- erence for the conversion may be input through the external VREF pin or generated inter- nally by the voltage reference generator.

Figure 34. Analog-to-Digital Converter Block Diagram ing codes) is guaranteed by design. sion is requested using the ADC Control register.

PS019910-0504 P r e l i m i n a r y Analog-to-Digital Converter Z8 Encore!® 64K Series Product Specification 172 Single-Shot Conversion When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion are as follows: 1. Enable the desired analog inputs by configuring the general-purpose I/O pins for alternate function. This configuration disables the digital input and output drivers. 2. Write to the ADC Control register to co nfigure the ADC and begin the conversion. The bit fields in the ADC Control register can be written simultaneously: – Write to the ANAIN[3:0] field to select one of the 12 analog input sources. –C l e a r CONT to 0 to select a single-shot conversion. – Write to the VREF bit to enable or disable the internal voltage reference generator. –S e t CEN to 1 to start the conversion. 3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered-down state, the ADC uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 4. When the conversion is complete, the ADC control logic performs the following operations: – 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}. – CEN resets to 0 to indicate the conversion is complete. – An interrupt request is sent to the Interrupt Controller. 5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered-down. Continuous Conversion When configured for continuous conversion, the ADC continuously performs an analog- to-digital conversion on the selected analog input. Each new data value over-writes the previous value stored in the ADC Data registers. An interrupt is generated after each con- version. In CONTINUOUS mode, users must be aware that ADC updates are lim- ited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not seen at the next output from the ADC. The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency. The steps for setting up the ADC and initiating continuous conversion are as follows: Caution:

PS019910-0504 P r e l i m i n a r y Analog-to-Digital Converter Z8 Encore!® 64K Series Product Specification 173 1. Enable the desired analog input by conf iguring the general-purpose I/O pins for alternate function. This disables the digital input and output driver. 2. Write to the ADC Control register to co nfigure the ADC for continuous conversion. The bit fields in the ADC Control register may be written simultaneously: – Write to the ANAIN[3:0] field to select one of the 12 analog input sources. –S e t CONT to 1 to select continuous conversion. – Write to the VREF bit to enable or disable the internal voltage reference generator. –S e t CEN to 1 to start the conversions. 3. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: – CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation. – An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete. 4. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0], ADCD_L[7:6]} every 256 system clock cycles. An interrupt request is sent to the Interrupt Controller when each conversion is complete. 5. To disable continuous conversion, clear the CONT bit in the ADC Control register to 0. DMA Control of the ADC The Direct Memory Access (DMA) Controller can control operation of the ADC includ- ing analog input selection and conversion enable. For more information on the DMA and configuring for ADC operations refer to the chapter Direct Memory Access Controller on page 160.

this bit to 0 when a conversion has been completed. in progress, the conversion restarts. This bit remains 1 until the conversion is complete. selected as the ADC reference voltage. provided through the VREF pin. 1 = Continuous conversion. ADC data updated every 256 system clock cycles. package style. Do not enable unavailable analog inputs. Table 85. ADC Control Register (ADCCTL)

put is held in this register. These bits are undefined after a Reset. Table 86. ADC Data High Byte Register (ADCD_H)

These bits are reserved and are always undefined. Table 87. ADC Data Low Bits Register (ADCD_L)

for Flash or ROM device-related information. grammed and erased in-circuit by either user code or through the On-Chip Debugger. which can be protected from programming and erase operations on a per sector basis. Table 88 describes the Flash memory configuration for each device in the 64K Series. Table 88. Flash Memory Configurations

Figure 35. Flash Memory Arrangement Table 89. Flash Memory Sector Addresses

128 Pages

512 Bytes per Page

Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase). Table 90. 64K Series Information Area Map

PS019910-0504 P r e l i m i n a r y Program Memory Z8 Encore!® 64K Series Product Specification 180 Timing Using the Flash Frequency Registers Before performing a program or erase operation on the Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis- ters allow programming and erasure of the Flash with system clock frequencies ranging from 20kHz through 20MHz (the valid range is limited to the device operating frequen- cies). The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Fre- quency value must contain the system clock frequency in KHz. This value is calculated using the following equation:. Flash programming and erasure are no t supported for system clock fre- quencies below 20KHz, above 20MHz, or outside of the device operating frequency range. The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper Flash programming and erase operations. Flash Read Protection The user code contained within the Flash memory can be protected from external access. Programming the Flash Read Protect Option Bit prevents reading of user code by the On- Chip Debugger or by using the Flash Controller Bypass mode. Refer to the Option Bits chapter and the On-Chip Debugger chapter for more information. Flash Write/Erase Protection The 64K Series provides several levels of protection against accidental program and era- sure of the Flash memory contents. This protection is provided by the Flash Controller unlock mechanism, the Flash Sector Protect register, and the Flash Write Protect option bit. Flash Controller Unlock Mechanism At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash memory. To program or erase the Flash memory, the Flash controller must be unlocked. After unlocking the Flash Controller, the Flash can be programmed or erased. Any value written by user code to the Flash Control register or Page Select Register out of sequence will lock the Flash Controller. The proper steps to unlock the Flash Controller from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. FFREQ[15:0] System Clock Frequency (Hz) Caution:

PS019910-0504 P r e l i m i n a r y Program Memory Z8 Encore!® 64K Series Product Specification 181 2. Write the page to be programmed or erased to the Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in step 2 to the Page Select register. Flash Sector Protection The Flash Sector Protect register can be configured to prevent sectors from being pro- grammed or erased. Once a sector is protected, it cannot be unprotected by user code. The Flash Sector Protect register is cleared after reset and any previously written protection values is lost. User code must write this register in their initialization routine if they want to enable sector protection. The Flash Sector Protect register shares its Register File address with the Page Select reg- ister. The Flash Sector Protect register is accessed by writing the Flash Control register with 5EH. Once the Flash Sector Protect register is selected, it can be accessed at the Page Select Register address. When user code writes the Flash Sector Protect register, bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than 5EH to the Flash Control register de-selects the Flash Sector Protect register and re-enables access to the Page Select register. The steps to setup the Flash Sector Protect register from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write 5EH to the Flash Control register to select the Flash Sector Protect register. 3. Read and/or write the Flash Sector Protect register which is now at Register File address FF9H. 4. Write 00H to the Flash Control register to return the Flash Controller to its reset state. Flash Write Protection Option Bit The Flash Write Protect option bit can be enabled to block all program and erase opera- tions from user code. Refer to the Option Bits chapter for more information. Byte Programming When the Flash Controller is unlocked, writes to Program Memory from user code will program a byte into the Flash if the address is located in the unlocked page. An erased Flash byte contains all ones (FFH). The programming operation can only be used to change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page Erase or Mass Erase operation. Byte Programming can be accomplished using the eZ8 CPU’s LDC or LDCI instructions. Refer to the eZ8 CPU User Manual for a description of the LDC and LDCI instructions.

PS019910-0504 P r e l i m i n a r y Program Memory Z8 Encore!® 64K Series Product Specification 182 While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Interrupts that occur when a Program- ming operation is in progress are serviced once the Programming operation is complete. To exit Programming mode and lock the Flash Controller, write 00H to the Flash Control register. User code cannot program Flash Memory on a page that lies in a protected sector. When user code writes memory locations, only addresses located in the unlocked page are pro- grammed. Memory writes outside of the unlocked page are ignored. Each memory location must not be programmed more than twice before an erase occurs. The proper steps to program the Flash from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write the page of memory to be programmed to the Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in step 2 to the Page Select register. 6. Write Program Memory using LDC or LD CI instructions to program the Flash. 7. Repeat step 6 to program additional memory locations on the same page. 8. Write 00H to the Flash Control register to lock the Flash Controller. Page Erase The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Page Select register identifies the page to be erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. Interrupts that occur when the Page Erase operation is in progress are serviced once the Page Erase operation is com- plete. When the Page Erase operation is complete, the Flash Controller returns to its locked state. Only pages located in unprotected sectors can be erased. The proper steps to perform a Page Erase operation are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write the page to be erased to the Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. Caution:

PS019910-0504 P r e l i m i n a r y Program Memory Z8 Encore!® 64K Series Product Specification 183 5. Re-write the page written in step 2 to the Page Select register. 6. Write the Page Erase command 95H to the Flash Control register. Mass Erase The Flash memory cannot be Mass Erased by user code. Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Programming algorithms by controlling the Flash programming signals directly. Flash Controller Bypass is recommended for gang programming applications and large volume customers who do not require in-circuit programming of the Flash memory. Refer to the document entitled Third-Party Flash Programming Support for Z8 Encore!® for more information on bypassing the Flash Controller. This document is available for download at www.zilog.com. Flash Controller Behavior in Debug Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger:

• The Flash Write Protect option bit is ignored.
• The Flash Sector Protect register is ignored for programming and erase operations.
• Programming operations are not limited to the page selected in the Page Select register.
• Bits in the Flash Sector Protect register can be written to one or zero.
• The second write of the Page Select register to unlock the Flash Controller is not necessary.
• The Page Select register can be written when the Flash Controller is unlocked.
• The Mass Erase command is enabled through the Flash Control register.

erase operations, or to select the Flash Sector Protect register. 8CH = Second unlock command. 5EH = Flash Sector Protect register select.

• All other commands, or any command out of sequence, lock the Flash Controller.

Table 91. Flash Control Register (FCTL)

File address with the Write-only Flash Control Register. These bits are reserved and must be 0. Table 92. Flash Status Register (FSTAT)

pages to be erased or programmed. Each Flash Page contains 512 bytes of Flash memory. of the address given by the PAGE field are erased to FFH. 0 = Information Area is not selected. ory address space at addresses FE00H through FFFFH. tions. Program Memory Address[15:9] = PAGE[6:0]. Table 93. Page Select Register (FPS)

accessed only after writing the Flash Control register with 5EH. User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code). 0 = Sector n can be programmed or erased from user code. 1 = Sector n is protected and cannot be programmed or erased from user code.

• User code can only write bits from 0 to 1.

Table 94. Flash Sector Protect Register (FPROT) R/W1 = Register is accessible for Read operations. Register can be written to 1 only (via user code).

These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value. Table 95. Flash Frequency High Byte Register (FFREQH) Table 96. Flash Frequency Low Byte Register (FFREQL)

Table 97 describes the ROM configuration for each device in the 64K Series. be verified by using the On-Chip Debugger’s Read Program Memory CRC command. Table 97. Z8 Encore!® 64K Series Memory Configurations Table 98. Z8 Encore!

tion on Read Protection and the Read Program Memory CRC command. The Page Select register enables access to the Information Area data. 0 = Information Area access is disabled. Program Memory address space at addresses FE00H through FFFFH. Table 99. Page Select Register (RPS)

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Option Bits 191 Option Bits Overview Option Bits allow user configuration of certain aspects of the 64K Series operation. The feature configuration data is stored in the Program Memory and read during Reset. The features available for control via the Option Bits are:

• Watch-Dog Timer time-out response selection–interrupt or Reset.
• Watch-Dog Timer enabled at Reset.
• The ability to prevent unwanted read access to user code in Program Memory.
• The ability to prevent accidental programming and erasure of the user code in Program Memory.
• V oltage Brown-Out configuration-always enabled or disabled during STOP mode to reduce STOP mode power consumption.
• Oscillator mode selection-for high, medium, and low power crystal oscillators, or external RC oscillator. Operation Option Bit Configuration By Reset Each time the Option Bits are programmed or erased, the device must be Reset for the change to take place. During any reset operation (System Reset, Reset, or STOP Mode Recovery), the Option Bits are automatically read from the Program Memory and written to Option Configuration registers. The Option Configuration registers control operation of the devices within the 64K Series. Option Bit control is established before the device exits Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not part of the Register File and are not accessible for read or write access. Option Bit Address Space The first two bytes of Program Memory at addresses 0000H (Table 100 and 101)and 0001H (Table 102) are reserved for the user Option Bits. Table 100 shows the option bits for Z8 Encore! 64K Series Flash devices. Table 101 shows the same information for the 64K Series ROM devices. The byte at Program Memory address 0000H configures user

Table 101. ROM Option Bits At Program Memory Address 0000H enabled for the eZ8 CPU to acknowledge the interrupt request. Table 100. Flash Option Bits At Program Memory Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write. Note: U = Unchanged by Reset. R/W = Read/Write.

PS019910-0504 P r e l i m i n a r y Option Bits Z8 Encore!® 64K Series Product Specification 193 the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This set- ting is the default for unprogrammed (erased) Flash. OSC_SEL[1:0]—Oscillator Mode Selection 00 = On-chip oscillator configured for use with external RC networks (<4MHz). 01 = Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). 10 = Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 10.0MHz). 11 = Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz). This setting is the default for unprogrammed (erased) Flash. VBO_AO—V oltage Brown-Out Protection Always On 0 = V oltage Brown-Out Protection is disabled in STOP mode to reduce total power con- sumption. 1 = V oltage Brown-Out Protection is always enabled including during STOP mode. This setting is the default for unprogrammed (erased) Flash. RP—Read Protect 0 = User program code is inaccessible. Limited control features are available through the On-Chip Debugger. 1 = User program code is accessible. All On-Chip Debugger commands are enabled. This setting is the default for unprogrammed (erased) Flash. Reserved These Option Bits are reserved for future use and must always be 1.This setting is the default for unprogrammed (erased) Flash. FWP—Flash Write Protect (Flash version only) FWP Description 0 Programming, Page Erase, and Mass Erase through User Code is disabled. Mass Erase is available through the On-Chip Debugger. 1 Programming, and Page Erase are enab led for all of Flash Program Memory.

default for unprogrammed (erased) Flash. Table 102. Options Bits at Program Memory Address 0001H Note: U = Unchanged by Reset. R = Read-Only. R/W = Read/Write.

• Reading and writing of the Register File
• Reading and writing of Program and Data Memory
• Setting of Breakpoints
• Execution of eZ8 CPU instructions Architecture The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver, auto-baud generator, and debug controller. Figure 36 illustrates the architecture of the On- Chip Debugger

Figure 36. On-Chip Debugger Block Diagram

one-pin interface is a bi-directional open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. pin to an RS-232 interface are depicted in Figures 37 and 38. an external pull-up resistor to ensure proper operation. Figure 37. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1)

Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)

• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute specific instructions.
• The system clock operates unless in STOP mode.
• All enabled on-chip peripherals operate unless in STOP mode.
• Automatically exits HALT mode.
• Constantly refreshes the Watch-Dog Timer, if enabled. Entering Debug Mode The device enters DEBUG mode following any of the following operations:
• Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface.
• eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled).
• If the DBG pin is Low when the device exits Reset, the On-Chip Debugger automatically puts the device into DEBUG mode. Exiting Debug Mode The device exits DEBUG mode following any of the following operations:
• Clearing the DBGMODE bit in the OCD Control Register to 0.
• Power-on reset
• V oltage Brown Out reset RS-232 TX RS-232 RX RS-232 Transceiver VDD DBG Pin 10K OhmOpen-Drain Buffer

• Asserting the RESET pin Low to initiate a Reset.
• Driving the DBG pin Low while the device is in STOP mode initiates a System Reset. OCD Data Format The OCD interface uses the asynchronous data format defined for RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit (Figure 39).

Figure 39. OCD Data Format mended maximum baud rates for sample crystal frequencies. Table 103. OCD Baud-Rate Limits

PS019910-0504 P r e l i m i n a r y On-Chip Debugger Z8 Encore!® 64K Series Product Specification 199 OCD Serial Errors The On-Chip Debugger can detect any of the following error conditions on the DBG pin:

• Serial Break (a minimum of nine continuous bits Low)
• Framing Error (received Stop bit is Low)
• Transmit Collision (OCD and host simultaneous transmission detected by the OCD) When the OCD detects one of these errors, it aborts any command currently in progress, transmits a Serial Break 4096 system clock cycles long back to the host, and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the inter- face, returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host transmits a Serial Break on the DBG pin when first connecting to the 64K Series devices or when recovering from an error. A Serial Break from the host resets the Auto- Baud Generator/Detector but does not reset the OCD Control register. A Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the open- drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character. Breakpoints Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If Breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP. If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK instruction, then the CPU is still enabled to service DMA and interrupt requests. The loop on BRK instruction can be used to service interrupts in the background. For interrupts to be serviced in the background, there cannot be any breakpoints in the inter- rupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine. For interrupts to be serviced in the background, interrupts must also be enabled. Debug- ging software should not automatically enable interrupts when using this feature, since interrupts are typically disabled during critical sections of code where interrupts should not occur (such as adjusting the stack pointer or modifying shared data). Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is loop- ing on a BRK instruction. When software wants to stop the CPU on the BRK instruction it is looping on, software should not set the DBGMODE bit of the OCDCTL register. The CPU may have vectored to and be in the middle of an interrupt service routine when this bit gets set. Instead, software must clear the BRKLP bit. This action allows the CPU to

DBGMODE bit and enter DEBUG mode. in DEBUG mode before these commands can be issued. memory must be erased and reprogrammed with the original data. Series products. When this option is enabled, several of the OCD commands are disabled. Table 104. On-Chip Debugger Commands

• Read OCD Revision (00H)—The Read OCD Revision command determines the version of the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision number changes. DBG ← 00H DBG → OCDREV[15:8] (Major revision number) DBG → OCDREV[7:0] (Minor revision number)
• Read OCD Status Register (02H)—The Read OCD Status Register command reads the OCDSTAT register. DBG ← 02H DBG → OCDSTAT[7:0]
• Write OCD Control Register (04H)—The Write OCD Control Register command writes the data that follows to the OCDCTL register. When the Read Protect Option Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0 and the only method of putting the device back into normal operating mode is to reset the device. Write Register 08H - Only writes of the Flash Memory Control registers are allowed. Additionally, only the Mass Erase command is allowed to be written to the Flash Control register. Read Register 09H - Disabled- Write Program Memory 0AH - Disabled Read Program Memory 0BH - Disabled Write Data Memory 0CH - Disabled Read Data Memory 0DH - Disabled Read Program Memory CRC 0EH - - Reserved 0FH - - Step Instruction 10H - Disabled Stuff Instruction 11H - Disabled Execute Instruction 12H - Disabled Reserved 13H - FFH - -

Table 104. On-Chip Debugger Commands (Continued)

PS019910-0504 P r e l i m i n a r y On-Chip Debugger Z8 Encore!® 64K Series Product Specification 202 DBG ← 04H DBG ← OCDCTL[7:0]

• Read OCD Control Register (05H)—The Read OCD Control Register command reads the value of the OCDCTL register. DBG ← 05H DBG → OCDCTL[7:0]
• Write Program Counter (06H)—The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the Program Counter (PC) values are discarded. DBG ← 06H DBG ← ProgramCounter[15:8] DBG ← ProgramCounter[7:0]
• Read Program Counter (07H)—The Read Program Counter command reads the value in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFFFH. DBG ← 07H DBG → ProgramCounter[15:8] DBG → ProgramCounter[7:0]
• Write Register (08H)—The Write Register command writes data to the Register File. Data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If the device is not in DEBUG mode, the address and data values are discarded. If the Read Protect Option Bit is enabled, then only writes to the Flash Control Registers are allowed and all other register write data values are discarded. DBG ← 08H DBG ← {4’h0,Register Address[11:8]} DBG ← Register Address[7:0] DBG ← Size[7:0] DBG ← 1-256 data bytes
• Read Register (09H)—The Read Register command reads data from the Register File. Data can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for all the data values. DBG ← 09H DBG ← {4’h0,Register Address[11:8] DBG ← Register Address[7:0] DBG ← Size[7:0] DBG → 1-256 data bytes
• Flash Version Only: Write Program Memory (0AH)—The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). The on-chip Flash Controller must be written to and

PS019910-0504 P r e l i m i n a r y On-Chip Debugger Z8 Encore!® 64K Series Product Specification 203 unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded. This command has no affect on ROM parts. DBG ← 0AH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes

• Read Program Memory (0BH)—The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for the data. DBG ← 0BH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes
• Write Data Memory (0CH)—The Write Data Memory co mmand writes data to Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded. DBG ← 0CH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes
• Read Data Memory (0DH)—The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in DEBUG mode, this command returns FFH for the data. DBG ← 0DH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes

PS019910-0504 P r e l i m i n a r y On-Chip Debugger Z8 Encore!® 64K Series Product Specification 204

• Read Program Memory CRC (0EH)—The Read Program Memory CRC command computes and returns the CRC (cyclic redundancy check) of Program Memory using the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory. DBG ← 0EH DBG → CRC[15:8] DBG → CRC[7:0]
• Step Instruction (10H)—The Step Instruction co mmand steps one assembly instruction at the current Program Counter (PC) location. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command. DBG ← 10H
• Stuff Instruction (11H)—The Stuff Instruction co mmand steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command. DBG ← 11H DBG ← opcode[7:0]
• Execute Instruction (12H)—The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over Breakpoints. The number of bytes to send for the instruction depends on the opcode. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command DBG ← 12H DBG ← 1-5 byte opcode On-Chip Debugger Control Register Definitions OCD Control Register The OCD Control register (Table 105) controls the state of the On-Chip Debugger. This register enters or exits DEBUG mode and enables the BRK instruction. It can also reset the Z8F642x familyZ8R642x family device.

mode, a “run” function can be implemented by writing 40H to this register. by resetting the device, it cannot be written to 0. 0 = The 64K Series device is operating in Normal mode. 1 = The 64K Series device is in DEBUG mode. BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit. 0 = BRK instruction is disabled. 1 = BRK instruction is enabled. an Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. CPU loops on the BRK instruction. 0 = BRK instruction sets DBGMODE to 1. 1 = eZ8 CPU loops on BRK instruction. These bits are reserved and must be 0. Table 105. OCD Control Register (OCDCTL)

automatically cleared to 0 when the reset finishes. the debugger and the system. CPU is running or if it is idling. 1 = The eZ8 CPU is either stopped or looping on a BRK instruction. 0 = The device is not in HALT mode. 1 = The device is in HALT mode. 0 = The Read Protect Option Bit is disabled (1). 1 = The Read Protect Option Bit is enabled (0), disabling many OCD commands. Table 106. OCD Status Register (OCDSTAT)

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y On-Chip Oscillator 207 On-Chip Oscillator Overview The products in the 64K Series feature an on-chip oscillator for use with external crystals with frequencies from 32KHz to 20MHz. In addition, the oscillator can support external RC networks with oscillation frequencies up to 4MHz or ceramic resonators with oscilla- tion frequencies up to 20MHz. This oscillator generates the primary system clock for the internal eZ8 CPU and the majority of the on-chip peripherals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32KHz–20MHz). If an external clock generator is used, the XOUT pin must be left unconnected. When configured for use with crystal oscillators or external clock drivers, the frequency of the signal on the XIN input pin determines the frequency of the system clock (that is, no internal clock divider). In RC operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle. Operating Modes The 64K Series products support 4 different oscillator modes:

• On-chip oscillator configured for use with external RC networks (<4MHz).
• Minimum power for use with very low frequency crystals (32KHz to 1.0MHz).
• Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 10.0MHz).
• Maximum power for use with high frequency crystals or ceramic resonators (8.0MHz to 20.0MHz). The oscillator mode is selected through user-programmable Option Bits. Refer to the Option Bits chapter for information. Crystal Oscillator Operation Figure 40 illustrates a recommended configuration for connection with an external funda- mental-mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz crys- tal specifications are provided in Table 107. Resistor R1 is optional and limits total power dissipation by the crystal. The printed circuit board layout must add no more than 4pF of

values of capacitors C1 and C2 to decrease loading. Figure 40. Recommended 20MHz Crystal Oscillator Configuration Table 107. Recommended Crystal Oscillator Specifications (20MHz Operation)

The External RC oscillator mode is applicable to timing insensitive applications. Figure 41. Connecting the On-Chip Oscillator to an External RC Network circuit board should be included in the estimation of the oscillator frequency. capacitance values in excess of 20pF are recommended.

Figure 42. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kΩ Resistor lation as soon as the supply voltage exceeds 2.7V .

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y Electrical Characteristics 211

Electrical Characteristics

All data in this chapter is pre-qualification and pre-characterization and is subject to change. Absolute Maximum Ratings Stresses greater than those listed in Table 108 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or VSS). Table 108. Absolute Maximum Ratings

1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),

RESET, and where noted otherwise.

Table 108. Absolute Maximum Ratings (Continued)

1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),

RESET, and where noted otherwise.

1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),

RESET, and where noted otherwise.

enced to VSS, the primary system ground. Table 109. DC Characteristics VIL2 Low Level Input V oltage -0.3 – 0.2*V DD VF o r R E S E T, DBG , and XIN. VIH1 High Level Input V oltage 0.7*V DD – 5.5 V Port A, C, D, E, F, and G pins. VIH2 High Level Input V oltage 0.7*V DD –V DD+0.3 V Port B and H pins.

1 This condition excludes all pins that have on-chip pull-ups, when driven Low. 2 These values are provided for design guidance only and are not tested in production. Table 109. DC Characteristics (Continued)

Table 110. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing only and are not tested in production.

Table 111. External RC Oscillator Electrical Characteristics and Timing soon as the supply voltage exceeds 2.7V . Table 112. Reset and STOP Mode Recovery Pin Timing

Table 113 list the Flash Memory electrical characteristics and timing. Table 114 lists the Watch-Dog Timer electrical characteristics and timing. Table 113. Flash Memory Electrical Characteristics and Timing Table 114. Watch-Dog Timer Electrical Characteristics and Timing

Table 115 provides electrical characteristics and timing information for the Analog-to-Digital Converter. Figure 49 illustrates the input frequency response of the ADC. Table 115. Analog-to-Digital Converter Electrical Characteristics and Timing

Figure 49. Analog-to-Digital Converter Frequency Response

AC characteristics and timing. Table 116. AC Characteristics Fsysclk System Clock Frequency – 20.0 MHz Read-only from Flash memory. require an external clock driver.

Figure 50. Port Input Sample Timing Table 117. GPIO Port Input Timing

0 Latched

Figure 51 and Table 118 provide timing information for GPIO Port pins. Figure 51. GPIO Port Output Timing Table 118. GPIO Port Output Timing

1 XIN Rise to Port Output Valid Delay – 15

ing specifications assume a 4µs maximum rise and fall time. Figure 52. On-Chip Debugger Timing Table 119. On-Chip Debugger Timing

1 XIN Rise to DBG Valid Delay – 15

sample MISO input data. Timing on the SS output pin(s) is controlled by software. Figure 53. SPI Master Mode Timing Table 120. SPI Master Mode Timing

1 SCK Rise to MOSI output Valid Delay -5 +5

Figure 54. SPI Slave Mode Timing Table 121. SPI Slave Mode Timing

1 SCK (transmit edge) to MISO output Valid Delay 2 * Xin

Z8 Encore!® 64K Series Product Specification PS019910-0504 P r e l i m i n a r y eZ8 CPU Instruction Set 236 eZ8 CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without having to be concerned with actual memory addresses or machine instruction for- mats. A program written in assembly language is called a source program. Assembly lan- guage allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called state- ments. Each statement can contain labels, operations, operands and comments. Labels can be assigned to a particular instruction step in a source program. The label iden- tifies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example. Assembly Language Source Program Example JP START ; Everything after the semicolon is a comment. START: ; A label called “START”. The first instruction ( JP START) in this ; example causes program execution to jump to the point within the ; program where the START label occurs. LD R4, R7 ; A Load (LD) instruction with two operands. The first operand, ; Working Register R4, is the destination. The second operand, ; Working Register R7, is the source. The contents of R7 is ; written into R4. LD 234H, #%01 ; Another Load (LD) instruction with two operands. ; The first operand, Extended Mode Register Address 234H, ; identifies the destination. The second operand, Immediate Data

PS019910-0504 P r e l i m i n a r y eZ8 CPU Instruction Set Z8 Encore!® 64K Series Product Specification 237 ; value 01H, is the source. The value 01H is written into the ; Register at address 234H. Assembly Language Syntax For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually has the operands in the order ’source, destination’, but ordering is opcode-dependent. The fol- lowing instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. Example 1: If the contents of Registers 43H and 08H are added and the result is stored in 43H, the assembly syntax and resulting object code is: Example 2: In general, when an instruction format requires an 8-bit register address, that address can specify any register location in the range 0 - 255 or, using Escaped Mode Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H, the assembly syntax and resulting object code is: See the device-specific Product Specification to determine the exact register file range available. The register file size varies, depending on the device type. eZ8 CPU Instruction Notation In the eZ8 CPU Instruction Summary and Description sections, the operands, condition codes, status flags, and address modes are represented by a notational shorthand that is described in Table 125. Assembly Language Syntax Example 1 Assembly Language Code ADD 43H, 08H (ADD dst, src) Object Code 04 08 43 (OPC src, dst) Assembly Language Syntax Example 2 Assembly Language Code ADD 43H, R8 (ADD dst, src) Object Code 04 E8 43 (OPC src, dst)

and Instruction Set Description sections. Table 125. Notational Shorthand b Bit b b represents a value from 0 to 7 (000B to 111B). p Polarity p Polarity is a single bit bi nary value of either 0B or 1B.

Table 126. Additional Symbols

ation decides if the conditional jump is executed. Table 127. Condition Codes

1010 A GT Greater Than (Z OR (S XOR V)) = 0

1011 B UGT Unsigned Greater Than (C = 0 AND Z = 0) = 1

1100 C NOV No Overflow V = 0

1101 D PL Plus S = 0

1110 E NZ Non-Zero Z = 0

1110 E NE Not Equal Z = 0

1111 F NC No Carry C = 0

1111 F UGE Unsigned Greater Than or Equal C = 0

• Arithmetic
• Bit Manipulation
• Block Transfer
• CPU Control
• Load
• Logical
• Program Control
• Rotate and Shift Tables 128 through 135 contain the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category. Within these tables, the source operand is identified as ’src’, the destination operand is ’dst’ and a con- dition code is ’cc’.

Table 128. Arithmetic Instructions

Table 129. Bit Manipulation Instructions Table 130. Block Transfer Instructions Table 128. Arithmetic Instructions (Continued)

Table 131. CPU Control Instructions Table 132. Load Instructions

Table 133. Logical Instructions Table 134. Program Control Instructions

required for the instruction execution. Table 135. Rotate and Shift Instructions Table 136. eZ8 CPU Instruction Summary Flags Notation: * = Value is a function of the result of the operation.

Table 136. eZ8 CPU Instruction Summary (Continued) Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

Flags Notation: * = Value is a function of the result of the operation.

not be tested and are used for Binary-Coded Decimal (BCD) arithmetic. positions in the Flags Register. tion restores the value saved on the stack into the Flags Register. Figure 58. Flags Register

Table 132. Figures 60 and 61 provide information on each of the eZ8 CPU instructions. Figure 59. Opcode Map Cell Description

Table 132. Opcode Map Abbreviations

Figure 60. First Opcode Map

Figure 61. Second Opcode Map after 1FH

Figure 64. 44-Lead Plastic Lead Chip Carrier Package (PLCC) Figure 65. 64-Lead Low-Profile Quad Flat Package (LQFP)

1. LEADS ARE COPLANAR WITHIN 0.004".
2. CONTROLLING DIMENSION : INCH

1.27 BSC

0.050 BSC

Figure 67. 80-Lead Quad-Flat Package (QFP)

0.80 BSC

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 265

Ordering Information

Description

Z8F16xx with 16KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F1621PM020SC 16KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F1621AN020SC 16KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F1621VN020SC 16KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F1622AR020SC 16KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F1622VS020SC 16KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Extended Temperature: -40° to +105°C Z8F1621PM020EC 16KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F1621AN020EC 16KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F1621VN020EC 16KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F1622AR020EC 16KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F1622VS020EC 16KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 266 Z8F24xx with 24KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F2421PM020SC 24KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F2421AN020SC 24KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F2421VN020SC 24KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F2422AR020SC 24KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F2422VS020SC 24KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Extended Temperature: -40° to +105°C Z8F2421PM020EC 24KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F2421AN020EC 24KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F2421VN020EC 24KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F2422AR020EC 24KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F2422VS020EC 24KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 267 Z8F32xx with 32KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F3221PM020SC 32KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F3221AN020SC 32KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F3221VN020SC 32KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F3222AR020SC 32KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F3222VS020SC 32KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Extended Temperature: -40° to 105°C Z8F3221PM020EC 32KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F3221AN020EC 32KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F3221VN020EC 32KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F3222AR020EC 32KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F3222VS020EC 32KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 268 Z8F48xx with 48KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F4821PM020SC 48KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F4821AN020SC 48KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F4821VN020SC 48KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F4822AR020SC 48KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F4822VS020SC 48KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8F4823FT020SC 48KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Extended Temperature: -40° to 105°C Z8F4821PM020EC 48KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F4821AN020EC 48KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F4821VN020EC 48KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F4822AR020EC 48KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F4822VS020EC 48KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8F4823FT020EC 48KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 269 Z8F64xx with 64KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F6421PM020SC 64KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F6421AN020SC 64KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F6421VN020SC 64KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F6422AR020SC 64KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F6422VS020SC 64KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8F6423FT020SC 64KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Extended Temperature: -40° to 105°C Z8F6421PM020EC 64KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8F6421AN020EC 64KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8F6421VN020EC 64KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8F6422AR020EC 64KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8F6422VS020EC 64KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8F6423FT020EC 64KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 270 Z8R16xx with 16KB ROM, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8R1621PM020SC 16KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R1621AN020SC 16KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R1621VN020SC 16KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R1622AR020SC 16KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R1622VS020SC 16KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Extended Temperature: -40° to +105°C Z8R1621PM020EC 16KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R1621AN020EC 16KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R1621VN020EC 16KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R1622AR020EC 16KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R1622VS020EC 16KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 271 Z8R24xx with 24KB ROM, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8R2421PM020SC 24KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R2421AN020SC 24KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R2421VN020SC 24KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R2422AR020SC 24KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R2422VS020SC 24KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Extended Temperature: -40° to +105°C Z8R2421PM020EC 24KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R2421AN020EC 24KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R2421VN020EC 24KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R2422AR020EC 24KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R2422VS020EC 24KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 272 Z8R32xx with 32KB ROM, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8R3221PM020SC 32KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R3221AN020SC 32KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R3221VN020SC 32KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R3222AR020SC 32KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R3222VS020SC 32KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Extended Temperature: -40° to +105°C Z8R3221PM020EC 32KB 2KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R3221AN020EC 32KB 2KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R3221VN020EC 32KB 2KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R3222AR020EC 32KB 2KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R3222VS020EC 32KB 2KB 46 24 4 12 1 1 2 PLCC 68-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 273 Z8R48xx with 48KB ROM, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8R4821PM020SC 48KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R4821AN020SC 48KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R4821VN020SC 48KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R4822AR020SC 48KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R4822VS020SC 48KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8R4823FT020SC 48KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Extended Temperature: -40° to 105°C Z8R4821PM020EC 48KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R4821AN020EC 48KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R4821VN020EC 48KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R4822AR020EC 48KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R4822VS020EC 48KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8R4823FT020EC 48KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 274 For technical and customer support, hardware and software development tools, visit the ZiLOG web site at www.zilog.com. The latest released version of ZDS can be down- loaded from this site. Z8R64xx with 64KB ROM, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8R6421PM020SC 64KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R6421AN020SC 64KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R6421VN020SC 64KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R6422AR020SC 64KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R6422VS020SC 64KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8R6423FT020SC 64KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Extended Temperature: -40° to 105°C Z8R6421PM020EC 64KB 4KB 29 23 3 8 1 1 2 PDIP 40-pin package Z8R6421AN020EC 64KB 4KB 31 23 3 8 1 1 2 LQFP 44-pin package Z8R6421VN020EC 64KB 4KB 31 23 3 8 1 1 2 PLCC 44-pin package Z8R6422AR020EC 64KB 4KB 46 24 4 12 1 1 2 LQFP 64-pin package Z8R6422VS020EC 64KB 4KB 46 24 4 12 1 1 2 PLCC 68-pin package Z8R6423FT020EC 64KB 4KB 60 24 4 12 1 1 2 QFP 80-pin package Z8F64200100KIT Development Kit Part Number Flash/ROM RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 275 Part Number Suffix Designations Example: Part number Z8F6421AN020SC is an 8-bit microcontroller product in an LQFP package, using 44 pins, operating with a maximum 20MHz ex ternal clock frequency over a 0ºC to +70ºC temperature range and built using the Plastic-Standard environmental flow. Precharacterization Product The product represented by this document is newly introduced and ZiLOG has not com- pleted the full characterization of the product. The document states what ZiLOG knows Z8 F 64 21 A N 020 S C Environmental Flow: C = Plastic Standard Temperature Range (°C): S = Standard, 0 to 70 E = Extended, -40 to +105 Speed: 020 = 20MHz Pin Count: M = 40 pins N = 44 pins R = 64 pins S = 68 pins T = 80 pins Package: A = LQFP F = QFP P = PDIP V = PLCC Device Type Memory Size: 64KB Flash/ROM, 4KB RAM 48KB Flash/ROM, 4KB RAM 32KB Flash/ROM, 2KB RAM 24KB Flash/ROM, 2KB RAM 16KB Flash/ROM, 2KB RAM Memory Type: F = Flash R = Read-Only Memory Device Family

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 276 about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield issues. ZiLOG , Inc. San Jose, CA 95126 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www.zilog.com Document Information Document Number Description The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table: PS Product Specification

0199 Unique Document Number

0204 Month and Year Published

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 277 Customer Feedback Form The Z8 Encore!® 64K Series Product Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Customer Information Product Information Name Country Company Phone Address Fax City/State/Zip E-Mail Part #, Serial #, Board Fab #, or Rev. # Software Version Document Number Host Computer Description/Type

PS019910-0504 P r e l i m i n a r y Packaging Z8 Encore!® 64K Series Product Specification 278 Return Information ZiLOG , Inc. San Jose, CA 95126 Fax: (408) 558-8536 Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 279 Index Symbols # 239 % 239 @ 239 Numerics 10-bit ADC 4 40-lead plastic dual-inline package 260 44-lead low-profile quad flat package 261 44-lead plastic lead chip carrier package 262 64-lead low-profile quad flat package 262 68-lead plastic lead chip carrier package 263 80-lead quad flat package 264 A absolute maximum ratings 211 AC characteristics 227 ADC 241 architecture 170 automatic power-down 171 block diagram 171 continuous conversion 172 control register 174 control register definitions 174 data high byte register 175 data low bits register 175 DMA control 173 electrical characteristics and timing 225 operation 171 single-shot conversion 172 ADCCTL register 174 ADCDH register 175 ADCDL register 175 ADCX 241 ADD 241 add - extended addressing 241 add with carry 241 add with carry - extended addressing 241 additional symbols 239 address space 17 ADDX 241 analog signals 14 analog-to-digital converter (ADC) 170 AND 244 ANDX 244 arithmetic instructions 241 assembly language programming 236 assembly language syntax 237 B B 239 b 238 baud rate generator, UART 108 BCLR 242 binary number suffix 239 BIT 242 bit 238 clear 242 manipulation instructions 242 set 242 set or clear 242 swap 242 test and jump 244 test and jump if non-zero 244 test and jump if zero 244 bit jump and test if non-zero 244 bit swap 245 block diagram 3 block transfer instructions 242 BRK 244 BSET 242 BSWAP 242, 245 BTJ 244 BTJNZ 244 BTJZ 244 C CALL procedure 244 capture mode 89 capture/compare mode 89

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 280 cc 238 CCF 243 characteristics, electrical 211 clear 243 clock phase (SPI) 127 CLR 243 COM 244 compare 89 compare - extended addressing 241 compare mode 89 compare with carry 241 compare with carry - extended addressing 241 complement 244 complement carry flag 242, 243 condition code 238 continuous conversion (ADC) 172 continuous mode 89 control register definition, UART 109 control register, I2C 154 counter modes 89 CP 241 CPC 241 CPCX 241 CPU and peripheral overview 3 CPU control instructions 243 CPX 241 customer feedback form 277 customer information 277 D DA 238, 241 data register, I2C 151 DC characteristics 214 debugger, on-chip 195 DEC 241 decimal adjust 241 decrement 241 decrement and jump non-zero 244 decrement word 241 DECW 241 destination operand 239 device, port availability 51 DI 243 direct address 238 direct memory access controller 160 disable interrupts 243 DJNZ 244 DMA address high nibble register 164 configuring for DMA_ADC data transfer 162 confiigurting DMA0-1 data transfer 161 control of ADC 173 control register 162 control register definitions 162 controller 5 DMA_ADC address register 166 DMA_ADC control register 167 DMA_ADC operation 161 end address low byte register 165 I/O address register 164 operation 160 start/current address low byte register 165 status register 168 DMAA_STAT register 168 DMAACTL register 167 DMAxCTL register 163 DMAxEND register 166 DMAxH register 164 DMAxI/O address (DMAxIO) 164 DMAxIO register 164 DMAxSTART register 165 document number description 276 dst 239 E EI 243 electrical characteristics 211 ADC 225 flash memory and timing 224 GPIO input data sample timing 228 watch-dog timer 224 enable interrupt 243 ER 238 extended addressing register 238 external pin reset 46 external RC oscillator 223

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 281 eZ8 CPU features 3 eZ8 CPU instruction classes 241 eZ8 CPU instruction notation 237 eZ8 CPU instruction set 236 eZ8 CPU instruction summary 245 F FCTL register 184 features, Z8 Encore! 1 first opcode map 258 FLAGS 239 flags register 239 flash controller 4 option bit address space 191 option bit configuration - reset 191 program memory address 0000H 192 program memory address 0001H 194 flash memory arrangement 178 byte programming 181 code protection 180 configurations 177, 189 control register definitions 184 controller bypass 183 electrical characteristics and timing 224 flash control register 184 flash status register 185 frequency high and low byte registers 188 mass erase 183 operation 179 operation timing 180 page erase 182 page select register 186, 190 FPS register 186, 190 FSTAT register 185 G gated mode 89 general-purpose I/O 51 GPIO 4, 51 alternate functions 52 architecture 52 control register definitions 54 input data sample timing 228 interrupts 54 port A-H address registers 55 port A-H alternate function sub-registers 57 port A-H control registers 56 port A-H data direction sub-registers 57 port A-H high drive enable sub-registers 59 port A-H input data registers 60 port A-H output control sub-registers 58 port A-H output data registers 61 port A-H STOP mode recovery sub-registers 59 port availability by device 51 port input timing 228 port output timing 229 H H 239 HALT 243 halt mode 50, 243 hexadecimal number prefix/suffix 239 I I2C 4 10-bit address read transaction 149 10-bit address transaction 146 10-bit addressed slave data transfer format 146 10-bit receive data format 149 7-bit address transaction 144 7-bit address, reading a transaction 148 7-bit addressed slave data transfer format 143, 144, 145 7-bit receive data transfer format 148 baud high and low byte registers 155, 157, 159 C status register 152 control register definitions 151 controller 138 controller signals 13 interrupts 140 operation 139 SDA and SCL signals 140

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 282 stop and start conditions 142 I2CBRH register 155, 157, 159 I2CBRL register 156 I2CCTL register 154 I2CDATA register 152 I2CSTAT register 152 IM 238 immediate data 238 immediate operand prefix 239 INC 241 increment 241 increment word 241 INCW 241 indexed 238 indirect address prefix 239 indirect register 238 indirect register pair 238 indirect working register 238 indirect working register pair 238 infrared encoder/decoder (IrDA) 119 instruction set, ez8 CPU 236 instructions ADC 241 ADCX 241 ADD 241 ADDX 241 AND 244 ANDX 244 arithmetic 241 BCLR 242 BIT 242 bit manipulation 242 block transfer 242 BRK 244 BSET 242 BSWAP 242, 245 BTJ 244 BTJNZ 244 BTJZ 244 CALL 244 CCF 242, 243 CLR 243 COM 244 CP 241 CPC 241 CPCX 241 CPU control 243 CPX 241 DA 241 DEC 241 DECW 241 DI 243 DJNZ 244 EI 243 HALT 243 INC 241 INCW 241 IRET 244 JP 244 LD 243 LDC 243 LDCI 242, 243 LDE 243 LDEI 242 LDX 243 LEA 243 load 243 logical 244 MULT 241 NOP 243 OR 244 ORX 244 POP 243 POPX 243 program control 244 PUSH 243 PUSHX 243 RCF 242, 243 RET 244 RL 245 RLC 245 rotate and shift 245 RR 245 RRC 245 SBC 242 SCF 242, 243 SRA 245 SRL 245

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 283 SRP 243 STOP 243 SUB 242 SUBX 242 SWAP 245 TCM 242 TCMX 242 TM 242 TMX 242 TRAP 244 watch-dog timer refresh 243 XOR 244 XORX 244 instructions, eZ8 classes of 241 interrupt control register 74 interrupt controller 5, 62 architecture 62 interrupt assertion types 65 interrupt vectors and priority 65 operation 64 register definitions 66 software interrupt assertion 65 interrupt edge select register 72 interrupt port select register 73 interrupt request 0 register 66 interrupt request 1 register 67 interrupt request 2 register 68 interrupt return 244 interrupt vector listing 62 interrupts not acknowledge 140 receive 140 SPI 130 transmit 140 UART 106 introduction 1 IR 238 Ir 238 IrDA architecture 119 block diagram 119 control register definitions 123 operation 120 receiving data 121 transmitting data 120 IRET 244 IRQ0 enable high and low bit registers 69 IRQ1 enable high and low bit registers 70 IRQ2 enable high and low bit registers 71 IRR 238 Irr 238 J JP 244 jump, conditional, relative, and relative conditional 244 L LD 243 LDC 243 LDCI 242, 243 LDE 243 LDEI 242, 243 LDX 243 LEA 243 load 243 load constant 242 load constant to/from program memory 243 load constant with auto-increment addresses 243 load effective address 243 load external data 243 load external data to/from data memory and auto- increment addresses 242 load external to/from data memory and auto-incre- ment addresses 243 load instructions 243 load using extended addressing 243 logical AND 244 logical AND/extended addressing 244 logical exclusive OR 244 logical exclusive OR/extended addressing 244 logical instructions 244 logical OR 244 logical OR/extended addressing 244 low power modes 49 LQFP

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 284 44 lead 261 64 lead 262 M master interrupt enable 64 master-in, slave-out and-in 126 memory program 18 MISO 126 mode capture 89 capture/compare 89 continuous 89 counter 89 gated 89 one-shot 89 PWM 89 modes 89 MOSI 126 MULT 241 multiply 241 multiprocessor mode, UART 104 N NOP (no operation) 243 not acknowledge interrupt 140 notation b 238 cc 238 DA 238 ER 238 IM 238 IR 238 Ir 238 IRR 238 Irr 238 p 238 R 238 r 238 RA 238 RR 238 rr 238 vector 238 X 238 notational shorthand 238 O OCD architecture 195 auto-baud detector/generator 198 baud rate limits 198 block diagram 195 breakpoints 199 commands 200 control register 204 data format 198 DBG pin to RS-232 Interface 196 debug mode 197 debugger break 244 interface 196 serial errors 199 status register 206 timing 230 OCD commands execute instruction (12H) 204 read data memory (0DH) 203 read OCD control register (05H) 202 read OCD revision (00H) 201 read OCD status register (02H) 201 read program counter (07H) 202 read program memory (0BH) 203 read program memory CRC (0EH) 204 read register (09H) 202 step instruction (10H) 204 stuff instruction (11H) 204 write data memory (0CH) 203 write OCD control register (04H) 201 write program counter (06H) 202 write program memory (0AH) 202 write register (08H) 202 on-chip debugger 5 on-chip debugger (OCD) 195 on-chip debugger signals 15 on-chip oscillator 207 one-shot mode 89

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 285 opcode map abbreviations 257 cell description 256 first 258 second after 1FH 259 Operational Description 98 OR 244 ordering information 265 ORX 244 oscillator signals 14 P p 238 packaging LQFP 44 lead 261 64 lead 262 PDIP 260 PLCC 44 lead 262 68 lead 263 QFP 264 part number description 275 part selection guide 2 PC 239 PDIP 260 peripheral AC and DC electrical characteristics 222 PHASE=0 timing (SPI) 128 PHASE=1 timing (SPI) 129 pin characteristics 16 PLCC 44 lead 262 68-lead 263 polarity 238 POP 243 pop using extended addressing 243 POPX 243 port availability, device 51 port input timing (GPIO) 228 port output timing, GPIO 229 power supply signals 15 power-down, automatic (ADC) 171 power-on and voltage brown-out 222 power-on reset (POR) 44 problem description or suggestion 278 product information 277 program control instructions 244 program counter 239 program memory 18 PUSH 243 push using extended addressing 243 PUSHX 243 PWM mode 89 PxADDR register 55 PxCTL register 56 Q QFP 264 R R 238 r 238 RA register address 238 RCF 242, 243 receive 10-bit data format (I2C) 149 7-bit data transfer format (I2C) 148 IrDA data 121 receive interrupt 140 receiving UART data-interrupt-driven method 103 receiving UART data-polled method 102 register 135, 164, 238 ADC control (ADCCTL) 174 ADC data high byte (ADCDH) 175 ADC data low bits (ADCDL) 175 baud low and high byte (I2C) 155, 157, 159 baud rate high and low byte (SPI) 137 control (SPI) 132 control, I2C 154 data, SPI 131 DMA status (DMAA_STAT) 168 DMA_ADC address 166 DMA_ADC control DMAACTL) 167 DMAx address high nibble (DMAxH) 164

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 286 DMAx control (DMAxCTL) 163 DMAx end/address low byte (DMAxEND) 166 DMAx start/current address low byte register (DMAxSTART) 165 flash control (FCTL) 184 flash high and low byte (FFREQH and FRE- EQL) 188 flash page select (FPS) 186, 190 flash status (FSTAT) 185 GPIO port A-H address (PxADDR) 55 GPIO port A-H alternate function sub-registers GPIO port A-H control address (PxCTL) 56 GPIO port A-H data direction sub-registers 57 I2C baud rate high (I2CBRH) 155, 157, 159 I2C control (I2CCTL) 154 I2C data (I2CDATA) 152 I2C status 152 I2C status (I2CSTAT) 152 I2Cbaud rate low (I2CBRL) 156 mode, SPI 135 OCD control 204 OCD status 206 SPI baud rate high byte (SPIBRH) 137 SPI baud rate low byte (SPIBRL) 137 SPI control (SPICTL) 133 SPI data (SPIDATA) 132 SPI status (SPISTAT) 134 status, I2C 152 status, SPI 134 UARTx baud rate high byte (UxBRH) 115 UARTx baud rate low byte (UxBRL) 116 UARTx Control 0 (UxCTL0) 112, 115 UARTx control 1 (UxCTL1) 113 UARTx receive data (UxRXD) 110 UARTx status 0 (UxSTAT0) 110 UARTx status 1 (UxSTAT1) 112 UARTx transmit data (UxTXD) 109 watch-dog timer control (WDTCTL) 94 watch-dog timer reload high byte (WDTH) 96 watch-dog timer reload low byte (WDTL) 97 watch-dog timer reload upper byte (WDTU) 96 register file 17 register file address map 21 register pair 238 register pointer 239 reset and STOP mode characteristics 43 and STOP mode recovery 43 carry flag 242 controller 5 sources 44 RET 244 return 244 return information 278 RL 245 RLC 245 ROM code protection 189 control register definitions 190 rotate and shift instructions 245 rotate left 245 rotate left through carry 245 rotate right 245 rotate right through carry 245 RP 239 RR 238, 245 rr 238 RRC 245 S SBC 242 SCF 242, 243 SCK 126 SDA and SCL (IrDA) signals 140 second opcode map after 1FH 259 serial clock 126 serial peripheral interface (SPI) 124 set carry flag 242, 243 set register pointer 243 shift right arithmetic 245 shift right logical 245 signal descriptions 13 single-shot conversion (ADC) 172 SIO 5 slave data transfer formats (I2C) 146 slave select 127

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 287 software trap 244 source operand 239 SP 239 SPI architecture 124 baud rate generator 131 baud rate high and low byte register 137 clock phase 127 configured as slave 125 control register 132 control register definitions 131 data register 131 error detection 130 interrupts 130 mode fault error 130 mode register 135 multi-master operation 129 operation 125 overrun error 130 signals 126 single master, multiple slave system 125 single master, single slave system 124 status register 134 timing, PHASE = 0 128 timing, PHASE=1 129 SPI controller signals 13 SPI mode (SPIMODE) 135 SPIBRH register 137 SPIBRL register 137 SPICTL register 133 SPIDATA register 132 SPIMODE register 135 SPISTAT register 134 SRA 245 src 239 SRL 245 SRP 243 SS, SPI signal 126 stack pointer 239 status register, I2C 152 STOP 243 STOP mode 49, 243 STOP mode recovery sources 47 using a GPIO port pin transition 48 using watch-dog timer time-out 48 SUB 242 subtract 242 subtract - extended addressing 242 subtract with carry 242 subtract with carry - extended addressing 242 SUBX 242 SWAP 245 swap nibbles 245 symbols, additional 239 system and core resets 44 T TCM 242 TCMX 242 test complement under mask 242 test complement under mask - extended addressing 242 test under mask 242 test under mask - extended addressing 242 timer signals 14 timers 5, 75 architecture 75 block diagram 76 capture mode 80, 89 capture/compare mode 83, 89 compare mode 81, 89 continuous mode 77, 89 counter mode 78 counter modes 89 gated mode 82, 89 one-shot mode 76, 89 operating mode 76 PWM mode 79, 89 reading the timer count values 84 reload high and low byte registers 85 timer control register definitions 84 timer output signal operation 84 timers 0-3 control 0 registers 88 control 1 registers 88 high and low byte registers 84, 87

PS019910-0504 P r e l i m i n a r y Index Z8 Encore!® 64K Series Product Specification 288 TM 242 TMX 242 transmit IrDA data 120 transmit interrupt 140 transmitting UART data-interrupt-driven method 101 transmitting UART data-polled method 100 TRAP 244 U UART 4 architecture 98 asynchronous data format without/with parity 100 baud rate generator 108 baud rates table 116 control register definitions 109 controller signals 14 data format 99 interrupts 106 multiprocessor mode 104 receiving data using interrupt-driven method 103 receiving data using the polled method 102 transmitting data using the interrupt-driven method 101 transmitting data using the polled method 100 x baud rate high and low registers 115 x control 0 and control 1 registers 112 x status 0 and status 1 registers 110, 112 UxBRH register 115 UxBRL register 116 UxCTL0 register 112, 115 UxCTL1 register 113 UxRXD register 110 UxSTAT0 register 110 UxSTAT1 register 112 UxTXD register 109 V vector 238 voltage brown-out reset (VBR) 45 W watch-dog timer approximate time-out delay 92 approximate time-out delays 91 CNTL 46 control register 94 electrical characteristics and timing 224 interrupt in normal operation 92 interrupt in STOP mode 92 operation 91 refresh 92, 243 reload unlock sequence 93 reload upper, high and low registers 95 reset 46 reset in normal operation 93 reset in STOP mode 93 time-out response 92 WDTCTL register 94 WDTH register 96 WDTL register 97 working register 238 working register pair 238 WTDU register 96 X X 238 XOR 244 XORX 244 Z Z8 Encore! block diagram 3 features 1 introduction 1 part selection guide 2