Z8PE002

Z8PE002 ZILOG | Alldatasheet

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*This document is considered preliminary until the completion of full characterization. P RELIMINARY P RODUCT S PECIFICATION Z8PE002 F EATURE NHANCED Z8P LUS 0.5K ROM O NE IME P ROGRAMMABLE (OTP) M ICROCONTROLLER

FEATURES

Microcontroller Core Features All Instructions Execute in one 1-µs Instruction Cycle with a 10-MHz Crystal 512 bytes x 8 On-Chip OTP EPROM Memory 64 x 8 General-Purpose Registers (SRAM) Six Vectored Interrupts with Fixed Priority Operating Speed: DC—10 MHz Six Addressing Modes: R IR X D RA , and IM Peripheral Features

14 Total Input/Output Pins

One 8-Bit I/O Port (Port A) – I/O Bit Programmable – Each Bit Programmable as Push-Pull or Open-Drain One 6-Bit I/O Port (Port B) – I/O Bit Programmable – Includes Special Functionality: Stop-Mode Re- covery Input, Comparator Inputs, Selectable Edge Interrupts, and Timer Output One Analog Comparator 16-Bit Programmable Watch-Dog Timer ( WDT Software Programmable Timers Configurable as: – Two 8-Bit Standard Timers and One 16-Bit Stan- dard Timer – One 16-Bit Standard Timer and One 16-Bit Pulse Width Modulator ( PWM ) Timer Additional Features On-Chip Oscillator that accepts External Crystal XTAL ), Ceramic Resonator, Inductor Capacitor ( LC or External Clocks External Resistor Capacitor ( RC ), an Oscillator Option Voltage Brown-Out/Power-On Reset ( V BO POR Programmable Options: – EPROM Protect RC Oscillator Power Reduction Modes: HALT Mode with Peripheral Units Active STOP Mode for Minimum Power Dissipation CMOS/Technology Features Low-Power Consumption 3.0V to 5.5V Operating Range @ 0 C to +70 C 4.5V to 5.5V Operating Range @ –40 C to +105 C 18-Pin DIP, SOIC, and 20-Pin SSOP Packages GENERAL DESCRIPTION The Z8PE002 is the newest member of the Z8Plus Micro- processor (MPU) family. Similar to the Z8E000 and Z8E001, the Z8PE002 offers easy software development, debug, prototyping, and an attractive One-Time Program- mable (OTP) solution. For applications demanding powerful I/O capabilities, the Z8PE002’s dedicated input and output lines are grouped into two ports, and are configurable under software control. Part Number ROM (Bytes) RAM* (Bytes) Speed (MHz) Z8PE002 512 64 10 Note: *General-Purpose.

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ing/timing and I/O data communications. Figure 1. Functional Block Diagram

Figure 2. EPROM Programming Mode Block Diagram

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Figure 3. 18-Pin DIP/SOIC Pin Identification Table 1. Standard Programming Mode

16 XTAL2 Crystal Oscillator Clock Output

17 XTAL1 Crystal Oscillator Clock Input

18 PB0 Port B, Pin 0 Input/Output

Figure 4. 18-Pin DIP/SOIC Pin Identification Table 2. EPROM Programming Mode

1 PGM Program Mode Input

5 ADCLR/V

15 GND Ground

16 NC No Connection

17 XTAL1 1-MHz Clock Input

18 ADCLK Address Clock Input

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Figure 5. 20-Pin SSOP Pin Identification Table 3. Standard Programming Mode

6 NC No Connection

15 NC No Connection

18 XTAL2 Crystal Oscillator Clock Output

19 XTAL1 Crystal Oscillator Clock Input

20 PB0 Port B, Pin 0 Input/Output

Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode Table 4. EPROM Programming Mode

17 GND Ground

18 NC No Connection

19 XTAL1 1-MHz Clock Input

20 ADCLK Address Clock Input

Z8Plus OTP Microcontroller ZiLOG

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Stresses greater than those listed under Absolute Maximum Ratings can cause permanent damage to the device. This rat- ing is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period can affect device reliability. Total power dissipation should not exceed 880 mW for the package. Power dissipation is calculated as follows: Parameter Min Max Units Note Ambient Temperature under Bias –40 +105 C Storage Temperature –65 +150 C Voltage on any Pin with Respect to V SS –0.6 +7 V 1 Voltage on VDD Pin with Respect to VSS –0.3 +7 V Voltage on PB5 Pin with Respect to VSS –0.6 V DD+1 V 2 Total Power Dissipation 880 mW Maximum Allowable Current out of VSS 40 mA 3 Maximum Allowable Current into VDD 40 mA 3 Maximum Allowable Current into an Input Pin –600 +600 µA 4 Maximum Allowable Current into an Open-Drain Pin –600 +600 µA 5 Maximum Allowable Output Current Sunk by Any I/O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Maximum Allowable Output Current Sunk by Port A 40 mA 3 Maximum Allowable Output Current Sourced by Port A 40 mA 3 Maximum Allowable Output Current Sunk by Port B 40 mA 3 Maximum Allowable Output Current Sourced by Port B 40 mA 3 Notes: 1. Applies to all pins except the PB5 pin and where otherwise noted. 2. There is no input protection diode from pin to V DD. 3. Peak Current. Do not exceed 25mA average current in either direction. 4. Excludes XTAL pins. 5. Device pin is not at an output Low state. Total Power Dissipation = V DD x [IDD – (sum of IOH)] + sum of [(VDD – VOH) x IOH] + sum of (VOL x IOL)

itive current flows into the referenced pin (Figure 7). TA = 25ºC, V CC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Figure 7. Test Load Diagram

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Table 5. DC Electrical Characteristics

1 Min Max Units Conditions Notes

1. Typical values are measured at V CC = 3.3V and VCC = 5.0V; VSS = 0V = GND.
2. For the analog comparator input when the analog comparator is enabled.
3. No protection diode is provided from the pin to V

CC. External protection is recommended.

1. All outputs are unloaded and all inputs are at the V CC or VSS level.
2. Same as note 5, except inputs are at V

Table 5. DC Electrical Characteristics (Continued)

1. Typical values are measured at V CC = 3.3V and VCC = 5.0V; VSS = 0V = GND.
2. For the analog comparator input when the analog comparator is enabled.
3. No protection diode is provided from the pin to V

CC. External protection is recommended.

1. All outputs are unloaded and all inputs are at the V CC or VSS level.
2. Same as note 5, except inputs are at V

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Table 6. DC Electrical Characteristics

1. Typical values are measured at V CC = 5.0V; VSS = 0V = GND.
2. For analog comparator input when analog comparator is enabled.
3. No protection diode is provided from the pin to V

CC. External protection is recommended.

1. All outputs are unloaded and all inputs are at V CC or VSS level.
2. Same as note 5, except inputs are at V

Table 6. DC Electrical Characteristics (Continued)

1. Typical values are measured at V CC = 5.0V; VSS = 0V = GND.
2. For analog comparator input when analog comparator is enabled.
3. No protection diode is provided from the pin to V

CC. External protection is recommended.

1. All outputs are unloaded and all inputs are at V CC or VSS level.
2. Same as note 5, except inputs are at V

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Figure 8. AC Electrical Timing Diagram Table 7. Additional Timing

1 Min Max Units Notes

1. Timing Reference uses 0.7 V CC for a logical 1 and 0.2 VCC for a logical 0.

During RESET, the value of the program counter is 0020H. contents of the general-purpose registers. or unknown from Power-Up are indicated by the letter U. from location 0020H. Figure 9 indicates reset timing. the remaining control registers. Table 8. Control and Peripheral Registers* FF Stack Pointer 0 0 UUUUUU Stack pointer is not affected by RESET. FB Interrupt Mask 00000000 All interrupts masked by RESET.

00000000 All interrupt requests cleared by

00000000 Deactivates all port special functions

00000000 Defines all bits as inputs in PortB after

D5 Port B Output UUUUUUUU Output register not affected by RESET. Note: *The SMR and WDT flags are set to indicate the source of the RESET.

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00000000 Defines all bits as inputs in PortA after

C0 TCTLLO 00000000 All standard timers are disabled. **Table 8. Control and Peripheral Registers* (Continued)** *The SMR and WDT flags are set to indicate the source of the RESET. Table 9. Flag Register Bit D1, D0

00 V BO/POR

Figure 9. Reset Timing Figure 10. Reset Circuitry with POR, WDT, VBO, and SMR

128 XTAL Clock Cycles

10 XTAL CLOCK CYCLES

64 SCLKSMR

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family may define the interrupts differently. gering edge options, and exact programming details. set to 1, the corresponding interrupt requests are enabled. IMASK registers are reset to 00h, disabling all interrupts. while the master enable is set. Table 10. Interrupt Types, Sources, and Vectors

1. Bits 0 to 5 are assigned to interrupt requests

IREQ0 to IREQ5, respectively. Table 11. Interrupt Mask Register—IMASK (FBh) Table 12. Interrupt Request Register–IREQ (FAh)

7 R/W 0 Reserved, must be 0

6 R/W 0 Reserved, must be 0

5 R/W 0

4 R/W 0

3 R/W 0

2 R/W 0

1 R/W 0

0 R/W 0

Z8Plus OTP Microcontroller ZiLOG

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IREQ SOFTWARE INTERRUPT GENERATION IREQ can be used to generate software interrupts by spec- ifying IREQ as the destination of any instruction referencing the Z8Plus Standard Register File. These software inter- rupts ( SWI) are controlled in the same manner as hardware generated requests. In other words, the IMASK controls the enabling of each SWI. To generate a SWI, the request bit in IREQ is set by the fol- lowing statement: OR IREQ,#NUMBER The immediate data variable, NUMBER, has a 1 in the bit position corresponding to the required level of SWI. For ex- ample, an SWI must be issued when an IREQ5 occurs. Bit 5 of NUMBER must have a value of 1. OR IREQ, #00100000B If the interrupt system is globally enabled, IREQ5 is en- abled, and there are no higher priority requests pending, control is transferred to the service routine pointed to by the IREQ5 vector. Note: Software may modify the IREQ register at any time. Care should be taken when using any instruction that modifies the IREQ register while interrupt sources are active. The software writeback always takes precedence over the hardware. If a software writeback takes place on the same cycle as an interrupt source tries to set an IREQ bit, the new interrupt is lost. Nesting of Vectored Interrupts Nesting vectored interrupts allows higher priority requests to interrupt a lower priority request. To initiate vectored in- terrupt nesting, perform the following steps during the in- terrupt service routine:

• PUSH the old IMASK on the stack
• Load IMASK with a new mask to disable lower prior- ity interrupts
• Execute an EI instruction
• Proceed with interrupt processing
• Execute a DI instruction after processing is complete
• Restore the IMASK to its original value by POPing the previous mask from the stack
• Execute IRET Depending on the application, some simplification of the above procedure may be possible. RESET Conditions The IMASK and IREQ registers initialize to 00h on RESET. PROGRAMMABLE OPTIONS EPROM Protect. When selecting the DISABLE EPROM PROTECT/ENABLE TESTMODE option, the user can read the software code in the program memory. ZiLOG’s inter- nal factory test mode, or any of the standard test mode meth- ods, are useful for reading or verifying the code in the mi- crocontroller when using an EPROM programmer. If the user should select the ENABLE EPROM PROTECT/DIS- ABLE TESTMODE option, it is not possible to read the code using a tester, programmer, or any other standard method. As a result, ZiLOG is unable to test the EPROM memory at any time after customer delivery. This option bit only affects the user’s ability to read the code and has no effect on the operation of the part in an appli- cation. ZiLOG tests the EPROM memory before customer delivery whether or not the ENABLE EPROM PRO- TECT/DISABLE TESTMODE option is selected; ZiLOG provides a standard warranty for the part. System Clock Source. When selecting the RC OSCILLA- TOR ENABLE option, the oscillator circuit on the micro- controller is configured to work with an external RC circuit. When selecting the Crystal/Other Clock Source option, the oscillator circuit is configured to work with an external crystal, ceramic resonator, or LC oscillator.

the watch-dog timer is only updated every 64th clock cycle. flag to 0; therefore, the user must clear the flag via software. Figure 11. TCTLHI Register for Control of WDT 0 = WDT disabled in HALT mode*Designates the default value after RESET.

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bits of this register to be written. WDT Time Select (D6, D5, D4). is enabled during HALT mode. Bits 2, 1 and 0. These bits are reserved and must be 0. applied to the timers and interrupt logic. immediately before the HALT instruction. gram execution restarts at 0020H, the reset restart address. Table 13. WDT Time-Out *TpC is an XTAL clock cycle. The default at reset is 001.

ZiLOG Z8Plus OTP Microcontroller DS008700-Z8X0799 P R E L I M I N A R Y 23 STOP MODE OPERATION The STOP mode provides the lowest possible device stand- by current. This instruction turns off the on-chip oscillator and internal system clock. To enter the STOP mode, the Z8Plus only requires a STOP instruction. It is not necessary to execute a NOP instruction immediately before the STOP instruction. The STOP mode is exited by any one of the following resets: POR or a Stop-Mode Recovery source. At reset generation, the processor always restarts the application program at ad- dress 0020H, and the STOP mode flag is set. Reading the STOP mode flag does not clear it. The user must clear the STOP mode flag with software. Note: Failure to clear the STOP mode flag can result in unde- fined behavior. The Z8Plus provides a dedicated Stop-Mode Recovery (SMR) circuit. In this case, a low-level applied to input pin PB0 (I/O Port B, bit 0) triggers an SMR. To use this mode, pin PB0 must be configured as an input and the special func- tion selected before the STOP mode is entered. The Low level on PB0 must be held for a minimum pulse width TWSM. Program execution starts at address 20h, after the POR delay. Notes: 1. The PB0 input, when used for Stop-Mode Recovery, does not initialize the control registers. The STOP mode current (ICC2) is minimized when:

• VCC is at the low end of the device’s operating range
• Output current sourcing is minimized
• All inputs (digital and analog) are at the Low or High rail voltages 2. For detailed information about flag settings, see the Z8Plus User’s Manual. 6F STOP ;enter STOP mode

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onator, LC clock, or an external clock source. more than 4 MHz to restrict EMI noise. Figure 12. Clock Circuit Figure 13. Z8Plus in RC Oscillator Mode

low impedances (not disturbed by stray effects). amplifier, and B = VI/VO is the gain of the feedback element. plifier in its linear region and provide the start-up transition. vides an additional phase shift. low as possible without resulting in overtone operation. to the oscillator pins of the Z8Plus. system ground) to reduce cross talk and noise injection. tem ground noise injection into the oscillator (Figure 15). widely from unit to unit, there is probably a gain problem. Figure 14. Pierce Oscillator with

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• To prevent induced noise, the crystal and load capaci- tors should be physically located as close to the Z8Plus as possible.
• Signal lines should not run parallel to the clock oscil- lator inputs. In particular, the crystal input circuitry and the internal system clock output should be separat- ed as much as possible.
• VCC power lines should be separated from the clock oscillator input circuitry.
• Resistivity between XTAL1 or XTAL2 (and the other pins) should be greater than 10 meg-Ohms. Crystals and Resonators Crystals and ceramic resonators (Figure 16) should exhibit the following characteristics to ensure proper oscillation: Depending on the operation frequency, the oscillator may require additional capacitors, C1 and C2, as illustrated in Figure 16 and Figure 17. The capacitance values are de- pendent on the manufacturer’s crystal specifications.

Figure 15. Circuit Board Design Rules

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lator (LC) network to generate an XTAL clock (Figure 17). is the total series capacitance including parasitics. at the top of the next column. to function as a pair of independent 8-bit standard timers. Figure 19. 16-Bit Standard Timer

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1. An interrupt is generated,
2. Control logic clears the appropriate control

tempt to use timer registers for any other function. tinues counting from the updated value. the same time that the timer reaches 0. 0, the timer initializes to the changed value. time, with no effect on the functionality of the timer. Figure 22. TCTLLO Register (*) indicates auto-reload is active. by cascading 8-bit timers T3 (MSB) and T2 (LSB).

Z8Plus OTP Microcontroller DS008700-Z8X0799 P R E L I M I N A R Y 31 If a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach before an interrupt is generated. In this case, a single interrupt is generated, and the interrupt corresponds to the even 8-bit timer. Example: Timers and are cascaded to form a single 16- bit timer. The interrupt for the combined timer is defined to be generated by timer rather than When a timer pair is specified to act as a single 16- bit timer, the even timer registers in the pair (timer or ) is defined to hold the timer’s least significant byte. In contrast, the odd timer in the pair holds the timer’s most significant byte. In parallel with the posting of the interrupt request, the in- terrupting timer’s count value is initialized by copying the contents of the auto-initialization value register to the count value register. Note: Any time that a timer pair is defined to act as a single 16- bit timer, the auto-reload function is performed automat- ically. All 16-bit timers continue counting while their interrupt re- quests are active and operate independently of each other. If interrupts are disabled for a long period of time, it is pos- sible for the timer to decrement to again before its initial interrupt is responded to. This condition is termed a degen- erate case, and hardware is not required to detect it. When the timer control register is written, all timers that are enabled by the WRITE begin counting from the value in the count register. In this case, an auto-initialization is not per- formed. All timers can receive an internal clock source input only. Each enabled timer is updated every 8th XTAL clock cycle. If and are defined to work independently, then each works as an 8-bit timer with a single auto-initialization reg- ister ( T0ARLO for , and T1ARLO for ). Each timer as- serts its predefined interrupt when it times out, optionally performing the auto-initialization function. If and are cascaded to form a single 16-bit timer, then the single 16- bit timer is capable of performing as a Pulse-Width Mod- ulator (PWM). This timer is referred to as T01 to distinguish it as having special functionality that is not available when T0 and T1 act independently. When T01 is enabled, it can use a pair of 16-bit auto-ini- tialization registers. In this mode, one 16-bit auto-initial- ization value is composed of the concatenation of T1ARLO and T0ARLO. The second auto-initialization value is com- posed of the concatenation of T1ARHI and T0ARHI. When T01 times out, it alternately initializes its count value using the Low auto-init pair, followed by the High auto-init pair. This functionality corresponds to a PWM. That is, the interrupt defines the end of the High section of the wave- form, and the T0 interrupt marks the end of the Low portion of the PWM waveform. The PWM begins counting with whatever data is held in the count registers. After this value expires, the first reload de- pends on the state of the PB1 pin if TOUT mode is selected. Otherwise, the Low value is applied first. After the auto-initialization is completed, decrementing oc- curs for the number of counts defined by the PWM_LO reg- isters. When decrementing again reaches 0, the T0 interrupt is asserted; and auto-init using the PWM_HI registers oc- curs. Decrementing occurs for the number of counts defined by the PWM_HI registers until reaching 0. From there, the T1 interrupt IRQ2 is asserted, and the cycle begins again. The internal timers can be used to trigger external events by toggling the PB1 output when generating an interrupt. This functionality can only be achieved in conjunction with the port unit defining the appropriate pin as an output signal with the timer output special function enabled. In this mode, the port output is toggled when the timer count reaches and continues toggling each time that the timer times out. TOUT Mode The PortB special function register PTBSFR (0D7H; Figure 23) is used in conjunction with the Port B directional control register PTBDIR (0D6; Figure 24) to configure PB1 for TOUT operation for T0. In order for TOUT to function, PB1 must be defined as an output line by setting PTBDIR bit 1 to 1. Configured in this way, PB1 is capable of being a clock output for T0, toggling the PB1 output pin on each T0 time- out. At end-of-count, the interrupt request line (IRQ0), clocks a toggle flip-flop. The output of this flip-flop drives the TOUT line, PB1. In all cases, when T0 reaches its end-of-count, TOUT toggles to its opposite state (Figure 25). If, for exam- ple, T0 is in Continuous Counting Mode, TOUT exhibits a 50-percent duty cycle output. If the timer pair is selected T01) as a PWM, the duty cycle depends on the High and Low reload values. At the end of each High time, PB1 tog- gles Low. At the end of each Low time, PB1 toggles HI.

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Figure 23. PortB Special Function Register Figure 24. Port B Directional Control Register Figure 25. Timer T0 Output Through T OUT

A is an 8-bit port, bit programmable as either inputs or outputs. input, and external interrupt inputs. bit position only affect the bit in question. Each port is defined by a set of four control registers (Figure 26). port bit operates as input or output. tionality that can be defined for each particular port bit. Figure 26. Port A Configuration with Open-Drain Capability and Schmitt-Trigger Table 14. I/O Ports Registers

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not changed and do not exhibit any effect on the hardware. do not sample the value being driven out. put register is driven directly onto the output pin. the Schmitt-trigger on the input is disabled to save power. trol and special function registers. priately, and all initialization is completed. corresponding bit in Port A as an input. special function register (PTASFR, Figure 26). Figure 27. Port A Directional Control Register

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Port B is a 6-bit (bidirectional), CMOS-compatible I/O port. INPUT while another bit is set to OUTPUT. Port B provide special functionality as indicated in Table 15. PB5 acts as the VPP pin for EPROM programming mode. Table 15. Port B Special Functions Figure 32. Port B Special Function Register

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Figure 35. Port B Pin 1 Diagram

Figure 36. Port B Pin 2 Diagram

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Figure 37. Port B Pins 3 and 4 Diagram

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Figure 41. Port B Special Function Register

ZiLOG Z8Plus OTP Microcontroller DS008700-Z8X0799 P R E L I M I N A R Y 43 I/O PORT RESET CONDITIONS Full Reset Port A and Port B output value registers are not affected by RESET. On RESET, the Port A and Port B directional control reg- isters are cleared to all zeros, which defines all pins in both ports as inputs. On RESET, the directional control registers redefine all pins as inputs, and the Port A and Port B input value registers overwrites the previously held data with the current sample of the input pins. On RESET, the Port A and Port B special function registers are cleared to 00h, which deactivates all port special func- tions. Note: The SMR and WDT time-out events are not full device resets. The port control registers are not affected by ei- ther of these events. ANALOG COMPARATOR The device includes one on-chip analog comparator. Pin PB4 features a comparator front end. The comparator ref- erence voltage is on pin PB3. Comparator Description The on-chip comparator can process an analog signal on PB4 with reference to the voltage on PB3. The analog func- tion is enabled by programming the Port B special function register bits 3 and 4. When the analog comparator function is enabled, bit 4 of the input register is defined as holding the synchronized out- put of the comparator, while bit 3 retains a synchronized sample of the reference input. If the interrupts for PB4 are enabled when the comparator special function is selected, the output of the comparator generates interrupts. COMPARATOR OPERATION The comparator output reflects the relationship between the analog input to the reference input. If the voltage on the an- alog input is higher than the voltage on the reference input, then the comparator output is at a High state. If the voltage on the analog input is lower than the voltage on the reference input, then the analog output is at a Low state. Comparator Definitions VICR The usable voltage range for the positive input and reference input is called the Comparator Input Common Mode Voltage Range ( VICR). Note: The comparator is not guaranteed to work if the input is outside of the VICR range. VOFFSET The absolute value of the voltage between the positive input and the reference input required to make the comparator output voltage switch is the Comparator Input Offset Volt- age ( VOFFSET). IIO For the CMOS voltage comparator input, the input offset current (IIO) is the leakage current of the CMOS input gate. HALT Mode The analog comparator is functional during HALT mode. If the interrupts are enabled, an interrupt generated by the comparator causes a return from HALT mode. STOP Mode The analog comparator is disabled during STOP mode. The comparator is powered down to prevent it from drawing any current. Low Voltage Protection. An on-board Voltage Compar- ator checks that the VCC is at the required level to ensure correct operation of the device. A reset is globally driven if VCC is below the specified voltage (Low Voltage Protec- tion). The device functions normally at or above 3.0V under all conditions, and is guaranteed to function normally at supply voltages above the Low Voltage Protection trip point. Be- low 3.0V, the device functions normally until the Low Volt-

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only, but is disabled in STOP mode (Figure 42). Figure 42. Voltage vs. Temperature

Z8Plus OTP Microcontroller ZiLOG

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PACKAGE INFORMATION

Figure 45. 18-Pin DIP Package Diagram Figure 46. 18-Pin SOIC Package Diagram

Figure 47. 20-Pin SSOP Package Diagram

Z8Plus OTP Microcontroller ZiLOG

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ORDERING INFORMATION

For fast results, contact your local ZiLOG sales office for assistance in ordering the part(s) required. Example: The Z8PE002PZ010SC is a 10-MHz DIP, 0ºC to 70ºC, with Plastic Standard Flow. Pre-Characterization Product The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. ©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG, Inc.

910 East Hamilton Avenue, Suite 110

Campbell, CA 95008 Telephone (408) 558-8500 FAX 408 558-8300 Internet: http://www.zilog.com Standard Temperature 18-Pin DIP Z8PE002PZ010SC 18-Pin SOIC Z8PE002SZ010SC 20-Pin SSOP Z8PE002HZ010SC Extended Temperature 18-Pin DIP Z8PE002PZ010EC 18-Pin SOIC Z8PE002SZ010EC 20-Pin SSOP Z8PE002CZ010EC Codes Preferred Package PZ = Plastic DIP Longer Lead Time SZ = SOIC HZ = SSOP Speed 010 = 10 MHz Standard Temperature S = 0°C to +70°C Extended Temperature E = –40°C to +105°C Environmental Flow C = Plastic Standard Z ZiLOG Prefix 8PE Z8Plus Product

002 Product Number

010 Speed

SC Temperature and Environmental Flow