Z8L38210ASC

Z80382 ZILOG | Alldatasheet

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P RELIMINARY P RODUCT S PECIFICATION Z80382, Z8L382 H IGH ERFORMANCE D ATA C OMMUNICATIONS P ROCESSORS

FEATURES

n Embedded Z380 ª Microprocessor Ð Maintains Object Code Compatibility with Z80 and Z180 ª Microprocessors Ð Enhanced Instruction Set for 16-Bit Operation Ð 16 MB Linear Addressing Ð Two Clock Cycle Instruction Execution Minimum Ð Four On-Chip Register Banks Ð BC/DE/HL/IX/IY Augmented to 32 Bits Ð Clock Divide-by-Two and Multiply-by-Two Options Ð Fully Static CMOS Design with Low-Power Standby Mode Ð 16-Bit Internal Bus Ð Dynamic Bus Sizing (8/16-Bit Inter-Operability) n

16550 Mimic with I/O Mailbox, DMA Mailbox, and 16 mA

n Three HDLC Synchronous Serial Channels Ð Serial Data Rate of up to 10 Mbps n GCI/SCIT Bus Interface n Eight Advanced DMA Channels with 24-Bit Addressing n Plug-and-Play ISA Interface n PCMCIA Interface n Two Enhanced ASCIs (UARTs) with 16-Bit Baud Rate Generators (BRG) n Clocked Serial I/O Channel (CSIO) for Use with Serial Memory n Two 16-Bit Timers with Flexible Prescalers n Three Memory Chip Selects with Wait-State Generators n Watch-Dog Timer (WDT) n Up to 32 General-Purpose I/O Pins n DC to 20 MHz Operating Frequency @ 5.0V n DC to 10 MHz Operating Frequency @ 3.3V n 144-Pin QFP and VQFP Style Packages GENERAL DESCRIPTION The Z80382 (Z382) is designed to address high-end data communication applications such as digital modems (IS- DN, GSM, Mobitex & Modacom), xDSL and analog mo- dems (V.34 and beyond). The Z382 provides a perfor- mance upgrade to existing Z80- and Z18x-based designs by utilizing the increased bandwidth of the 380C proces- sor. The Z8L382 is a low voltage version of the device. Note: In this document the notation Ò380CÓ denotes the Z380-compatible CPU core which is embedded in the Z382. The 380C microprocessor is a high-performance proces- sor with fast and efficient throughput and increased mem- ory addressing capabilities. The 380C offers a continuing growth path for present Z80- or Z18x-based designs, while maintaining Z80 and Z180 object code compatibility. Its en- hancements include added instructions, expanded16 MB address space and flexible bus interface timing. In the 380C, the basic addressing modes of the Z80 micro- processor have been augmented to include Stack Pointer Relative loads and stores, 16-bit and 24-bit indexed off- sets, and more flexible Indirect Register addressing. Inter- nally, all of the addressing modes allow up to 32-bit linear addressing; however, because the Z382 has only 24 ad- dress pins, it can only address 16 MB of memory.

High-Performance Data Communications Processors Zilog P R E L I M I N A R Y DS97Z382000 GENERAL DESCRIPTION (Continued) Other additions to the instruction set include a full comple- ment of 16-bit arithmetic and logical operations, 16-bit I/O operations, multiply and divide, and a complete set of reg- ister-to-register loads and exchanges. The 380C register file includes alternate versions of the IX and IY registers. There are four banks of registers in the 380C, along with instructions for switching among them. All of the 16-bit register pairs and index registers in the ba- sic Z80 microprocessor register file are expanded to 32 bits. The Z382 includes dynamic bus sizing to allow any mix of 16- and 8-bit memory, and I/O devices in a system. One application for this capability would be to copy code from a low-cost, slow 8-bit ROM to 16-bit RAM, from which it can be executed at much higher speeds. Memory bus sizes can be configured internally by software to eliminate the need for external logic to drive MSIZE. Some features that have traditionally been handled by ex- ternal peripherals have been incorporated in the Z382. These on-chip peripherals reduce system chip count and interconnections on the external bus. These peripherals, il- lustrated in the Z382 Block Diagram in Figure 1, are sum- marized below. HDLC Synchronous Channels. Three HDLC channels operate at serial data rates of up to 10 Mbps and feature 8-byte receive and transmit FIFOs. These can be used for modems, general data communications, and ISDN. The ISDN can be handled separately or through the GCI/SCIT bus interface. HDLC Channels always transfer data through the DMA channels. A transparent mode is select- able. Two of the HDLC cells can be pin multiplexed with the ASCIs (UARTs) to provide dynamically switchable (async-sync) DTE interfaces. DMA Channels . The eight DMA channels provide 24-bit memory addressing and can transfer memory block sizes of up to 64 KB (16-bits). These DMA channels can be dy- namically assigned to serve the HDLC ports, Mimic COM port, Host DMA Mailbox, or ASCIs in any mixture. Linked list operation allows all HDLC transmitters and receivers to operate at or above E1 rates simultaneously without load- ing the bus bandwidth.

16550 Mimic

. Provides connection to a PC ISA bus and emulation of the 16550 UART register set. Improvements include 16 mA output drivers and internal COM port ad- dress decoding to reduce external PC interface compo- nents. ASCI . Two flexible asynchronous serial channels with baud rate generators, modem control and status. CSIO . A clocked serial I/O channel which can be used for serial memory interface. Timers . Two 16-bit counter/timers with flexible prescalers for wide-range timing applications. GCI/SCIT Bus Interface . A common interface to ISDN in- terface devices. Internal signals from this module can be connected to the HDLC channels to provide B-channels and D-channel for ISDN. Plug-and-Play ISA Interface . Provides auto-configura- tion in ISA (AT bus) applications. PCMCIA Interface . Provides connectivity to a PCMCIA bus. 32-Bit General-Purpose I/O . For non-PC add-in applica- tions, four 8-bit ports are provided for general- purpose I/O. In ISA or PCMCIA applications, the pins from two of the ports are reallocated to host bus signals and are not avail- able. Pins from the other two ports are selectively multi- plexed with on-chip peripheral functions (ASCIs, CSI/O, PRT). These pins are individually programmable for in- put/output mode. I/O Chip Selects. Two I/O chip selects are provided to support I/O access of external peripherals. Each has a pro- grammable base address and provides I/O decode sizes ranging from 8 to 512 bytes. ROM/RAM Chip Selects with Wait-State Generators Chip select outputs are provided to decode memory ad- dresses and provide memory chip enables. Each chip se- lect has its own Wait State Generator to allow use of mem- ories with different speeds. Watch-Dog Timer . A Watch-Dog Timer (WDT) with a wide range of time-constants prevents code runaway and pos- sible resulting system damage. The /RESET input can be forced as an output upon the terminal count of the WDT. This allows external peripherals to be reset along with the Z382.

Figure 1. Z80382 Block Diagram

Figure 2. Z80382 144-Pin QFP and VQFP Pin Description

may affect device reliability. into the referenced pin (Figure 3, Test Load Diagram). All AC parameters assume a load capacitance of 50 pF. Figure 3. Test Load Diagram

High-Performance Data Communications Processors Zilog P R E L I M I N A R Y DS97Z382000 DC CHARACTERISTICS Pin Numbers and Input/Output Classifications Pin Input Class Output Class Pin Number(s) /BHEN O 118 /BLEN O 119 /BUSACK O 132 /BUSREQ I 133 /CTS0//HRD//PCIORD I 61 /CTS0//TREFA I O 111 /CTS1//HWR//PCIOWR I 60 /CTS1//TREFC I O 110 /DCD0//HDAK0//PCWE I 89 /DCD0//TREFR I O 112 /DCD1/HA9 I 66 /HALT O 121 /INT0-3 R 136 - 139 /IORD I 3 125 /IORQ I 3 115 /IOWR I 3 123 /M1 I 3 116 /MRD I 3 126 /MSIZE I D 117 /MWR I 3 124 /NMI R 135 /RAMCSL O 43 /RESET R D 134 /ROMCS O 42 /RTS0/HINT2/STSCHG H 88 /STNBY O 120 /TXEN1-0//RTS1-0 O 94 -93 /WAIT I D 130 A23-0 I 3 141 - 144, 1 - 4, 6 - 13, 15 - 22 BUSCLK H 127 CKA0/HDRQ1/PCRESET I H 92 CKA1/HA10 I 3 65 CKS/HA11 I 3 64 CLKI R 128 CLKO O 129 D15-0 I 3 24 - 31, 33 - 40 DCL/RXC2/BCL2 I 106 DD/TXD2 I D (DD) O (TXD2) 107 DU/TXC2/FSC2 I D (DU) O (TXC2, FSC2) 105 FSC/RXD2 I 108 IOCLK I O 114 PA7-0/HD7-0 I H 78 -85 PB0/CKS I 3 58

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y PB1/RXS i 3 57 PB2/TXS I 3 56 PB3/RXA1 I 3 55 PB4/TXA1 I 3 54 PB5/CKA0 I 3 53 PB6/RXA0 I 3 52 PB7/TXA0 I 3 51 PC2//TXEN2/TOUT I 3 109 PC3/CKA1 I 3 49 PC4/IEO I 3 48 PC5/IEI I 3 47 PC6//IOCS1 I 3 45 PC7//RAMCSH I 3 44 PD7-0/HA7-0 I 3 69 - 76 RXA0//HDAK1//PCOE I D 90 RXA1/HA8 I 3 67 RXC1-0/BCL1-0/PC1-0 I 3 101, 97 RXD1-0/RXA1-0 I O 103, 99 RXS/HAEN//PCREG I D 63 TOUT//IOCS2 3 46 TXA0/HDRQ0//PCCE1 I H 91 TXA1/HINT1//PCIRQ H 87 TXC1-0/FSC1-0/CKA1-0 I 3 100, 96 TXD1-0/TXA1-0 O 102, 98 TXS//HDOEN//INPACK O 62 V DD 5, 23, 41, 59, 77, 95, 113, 131 VSS 14, 32, 50, 68, 86, 104, 122, 140 Note: 1. Characteristics of each pin are listed in terms of the classifications in the DC Characteristics Tables 1 and 2 which follow. Pin Input Class 1 Output Class1 Pin Number(s)

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Specifications apply over Standard Operating Conditions unless otherwise noted. Table 1. Output Class Characteristics

1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific output pins in each
2. Applies to Output only or I/O.

Table 2. Input Class Characteristics Note: Inputs of this type include a weak-latch circuit, except that a register bit can disable those for pins PB7-0. Note: Inputs of this type except CLKI include a weak-latch circuit.

1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific input pins in each cla ss.

Table 3. DC Electrical Characteristics

1. On-chip peripherals with independent clocks are inactive (not being clocked).
2. BUSCLK is the internal processor clock frequency.

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380C Processor Timing (See Figure 4) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Symbol Parameter Z80382 Z8L382 Notes UnitMin. Max. Min. Max. t1 Clock Cycle Time 25 DC 50 DC 1 ns t2 Clock High Time 10 20 1 ns t3 Clock Low Time 10 20 1 ns t4 Clock Rise Time 3 5 1 ns t5 Clock Fall Time 3 5 1 ns t6 CLKI Low to BUSCLK High Delay 25 35 ns t7 CLKI High to BUSCLK Low Delay 25 35 ns t8 BUSCLK High to Output Valid 10 10 2 ns t9 BUSCLK Low to Output Valid 10 10 3 ns t10 Input Setup to BUSCLK Rise 10 15 4 ns t11 Input Hold from BUSCLK High 0 0 4 ns t12 /BUSREQ Setup to BUSCLK Fall 10 15 5 ns t13 /BUSREQ Hold from BUSCLK Low 0 0 5 ns t14 /WAIT Setup to BUSCLK Rise 10 15 6 ns t15 /WAIT Hold from BUSCLK High 0 0 6 ns t16 /WAIT Setup to BUSCLK Fall 15 15 6 ns t17 /WAIT Hold from BUSCLK Low 0 0 6 ns t18 /NMI Width Low 15 15 ns t19 /RESET Width Low 10 10 t1 t20 /INT1, /INT2, /INT3 Low Width 15 15 7 ns t21 /INT1, /INT2, /INT3 High Width 15 15 7 ns Notes: 1. Applies to the oscillator or external clock input. The maximum internal clock frequency (BUSCLK) is limited to 20 MHz for the Z80382 and 10 MHz for the Z8L382. Input clock frequencies greater than these values must use the CLKI/2 mode for creating BUSCLK. This is the default state after Reset. 2. Applies to A23-0, /BHEN, /BLEN, IOCLK, /IOCS1, /IOCS2, /ROMCS, /RAMCSL, /RAMCSH, /M1, /BUSACK, /MRD, /MWR, /TRE- FA, /TREFC, /TREFR 3. Applies to D15-0, /HALT, /STNBY, /IORQ, /IORD, /IOWR, /MSIZE, /BUSACK, /MRD, /MWR, /TREFC, /TREFR 4. Applicable for Data Bus and /MSIZE inputs. 5. /BUSREQ can also be asserted/deasserted asynchronously. 6. External waits asserted at /WAIT input. 7. In edge-triggered mode.

Figure 4. 380C Processor Timing

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Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. UnitParameter Min. Max. Min. Max. Note: Timings also apply for reads from registers located in the attribute memory space. Figure 5. Host - PCMCIA Attribute Memory Read Timing

Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. UnitParameter Min. Max. Min. Max. Note: Timings also apply for writes to registers located in the attribute memory space. Figure 6. Host - PCMCIA Attribute Memory Write Timing

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Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 7. Host - PCMCIA I/O Read Timing

Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 8. Host PCMCIA I/O Write Timing

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Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 9. Timer Output Timing

Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 10. CSI/O Receive and Transmit Timing

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Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 11. ASCI Transmitter Timing

Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 12. ASCI Receiver Timing

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Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 13. Baud Rate Generator Timing

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Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Figure 16. General-Purpose I/O Port Timing

Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Units NotesMin. Max. Min. Max. Note: 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual. Figure 17. HDLC Receive Timing (Full Time HDLC, RxC Input) Note 1. HDLC clock triggering polarity is configurable by means of RIRn[6]. See Z80382 User Manual.

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Figure 18. HDLC Receive Timing (Full Time HDLC, RxC Output) Note 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual.

Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Units NotesMin. Max. Min. Max. Figure 19. HDLC Transmit Timing (Full Time HDLC)

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Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Units NotesMin. Max. Min. Max. Note: 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual. Figure 20. HDLC Timing - Non-GCI TDM Mode (Shown for Start = 3, Length = 2, Negative Edge RxD Sampling)

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 27 GCI/SCIT Timing - Slave Characteristics (See Figure 21) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. GCI/SCIT Timing - Master Characteristics (See Figure 21) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Symbol Parameter Z80382 Z8L382 UnitsMin. Max. Min. Max. t131 DCL Data Clock Rise/Fall Time 5 10 ns t132 DCL Clock Period 50 50 ns t133 DCL Pulse Width High 15 15 ns t134 FSC Setup to DCL Fall 30 30 ns t135 FSC Hold from DCL Low 5 10 ns t136 DCL High to DU/DD Transmit Data Valid 15 20 ns t137 FSC High to DU/DD Transmit Data Valid 15 20 ns t138 DU/DD Receive Data Setup to DCL Fall 15 20 ns t139 DU/DD Receive Data Hold from DCL Low 0 0 ns Symbol Parameter Z80382 Z8L382 UnitsMin. Max. Min. Max. t131 DCL Data Clock Rise/Fall Time 5 10 ns t132 DCL Clock Period 50 50 ns t133 DCL Pulse Width High 15 15 ns t134 FSC Setup to DCL Fall 30 30 ns t135 FSC Hold from DCL Low 5 10 ns t136 DCL High to DU/DD Transmit Data Valid 15 20 ns t137 FSC High to DU/DD Transmit Data Valid 15 20 ns t138 DU/DD Receive Data Setup to DCL Fall 15 20 ns t139 DU/DD Receive Data Hold from DCL Low 0 0 ns t140 FSC High from DCL High 0 0 ns

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Low state and negated in the High state. such pins are described using their function in that mode. depending on the mode under which the Z382 is operating. that the signal may be assigned to pin ÒxxÓ or pin ÒyyÓ. Figure 21. GCI/SCIT Slave and Master Timing

Table 4. MPU Signals /BLEN, /MRD, /MWR, /IORQ, /IORD, and /IOWR. formed to transfer the other data byte, also on D7-0. to transfer the other data byte, also on D7-0. only for those using a Z380 Emulator in a Z382-based project. maskable interrupt requests. divided by two or times two. should be attached to D15-8 (this difference tends to equalize electrical loading). low- or high-level sensitive, or as falling- or rising-edge triggered.

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abled, in which case BUSCLK is the timing reference for I/O transactions. Note: The INTACK output of the Z380 has been omitted on the Z382 for pinning reasons. read and write transactions and interrupt acknowledge transactions. data from the peripherals during I/O read transactions. data into the peripherals during I/O write transactions. devices. The base I/O address and range are programmable. sy-chaining by devices that include explicit clearing of IUS (for example, SCC). until the end of T4 during memory read transactions. they are enabled in 8-bit mode and the address falls within their range.

memory location should store the data on the databus, as qualified by /BHEN and /BLEN. /MWR is active from the end of T2 until the end of T4 during memory write transactions. the maskable interrupt inputs /INT3-/INT0. to initialize the Z382. The effect of /RESET is described in detail in the Reset section. or as the /RAS signal at higher processor clock rates. refresh transaction. It can be used as the /CAS signal for DRAM accesses. refresh transaction. It can be used as the /RAS signal for DRAM accesses. insert Wait states into the current bus transaction. Table 5. UART, Timer and CSIO Signals Clear to Send 0, 1 (Inputs, active Low): Transmit control signals for the ASCI channels. nels. /DCD1 is not available in ISA applications.

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Receive Data 0, 1 (Inputs): ASCI Receive data. Transmit Data 0, 1 (Outputs): ASCI Transmit data. CKS 58/64 Serial Clock (Bidirectional): The clock for the CSIO channel. RXS 57/63 Clocked Serial Receive Data (Input): Receive data for the CSIO channel. TXS 56/62 Clocked Serial Transmit Data (Output): Transmit data from the CSIO channel. TOUT 46/109 Timer Out (Output, active High): Pulse output from PRT1. Table 6. ISA Bus Signals HD7-0 78 - 85 Host Data Bus (Input/Output, tri-state): ISA or PCMCIA data bus. accesses. Bits 11-10 are decoded only by the Plug and Play ISA module. write operation is taking place. that a read operation is taking place. controller has acknowledged the request and is transferring data. fer operation from the Host.

Table 7. Parallel Ports tions all four ports are available with minimal multiplexing. Table 8. HDLC Serial Channel and GCI/SCIT Signals trollers when they are not operating by means of the GCI/SCIT interface. lers when they are not operating by means of the GCI/SCIT interface. non-GCI TDM mode, these pins carry the Frame Sync pulse. HDLC Clock/Bit Clock (inputs): Optional external bit clock inputs. enable an external driver on the TxD line. al data streams of the GCI/SCIT interface. DCL 106 GCI/SCIT Clock (input): Bit clock for the GCI/SCIT interface. FSC 108 GCI/SCIT Frame Sync (input): This pin is used to synchronize the GCI/SCIT serial frames.

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Table 9. PCMCIA Interface Signals uration registers, and Mimic. Decoded by the I/O address decoder. Mimic, the attribute memory, and the configuration registers. read cycle is within the configured range, and reads from the Mimic. /PCIOWR 60 PCMCIA I/O Write (input, active Low): This signal is used to write to the Mimic. a read from attribute memory or a configuration register as selected by HA9-1. to: an even addressed byte in attribute memory, a configuration register, or the Mimic. cess to the attribute memory range or to the I/O address range. PACK is activated with /PCIORD. Host. This choice is made by means of bit 6 of the Configuration Option Register. PCRESET 92 PCMCIA Reset (input, active High): Setting PCRESET High resets the PCMCIA interface. controller, and the Ready/Busy (/PCIRQ) signal has to be deactivated. uleÕs 380C Control Register.

ther described in the sections which follow. bus bandwidth and instruction fetch/execute overlap. with a 32-bit ALU and 32-bit registers. Table 10. Other Signals CLKI 128 Clock/Crystal (input, active High): An externally generated clock can be input at this pin. or multiplied by two, under software control. disabled by software to save power and noise when an external clock is used. this signal should be connected to the IEI input of the highest-priority such device. the same voltage externally.

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CENTRAL PROCESSING UNIT (Continued) because of the possibility of "misplacing" interrupt service routines or vector tables during the translation from Ex- tended mode back to Native mode. In addition to Native and Extended mode, which is specific to memory space addressing, the 380C can operate in ei- ther Word or Long Word mode specific to data load and ex- change operations. In Word mode (the reset configura- tion), all word load and exchange operations manipulate 16-bit quantities. For example, only the low-order words of the source and destination are exchanged in an exchange operation, with the high-order words unaffected. In Long Word mode, all 32 bits of the source and destina- tion are exchanged. The 380C implements two instruc- tions plus decoder directives to allow switching between Word and Long Word modes. The two instructions perform a global switch, while the decoder directives select a par- ticular mode only for the instruction that they precede. Note that all word data arithmetic (as opposed to address manipulation arithmetic), rotate, shift and logical opera- tions are always in 16-bit quantities. They are not con- trolled by either the Native/Extended or Word/Long Word selections. The exceptions to the 16-bit quantities are, of course, those multiply and divide operations with 32-bit products or dividends. Lastly, all word input/output operations are performed on 16-bit values. CPU Address Spaces The 380C architecture supports five distinct address spac- es corresponding to the different types of locations that can be accessed by the CPU. These five address spaces are: CPU register space, CPU control register space, memory address space, and I/O address space (on-chip and external). CPU Register Space The CPU register space is shown in Figure 26 and con- sists of all of the registers in the CPU register file. These CPU registers are used for data and address manipula- tion, and are an extension of the Z80 CPU register set, with four sets of this extended Z80 CPU register set present in the 380C. Access to these registers is specified in the in- struction, with the active register set selected by bits in the Select Register (SR) in the CPU control register space. Primary and Working Registers. The working register set is divided into the two register files; the primary file and the alternate file (designated by Ô). Each file contains an 8- bit Accumulator (A), a Flag register (F), and six general- purpose registers (B, C, D, E, H, and L). Only one file can be active at any given time, although data in the inactive file can still be accessed. Exchange instructions allow the programmer to exchange the active file with the inactive file. The accumulator is the destination register for 8-bit arith- metic and logical operations. The six general-purpose reg- isters can be paired (BC, DE, and HL), and are extended to 32 bits by the ÔzÕ extension to the register to form three 32-bit general-purpose registers. The HL register serves as the 16-bit or 32-bit accumulator for word operations. CPU Flag Register. The Flag register contains six flags that are set or reset by various CPU operations: Index Registers. The four Index registers, IX, IXÕ, IY and IYÕ, each hold a 32-bit base address that is used in the In- dexed addressing mode. The Index registers can also function as general-purpose registers with the upper and lower bytes of the lower 16 bits being accessed individual- ly. Interrupt Register. The Interrupt register (I) is used in in- terrupt modes 2 and 3 for /INT0 to generate a 32-bit indi- rect address to an interrupt service routine. The I register supplies the upper 24 or 16 bits of the indirect address and the interrupting peripheral supplies the lower 8 or 16 bits. In the Assigned Vectors mode for /INT1-3, the upper 16 bits of the vector are supplied by the I register; bits 15-9 are the assigned vector base and bits 8-0 are the assigned vector unique to each of /INT1-3. Program Counter. The Program Counter (PC) is used to sequence through instructions in the currently executing program and to generate relative addresses. The PC con- tains the 32-bit address of the current instruction being fetched from memory. In the Native mode, the PC is effec- tively only 16 bits long, as carries from bit 15 to bit 16 are inhibited in this mode. In Extended mode, the PC is al- lowed to increment across all 32 bits. R Register. The R register can be used as a general-pur- pose 8-bit read/write register. Ð Carry Ð Add/Subtract Ð Parity/Overßow Ð Half Carry Ð Zero Ð Sign

addressing allows parameter passing using the SP. terrupt mode in effect, and other items of this type. present on the upper byte of the external data bus. dress, data and control busses. Figure 22. 380C Processor Core Register Set

4 Sets of Registers

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CENTRAL PROCESSING UNIT (Continued) tion) and the Rotate Digit instructions. Bytes are operated on by 8-bit load, arithmetic, logical, and shift and rotate in- structions. Words are operated on in a similar manner by the word load, arithmetic, logical, and shift and rotate in- structions. Block move and search operations can manip- ulate byte strings and word strings up to 64 KB or words long. Block I/O instructions have identical capabilities. Addressing Modes Addressing modes are used by the 380C to calculate the effective address of an operand needed for execution of an instruction. Seven addressing modes are supported by the CPU. Of these seven, one is an addition to the Z80 CPU addressing modes (Stack Pointer Relative) and the re- maining six modes are either existing or extensions to the Z80 CPU addressing modes. Register Addressing The operand is one of the 8-bit registers (A, B, C, D, E, H, L, IXU, IXL, IYU, IYL, A', B', C', D', E', H' or L'); or is one of the 16-bit or 32-bit registers (BC, DE, HL, IX, IY, BC', DE', HL', IX', IY' or SP) or one of the special registers (I or R). Immediate Addressing The operand is in the instruction itself and has no effective address. The DDIR IB and DDIR IW decoder directives al- low specification of 24-bit and 32-bit immediate operands, respectively. Indirect Register Addressing The contents of a register specify the effective address of an operand. The HL register is the primary register used for memory accesses, but BC and DE can also be used. (For the JP instruction, IX and IY can also be used for in- direction.) The BC register is used for I/O space accesses. Direct Addressing The effective address of the operand is the location whose address is contained in the instruction. Depending on the instruction, the operand is either in the I/O or memory ad- dress space. Sixteen bits of direct address is the norm, but the DDIR IB and DDIR IW decoder directives allow 24-bit and 32-bit direct addresses, respectively. Indexed Addressing The effective address of the operand is the location com- puted by adding the two's-complement signed displace- ment contained in the instruction to the contents of the IX or IY register. Eight bits of index is the norm, but the DDIR IB and DDIR IW decoder directives allow 16-bit and 24-bit indexes, respectively. Program Counter Relative Addressing An 8-, 16- or 24-bit displacement contained in the instruc- tion is added to the Program Counter to generate the ef- fective address. This mode is available only for Jump and Call instructions. Stack Pointer Relative Addressing The effective address of the operand is the location com- puted by adding the two's-complement signed displace- ment contained in the instruction to the contents of the Stack Pointer. Eight bits of index is the norm, but the DDIR IB and DDIR IW decoder directives allow 16- and 24-bit in- dexes, respectively. Instruction Set The 380C instruction set is an expansion of the Z80 in- struction set; the enhancements include support for addi- tional addressing modes and a number of new instruc- tions. The 380C is opcode compatible with the Z80 CPU and Z180 MPU. Thus, a Z80/Z180 program can be executed on the 380C without modification. The instruction set is divided into 12 groups by function; these are listed below. Consult the Z380 UserÕs Manual for additional details on the instruction set. Ð 8-bit Load/Exchange Ð 16/32-bit Load, Exchange, Swap and Push/Pop Ð Block Transfers and Search Ð 8-bit Arithmetic and Logical Operations Ð 16/32-bit Arithmetic Operations Ð 8-bit Bit Manipulation, Rotate and Shift Ð 16-bit Rotates and Shifts Ð Program Control Ð I/O Operations (Internal) Ð I/O Operations (External) Ð CPU Control Ð Decoder Directives

the 16x50 register set and the same interrupt structure. the register set by the internal processor of the Z382. or all interrupts can be disabled by writing a single bit. or whether A15-8 must be zero to access the registers. put in high-speed applications. Figure 23. 16550 Mimic Block Diagram

16550 Mimic Side or Host Side Interface

40 P R E L I M I N A R Y DS97Z382000

have the respective error bit set. BRG to achieve the correct delay interval for timeout. FIFO 380C write or Host read access. empty or the 380C reads the IUS/IP register. Figure 24. 16550 Mimic Receiver FIFO Block Diagram

16550 Mimic or PC Side Interface

non-empty or the IIR register is read by the Host. a corresponding interrupt to the 380C. Figure 25. 16550 Mimic Transmitter FIFO Block Diagram

16550 Mimic or PC Side Interface5

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HOST INTERFACE (Continued) Mimic-Host Interface Registers In addition to the Mimic programming registers, the Z382 contains a register set for interfacing with the Host by means of the Mimic. These registers are used to emulate the 16550 UART so that the Host can access these regis- ters just as if it was interfacing with the UART. This pro- vides software compatibility with existing Host communi- cation software. The registers are: Baud Rate Generator The Baud Rate Generator (BRG) provides emulation tim- ing for the Mimic. The BRG output clocks the Mimic emu- lation counter, while the BRG itself is clocked by the BUS- CLK output of the 380C. Two 8-bit registers are provided to program the BRG time constant. Design is such that on- the-fly modification of the registers does not cause irregu- lar BRG output. Host DMA Mailbox The Host DMA Mailbox facility provides a path for Host DMA data transfers separate from the Mimic COM port. Commands and data flow over the COM port, while the DMA path can be used for other purposes. The Host DMA Mailbox feature includes control registers that allow Host DMA data transfer between Host memory and, for exam- ple, a modem speaker/microphone codec. Transfers are driven by the HostÕs DMA on one side; Z382 DMA chan- nel(s) or programmed I/O can be used on the other side. Thus, several modes of operation can be programmed: Ð Host DMA Write, Z382 Polled Input Ð Host DMA Read, Z382 Polled Output Ð Host DMA Write with Z382 DMA Ð Host DMA Read with Z382 DMA On the ISA bus, the Z382 can use two independent DMA Mailbox facilities. When either of these facilities is enabled in the Plug and Play module, that module signals a DMA request by driving HDREQ0 or HDREQ1 High; if a facility is disabled, the corresponding HDREQ pin is tri-stated. A Low on one of the Acknowledge signals, /HDACK0 or /HDACK1, more or less simultaneously with /HWR or /HRD Low when the corresponding HDREQ line is being driven High, indicates a DMA cycle. In a PCMCIA socket, only one DMA Mailbox can be used. When an option bit in one of the PCMCIA registers is 1, a DMA request is signalled by setting the /INPACK output low. A DMA cycle is signalled by having the /PCREG line High while /PCIORD or /PCIOWR goes Low. Plug and Play Interface This module, with support from appropriate Z382-based firmware, complies with version 1.0a of the Microsoftª /In- telª ÒPlug and Play ISAÓ specification. The Z382Õs PnP module provides for I/O address decod- ing, interrupt channel selection and DMA channel selec- tion. Pin limitations constrain the internal address decod- ing for I/O addresses to 12 bits. Since 16-bit decoding is preferred for full Plug and Play compliance, an additional input, HAEN, is provided which must be Low for a valid ad- dress decode. This permits external decoding of HA15-12. Register Host Address 380C I/O Address Receiver Buffer Register %00 2 %00F0 Transmit Holding Register %00 2 %00F0 Interrupt Enable Register %01 2 %00F1 Interrupt ID Register %02 -- Line Control Register %03 %00F3 Modem Control Register %04 %00F4 Line Status Register %05 %00F5 Modem Status Register %06 %00F6 Scratch Register %07 %00F7 Divisor Latch MS Byte %01 3 %00F9 Divisor Latch LS Byte %00 3 %00F8 FIFO Control Register %02 %00E9 Mimic ModiÞcation Reg. -- %00E9 Note: 1. The host address is relative to the Mimic base address d coded by the PnP ISA or PCMCIA modules in the Z382. 2. DLAB (LCR[7]) = 0. 3. DLAB (LCR[7]) = 1.

1. As part of sending an ÒInitiation keyÓ to all the PnP
2. To select a register on one or all PnP cards as the
3. To select a register on one card, or the ÒIsolationÓ

subsequent read from the Read Data port. ulated with hardware registers. Figure 26. Plug and Play Interface

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HOST INTERFACE (Continued) Each PnP card manufactured must have a non-zero 64-bit identity value that is divided into a 16-bit vendor ID, a 16- bit product ID including revision, and a 32-bit serial num- ber. 380C firmware has complete control of this number; no mechanism for storing or determining it is included in the PnP interface. After sending an Initiation key, the Host can only access a few of these registers in a defined sequence, called the Isolation protocol, which selects the PnP card with the 64- bit value having the most low-order ones, among those in the system. The timing requirements of the Isolation proto- col are quite slow compared to the speed of the 380C pro- cessor, and the 64-bit ID and an associated 8-bit check- sum are sequenced to the PnP interface by the 380C, on a polled or interrupt-driven basis. After ÒisolatingÓ a card by means of the Isolation protocol, host software assigns the ÒisolatedÓ card a ÒCard Select NumberÓ (CSN), starting with 01H and ascending for sub- sequent cards. Assigning a CSN eliminates the card from future repetitions of the protocol. Then, or later, host soft- ware reads the characteristics of the card, called the Re- source Data, in a handshake manner with 380C firmware. Host software repeats this process until it determines that it has seen all of the PnP cards in the system. Then it allo- cates resources including memory and I/O space address- es, interrupt levels, and DMA channels, and uses the var- ious cardsÕ CSNs to write these allocations to ÒConfiguration registersÓ in the PnP register space. Finally, host software places all the PnP interfaces in the system back in ÒWait for KeyÓ state, in which they perform address decoding and interface the interrupt and DMA re- quests and acknowledgments, but have no affect on other system operations. If the host software thereafter deter- mines that the system needs reconfiguring, it sends anoth- er Initiation key. In this case, however, it can address a specific card using the previously assigned CSN. Configuration Registers The following Configuration registers are implemented in the Z382 to provide for the resources required by the host to interface to the host-accessible functions within the chip: Ð I/O Mailbox I/O Address Ð Mimic I/O Address Ð Interrupt Request Level - can be selected to be output on either of the two available interrupt output lines. A unique Z382 feature allows these two pins to be conÞgured to be any two of the ISA- bus interrupt lines. Ð DMA Channel 0, DMA Channel 1 - A unique Z382 feature allows the two DMA pin pairs to be conÞgured to be any two of the seven ISA-bus DMA channels. Host writes to the Configuration registers are effective im- mediately, in hardware, so there is no urgent need for the 380C processor to ÒtranslateÓ them into other register val- ues. But the 380C processor can use the interrupt that oc- curs when the Host terminates Configuration state to ex- amine what the Host has done to the Configuration registers, and operate accordingly in the future. PCMCIA Interface The PCMCIA Interface block integrates all the functions necessary for the operation of I/O interface cards in a PC- MCIA 2.0 and 3.0 socket. These functions are: Ð PCMCIA Interface Control Ð Attribute Memory Ð ConÞguration Registers Ð I/O Interface Ð ConÞgurable Address Decoder Ð ConÞgurable Interrupt Logic Ð Z380 Interface

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HOST INTERFACE (Continued) Base Address Registers These seven registers are written by the 380C with the base addresses of 8-byte windows in the hostÕs I/O ad- dress space which the host can use to communicate with the host-accessible registers in the Mimic. Configuration Registers There are five configuration registers of the PCMCIA 3.0 standard and additionally a version number register, two image base address registers, and the seven base ad- dress registers described above. The Host accesses these registers to configure the interface and to retrieve status. Configuration Option Register. This register is used on one side to configure the PCMCIA interface, controlling items such as type of interrupt, DMA enable, and selection of the Base Address Register. On the other side, a reset can be triggered by setting a certain bit. Card Configuration and Status Register. This register contains information about the status of the interface, in- cluding whether certain signals have changed, interrupts, and power down. Pin Replacement Register. This register is used to pro- vide the status information which is otherwise provided on the /PCIRQ pin (RDY/BSY). Socket and Copy Register. The Socket and Copy regis- ter is implemented for PCMCIA hosts expecting this op- tional PCMCIA register in a PCMCIA card. The register has no function in the Z382. Extended Status Register. The extended status register is used to enable and provide status information of exter- nal events. Image Base Address Registers. These registers deliver a copy of the configured base address. Interface Version Number Register. This register pro- vides the version number of the PCMCIA interface. It also contains a bit which can be written to disable attribute memory write protection, allowing the host to write to the attribute memory. Z380 Control Register. The Z380 Control Register (ZCR) controls the functions of the PCMCIA block by means of the Z380 controller. Accessible only to the 380C, it controls access to the attribute memory by the 380C and allows the 380C to signal major status changes to the host. Decoding and Routing Functions The PCMCIA interface uses the values programmed in the Configuration Registers to decode a Mimic chip select when the host I/O address signals match the programmed conditions. Unlike the Plug and Play interface the PCMCIA interface does not perform any routing functions on interrupt and DMA control signals. These are performed at the PCMCIA socket controller on the host side.

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 47 DMA CHANNELS The DMA channels of the Z382 build on ZilogÕs experience with the Z16C32 IUSC. They have only one mode of oper- ation, which combines features of the IUSCÕs Array and Linked List modes. Each DMA channel has a pointer into a list structure, entries in which contain the addresses and lengths of data buffers. Since the on-chip peripherals of the Z382 all operate with 8-bit data only, particularly the HDLC channels which the DMA channels are primarily intended to serve, the DMA channels also perform only 8-bit data transfers when oper- ating with data buffers. However, because fetching a new list entry is an overhead operation that can compromise maximum data rates, list accesses use 16-bit transfers. DMA Channel/Device Interface The interface between the DMA channel and its client de- vice includes six lines: All of these lines are bused, and are driven by the DMA channel and its client device that are currently selected by the DMA scanner. Operation A DMA channel starts operating when software loads an address into its List Address Register (LAR). Writing the fi- nal (MS) byte of this register sets the channelÕs Run bit, which makes it request bus access from the processor. When the processor grants bus access, the DMA channel proceeds to fetch the first Òlist entryÓ from memory, begin- ning at the address in the LAR. List entries always begin at an 8-byte boundary, that is, at an address having its LS three bits Ô000Õ. The general for- mat of a list entry includes eight bytes: The Type/Status byte defines various kinds of list entries, as follows: Data Request Device to DMA Terminate Device to DMA Type Fetch DMA to device Data Acknowledge DMA to device End of Buffer DMA to device Store Status DMA to device Figure 29. General Format of a DMA List Entry

00 End of List

01 Transfer in List

02 Ready Buffer, no Command, no End of

Buffer notiÞcation

03 Ready Buffer, no Command, notify device at

04 Buffer in Progress

05 Completed Buffer (no Status)

40-7F Ready Buffer, with Command, no End of Buffer notiÞcation 80-BF Ready Buffer, with Command, notify device at End of Buffer C0-FF Completed Buffer (with Status) Address 7-0 Address 15-8 Address 23-16 Type/Status should be 00 Length 7-0 Length 15-8 Address of Byte should be 00 [LAR23-3] + 000 [LAR23-3] + 001 [LAR23-3] + 010 [LAR23-3] + 011 [LAR23-3] + 100 [LAR23-3] + 101 [LAR23-3] + 110 [LAR23-3] + 111

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DMA CHANNELS (Continued) On fetching any Type/Status value except Transfer in List or Ready Buffer, the DMA channel clears its Run bit and requests an interrupt if its List Interrupt Enable bit is 1. This checking of the Type/Status byte helps prevent disorderly operation as well as buffer-ring wraparound. On fetching a Transfer in List entry, the DMA channel fetches the Address portion of the entry, loads it into its LAR, and proceeds to fetch another list entry from that ad- dress. This is the mechanism by which buffer rings and linked lists are constructed. If software needs to know when a certain amount of data has been sent or received, such as an Address field in a received HDLC frame, it can set up a buffer of that length with its own list entry. The DMA channel can provide an in- terrupt at the end of the buffer if desired. When a DMA channel fetches a Type/Status byte from memory, it asserts the Type Fetch signal to its client de- vice. This prompts the client device to capture the Com- mand if bits D7-6 of the Type/Status byte are 01 or 10. For example, the HDLC Transmitter uses the three LS bits of such a Type/Status byte to indicate how many bits to send from the last byte of the frame. The HDLC Receiver doesnÕt use any Command bits, so that Ready Buffer codes, with and without Command, are equivalent for HDLC reception. Upon fetching any Ready Buffer entry, the DMA channel rewrites the Type/Status byte to the ÒBuffer in ProgressÓ code, and then fetches the Address and Buffer Length fields and loads them into its Buffer Address and Length Registers (BAR and BLR) respectively. Thereafter the DMA channel transfers data into or out of the buffer, under control of the Data Request line from its client device. If there is no request at this point, as would typically be the case when software starts a ÒreceiveÓ channel, the DMA channel relinquishes bus control to the processor or anoth- er DMA channel, and goes idle until the device asserts Data Request and/or Terminate. For Type/Status bytes re- questing ÒNotify device at end of bufferÓ, the DMA channel will assert its clientÕs End of Buffer line at the appropriate time. Once a DMA channel has been started and has fetched its first list entry, it does nothing further unless and until its cli- ent device asserts Data Request and/or Terminate. When the client devices does so, the DMA channel requests bus access from the processor. When access is granted, or when it is continuing operation after fetching a list entry, the DMA channel proceeds as follows: If the device is asserting Data Request, with or without Ter- minate: How (and whether) a client device uses ÒEnd of BufferÓ is device-dependent. The HDLC Transmitter passes this in- dication through its TxFIFO, and terminates the Tx frame after sending the data with which the DMA channel assert- ed End of Buffer. (Because of this facility, the only time that an ÒunderrunÓ may occur at the HDLC Transmitter is when the DMA doesnÕt provide data fast enough, INSIDE a frame.) The HDLC Receiver doesnÕt do anything with ÒEnd of Buff- er,Ó so Ready Buffer codes with or without ÒEOBÓ are equivalent for HDLC receiving. At the end of each data transfer, the DMA channel incre- ments the BAR by 1 and decrements the BLR by 1. If the device signalled Data Request but not Terminate, and the Buffer Length Register has not been counted down to zero, and the Burst bit in the channelÕs DCSR is set, the DMA channel checks Data Request again. If Burst is 0, and/or if the device negates Data Request, the chan- nel gives the bus back to the processor or another DMA channel, else it goes back to do another data transfer. a. The DMA channel asserts Data Acknowledge to the device. b. If its BLR indicates the buffer is ending, and the Sta- tus/Type byte for this buffer said ÒNotify DeviceÓ, the DMA channel also asserts the End of Buffer signal. c. At the same time, the DMA channel places the ad- dress in its BAR on the address bus, and sets the con- trol signals for a memory read or write per the I/O bit in its DMA Control/Status Register (DCSR). d. Depending on the data direction, Data Acknowledge makes the device either provide a byte of data on the data bus, or capture a byte of data from the data bus.

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 49 If the device signalled Data Request, but not Terminate, and the Buffer Length Register has now been counted down to zero, the DMA channel proceeds as follows: Terminate The HDLC receiver asserts this signal for an End of Frame, Abort, or Overrun condition. The HDLC Transmit- ter does so for an Underrun condition. After the DMA chan- nel transfers a byte, if the device signals Data Request and Terminate, or if the device signals Terminate without Data Request, the DMA channel proceeds as follows: Note: If the device encounters an error from which operation canÕt continue without processor attention, then after signalling Terminate and storing a status byte as described above, the device should refrain from asserting Data Request until software has done so. (The HDLC Transmitter does this for Underrun.) Per-Channel Registers There are eight DMA channels in the Z382. Each channel includes the following registers: The LAR and DCSR are read/write registers; software can track the progress of a DMA by monitoring its LAR. BARs and BLRs are accessible only by using special modes se- lected in the centralized DMA Control Register; the chan- nel stores ending BLR values in the list. List Address Register A three-byte register whose 21 most significant bits con- tain the base address of the current list. The DMA channel begins operation when the 380C writes the most signifi- cant byte of this register. The DMA controller updates this register as it processes new lists in response to links from previous lists. The three LS bits of the LAR are ignored on writing, and always read back as 100 (thus pointing at the current Type/Status byte in the list). Buffer Address Register The DMA controller loads the initial value of the current buffer address into this register from the address field of the current list. At the end of each data transfer, the DMA channel increments the BAR by one. Buffer Length Register The DMA controller loads the initial value of the current buffer length into this register from the buffer length field of the current list. At the end of each data transfer, the DMA channel decrements the BLR by one. a. It puts the address of the Type/Status byte (from the LAR) on the address bus, and writes the code for ÒCompleted Buffer (no Status)Ó into that byte. b. If the DMA channelÕs Buffer IE field indicates Òinterrupt for all buffersÓ, or Òinterrupt for Notify buffersÓ and this was a Notify buffer, it sets its IP bit to request an inter- rupt. c. It increments the LAR to the address following this list entry, and goes back to fetch a new list entry from that address, as described above. a. It places the address of the Length field on the ad- dress bus, and writes the current (16-bit) value in its BLR to memory at that address and the next higher address. This value enables software to tell how much data was actually written into, or read out of, this buffer. b. It puts the address of the Type/Status byte on the ad- dress bus, sets the control signals for a memory write, signals ÒCompleted Buffer (with Status)Ó, and asserts the Store Status signal to the device. c. In response to Store Status, the device can place up to 6 bits of status on D5-0. For the HDLC receiver, this status includes Overrun, End of Frame, Abort, CRC Error, and the residual bit count. For the HDLC Transmitter, only Underrun will prompt a Terminate indication, so the specific status bits are unimportant. 1. After the Type/Status byte has been written, the DMA channel advances the LAR over this list entry, in other words, to the address of the next entry. e. If the DMA channelÕs Buffer IE field indicates any- thing other than Óno buffer interruptsÓ, it requests an interrupt. f. The DMA channel then goes back to fetch another list entry from the address in the LAR, as described above. List Address Register (LAR, 21 bits) Buffer Address Register (BAR, 24 bits) Buffer Length Register (BLR, 16 bits) DMA Control/Status Register (DCSR, 8 bits)

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DMA CHANNELS (Continued) DMA Control/Status Register Controls items such as I/O Direction, enabling/disabling Burst Mode, and enabling and disabling interrupts. Also provides certain per channel DMA and interrupt status conditions. Centralized DMA Registers Two registers provide overall control and status of the DMA subsystem: DMA Control Register (DMACR) This register controls when bus control is returned to the 380C processor after a DMA channel has operated. It also provides modes whereby the Buffer Address and Buffer Length per-channel registers can be read and written. DMA Vector Register (DMAVR This register contains the base interrupt vector for the DMA channels. It also identifies, during an interrupt ac- knowledge cycle, the interrupting DMA Channel. SERIAL COMMUNICATION CHANNELS The Z382 provides several means of serial data communi- cations. These are the Asynchronous Serial Communica- tion Interface (ASCI), the HDLC controllers, the GCI/SCIT interface and the Clocked Serial I/O Channel. Asynchronous Serial Communications Inter- face (ASCI) The Z382 provides two independently programmable AS- CIs (UARTs), each including a flexible baud rate genera- tor. Key features of the ASCIs include: n Full-duplex operation n Programmable data format Ð 7- or 8- data bits with optional ninth bit for multiprocessor communication Ð One or two stop bits Ð Odd, even or no parity n Programmable baud rate generator Ð Divide-by-one, divide-by-16 and divide-by-64 modes n Up to three modem control signals per channel, depending on operating mode of the Z382 n Programmable interrupt conditions n Four level data/status FIFOs for the receivers n Receive parity, framing and overrun error detection n Optional operation with on-chip DMA controllers Figure 34 below illustrates the major functional blocks within the ASCI. Transmit Data Register Data written to the ASCI Transmit Data Register (TDR) is transferred to the Transmit Shift Register (TSR) as soon as the TSR is empty. Data can be written while the TSR is shifting out the previous byte of data, providing double buffering for the transmit data. Data transfers into the TDR can be performed using I/O in- structions or by using one of the DMA channels. This DMA process loads characters into the TDR as an associated status bit indicates that it has become available for data. n DMA Control Register (DMACR) n DMA Vector Register (DMAVR)

Figure 30. Asynchronous Serial Communications Interface (ASCI) Block Diagram

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SERIAL COMMUNICATION CHANNELS (Continued) Transmit Shift Register When the ASCI Transmit Shift Register receives data from the ASCI Transmit Data Register, the data is shifted out to the TxA pin. When transmission is completed, the next byte (if available) is automatically loaded from the TDR into the TSR and the next transmission starts. If no data is available for transmission, the TSR idles at a continuous High level. Receive Shift Register When the receiver is enabled, the RXA pin is monitored for a low. One-half bit time after a low is sensed at RXA, the ASCI samples RXA again. If it has gone back to High, the ASCI ignores the previous low and resumes looking for a new one, but if RXA is still low, it considers this a start bit and proceeds to clock in the data based upon the internal baud rate generator or the external clock at the CKA pin. The number of data bits, parity, multiprocessor and stop bits are selected by means of control bits in the CNTLA and CNTLB registers. After the data has been received, the appropriate MP, par- ity and one stop bit are checked. Data and any errors are clocked into the receive data and status FIFOs during the stop bit if there is an empty position available. Interrupts, Receive Data Register Full Flag, and DMA requests will also go active during this time. If there is no space in the FIFO at the time that the RSR attempts to transfer the re- ceived data into it, an overrun error occurs. Receive Data FIFO When a complete incoming data byte is assembled in the RSR, it is automatically transferred to the FIFO, which serves to reduce the incidence of overrun errors. The top (oldest) character in the FIFO (if any) can be read by means of the Receive Data Register (RDR). An overrun occurs if the receive FIFO is still full when the receiver completes assembly of a character and is ready to transfer it to the FIFO. If this occurs, the overrun error bit associated with the previous byte in the FIFO is set. The latest data byte is not transferred from the shift register to the FIFO in this case, and is lost. Once an overrun occurs, the receiver does not place any further data in the FIFO until the last good byte received has come to the top of the FIFO and sets the Overrun latch, and software then clears the Overrun latch. When a break occurs (defined as a framing error with the data equal to all zeros), the all-zero byte with its associated error bits are transferred to the FIFO if it is not full. If the FIFO is full, an overrun is generated, but the break, fram- ing error and data are not transferred to the FIFO. Any time a break is detected, the receiver will not receive any more data until the RXA pin returns to a high state. Data transfers from the receive FIFO can be performed us- ing I/O instructions or by using one of the DMA channels. This DMA process reads characters from the RDR as an associated status bit indicates that data is available. The RxDMA request is disabled when any of the error flags (PE, FE or OVRN) is set, so that software can identify with which character a problem is associated. ASCI Status FIFO/Register This FIFO contains Parity Error, Framing Error, Rx Over- run, and Break status bits associated with each character in the receive data FIFO. The status of the oldest character (if any) can be read from the ASCI status register, which also provides several other, non-FIFOed status conditions. The outputs of the error FIFO go to the set inputs of soft- ware-accessible error latches in the status register. Writing a 0 to the Error Flag Reset (EFR) bit in CNTLA is the only way to clear these latches. In other words, when an error bit reaches the top of the FIFO, it sets an error latch. If the FIFO has more data and the software reads the next byte out of the FIFO, the error latch remains set and does so until the software writes a 0 to the EFR bit. The error bits are cumulative, so if additional errors are in the FIFO they will set any unset error latches as they reach the top. Baud Rate Generator The baud rate generator has two modes. The first is the same as that used in most previous Zilog processors, such as the Z80180, and provides a dual set of fixed clock divide ratios. In the second mode, the BRG is configured as a six- teen-bit down counter that divides the processor clock by the value in a software accessible, sixteen-bit, time con- stant register. This allows virtually any frequency to be cre- ated by appropriately selecting the main processor clock frequency. The BRG can also be disabled in favor of an ex- ternal clock on the CKA pin. The Receiver and Transmitter will subsequently divide the output of the Baud Rate Generator (or the signal from the CKA pin) by 1, 16 or 64 under program control.

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 53 ASCI Register Set Each ASCI contains a set of registers for programming various aspects of its operation. These registers are: HDLC Serial Channels The Z382 features three high-speed serial channels, each comprised of a transmitter and a receiver, which can oper- ate in HDLC or transparent (unframed) modes. All data transfers to and from the HDLC channels are carried out by the DMA channels. Thus, each HDLC channel must have an assigned DMA channel to perform its function. Fa- cilities for interrupt-driven or polled transfer of HDLC data are not provided. Software can select whether each channelÕs I/O is on de- vice pins or on the internal TDM highway (the GCI/SCIT bus in the Z382). If device pins are used, they can be con- figured as either a classic synchronous serial interface, or as the interface to an external TDM highway or highways. The differences in pin use are as follows: Eight-character FIFOs on both the transmit and receive side reduce the possibility of overrun and underrun condi- tions to a minimum, at data rates up to and beyond E1 (2.048 Mbps). n Control Register A n Control Register B n Time Constant High Register n Time Constant Low Register n Extension Control Register n Status Register n Receive Data Register n Transmit Data Register n DMA Control Register n Control Register A Pin TDM Operation Full Time Operation TxD Tri-stated outside the time slot. Driven full time RxD Sampled within the time slot. Sampled in every bit time RxC/BCL Common clock for Rx and Tx. Rx Clock, optional Tx Clock TxC/FSC Frame Sync pulse for Rx and Tx. Tx Clock in or out. TxEN Asserted within the time slot, optional enable for an external driver. Asserted whenever Tx is enabled.

54 P R E L I M I N A R Y DS97Z382000

Figure 31. HDLC Channel Block Diagram (One of Three Channels Shown) Transmit Control/Status Reg.

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 55 Interface with a Common TDM Module (for example, GCI/SCIT) The interface between an HDLC channel and the GCI/SCIT module includes: TDM Processing When the Transmit (Receive) TDM Length register is non- zero, the Transmitter (Receiver) activates its Time Slot As- signer to clock Tx (Rx) data only within the time slot. If a TDM Start register is non-zero, then after each pulse on Frame Sync, the Time Slot Assigner blocks clocking for the number of bits specified by the TDM Start register. Then, or immediately at Frame Sync if the Start value is zero, it enables clocking for the number of bits specified by the TDM Length register. Thereafter, it again blocks clocking until the next Frame Sync pulse. For example, the Start and Length values for the GCI subchannels are: Type/Status Bytes in DMA Lists Note: Please refer to the description of Type/Status bytes in the section on the DMA channels in conjunction with this topic. Type/Status Bytes in Transmitter DMA Lists. In HDLC mode, a frame to be transmitted can be contained in one or more DMA buffers. The DMA list entry for the last (or only) buffer of a frame should have its Type/Status byte coded as ÒReady Buffer, notify at End of BufferÓ. This makes the Transmitter send the CRC (if enabled) and a closing Flag after the last byte of the buffer. Buffers that do not include the end of a frame should have their Type/Sta- tus bytes coded as ÒReady Buffer, no End of Buffer Notifi- cationÓ. Two control fields for the Transmitter do not reside in pro- cessor-accessible register bits, but can be controlled sep- arately for each frame in Type/Status bytes in the DMA list: Either of these items can be changed automatically from one frame to the next if the Type/Status byte for the frame is coded as ÒReady Buffer, with CommandÓ and the control bits of that byte are set appropriately. In HDLC modes or in Transparent mode with the Underrun Wait bit set to 1, completed Buffer codes in Type/Status bytes in Transmitter DMA lists are stored as Òwith StatusÓ if the Transmitter encountered an Underrun while sending the data in the buffer. In all other cases, Type/Status bytes in Transmitter DMA lists are stored as Òno status.Ó Type/Status Bytes in Receiver DMA Lists. HDLC re- ceivers do not use the Command nor End of Buffer notifi- cation features of the DMA channels. Thus all ÒReady Buff- erÓ codes in Type/Status bytes in Receiver DMA lists are equivalent. A received frame can be contained in one DMA buffer, or can span two or more buffers. The end of a frame always makes the Receiver terminate its current DMA buffer and store frame status in its Type/Status byte. When a buffer is filled with receive data, without the last character of the frame being stored in that buffer, that buff- erÕs Type/Status byte is stored as ÒCompleted Buffer (no Status)Ó. Buffers that include the last character of a frame, and buffers that couldnÕt be completed because the Re- ceiver encountered an Overrun condition, are stored as ÓCompleted Buffer (with Status)Ó. The least significant five bits of such a Type/Status byte indicate the status of the buffer. TxD A bused line onto which HDLC Transmitters place data in their time slots, as directed by software programming. RxD A bused line from which HDLC Receivers take data in their time slots, as directed by software programming. BCL A common bit clock for HDLC Transmitters and Receivers. Transmitters change data on TxD on falling edges of BCL, and Receivers sample data from RxD on rising edges of BCL. FSC Frame Sync, synchronous to BCL. Transmitters and Receivers measure their time slots independently from the rising edge of this signal. The duration of FSC can be one or more BCL cycles. TxEN An output from each Transmitter to the common TDM module, indicating its time slot, that is, when it is placing data on TxD. Channel Start Length B1 (64K bps) 0 8 B1 (56K) 0 7 B2 (64K) 8 8 B2 (56K) 8 7 D2 42 IC1 32 8 IC2 40 8 1. How many bits the Transmitter sends from the last byte of the frame. 2. Whether the Transmitter sends its accumulated CRC at the end of the frame.

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SERIAL COMMUNICATION CHANNELS (Continued) Baud Rate Generator and DPLL If an HDLC channelÕs Tx clock is taken from its Baud Rate Generator (BRG), and/or its Rx clock is taken from its DPLL, then the channelÕs BRG operates. A BRG counts down from the 16-bit value programmed into its Time Con- stant LS and MS registers, using the processorÕs BUS- CLK. Each time the value is zero, the BRG toggles its out- put to the DPLL, and one clock later it reloads the value from the Time Constant registers. If an HDLC channelÕs Rx clocking is taken from its DPLL, software should program the channelÕs Time Constant registers with a 16-bit value that corresponds to 16 times the nominal data rate. Conceptually, when the DPLL de- tects a change on the raw Rx Data (before NRZI decod- ing), it clears a counter that is incremented at 16X the nom- inal bit rate. Half a bit time thereafter, it provides an active edge on its Rx clock output. Thereafter, in the absence of further data transitions it provides the Rx clock as the BRG output divided by 16. Per-Channel Registers Each HDLC channel includes the following I/O-mapped registers that can be read and written by the 380C proces- sor: Transmit Mode Register. Selects the main operating mode of the Transmitter (transparent, HDLC, NRZI HDLC), its I/O configuration (TDM, I/O by means of device pins, and so on), when DMA data transfers are requested, and action to be taken if an underrun occurs. Tx Control/Status Register. Controls the minimum num- ber of bits sent between frames and the minimum number of bits sent after the Transmitter is enabled before the first data character of a frame is sent, what the Transmitter sends between frames, and the type of CRC used. It also provides feedback on the current state of the transmitter. Transmit Interrupt Register. Controls and provides sta- tus of potential interrupting conditions in the transmitter. It also provides the mechanism for clearing conditions which are causing an interrupt. Transmit Fill Register. Holds a character that can be sent between frames in HDLC mode, or in case of an Underrun in Transparent mode. Receive Mode Register. Selects the main operating mode of the Receiver (transparent, HDLC, NRZI HDLC), its I/O configuration (TDM, I/O by means of device pins, and so on), when DMA data transfers are requested, when the receiver begins assembling characters when it is switched from the inactive state to transparent mode, and the type of CRC used in HDLC modes. Receive Interrupt Register. Most of the interrupt require- ments for HDLC reception can be handled by enabling Status interrupts in the DMA channel associated with each Receiver. The only Receiver interrupt condition that is not handled by this means is the Idle condition. Idle interrupts are controlled by this register. This register also allows several commands which deal with interrupts and Hunt mode to be issued to the receiver. DMA Select Register. Selects the DMA channels to be used by the receiver and transmitter and enables their op- eration. Counter Access Port. Allows the 380C to write and read the starting values for various counters in the HDLC chan- nel. These are the Baud Rate Generator time constant, the Transmitter TDM start and length values, and the Receiver TDM start and length values. Global HDLC Vector Register This register provides the base interrupt vector for the HDLC channels and identifies the HDLC device which is causing an interrupt to be issued. n Transmit Mode Register n Transmit Control/Status Register n Transmit Interrupt Register n Transmit Fill Register n Receive Mode Register n Receive Interrupt Register n DMA Select Register n Counter Access Port

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SERIAL COMMUNICATION CHANNELS (Continued) Start of Transmission: The first byte of data is placed on the bus and MX is activated (Low). MX remains active, and the data is repeated until an inactive-to-active transition of MR is received, indicating that the data has been captured by the receiver. Subsequent Transmissions: The second and subse- quent bytes are placed on the bus after the inactive to ac- tive transition of MR. At the time that the second byte is transmitted, MX is returned inactive for one frame time only; the data is valid in the same frame. In the following frame, MX returns active again and the same byte is trans- mitted. Data is repeated in subsequent frames and MX re- mains active until acknowledgment is detected (MR transi- tion from inactive to active). Maximum Speed Case: The transmitter is capable of min- imizing the delay between bytes to achieve higher data throughput than is provided by the general case described above. The first and second bytes are transmitted normal- ly, However, starting with the third byte, the transmitter will deactivate MX and transmit new data one frame time after MR is deactivated. In this way, the transmitter is anticipat- ing that MR will be reactivated, which it will do one frame time after it is deactivated, unless an abort is signalled by the receiver. End of Message (EOM): The transmitter sends an EOM, normally after the last byte of data has been transmitted, by not reactivating MX after deactivating it in response to MR going inactive. Reception: At the time the receiver sees the first byte, in- dicated by the inactive-to-active transition of MX, MR is by definition inactive. In response to the activation of MX, the data is read off the bus and MR is activated. MR remains active until the next byte is received or an end of message is detected. Subsequent data is received from the bus on each falling edge of MX, and a monitor channel receive data available interrupt is generated. Note that the data may actually be valid at the time that MX went inactive, one frame time prior to going active. MR is deactivated after the data is read and reactivated one frame time later. The transmitter will detect MR going inactive and anticipate its reactivation one frame later. The reception of data is termi- nated by the reception of an end of message indication. Abort: The abort is a signal from the receiver to the trans- mitter indicating that the data has been missed. It is not an abort in the classical sense, which is an indication that the current message should be ignored. The receiver indi- cates an abort by holding MR inactive for two or more frames in response to MX going inactive. Flow Control: The receiver can hold off the transmitter by keeping MR active until the receiver is ready for the next byte. The transmitter will not start the next transmission cy- cle until MR goes inactive.

able interrupt, instructing the processor to read this data. ed in the status bit by the transmitter. ries of software handshakes by means of the C/I0 channel. Figure 33. Monitor Handshake Timing

60 P R E L I M I N A R Y DS97Z382000

spond by sending the deactivation indication. ing an activation request over the C/I0 channel. the C/I0 channel-based activation procedure. grammed for any of the subchannels shown above. tus conditions for Monitor 0 and 1 channels. tions for the GCI/SCIT module. rupts from the various channels in the GCI/SCIT module. block diagram of the CSI/O is illustrated below. Figure 34. CSI/O Block Diagram

while a transmit or receive is in progress must be avoided. Figure 35. Programmable Reload Timer Block Diagram

62 P R E L I M I N A R Y DS97Z382000

ue contained in its Timer Reload Register (RLDR). Figure 36. PRT Operation Timer Control Register ReadNote: f is BUSCLK divided by the value specified in TPR.

register in order to disable the WDT. and D are used by the Mimic feature in Host applications. access is limited to a single page (A[15-8] = 0). are inputs and which are outputs. on the external pins is returned. used for implementation of the ÒHost I/O MailboxÓ feature. I/O decode sizes ranging from 8 to 512 bytes. Figure 37. WDT Block Diagram

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COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued) I/O Chip Select Registers The following I/O-mapped registers are associated with the I/O chip selects and can be read and written by the 380C processor: I/O Chip Select 1/2 High and Low Address Registers. Specify the base address and the I/O block size for I/O Chip Selects 1 and 2. RAM AND ROM Chip Selects Three memory chip select outputs are provided: /ROMCS, /RAMCSL, and /RAMCSH. They support both 8- and 16- bit memories, and are asserted for a selected address range (4 KB to 8 MB) during both memory and I/O cycles. Unlike Chip Select and /MSIZE signalling, wait state gen- eration can be specified which occurs only during memory cycles. For the selected ROM and/or RAM range, the /MSIZE pin can be programmed to be forced Low in an open-drain fashion when the address is in the programmed range, thus forcing 8-bit accesses in one or both ranges. When /MSIZE is forced for 8-bit RAM in this way, /RAMCSL is as- serted for all cycles in the selected address range, and the /RAMCSH pin assumes its alternate use as port pin PC7. When /MSIZE is not forced for 8-bit RAM, /RAMCSL is qualified by /BLEN, and /RAMCSH acts as a chip select output pin and is qualified by /BHEN. RAM and ROM Chip Select Registers The following I/O-mapped registers are associated with the RAM and ROM chip selects and can be read and writ- ten by the 380C processor: RAM Address High and Low Registers: Specify which bits of the address bus are used in the address compari- son and thus, implicitly, the memory block size. This can range from 4 KB to 8 MB. ROM Address High and Low Registers: Specify which bits of the address bus are used in the address compari- son and thus, implicitly, the memory block size. This can range from 4 KB to 8 MB. Memory Mode Register 1. Enables the ROM chip select, specifies the number of wait states for the ROM chip se- lect, and specifies the number of T1 wait states for the RAM chip select. Memory Mode Register 2. Enables the RAM chip select, specifies 8- or 16-bit memory accesses for the RAM and ROM chip selects independently, and specifies the num- ber of T2 and T3 wait states for the RAM chip select. Interrupt Logic The Z382Õs interrupt structure provides compatibility with the existing Z80 and Z180 with the following exception: the undefined Opcode trapÕs occurrence is with respect to the Z380 instruction set, and its response is improved (versus the Z180) to make trap handling easier. The Z380 offers additional features to enhance flexibility in system design. Of the five external interrupt inputs provided, /NMI is a non- maskable interrupt. The remaining inputs, /INT3-0, are asynchronous maskable interrupt requests. In an Interrupt Acknowledge transaction, address outputs A23-4 are driven to a logic High. One output among A3-0 is driven Low to indicate the maskable interrupt request being acknowledged. For example, when /INT0 is being acknowledged, A3-1 are High and A0 is Low. Interrupt modes 0 through 3 are supported for maskable interrupt request /INT0, which can be driven by external and on-chip sources. Modes 0, 1 and 2 have the same schemes as those in the Z80 and Z180. Mode 3 is similar to mode 2, except that 16-bit interrupt vectors are expect- ed from the I/O devices. Note that 8-bit and 16-bit I/O de- vices can be intermixed in this mode by having external pull up resistors at the data bus signals D15-8, for exam- ple. The external maskable interrupt requests /INT3-1, as well as the less complex on-chip peripherals (PRTs, ASCIs, and CSI/O) are handled in an assigned interrupt vectors mode. INT3-1 can be used as Low or High active level- sensitive inputs, or as falling or rising edge-triggered in- puts. The Z382 can operate in either the Native or Extended Mode. In Native Mode, PUSHing and POPing of the stack to save and retrieve interrupted PC values in interrupt han- dling are done in 16-bit sizes, and the stack pointer rolls over at the 64-KB boundary. In Extended Mode, the PC PUSHes and POPs are done in 32-bit sizes, and the stack pointer rolls over at the 4-GB memory space boundary. The Z382 provides an Interrupt Register Extension, whose contents are always output as the address bus signals A23-16 when fetching the starting addresses of service routines from memory in interrupt modes 2 and 3 and the assigned vectors mode. In Native Mode, such fetches are automatically done in 16-bit sizes and in Extended Mode, n I/OCS1 High and Low Address Registers n I/OCS2 High and Low Address Registers n RAM Address High and Low Registers n ROM Address High and Low Registers n Memory Mode Register 1 n Memory Mode Register 2

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 65 in 32-bit sizes. These starting addresses should be even- aligned in memory locations. That is, their least significant bytes should have addresses with A0 = 0. Interrupt Priority Ranking The Z382 assigns a fixed priority ranking to handle its ma- jor categories of interrupt sources, as follows: INT0 Peripherals Those on-chip peripherals capable of generating their own interrupt vectors, including the Mimic, DMAs, and HDLC controllers, have their interrupt requests logically ORÕed with the external /INT0 pin to produce the INT0 signal pre- sented to the 380C processor. These interrupt sources are consecutive in the INT0 daisy-chain, but their relative pri- ority can be programmed in the System Configuration Register. Their priority relative to external INT0 sources is controlled by how the Z382Õs IEI and IEO pins are connect- ed. Assigned Interrupt Vectors Mode (INT1-3, PRTs, CSI/O, ASCIs) When the Z382 recognizes /INT1-3, or a request from an on-chip peripheral that cannot supply an interrupt vector (a PRT, CSI/O, or ASCI), it generates an Interrupt Acknowl- edge transaction which is different from that for /INT0. This Interrupt Acknowledge transaction has /IORQ active for external monitoring purposes, but /M1, /IORD, and /IOWR inactive so as not to stimulate external devices. The inter- rupted PC value is PUSHed onto the stack. IEF1 and IEF2 are cleared, disabling further maskable interrupt requests. The starting address of an interrupt service routine is fetched from a table entry and loaded into the PC to re- sume execution. The address of the table entry is com- posed of the I Extend contents as A31-16, the seven Vec- tor Base bits of the Assigned Vectors Base Register as A15-9 and an assigned interrupt vector specific to the re- quest being recognized as A8-0. The assigned vectors are as follows: Trap Interrupt The 380C generates a trap when an undefined opcode is encountered. The trap is enabled immediately after reset, and it is not maskable. This feature can be used to in- crease software reliability or to implement extended in- structions. An undefined opcode can be fetched from the instruction stream, or it can be returned as a vector in an interrupt acknowledge transaction in interrupt mode 0. Nonmaskable Interrupt The nonmaskable interrupt input /NMI is edge sensitive, with the 380C internally latching the occurrence of its fall- ing edge. When the latched version of /NMI is recognized, the interrupted PC (Program Counter) value is pushed onto the stack, certain status flag manipulations are per- formed, and the 380C commences to fetch and execute in- structions from address 00000066H. RETI Instruction The original Z80 family I/O devices (PIO, SIO, CTC) are designed to monitor the Return from Interrupt Opcodes in the instruction stream, signifying the end of the current in- terrupt service routine. On the Z382, the M1 signal is active during all instruction fetch transactions. Since the Z382 may not execute an RETI that it fetches, and because it supports a 16-bit data bus, only half of which is visible to an 8-bit peripheral, the Z382 does not support RETI de- coding by the PIO, SIO, and CTC. Priority Interrupt Sources Highest Trap (undeÞned opcode) /NMI /INT0 (includes DMAs, Mimic, HDLC controllers) /INT1 /INT2 GCI/SCIT PRT0 PRT1 CSI/O ASCI0 ASCI1 Plug and Play ISA or PCMCIA I/O Mailbox Lowest /INT3 Interrupt Source Assigned Interrupt Vector /INT1 00H /INT2 04H Reserved 08H GCI/SCIT 0CH PRT0 10H PRT1 14H CSI/O 18H ASCI0 1CH ASCI1 20H Plug and Play or PCMCIA 24H I/O Mailbox 28H /INT3 2CH

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COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued) Interrupt Registers The following I/O-mapped registers are associated with in- terrupts and can be read and written by the 380C proces- sor: Interrupt Enable Register. Provides the current status of the /INT3-0 pins and controls whether /INT3, /INT2, /INT1, and /INT0 are enabled or disabled. Note that these flags are also affected by enable and disable interrupt instruc- tions (DI (n) and EI (n)). Assigned Vectors Base Register. The Interrupt Register Extension, Iz, together with the contents in bits 1-7 of this register, define the base address of the assigned interrupt vectors table in memory space. INT3-1 Control Register. Controls when and how the Z382 recognizes an interrupt on the corresponding pins (High or Low Level sensitive, Falling or Rising Edge Trig- gered) and provides the means for clearing edge triggered interrupt requests if such are specified for /INT3-1. Trap and Break Register. Two bits of this register provide status on traps. One bit is set if an undefined opcode is fetched in the instruction stream. A second bit is set if an undefined opcode is returned as a vector in an interrupt ac- knowledge transaction in mode 0. Z380-Compatible Peripheral Functions The Z382 incorporates a number of Z80380 compatible functions. The Z382Õs I/O bus can be programmed to run at a slower rate than its memory bus. In addition, a heart- beat transaction can be generated on the I/O bus that em- ulates a Z80 instruction fetch cycle. Such cycles are need- ed for a particular Z80 family I/O device to perform its interrupt functions. Finally, a DRAM refresh function is in- corporated, with programmable refresh transaction burst size. I/O Bus Control The Z382 is designed to interface easily with external I/O devices that can be of either the Z80 or Z8500 product family by supplying four I/O bus control signals: /M1, /IORQ, /IORD, and /IOWR. In addition, the Z382 supplies an IOCLK that is a divided down version of its BUSCLK. Programmable wait states can be inserted in the various I/O transactions. DRAM Refresh The Z382 is capable of providing refresh transactions to dynamic memories that have internal refresh address counters. A user can select how often refresh requests should be made to the Z80Õs External Interface Logic, as well as the burst size (number of refresh transactions) for each request iteration. The External Interface Logic grants these requests by performing refresh transactions with CAS-before-RAS timing on the /TREFR, /TREFA and /TREFC bus control signals. In these transactions, /BHEN, /BLEN and the user specified chip select signal(s) are driv- en active to facilitate refreshing all the DRAM modules at the same time. A user can also specify the T1, T2 and T3 waits to be inserted. Note: The Z382 cannot provide refresh transactions when it relinquishes the system bus, with its /BREQ input active. In that situation, the number of missed refresh requests are accumulated in a counter, and when the Z382 regains the system bus, the missed refresh transactions will be performed. Low Power Standby Mode The Z382 provides an optional standby mode to minimize power consumption during system idle time. If this option is enabled, executing the Sleep instruction stops the Z382Õs oscillator if it is in use, and in any case stops clock- ing internal to the Z382 (except to PRT0 if it is enabled) and at the BUSCLK and IOCLK outputs. The /STNBY and /HALT signals go Low to indicate that the Z382 is entering the standby mode. All Z382 operations are suspended, the bus control signals are driven inactive and the address bus is driven High. Standby mode can be exited by asserting any of the /RESET, /NMI, /INT3-/INT0 (if enabled), or op- tionally, /BREQ inputs. If standby mode is not enabled, the Sleep instruction does not stop the Z382Õs oscillator if it is in use, but blocks clock- ing from internal modules, except PRT0 if it is enabled. In this case, /STNBY (but not /HALT) goes Low to indicate the Z382Õs status. n Interrupt Enable Register n Assigned Vectors Base Register n INT3-1 Control Register n Trap and Break Register

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 67 Peripheral Function Control Registers The functions described above are controlled by a number of I/O mapped on-chip registers: Clock Control Register. Controls how BUSCLK is de- rived from the input clock (CLKI, CLKI/2 or CLKI x 2), pro- vides a means of disabling CLKO to save power and re- duce noise if an external clock is used, and controls the I/O Clock Rate (BUSCLK/8 to BUSCLK). I/O Waits Register. Allows for up to seven wait states to be inserted in external I/O read and write transactions, and at the latter portions of interrupt transactions to capture in- terrupt vectors. Also allows for up to seven wait states to be inserted at the early portions of interrupt acknowledge transactions, for the interrupt daisy chain through on-chip and possibly external I/O devices to settle. Refresh Register 0. Defines the interval between refresh requests to the Z382Õs External Interface Logic. Refresh Register 1. Provides the Missed Requests Count. This count increments by one when a refresh re- quest is made and decrements by one when the Z382Õs External Interface Logic completes each burst of refresh transactions. A user can read the count status, and if nec- essary, take corrective actions such as adjusting the burst size. Refresh Register 2. Enables the refresh function and de- fines the number of refresh transactions per refresh re- quest made to the Z382Õs External Interface Logic. Refresh Wait Register. Defines the number of T1, T2 and T3 wait states to be inserted in refresh transactions. Standby Mode Control Register. Enables the Z382 to go into low-power standby mode when the Sleep instruction is executed, allows asserting /BREQ to exit the mode, and specifies the approximate running duration of a warm-up counter that provides a delay before the Z382 resumes its clocking and operations, from the time an interrupt or bus request (if so enabled) is asserted to exit standby mode. Device Configuration In addition to the configuration options provided in the reg- isters associated with each of the major functional blocks in the Z382, there are two registers which control the over- all device configuration: n Clock Control Register n I/O Waits Register n Refresh Registers 0, 1 and 2 n Refresh Wait Register n Standby Mode Control Register n System Configuration Register n Pin Multiplexing Register

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COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued) System Configuration Register The System Configuration Register controls the major modes of the Z382: n How pins 60 - 92 are used: Ð connected to the ISA bus of a host PC; Ð connected to the PCMCIA bus of a host PC; Ð used for the ASCIs, CSI/O, and ports A and D, except that the full-time outputs among these signals (TXA0, TXA1, RTS0, TxS) are disabled; Ð used for the ASCIs, CSI/O, and ports A and D, including the TXA0, TXA1, RTS0, and TxS outputs. n How pins 110-112 are used: Ð /DCD0, /CTS0, /CTS1 ASCI control signals; Ð TREFA, TREFC, and TREFR DRAM control signals. n D15 - 0 use during reads from on-chip I/O devices: Ð the D15-0 pins are driven as outputs from the Z382; Ð the pins are left tri-stated to reduce power consumption, noise, and EMI/RFI to some extent. n I/O address decoding of the Mimic and Parallel Ports: Ð A15-8 must be zero to access these features; Ð the address decoding for these ports disregards address lines above A7, so that these devices are replicated in each 256-byte ÒpageÓ of I/O space as on the Z80182, 187, and 189. n The relative interrupt priority of the Mimic, HDLC channels, and DMA channels on the INT0 daisy chain. In addition to the control above, certain pins are multi- plexed automatically based on the state of register bits in their associated functions. Pin Multiplexing Register The Pin Multiplexing Register controls smaller-scale pin multiplexing issues than those handled in the System Con- figuration Register. n Whether the pins normally used for HDLC 0 are used for ASCI0 signals instead. n Whether the pins normally used for HDLC 1 are used for ASCI1 signals instead. n The functions of pins 47, 48, 49, 53, 56, 57, 58 and 109. Programable Low Noise Drivers To help reduce noise generated by the output switching of the Z382, selected outputs can be placed in a reduced drive configuration. When a pin is placed in low noise mode, its drive is reduced to 1/3 of its normal output drive current. This decreases the slew rate of the driver, which reduces current spikes induced onto the power bussing of the Z382. The Output Drive Control Register provides this function for a number of groups of Z382 output or I/O pins.

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 69 Z382 I/O REGISTER MAPS Z80380-COMPATIBLE REGISTERS Z80382 ASCI, PRT, CSIO, WDT REGISTERS Register Name Z382 Address Z380 Address Access Assigned Vectors Base Register %0018 %0018 R/W Trap and Break Register %0019 %0019 R/W I/O Waits Register %001E %000E R/W Refresh Waits Register %001F %000F R/W Clock Control Register %0021 %0011 R/W Refresh Register 0 %0023 %0013 R/W Refresh Register 1 %0024 %0014 R/W Refresh Register 2 %0025 %0015 R/W Standby Mode Control Register %0026 %0016 R/W Interrupt Enable Register %0027 %0017 R/W Chip Version ID Register %0020 %00FF RO Register Name I/O Address Access ASCI Control Register A Ch 0 %0000 R/W ASCI Control Register A Ch 1 %0001 R/W ASCI Control Register B Ch 0 %0002 R/W ASCI Control Register B Ch 1 %0003 R/W ASCI Status Register Ch 0 %0004 R/W ASCI Status Register Ch 1 %0005 R/W ASCI TX Data Register Ch 0 %0006 R/W ASCI TX Data Register Ch 1 %0007 R/W ASCI RX Data Register Ch 0 %0008 R/W ASCI RX Data Register Ch 1 %0009 R/W CSI/O Control Register %000A R/W CSI/O Tx/Rx Data Register %000B R/W Timer Data Register Ch OL %000C R/W Timer Data Register Ch OH %000D R/W Reload Register Ch OL %000E R/W Reload Register Ch OH %000F R/W Timer Control Register %0010 R/W Timer Prescale Register %0011 R/W ASCI0 Extension Control Register %0012 R/W ASCI1 Extension Control Register %0013 R/W

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Z80382 ASCI, PRT, CSIO, WDT REGISTERS (Continued) PORT AND NEW Z80382 REGISTERS Timer Data Register Ch 1L %0014 R/W Timer Data Register Ch 1H %0015 R/W Reload Register Ch 1L %0016 R/W Reload Register Ch 1H %0017 R/W ASCI0 Time Constant Low %001A R/W ASCI0 Time Constant High %001B R/W ASCI1 Time Constant Low %001C R/W ASCI1 Time Constant High %001D R/W WDT Master Register %0028 R/W WDT Command Register %0029 WO Register Name I/O Address Access IOCS1 Low Register %002A R/W IOCS1 High Register %002B R/W IOCS2 Low Register %002C R/W IOCS2 High Register %002D R/W RAM Low Register %002E R/W RAM High Register %002F R/W ROM Low Register %0030 R/W ROM High Register %0031 R/W Memory Mode Register 1 %0032 R/W Memory Mode Register 2 %00D3 R/W System ConÞguration Register %0036 R/W Pin Multiplexing Register %0037 R/W ASCI0 DMA Control Register %0038 R/W ASCI1 DMA Control Register %0039 R/W Output Drive Control Register %003A R/W INT3-1 Control Register %003B R/W Port A Data Register %00EE R/W Port A Data Direction Register %00ED R/W Port B Data Register %00E5 R/W Port B Data Direction Register %00E4 R/W Port C Data Register %00DE R/W Port C Data Direction Register %00DD R/W Port D Data Register %00E8 R/W Port D Data Direction Register %00E7 R/W Register Name I/O Address Access

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 71 DMA REGISTERS Register Name I/O Address Access DMA Control Register %003E R/W DMA Vector Register %003F R/W DMA0 List Address Register Low* %0040 R/W DMA0 List Address Register Middle* %0041 R/W DMA0 List Address Register High* %0042 R/W DMA0 Control/Status Register %0043 R/W DMA1 List Address Register Low* %0044 R/W DMA1 List Address Register Middle* %0045 R/W DMA1 List Address Register High* %0046 R/W DMA1 Control/Status Register %0047 R/W DMA2 List Address Register Low* %0048 R/W DMA2 List Address Register Middle* %0049 R/W DMA2 List Address Register High* %004A R/W DMA2 Control/Status Register %004B R/W DMA3 List Address Register Low* %004C R/W DMA3 List Address Register Middle* %004D R/W DMA3 List Address Register High* %004E R/W DMA3 Control/Status Register %004F R/W DMA4 List Address Register Low* %0050 R/W DMA4 List Address Register Middle* %0051 R/W DMA4 List Address Register High* %0052 R/W DMA4 Control/Status Register %0053 R/W DMA5 List Address Register Low* %0054 R/W DMA5 List Address Register Middle* %0055 R/W DMA5 List Address Register High* %0056 R/W DMA5 Control/Status Register %0057 R/W DMA6 List Address Register Low* %0058 R/W DMA6 List Address Register Middle* %0059 R/W DMA6 List Address Register High* %005A R/W DMA6 Control/Status Register %005B R/W DMA7 List Address Register Low* %005C R/W DMA7 List Address Register Middle* %005D R/W DMA7 List Address Register High* %005E R/W DMA7 Control/Status Register %005F R/W Note: * These addresses can be selected to access the Buffer Address and Buffer Length register for testing.

High-Performance Data Communications Processors Zilog

72 P R E L I M I N A R Y DS97Z382000

Register Name I/O Address Access HDLC Vector Register %003D R/W HDLC0 Transmit Mode Register %0060 R/W HDLC0 Transmit Interrupt Register %0061 R/W HDLC0 Transmit Control/Status %0062 R/W HDLC0 Transmit Fill Register %0063 R/W HDLC0 Receive Mode Register %0064 R/W HDLC0 Receive Interrupt Register %0065 R/W HDLC0 Counter Access Port %0066 R/W HDLC0 DMA Select Register %0067 R/W HDLC1 Transmit Mode Register &0068 R/W HDLC1 Transmit Interrupt Register %0069 R/W HDLC1 Transmit Control/Status Register %006A R/W HDLC1 Transmit Fill Register %006B R/W HDLC1 Receive Mode Register %006C R/W HDLC1 Receive Interrupt Register %006D R/W HDLC1 Counter Access Port %006E R/W HDLC1 DMA Select Register %006F R/W HDLC2 Transmit Mode Register %0070 R/W HDLC2 Transmit Interrupt Register %0071 R/W HDLC2 Transmit Control/Status Register %0072 R/W HDLC2 Transmit Fill Register %0073 R/W HDLC2 Receive Mode Register %0074 R/W HDLC2 Receive Interrupt Register %0075 R/W HDLC2 Counter Access Port %0076 R/W HDLC2 DMA Select Register %0077 R/W Register Name I/O Address Access GCI Control Register %00C0 R/W GCI Status Register 1 %00C1 RO GCI Status Register 2 %00C2 R/W GCI Interrupt Enable Register %00C3 R/W MON0 Transmit Data Register %00C4 WO MON0 Receive Data Register %00C4 RO MON1 Transmit Data Register %00C5 WO MON1 Receive Data Register %00C5 RO C/I0 Transmit Data Register %00C6 WO C/I0 Receive Data Register %00C6 RO C/I1 Transmit Data Register %00C7 WO C/I1 Receive Data Register %00C7 RO

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 73 Z80382 MIMIC REGISTERS Register Name I/O Address Access Host MMC Mimic Master Control Register %00FF R/W None IUS/IP Interrupt Pending %00FE R/Wb7 None IE Interrupt Enable %00FD R/W None IVEC Interrupt Vector %00FC R/W None RTCR Receive Time Constant %00FB R/W None TTCR Transmit Time Constant %00FA R/W None DLM Divisor Latch (MSByte) %00F9 RO %01, DLAB=1, R/W DLL Divisor Latch (LSByte) %00F8 RO %00, DLAB=1, R/W SCR Scratch Register %00F7 RO %07, R/W MSR Modem Status Register %00F6 R/Wb7-4 %06, RO LSR Line Status Register %00F5 R/Wb6432 %05, RO MCR Modem Control Register %00F4 RO %04, R/W LCR Line Control Register %00F3 RO %03, R/W IER Interrupt Enable Register %00F1 RO %01, DLAB=0, R/W RBR Receiver Buffer Register %00F0 WO %00, DLAB=0, RO THR Transmitter Holding Register %00F0 RO %00, DLAB=0, WO Mimic DMA Control Register %00EF R/W None FSCR FIFO Status and Control Register %00EC R/W7-4 None TTTC Transmitter Timeout Time Constant Register %00EB R/W None RTTC Receiver Timeout Time Constant Register %00EA R/W None IIR Interrupt IdentiÞcation Register None None %02, RO FCR FIFO Control Register %00E9 RO %02, RO Mimic ModiÞcation Register %00E9 WO None Host DMA Control Register %00e6 R/W None Mimic BRG High Constant Register %00E1 R/W Mimic BRG Low Constant Register %00E0 R/W IOBRG Register %00D6 R/W Host I/O Status Register %00D5 W bit1/R Base + 10b R Host DMA Mailbox Control Register %00D2 R/W None Host DMA Transmit Register 1 %00D1 RO /HDAK1, /HWR lo (Note) Host DMA Receive Register 1 %00D1 WO /HDAK1, /HRD lo Host DMA Transmit Register 0 %00D0 RO /HDAK0, /HWR lo Host DMA Receive Register 0 %00D0 WO /HDAK0, /HRD lo

High-Performance Data Communications Processors Zilog

74 P R E L I M I N A R Y DS97Z382000

PCMCIA MEMORY AND REGISTERS PLUG AND PLAY ISA REGISTERS Register Name I/O Address Access Host Low Attribute Memory %0100-177 R/W Attr 00-EE even Base Address Registers 0-6 %0178-17E R/W Attr F0-FC even Z80 Control Register %017F R/W None ConÞguration Option Register %0180 R/W Attr 100 ConÞguration Status Register %0181 R/W Attr 102 Pin Replacement Register %0182 R/W Attr 104 Socket Copy Register %0183 R/W Attr 106 Extended Status Register %0184 R/W Attr 108 Image Base Address Registers %0185,6 R/W Attr 10A, C Version Number Register %0187 R/W Attr 10E High Attribute Memory %0188-1FF R/W Attr 110-1FE even Register Name I/O Address Access Host PnP Address Register None I/O %0279, WO PnP Write Data Register None I/O %0A79, WO PnP Read Data Register None I/O %0203-3FF , RO Read Address Register None Pnp %00, WO Isolation Register None PnP %01, RO ConÞguration Control Register None PnP %02, WO Wake Register None PnP %03, WO PnP Master Register %0102 R/W None Resource Data Register %0104 WO PnP %04, RO PnP Status Register %0105 RO PnP %05, RO Card Select Number (CSN) Register %0106 RO PnP %06, R/W Logical Device Number Register None PnP %07, RO Activate Register %0130 R/W PnP %30, R/W I/O Range Check Register None PnP %31, R/W I/O Mailbox Base Address Registers %0160,1 R/W PnP %60,1, R/W Mimic Base Address Registers %0162,3 R/W PnP %62,3, R/W Interrupt Request Level Register %0170 R/W PnP %70, R/W DMA Channel 0,1 Registers %0174,5 R/W PnP %74,5, R/W

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 75

PACKAGE INFORMATION

Figure 38. 144-Lead QFP Package Diagram

76 P R E L I M I N A R Y DS97Z382000

Figure 39. 144-Lead VQFP Package Diagram

Zilog High-Performance Data Communications Processors DS97Z382000 P R E L I M I N A R Y 77

ORDERING INFORMATION

F = QFP (Plastic Quad Flatpack) A = VQFP (Very Small QFP) Temperature S = 0 to +70°C Speeds 10 = 10 MHz 20 = 20 MHz Environmental C = Plastic Standard Example: © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ZilogÕs products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com Part Number V DD Clock Speed(1) Package Type Package Code Oper. Temp. Z8038220ASC 5V ±10% 20 MHz VQFP MKT71C1173-00 0 to +70 °C Z8038220FSC 5V ±10% 20 MHz QFP MKT71C1163-00 0 to +70 °C Z8L38210ASC 3.3V ±10% 10 MHz VQFP MKT71C1173-00 0 to +70 °C Z8L38210FSC 3.3V ±10% 10 MHz QFP MKT71C1163-00 0 to +70 °C Note: 1. Refers to maximum internal bus clock frequency. See AC specifications for maximum external clock speed. Z 80382 20 F S C Environmental Flow Temperature Package Speed Product Number Zilog PreÞx is a Z80382, 20 MHz, QFP , 0° to +70°C, Plastic Standard Flow