Z8L180

Z80180 ZILOG | Alldatasheet

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ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAMILTON AVENUE • CAMPBELL, CA 95008 Z8018x Family MPU User Manual UM005001-ZMP0400

This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Windows is a registered trademark of Microsoft Corporation. Document Disclaimer © 2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

This user manual describes the features of the Z8018x Family MPUs.This manual provides basic programming information for the Z80180/Z8S180/ Z8L180. These cores and base perippheral sets are used in a large family of ZiLOG products. Below is a list of ZiLOG products that use this class of processor, along with the associated processor family.This document is also the core user manual for the following products: Intended Audience This manual is written for those who program the Z8018x Family. Manual Organization The Z8018x Family User Manual is divided into five sections, seven appendices, and an index. Part Family Z80180 Z80180 Z8S180 Z8S180 Z8L180 Z8L180 Z80181 Z80180 Z80182 Z80180, Z8S180* Z80S183 Z8S180 Z80185/195 Z8S180 Z80189 Z8S180 * Part number-dependant

Presents features, a general description, pins descriptions, block diagrams, registers, and details of operating modes for the Z8018x MPUs. Software Architecture Provides instruction sets and CPU registers for the Z8018x MPUs. DC Characteristics Presents the DC parameters and absolute maximum ratings for the Z8X180 MPUs. AC Characteristics Presents the AC parameters for the Z8018x MPUs. Timing Diagrams Contains timing diagrams and standard test conditions for the Z8018x MPUs. Appendices The appendixes in this manual provide additional information applicable to the Z8018x family of ZiLOG MPUs:

• Instruction set
• Instruction summary table
• Op Code map
• Bus Control signal conditions in each machine cycle and interrupt conditions
• Operating mode summary
• Status signals
• I/O registers and ordering information

v Table of Contents HALT and Low Power Operation Modes Low Power Modes

Table 5. Power-Down Modes Table 7. I/O Address Map

Table 51. Bus and Control Signal Condition in Each Table 56. Pin Status During RESET and

Z80180, Z8S180, Z8L180 MPU Operation

FEATURES

• Operating Frequency to 33 MHz
• On-Chip MMU Supports Extended Address Space
• Two DMA Channels
• On-Chip Wait State Generators
• Two Universal Asynchronous Receiver/Transmitter (UART) Channels
• Two 16-Bit Timer Channels
• On-Chip Interrupt Controller
• On-Chip Clock Oscillator/Generator
• Clocked Serial I/O Port
• Code Compatible with ZiLOG Z80 CPU
• Extended Instructions GENERAL DESCRIPTION Based on a microcoded execution unit and an advanced CMOS manufacturing technology, the Z80180, Z8S180, Z8L180 (Z8X180) is an 8-bit MPU which provides the benefits of reduced system costs and low power operation while offering higher performance and maintaining compatibility with a large base of industry standard software written around the ZiLOG Z8X CPU. Higher performance is obtained by virtue of higher operating frequencies, reduced instruction execution times, an enhanced instruction set, and an

on-chip memory management unit (MMU) with the capability of addressing up to 1 MB of memory. Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels. Also included on-chip are several glue functions such as dynamic RAM refresh control, wait state generators, clock oscillator, and interrupt controller. Not only does the Z8X180 consume a low amount of power during normal operation, but processors with Z8S180 and Z8L180 class processors also provides two operating modes that are designed to drastically reduce the power consumption even further. The SLEEP mode reduces power by placing the CPU into a stopped state, thereby consuming less current, while the on-chip I/O device is still operating. The SYSTEM STOP mode places both the CPU and the on-chip peripherals into a stopped state, thereby reducing power consumption even further. When combined with other CMOS VLSI devices and memories, the Z8X180 provides an excellent solution to system applications requiring high performance, and low power operation. Figures 1 through 3 illustrate the three pin packages in the Z8X180 MPU family:

• 64-Pin Dual In-line Package (DIP), Figure 1
• 68-Pin Plastic Leaded Chip Carrier (PLCC), Figure 2
• 80-Pin Quad Flat Pack (QFP), Figure 3 Pin out package descriptions for other Z8X180-based products are covered in their respective product specifications. Figure 4 depicts the block diagram that is shared throughout all configurations of the Z8X180.

Figure 1. 64-Pin DIP

Figure 2. 68-Pin PLCCA15

Figure 3. 80-Pin QFP

Figure 4. Z80180/Z8S180/Z8L180 Block Diagram

A0– A19. Address Bus (Output, Active High, 3-state). A0– A19 form a 20- bit address bus. The Address Bus provides the address for memory data bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64K. The address bus enters a high impedance state during RESET and external bus acknowledge cycles. Address line A18 is multiplexed with the output of PRT channel 1 (TOUT, selected as address output on RESET) and address line A19 is not available in DIP versions of the Z8X180. BUSACK . Bus Acknowledge (Output, Active Low). BUSACK indicates that the requesting device, the MPU address and data bus, and some control signals, have entered their high impedance state. BUSREQ. Bus Request (Input, Active Low). This input is used by external devices (such as DMA controllers) to request access to the system bus. This request has a higher priority than NMI and is always recognized at the end of the current machine cycle. This signal stops the CPU from executing further instructions and places the address and data buses, and other control signals, into the high impedance state. CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional, Active High). These pins are the transmit and receive clocks for the ASCI channels. CKA0, is multiplexed with DRE Q0 and CKA1 is multiplexed with TEND0. CKS. Serial Clock (Bidirectional, Active High). This line is the clock for the CSIO channel. CLOCK (PHI). System Clock (Output, Active High). The output is used as a reference clock for the MPU and the external system. The frequency of this output is equal to one-half that of the crystal or input clock frequency. CTS0, CTS1. Clear to Send 0 and 1 (Inputs, Active Low). These lines are modem control signals for the ASCI channels. CTS1 is multiplexed with RXS.

D0– D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high impedance state during RESET and external bus acknowledge cycles. DCD0. Data Carrier Detect 0 (Input, Active Low). This input is a programmable modem control signal for ASCI channel 0. DREQ0, DREQ1. DMA Request 0 and 1 (Input, Active Low). DREQ is used to request a DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these inputs to determine when an external device is ready for a read or write operation. These inputs can be programmed to be either level- or edge-sensed. DREQ 0 is multiplexed with CKA0. E. Enable Clock (Output, Active High). Synchronous machine cycle clock output during bus transactions. EXTAL. External Clock/Crystal (Input, Active High). Crystal oscillator connection. An external clock can be input to the Z8X180 on this pin when a crystal is not used. This input is Schmitt-triggered. HALT. Halt/Sleep Status (Output, Active Low). This output is asserted after the CPU has executed either the HALT or SLP instruction, and is waiting for either non-maskable or maskable interrupt before operation can resume. HALT is also used with the M1 and ST signals to decode status of the CPU machine cycle. INT0. Maskable Interrupt Request 0 (Input, Active Low). This signal is generated by external I/O devices. The CPU honors this request at the end of the current instruction cycle as long as the NMI and BUSREQ signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the M1 and IORQ signals become Active. INT1, INT2. Maskable Interrupt Requests 1 and 2 (Inputs, Active Low) . This signal is generated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the NMI,

BUSREQ, and INT0 signals are inactive. The CPU acknowledges these interrupt requests with an interrupt acknowledge cycle. Unlike the acknowledgment for INT0, during this cycle neither the M1 or IORQ signals become Active. IORQ. I/O Request (Output, Active Low, 3-state). IORQ indicates that the address bus contains a valid I/O address for an I/O read or I/O write operation. IORQ is also generated, along with M1, during the acknowledgment of the INT0 input signal to indicate that an interrupt response vector can be placed onto the data bus. This signal is analogous to the IOE signal of the Z64180. M1. Machine Cycle 1 (Output, Active Low). Together with MREQ, M1 indicates that the current cycle is the Op Code fetch cycle of an instruction execution. Together with IORQ, M1 indicates that the current cycle is for an interrupt acknowledge. It is also used with the HALT and ST signal to decode status of the CPU machine cycle. This signal is analogous to the LIR signal of the Z64180. MREQ. Memory Request (Output, Active Low, 3-state). MREQ indicates that the address bus holds a valid address for a memory read or memory write operation. This signal is analogous to the ME signal of the Z64180. NMI. Non-maskable Interrupt (Input, negative edge triggered). NMI has a higher priority than INT and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. This signal forces CPU execution to continue at location 0066H. RD. Read (Output active Low, 3-state). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O or memory device must use this signal to gate data onto the CPU data bus. RFSH. Refresh (Output, Active Low). Together with MREQ, RFSH indicates that the current CPU machine cycle and the contents of the address bus must be used for refresh of dynamic memories. The low order 8 bits of the address bus (A7 – A0) contain the refresh address. This signal is analogous to the REF signal of the Z64180.

programmable modem control signal for ASCI channel 0. are the receive data to the ASCI channels. Table 1. Status Summary

0 X1 1 DMA operation

TOUT. Timer Out (Output, Active High). TOUT is the pulse output from PRT channel 1. This line is multiplexed with A18 of the address bus. TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These signals are the transmitted data from the ASCI channels. Transmitted data changes are with respect to the falling edge of the transmit clock. TXS. Clocked Serial Transmit Data (Output, Active High). This line is the transmitted data from the CSIO channel. WAIT. Wait (Input; Active Low). WAIT indicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. This input is used to induce additional clock cycles into the current machine cycle. The WAIT input is sampled on the falling edge of T2 (and subsequent Wait States). If the input is sampled Low, then additional Wait States are inserted until the WAIT input is sampled High, at which time execution continues. WR. Write (Output, Active Low, 3-state). WR indicates that the CPU data bus holds valid data to be stored at the addressed I/O or memory location. XTAL. Crystal (Input, Active High). Crystal oscillator connection. This pin must be left open if an external clock is used instead of a crystal. The oscillator input is not a TTL level (reference DC characteristics). Multiplexed pins are described in Table2.

• Direct Memory Access (DMA) Control (2 channels)
• Asynchronous Serial Communications Interface (ASCI, 2 channels),

Table 2. Multiplexed Pin Descriptions are cleared to 0, A18 function is selected. During RESET, this pin is initialized as CKA 0 pin. set to 1, DREQ0 function is always selected. is selected. If CTS1E bit is 0, RXS function is selected.

• Programmable Reload Timers (PRT, 2 channels)
• Clock Serial I/O (CSIO) channel. Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195) feature, in addition to these blocks, additional peripherals and are covered in their associated Product Specification Clock Generator This logic generates the system clock from either an external crystal or clock input. The external clock is divided by two and provided to both internal and external devices. Bus State Controller This logic performs all of the status and bus control activity associated with both the CPU and some on-chip peripherals. This includes Wait State timing, RESET cycles, DRAM refresh, and DMA bus exchanges. Interrupt Controller This block monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the CPU. To remain compatible with the Z80 CPU, three different interrupt modes are supported. Memory Management Unit The MMU allows the user to map the memory used by the CPU (logically only 64K) into the 1MB addressing range supported by the Z8X180. The organization of the MMU object code features compatibility with the Z80 CPU while offering access to an extended memory space. This capability is accomplished by using an effective common area - banked area scheme.

The CPU is microcoded to provide a core that is object code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply and divide. This core has been enhanced to allow many of the instructions to execute in fewer clock cycles. DMA Controller The DMA controller provides high speed transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O and I/O to I/O. Transfer modes supported are REQUEST, BURST, and CYCLE STEAL. DMA transfers can access the full 1MB addressing range with a block length up to 64KB, and can cross over 64K boundaries. Asynchronous Serial Communications Interface (ASCI) The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels can also support a multiprocessor communications format. Programmable Reload Timer (PRT) This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow for waveform generation. Clocked Serial I/O (CSIO) The CSIO channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple high-speed data connection to another microprocessor or microcomputer.

the IORQ, RD, and WR signals, and the RETI operation. Figure 5. Operation Mode Control Register and the INT0 acknowledge cycle (Figure 6).

The user must program the Operation Mode Control Register before the first I/O instruction is executed. CPU Timing This section explains the Z8X180 CPU timing for the following operations:

• Instruction (Op Code) fetch timing
• Operand and data read/write timing
• I/O read/write timing
• Basic instruction (fetch and execute) timing
• RESET timing
• BUSREQ/BUSACK bus exchange timing The basic CPU operation consists of one or more Machine Cycles (MC). A machine cycle consists of three system clocks, T1, T2, and T3 while accessing memory or I/O, or it consists of one system clock (T1) during CPU internal operations. The system clock is half the frequency of the Crystal oscillator (that is, an 8-MHz crystal produces 4 MHz or 250 nsec). For interfacing to slow memory or peripherals, optional Wait States (TW) may be inserted between T2 and T3. Instruction (Op Code) Fetch Timing Figure 9 illustrates the instruction (Op Code) fetch timing with no Wait States. An Op Code fetch cycle is externally indicated when the M output pin is Low. In the first half of T1, the address bus (A0 – A19) is driven from the contents of the Program Counter (PC). This address bus is the translated address output of the Z8X180 on-chip MMU. In the second half of T1, the MREQ. (Memory Request) and RD (Read) signals are asserted Low, enabling the memory. Note:

Figure 10. Op Code Fetch (with Wait State) Timing Diagram

• The M1 output is held inactive
• The read cycle timing is relaxed by one-half clock cycle because data is latched at the falling edge of T3 Instruction operands include immediate data, displacement, and extended addresses, and contain the same timing as memory data reads. During memory write cycles the MREQ signal goes active in the second half of T1. At the end of T1, the data bus is driven with the write data. At the start of T2, the WR signal is asserted Low enabling the memory. MREQ and WR go inactive in the second half of T3 followed by disabling of the write data on the data bus. T1 T2T2 TW TW T3 T1 Phi A0– A19 D0– D7 MREQ RD WAIT Op Code

(Tw), while Figure 12 illustrates read/write timing with Wait States (TW). Figure 11. Memory Read/Write (without Wait State) Timing Diagram

Figure 13. I/O Read/Write Timing Diagram

Figure 14. Instruction Timing Diagram to the contents of an index register (IX).

Figure 17. Bus Exchange Timing During CPU Internal Operation can be inserted in both CPU execution and DMA transfer cycles. TW, another TW is inserted into the bus cycle.

Figure 19. Memory and I/O Wait State Insertion (DCNTL – DMA/Wait automatically generated by the on-chip Wait State generator. Table 3. Memory Wait States

Table 4. Wait State Insertion

1. For Z8X180 internal I/O register access (I/O addresses 0000H-003FH), IWI1 and IWI0 do not
2. For interrupt acknowledge cycles in which M

stacking cycle, memory access timing applies.

Also, the WAIT input is ignored during RESET. For example, if RESET is detected while the Z8X180 is in a Wait State (TW), the Wait Stated cycle in progress is aborted, and the RESET sequence initiated. Thus, RESET has higher priority than WAIT. HALT and Low Power Operation Modes (Z80180-Class Processors Only) The Z80180 can operate in two different modes:

• HALT mode
• IOSTOP mode and two low-power operation modes:
• SLEEP
• SYSTEM STOP In all operating modes, the basic CPU clock (XTAL, EXTAL) must remain active. HALT Mode HALT mode is entered by execution of the HALT instruction (Op Code 76H) and has the following characteristics:
• The internal CPU clock remains active
• All internal and external interrupts can be received
• Bus exchange ( BUSREQ and BUSACK) can occur
• Dynamic RAM refresh cycle ( RFSH) insertion continues at the programmed interval
• I/O operations (ASCI, CSI/O and PRT) continue
• The DMAC can operate

• The HALT output pin is asserted Low
• The external bus activity consists of repeated dummy fetches of the Op Code following the HALT instruction. Essentially, the Z80180 operates normally in HALT mode, except that instruction execution is stopped. HALT mode can be exited in the following two ways:
• RESET Exit from HALT Mode If the RESET input is asserted Low for at least six clock cycles, HALT mode is exited and the normal RESET sequence (restart at address 00000H) is initiated.
• Interrupt Exit from HALT mode When an internal or external interrupt is generated, HALT mode is exited and the normal interrupt response sequence is initiated. If the interrupt source is masked (individually by enable bit, or globally by IEF1 state), the Z80180 remains in HALT mode. However, NMI interrupt initiates the normal NMI interrupt response sequence independent of the state of IEF1. HALT timing is illustrated in Figure 20.

Figure 20. HALT Timing Diagram SLEEP mode is entered by execution of the 2-byte SLP instruction.

• The internal CPU clock stops, reducing power consumption
• The internal crystal oscillator does not stop
• Internal and external interrupt inputs can be received
• DRAM refresh cycles stop
• I/O operations using on-chip peripherals continue
• The internal DMAC stop
• BUSREQ can be received and acknowledged
• Address outputs go High and all other control signal outputs become inactive High RD MREQ Phi A0– A19 INT1, NMI T3 T1 T2 T3 T1 T2 HALT Op Code HALT mode Interrupt acknowledge cycle HALT HALT Op Code address HALT Op Code address + 1 Fetch Cycle

• Data Bus, 3-state SLEEP mode is exited in one of two ways as described below.
• RESET Exit from SLEEP mode. If the RESET input is held Low for at least six clock cycles, it exits SLEEP mode and begins the normal RESET sequence with execution starting at address (logical and physical) 00000H.
• Interrupt Exit from SLEEP mode. The SLEEP mode is exited by detection of an external ( NMI, INT0, INT2) or internal (ASCI, CSI/O, PRT) interrupt. In case of NMI, SLEEP mode is exited and the CPU begins the normal NMI interrupt response sequence. In the case of all other interrupts, the interrupt response depends on the state of the global interrupt enable flag IEF1 and the individual interrupt source enable bit. If the individual interrupt condition is disabled by the corresponding enable bit, occurrence of that interrupt is ignored and the CPU remains in the SLEEP mode. Assuming the individual interrupt condition is enabled, the response to that interrupt depends on the global interrupt enable flag (IEF1). If interrupts are globally enabled (IEF1 is 1) and an individually enabled interrupt occurs, SLEEP mode is exited and the appropriate normal interrupt response sequence is executed. If interrupts are globally disabled (IEF1 is 0) and an individually enabled interrupt occurs, SLEEP mode is exited and instruction execution begins with the instruction following the SLP instruction. This feature provides a technique for synchronization with high speed external events without incurring the latency imposed by an interrupt response sequence. Figure 21 depicts SLEEP timing.

Figure 21. SLEEP Timing Diagram IOSTOP mode is by resetting the IOSTOP bit in ICR to 0. SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes.

Low Power Modes (Z8S180/Z8L180 only) The following section is a detailed description of the enhancements to the Z8S180/L180 from the standard Z80180 in the areas of STANDBY, IDLE and STANDBY QUICK RECOVERY modes. Add-On Features There are five different power-down modes. SLEEP and SYSTEM STOP are inherited from the Z80180. In SLEEP mode, the CPU is in a stopped state while the on-chip I/Os are still operating. In I/O STOP mode, the on- chip I/Os are in a stopped state while leaving the CPU running. In SYSTEM STOP mode, both the CPU and the on-chip I/Os are in the stopped state to reduce current consumption. The Z8S180 features two additional power-down modes, STANDBY and IDLE, to reduce current consumption even further. The differences in these power-down modes are summarized in Table5.

• STANDBY mode
• IDLE mode The STANDBY/IDLE mode is selected by multiplexing bits 1 and 3 of the CPU Control Register (CCR, I/O Address = 1FH). To enter STANDBY mode:

Table 5. Power-Down Modes (Z8S180/Z8L180-Class Processors Only)

1.5 Clock

be achieved if INTERRUPT is used as the Recovery Source.

1. Set bits 6 and 3 to 1 and 0, respectively. 2. Set the I/O STOP bits (bit 5 of ICR, I/O Address = 3FH) to 1. 3. Execute the SLEEP instruction. When the device is in STANDBY mode, it performs similar to the SYSTEM STOP mode as it exists on the Z80180-class processors, except that the STANDBY mode stops the external oscillator, internal clocks and reduces power consumption to 50 µA (typical). Because the clock oscillator has been stopped, a restart of the oscillator requires a period of time for stabilization. An 18-bit counter has been added in the Z8S180Z8L180 to allow for oscillator stabilization. When the part receives an external IRQ or BUSREQ during STANDBY mode, the oscillator is restarted and the timer counts down 2 17 counts before acknowledgment is sent to the interrupt source. The recovery source must remain asserted for the duration of the 2 17 count, otherwise STANDBY restarts. STANDBY Mode Exit with BUS REQUEST Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the Z8S180 exits STANDBY mode when the BUSREQ input is asserted. The crystal oscillator is then restarted. An internal counter automatically provides time for the oscillator to stabilize, before the internal clocking and the system clock output of the Z8S180 are resumed. The Z8S180 relinquishes the system bus after the clocking is resumed by:

• 3-State the address outputs A19–A0
• 3-State the bus control outputs MREQ, IORQ, RD, and WR
• Asserting BUSACK The Z8S180 regains the system bus when BUSREQ is deactivated. The address outputs and the bus control outputs are then driven High. The STANDBY mode is exited.

If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting the BUSREQ does not cause the Z8S180/Z8L180-class processors to exit STANDBY mode. If STANDBY mode is exited because of a reset or an external interrupt, the Z8S180/Z8L180-class processors remains relinquished from the system bus as long as BUSREQ is active. STANDBY Mode EXit with External Interrupts STANDBY mode can be exited by asserting input NMI. The STANDBY mode may also exit by asserting INT0. INT1 or INT2, depending on the conditions specified in the following paragraphs. INT0 wake-up requires assertion throughout duration of clock stabilization time (2 17 clocks). If exit conditions are met, the internal counter provides time for the crystal oscillator to stabilize, before the internal clocking and the system clock output within the Z8S180/Z8L180-class processors resume.

• Exit with Non-Maskable Interrupts If NMI is asserted, the CPU begins a normal NMI interrupt acknowledge sequence after clocking resumes.
• Exit with External Maskable Interrupts If an External Maskable Interrupt input is asserted, the CPU responds according to the status of the Global Interrupt Enable Flag IEF1 (determined by the ITE1 bit) and the settings of the corresponding interrupt enable bit in the Interrupt/Trap Control Register (ITC: I/O Address = 34H). If an interrupt source is disabled in the ITC, asserting the corresponding interrupt input does not cause the Z8S180/Z8L180-class processors to exit STANDBY mode. This condition is true regardless of the state of the Global Interrupt Enable Flag IEF1.

If the Global Interrupt Enable Flag IEF1 is set to 1, and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input causes the Z8S180/Z8L180-class processors to exit STANDBY mode. The CPU performs an interrupt acknowledge sequence appropriate to the input being asserted when clocking is resumed if:

• The interrupt input follows the normal interrupt daisy-chain protocol
• The interrupt source is active until the acknowledge cycle is complete If the Global Interrupt Enable Flag IEF1 is disabled (reset to 0) and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input still causes the Z8S180/Z8L180-class processors to exit STANDBY mode. The CPU proceeds to fetch and execute instructions that follow the SLEEP instruction when clocking resumes. If the Extend Maskable Interrupt input is not active until clocking resumes, the Z8S180/Z8L180-class processors do not exit STANDBY mode. If the Non-Maskable Interrupt ( NMI ) is not active until clocking resumes, the Z8S180/Z8L180-class processors still exits the STANDBY mode even if the interrupt sources go away before the timer times out, because NMI is edge-triggered. The condition is latched internally when NMI is asserted Low. IDLE Mode IDLE mode is another power-down mode offered by the Z8S180/ Z8L180-class processors. 1. Set bits 6 and 3 to 0 and 1, respectively. 2. Set the I/O STOP bit (bit 5 of ICR, I/O Address = 3FH to 1. 3. Execute the SLEEP instruction When the part is in IDLE mode, the clock oscillator is kept oscillating, but the clock to the rest of the internal circuit, including the CLKOUT, is stopped completely. IDLE mode is exited in a similar way as STANDBY mode, using RESET, BUS REQUEST or EXTERNAL INTERRUPTS,

except that the 2 17 bit wake-up timer is bypassed. All control signals are asserted eight clock cycles after the exit conditions are gathered. STANDBY-QUICK RECOVERY Mode STANDBY-QUICK RECOVERY mode is an option offered in STANDBY mode to reduce the clock recovery time in STANDBY mode from 2 17 clock cycles (4 µs at 33 MHz) to 2 6 clock cycles (1.9 µs at 33 MHz). This feature can only be used when providing an oscillator as clock source. To enter STANDBY-QUICK RECOVERY mode: 1. Set bits 6 and 3 to 1 and 1, respectively. 2. Set the I/O STOP bit (bit 5 of ICR, I/O Address = 3FH) to 1. 3. Execute the SLEEP instruction When the part is in STANDBY-QUICK RECOVERY mode, the operation is identical to STANDBY mode except when exit conditions are gathered, using RESET, BUS REQUEST or EXTERNAL INTERRUPTS. The clock and other control signals are recovered sooner than the STANDBY mode. If STANDBY-QUICK RECOVERY is enabled, the user must ensure stable oscillation is obtained within 64 clock cycles Internal I/O Registers The Z8X180 internal I/O Registers occupy 64 I/O addresses (including reserved addresses). These registers access the internal I/O modules (ASCI, CSI/O, PRT) and control functions (DMAC, DRAM refresh, interrupts, wait state generator, MMU and I/O relocation). Note:

To avoid address conflicts with external I/O, the Z8X180 internal I/O addresses can be relocated on 64-byte boundaries within the bottom 256 bytes of the 64KB I/O address space. I/O Control Register (ICR) ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode. I/O Control Register (ICR: 3FH) Bit 7 6 5 4 3 2 1 0 Bit/Field IOA7 IOA6 IOSTP — — — — — R/W R/W R/W R/W Reset 0 0 0 R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7– 6 IOA7:6 R/W IOA7 and IOA6 relocate internal I/O as depicted in Figure . The high-order 8 bits of 16-bit internal I/O addresses are always 0. IOA7 and IOA6 are cleared to 0 during RESET. 5 IOSTP R/W IOSTOP mode is enabled when IOSTP is set to 1. Normal. I/O operation resumes when IOSTP is reset to 0.

Figure 22. I/O Address Relocation The internal I/O register addresses are described in Table6 and Table7.

OTDMR and TSTIO (see Instruction Set). external read data is ignored by the Z8X180. internal I/O addresses and duplicate I/O accesses. Table 6. I/O Address Map for Z80180-Class Processors Only

Table 6. I/O Address Map for Z80180-Class Processors Only (Continued)

Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)

Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)

Clock Multiplier Register (CMR: 1EH) (Z8S180/L180-Class Processors Only) Bit 7 6 0 Bit/Field X2 Reserved R/W R/W ? Reset 0 1 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 X2 Clock

6– 0 Reserved ? ? Reserved

CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only) Bit 7 6 5 4 3 2 1 0 Bit/Field Clock Divide STAND BY/ IDLE Enable BREXT LNPHI STAND BY/ IDLE Enable LNIO LNCPU CTL LNAD/ DATA R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 Clock

6 STANDBY

/IDLE Mode R/W In conjunction with Bit 3 No STANDBY IDLE after SLEEP STANDBY after SLEEP STANDBY after SLEEP 64 Cycle Exit (Quick Recovery)

5 BREXT R/W 0

Ignore BUSREQ in STANDBY/IDLE STANDBY/IDLE exit on BUSREQ

4 LNPHI R/W 0

33% Drive on EXTPHI Clock

3 STANDBY

/IDLE Mode R/W In conjunction with Bit 6 No STANDBY IDLE after SLEEP STANDBY after SLEEP STANDBY after SLEEP 64 Cycle Exit (Quick Recovery)

Memory Management Unit (MMU) The Z8X180 features an on-chip MMU which performs the translation of the CPU 64KB (16-bit addresses 0000H to FFFFH) logical memory address space into a 1024KB (20-bit addresses 00000H to FFFFFH) physical memory address space. Address translation occurs internally in parallel with other CPU operation. Logical Address Spaces The 64KB CPU logical address space is interpreted by the MMU as consisting of up to three separate logical address areas, Common Area 0, Bank Area, and Common Area 1. As depicted in Figure 23, a variety of logical memory configurations are possible. The boundaries between the Common and Bank Areas can be programmed with 4KB resolution.

2 LNIO R/W 0

33% Drive on certain external I/O

1 LNCPUCTL R/W 0

33% Drive on CPU control signals

0 LNAD/

33% drive on A10–A0, D7–D0 Bit Position Bit/Field R/W Value Description

• Memory Cycles Address Translation occurs for all memory access cycles including instruction and operand fetches, memory data reads and writes, hardware interrupt vector fetch, and software interrupt restarts.
• I/O Cycles The MMU is logically bypassed for I/O cycles. The 16-bit logical I/O address space corresponds directly with the 16-bit physical I/O address space. The four high-order bits (A16–A19) of the physical address are always 0 during I/O cycles.

Figure 26. I/O Address Translation

• DMA Cycles When the Z8X180 on-chip DMAC is using the external bus, the MMU is physically bypassed. The 20-bit source and destination registers in the DMAC are directly output on the physical address bus (A0–A19). MMU Registers Three MMU registers are used to program a specific configuration of logical and physical memory. LA15 PA19 LA0 PA16 PA15 PA0 “0000” Logical Address Physical Address

• MMU Common/Bank Area Register (CBAR)
• MMU Common Base Register (CBR)
• MMU Bank Base Register (BBR) CBAR is used to define the logical memory organization, while CBR and BBR are used to relocate logical areas within the 1024KB physical address space. The resolution for both setting boundaries within the logical space and relocation within the physical space is 4KB. The CA field of CBAR determines the start address of Common Area 1 (Upper Common) and by default, the end address of the Bank Area. The BA field determines the start address of the Bank Area and by default, the end address of Common Area 0 (Lower Common). The CA and BA fields of CBAR may be freely programmed subject only to the restriction that CA may never be less than BA. Figures 27 and 28 illustrate examples of logical memory organizations associated with different values of CA and BA.

Figure 27. Logical Memory Organization

Figure 28. Logical Space Configuration (Example)

MMU Common/Bank Area Register (CBAR) CBAR specifies boundaries within the Z8X180 64KB logical address space for up to three areas; Common Area 0, Bank Area and Common Area 1. MMU Common/Bank Area Register (CBAR: 3AH) Bit 7 6 5 4 3 2 1 0 Bit/Field CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7– 4 CA7– 4 R/W CA specifies the start (low) address (on 4KB boundaries) for the Common Area 1. This also determines the last address of the Bank Area. 3– 0 BA3– 0 R/W BA specifies the start (low) address (on 4KB boundaries) for the Bank Area. This also determines the last address of the Common Area 0.

MMU Common Base Register (CBR) CBR specifies the base address (on 4K boundaries) used to generate a 20- bit physical address for Common Area 1 accesses. All bits of CBR are reset to 0 during RESET. MMU Common Base Register (CBR: 38H) Bit 7 6 5 4 3 2 1 0 Bit/Field CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7– 0 CB7– 0 R/W CBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Common Area 1 accesses.

MMU Bank Base Register (BBR) BBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Bank Area accesses. All bits of BBR are reset to 0 during RESET. Physical Address Translation Figure 29 illustrates the way in which physical addresses are generated based on the contents of CBAR, CBR and BBR. MMU comparators classify an access by logical area as defined by CBAR. Depending on which of the three potential logical areas (Common Area 1, Bank Area, or Common Area 0) is being accessed, the appropriate 8- or 7-bit base address is added to the high-order 4 bits of the logical address, yielding a 19- or 20-bit physical address. CBR is associated with Common Area 1 accesses. Common Area 0, if defined, is always based at physical address 00000H. MMU Bank Base Register (BBR: 39H) Bit 7 6 5 4 3 2 1 0 Bit/Field BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7– 0 BB7– 0 R/W BBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Bank Area accesses.

During RESET, all bits of the CA field of CBAR are set to 1 while all bits of the BA field of CBAR, CBR and BBR are reset to 0. The logical 64KB address space corresponds directly with the first 64KB 0000H to FFFFH) of the 1024KB 00000H. to FFFFFH) physical address space. Thus, after RESET, the Z8X180 begins execution at logical and physical address 0. MMU Register Access Timing When data is written into CBAR, CBR or BBR, the value is effective from the cycle immediately following the I/O write cycle which updates these registers. During MMU programming insure that CPU program execution is not disrupted. The next cycle following MMU register programming is normally an Op Code fetch from the newly translated address. One technique is to localize all MMU programming routines in a Common Area that is always enabled.

section (that is, PRT, DMAC, ASCI, and CSI/O). Figure 31. Interrupt Sources two flags which are associated with interrupt processing.

Interrupt Vector Register (I) Mode 2 for INT0 external interrupt, INT1 and INT2 external interrupts, and all internal interrupts (except TRAP) use a programmable vectored technique to determine the address at which interrupt processing starts. In response to the interrupt a 16-bit address is generated. This address accesses a vector table in memory to obtain the address at which execution restarts. While the method for generation of the least significant byte of the table address differs, all vectored interrupts use the contents of I as the most significant byte of the table address. By programming the contents of I, vector tables can be relocated on 256 byte boundaries throughout the 64KB logical address space. I is read/written with the LD A, I and LD I, A instructions rather than I/O (IN, OUT) instructions. I is initialized to 00H during RESET. Interrupt Vector Low Register This register determines the most significant three bits of the low-order byte of the interrupt vector table address for external interrupts INT1 and INT2 and all internal interrupts (except TRAP). The five least significant bits are fixed for each specific interrupt source. By programming IL, the Function Name Access Method Interrupt Vector High I LD A,I and LD I, A instructions Interrupt Vector Low IL I/O instruction (addr = 33H) Interrupt/Trap Control ITC I/O instruction (addr = 34H) Interrupt Enable Flag 1,2 IEF1, IEF2 El and DI Note:

vector table can be relocated on 32 byte boundaries. IL is initialized to 00H during RESET. INT/TRAP Control Register (ITC) ITC is used to handle TRAP interrupts and to enable or disable the external maskable interrupt inputs INT0, INT1 and INT2. Interrupt Vector Low Register (IL: 33H) Bit 7 6 5 4 3 2 1 0 Bit/Field IL7 IL6 IL5 ? R/W R/W R/W R/W ? Reset 00H 00H 00H ? Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7– 5 IL7– 5 R/W The IL register is an internal I/O register which is programmed with the OUT0 instruction and can be read using the IN0 instruction. 4– 0 ? N/A Interrupt source dependent code

Interrupt Enable Flag 1,2 (IEF1, IEF2) IEF1 controls the overall enabling and disabling of all internal and external maskable interrupts (that is, all interrupts except NMI and TRAP. INT/TRAP Control Register (ITC: 34H) Bit 7 6 5 4 3 2 1 0 Bit/Field TRAP UFO ? ITE2 ITE1 ITE0 R/W R/W R N/A R/W R/W R/W Reset 0 0 0 0 0 1 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7 TRAP R/W This bit is set to 1 when an undefined Op Code is fetched. TRAP can be reset under program control by writing it with 0, however, it cannot be written with 1 under program control. 6 UFO R Undefined Fetch Object (bit 6). When a TRAP interrupt occurs the contents of UFO allow determination of the starting address of the undefined instruction. This action is necessary since the TRAP may occur on either the second or third byte of the Op Code. UFO allows the stacked PC value to be correctly adjusted. If UFO = 0, the first Op Code should be interpreted as the stacked PC-1. If UFO = 1, the first Op Code address is stacked PC-2. 2– 0 ITE2– 0 R/W Interrupt Enable — ITE2, ITE1 and ITE0 enable and disable the external interrupt inputs INT2 , INT1 and INT0, respectively. If reset to 0, the interrupt is masked.

The purpose of IEF2 is to correctly manage the occurrence of NMI. CPU Status Register by executing LD A, I or LD A, R instructions. Table 8. State of IEF1 and IEF2

1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1.
2. The current PC (Program Counter) value, reflecting location of the

undefined Op Code, is saved on the stack.

1. The Z8X180 vectors to logical address 0. Note that if logical address

Table 8. State of IEF1 and IEF2 (Continued)

Figure illustrates Trap Timing - 3rd Op Code undefined. Figure 32. TRAP Timing Diagram -2nd Op Code Undefined

Figure 33. TRAP Timing - 3rd Op Code Undefined

• NMI–Non-maskable interrupt
• INT0–Maskable Interrupt Level 0
• INT1–Maskable Interrupt Level 1
• INT2–Maskable Interrupt Level 2 NMI, INT1, and INT2 feature fixed interrupt response modes. INT0 has 3 different software programmable interrupt response modes—Mode 0, Mode 1 and Mode 2. NMI - Non-Maskable Interrupt The NMI interrupt input is edge-sensitive and cannot be masked by software. When NMI is detected, the Z8X180 operates as follows: Phi A0– A19 WR RD MREQ D0– D7 MI TiT1 TiTiT1 T2 T3 T2T3 T1 T3T1 T2T3T1 T2 TTP T1 T2 T3 Memory PC stacking Restart from 0000H Op Code fetch cycle 0000HSP-1 SP-2 PCLPCH IX+d, IY+dPC 3rd Op Code Fetch Cycle Undefined Op Code Read Cycle

1. DMAC operation is suspended by the clearing of the DME (DMA Main Enable) bit in DCNTL. 2. The PC is pushed onto the stack. 3. The contents of IEF1 are copied to IEF2. This saves the interrupt reception state that existed prior to NMI. 4. IEF1 is cleared to 0. This disables all external and internal maskable interrupts (that is, all interrupts except NMI and TRAP). 5. Execution commences at logical address 0066H. The last instruction of an NMI service routine must be RETN (Return from Non-maskable Interrupt). This restores the stacked PC, allowing the interrupted program to continue. Furthermore, RETN causes IEF2 to be copied to IEF1, restoring the interrupt reception state that existed prior to NMI. NMI, because it can be accepted during Z8X180 on-chip DMAC operation, can be used to externally interrupt DMA transfer. The NMI service routine can reactivate or abort the DMAC operation as required by the application. For NMI, take special care to insure that interrupt inputs do not overrun the NMI service routine. Unlimited NMI inputs without a corresponding number of RETN instructions eventually cause stack overflow. Figure 34 depicts the use of NMI and RETN while Figure 35 details NMI response timing. NMI is edge sensitive and the internally latched NMI falling edge is held until it is sampled. If the falling edge of NMI is latched before the falling edge of the clock state prior to T3 or T1 in the last machine cycle, the internally latched NMI is sampled at the falling edge of the clock state prior to T3 or T1 in the last machine cycle and NMI acknowledge cycle begins at the end of the current machine cycle. Note:

Figure 34. NMI Use

Figure 35. NMI Timing

1. IEF1 is 0, so INT0 is masked
2. ITE0 is 1, so INT0 is enabled by execution of the El (Enable

selected with the IM 0, IM 1 and IM 2 (Set Interrupt Mode) instructions.

• Mode 0–Instruction fetch from data bus
• Mode 1–Restart at logical address 0038H
• Mode 2–Low-byte vector table address fetch from data bus INT0 Mode 0 During the interrupt acknowledge cycle, an instruction is fetched from the data bus (DO – D7) at the rising edge of T3. Often, this instruction is one of the eight single byte RST (RESTART) instructions which stack the PC and restart execution at a fixed logical address. However, multibyte instructions can be processed if the interrupt acknowledging device can provide a multibyte response. Unlike all other interrupts, the PC is not automatically stacked:

Figure 36. INT0 Mode 0 Timing Diagram

Figure 38. INT0 Mode 1 Timing restart addresses stored in low byte, high byte order.

Figure 39. INT0 Mode 2 Vector Acquisition the vector table and execution begins at that address. external vector fetch cycles. Mode 2 INT0 interrupt. Figure illustrates INT0 interrupt Mode 2 Timing.

256 Bytes

Figure 40. INT0 Interrupt Mode 2 Timing Diagram

Figure 41. INT1, INT2 Vector Acquisition 1,2) of the INT/TRAP control register to 0. During RESET, IEF1, ITE1 and ITE2 bits are reset to 0. as INT1 and INT2. Internal interrupts are globally masked by IEF1 is 0.

32 Bytes

vector of INT1 INT2 and internal interrupt are summarized in Table9. interrupt request is accepted. Table 9. Vector Table

Interrupt Sources During RESET Interrupt Vector Register (I) All bits are reset to 0. Because I = 0 locates the vector tables starting at logical address 0000H vectored interrupts ( INT0 Mode 2, INT1, INT2, and internal interrupts) overlap with fixed restart interrupts like RESET (0), NMI (0066H), INT0 Mode 1 (0038H) and RST (0000H-0038H). The vector table(s) are built elsewhere in memory and located on 256 byte boundaries by reprogramming I with the LD I, A instruction. IL Register Bits 7 - 5 are reset to 0 The IL Register can be programmed to locate the vector table for INT1, INT2 and internal interrupts on 32-byte subboundaries within the 256 byte area specified by I. IEF1, IEF2 Flags Reset to 0. Interrupts other than NMI and TRAP are disabled. ITC Register ITE0 set to 1. ITE1, ITE2 reset to 0. INT0 can be enabled by the EI instruction, which sets IEF1 to 1. Enabling INT1 and INT2 also requires that the ITE1 and ITE2 bits be respectively set to 1 by writing to ITC. I/O Control Registers Interrupt enable bits reset to 0. All Z8X180 on-chip I/O (PRT, DMAC, CSI/O, ASCI) interrupts are disabled and can be individually enabled by writing to each I/O control register interrupt enable bit.

the instruction and behave accordingly. peripherals are connected to the Z8018X. Figure 42. RETI Instruction Sequence Note: RETI machine cycles 9 and 10 not shown.

Table 10. RETI Control Signal States

1 T1-T3 1st

2 TI-T3 2nd

3 T1 Don't

4 T1 Don't

5 T1 Don't

6 T1-T3 1st

7 T1 Don't

8 T1-T3 2nd

9 T1-T3 SP data 0 1 0 1 1 1 1 1

10 T1-T3 SP+1 data 0 1 0 1 1 1 1 1

Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram

• Two Wait States are automatically inserted.

Refresh Control Register (RCR) The RCR specifies the interval and length of refresh cycles, while enabling or disabling the refresh function. Refresh Control Register (RCR: 36H) Bit 7 6 5 4 3 2 1 0 Bit/Field REFE REFW ? CYC1 CYC0 R/W R/W R/W ? R/W R/W Reset 1 1 ? 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 REFE R/W

REFE: Refresh Enable Disables the refresh controller Enables refresh cycle insertion.

6 REFW R/W

Refresh Wait (bit 6) Causes the refresh cycle to be two clocks in duration. Causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle (TRW). 1– 0 CYC1– 0 R/W Cycle Interval — CYC1 and CYC0 specify the interval (in clock cycles) between refresh cycles. In the case of dynamic RAMs requiring 128 refresh cycles every 2 ms (or 256 cycles in every 4 ms), the required refresh interval is less than or equal to 15.625 µs. Thus, the underlined values indicate the best refresh interval depending on CPU clock frequency. CYC0 and CYC1 are cleared to 0 during RESET. Refer to Table11.

with an interval of ten clock cycles and are three clock cycles in duration.

1. Refresh Cycle insertion is stopped when the CPU is in the following
2. Refresh cycles are suppressed when the bus is released in response to

relationship with the bus exchange. Table 11. DRAM Refresh Intervals

1. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is requested during SLEEP mode, the refresh cycle request is internally latched (until replaced with the next refresh request). The latched refresh cycle is inserted at the end of the first machine cycle after SLEEP mode is exited. After this initial cycle, the time at which the next refresh cycle occurs depends on the refresh time and has no timing relationship with the exit from SLEEP mode. 4. Regarding (2) and (3), the refresh address is incremented by one for each successful refresh cycle, not for each refresh request. Thus, independent of the number of missed refresh requests, each refresh bus cycle uses a refresh address incremented by one from that of the previous refresh bus cycles. DMA Controller (DMAC) The Z8X180 contains a two-channel DMA (Direct Memory Access) controller which supports high speed data transfer. Both channels (channel 0 and channel 1) feature the following capabilities:

• Memory Address Space Memory source and destination addresses can be directly specified anywhere within the 1024KB physical address space using 20-bit source and destination memory addresses. In addition, memory transfers can arbitrarily cross 64KB physical address boundaries without CPU intervention.
• I/O Address Space I/O source and destination addresses can be directly specified anywhere within the 64KB I/O address space (16-bit source and destination I/O addresses).
• Transfer Length Up to 64KB are transferred based on a 16- bit byte count register.

• DREQ Input Level- and edge-sense DREQ input detection are selectable. TEND Output Used to indicate DMA completion to external devices.
• Transfer Rate Each byte transfer occurs every 6 clock cycles. Wait States can be inserted in DMA cycles for slow memory or I/O devices. At the system clock ( φ) = 6 MHz, the DMA transfer rate is as high as 1.0 megabytes/second (no Wait States). There is an additional feature disc for DMA interrupt request by DMA END. Each channel has the following additional specific capabilities: Channel 0
• Memory to memory
• Memory to I/O
• Memory to memory mapped I/O transfers.
• Memory address increment, decrement, no-change
• Burst or cycle steal memory to/from memory transfers
• DMA to/from both ASCI channels
• Higher priority than DMAC channel 1 Channel 1
• Memory to/from I/O transfer
• Memory address increment, decrement DMAC Registers Each channel of the DMAC (channel 0, 1) contains three registers specifically associated with that channel.

• SAR0–Source Address Register
• DAR0–Destination Address Register
• BCR0–Byte Count Register Channel 1
• MAR1– Memory Address Register
• IAR1–I/O Address Register
• BCR1–Byte Count Register The two channels share the following three additional registers in common:
• DSTAT–DMA Status Register
• DMODE–DMA Mode Register
• DCNTL–DMA Control Register DMAC Block Diagram Figure 45 depicts the Z8X180 DMAC Block Diagram.

Figure 45. DMAC Block Diagram

DMA Destination Address Register Channel 0 (DAR0 I/O Address = 23H to 25H) Specifies the physical destination address for channel 0 transfers. The register contains 20 bits and can specify up to 1024KB memory addresses or up to 64KB I/O addresses. Channel 0 destination can be memory, I/O, or memory mapped I/O. DMA Byte Count Register Channel 0 (BCR0 I/O Address = 26H to 27H) Specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64KB transfers. When one byte is transferred, the register is decremented by one. If n bytes are transferred, n is stored before the DMA operation. DMA Memory Address Register Channel 1 (MAR1: I/O Address = 28H to 2AH) Specifies the physical memory address for channel 1 transfers. This address may be a destination or source memory address. The register contains 20 bits and may specify up to 1024KB memory address. DMA I/O Address Register Channel 1 (IAR1: I/O Address = 2BH to 2CH) Specifies the I/O address for channel 1 transfers. This address may be a destination or source I/O address. The register contains 16 bits and may specify up to 64KB I/O addresses. DMA Byte Count Register Channel 1 (BCR1: I/O Address = 2EH to 2FH) Specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64KB transfers. When one byte is transferred, the register is decremented by one.

DMA Status Register (DSTAT) DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DSTAT also determines DMA transfer status, that is, completed or in progress. DMA Status Register (DSTAT: 30H) Bit 7 6 5 4 3 2 1 0 Bit/Field DE1 DE0 DWE1 DWE0 DIE1 DIE0 ? DME R/W R/W R/W W W R/W R/W ? R Reset 0 0 1 1 0 0 ? Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 DE1 R/W Enable Channel 1 — When DE1 = 1 and DME = 1,

channel 1 DMA is enabled. When a DMA transfer terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC. When DE1 = 0 and the DMA interrupt is enabled (DIE1 = 1), a DMA interrupt request is made to the CPU. To perform a software write to DE1, DWE1 is written with 0 during the same register write access. Writing DE1 to 0 disables channel 1 DMA, but DMA is restartable. Writing DE1 to 1 enables channel 1 DMA and automatically sets DME (DMA Main Enable) to 1. DE1 is cleared to 0 during RESET.

6 DE0 R/W Enable Channel 0 — When DE0 = 1 and DME = 1,

channel 0 DMA is enabled. When a DMA transfer terminates BCR0 = 0), DE0: is reset to 0 by the DMAC. When DE0 = 0 and the DMA interrupt is enabled (DIE0 = 1), a DMA interrupt request is made to the CPU. To perform a software write to DE0, DWE0 must be written with 0 during the same register write access. Writing DE0 to 0 disables channel 0 DMA. Writing DE0 to 1 enables channel 0 DMA and automatically sets DME (DMA Main Enable) to 1. DE0 is cleared to 0 during RESET.

5 DWE1

W Bit Write Enable 1 — When performing any software write to DEI, DWE1 must be written with 0 during the same access. DWE1 write value of 0 is not held and DWE1 is always read as 1.

4 DWE0 W Bit Write Enable 0 — When performing any software

write to DE0, DWE0 must be written with 0 during the same access. DWE0 write value of 0 is not held and DWE0 is always read as 1.

3 DIE1 R/W DMA Interrupt Enable Channel 1 — When DIE1 is set

to 1, the termination channel 1 DMA transfer (indicated when DE1 is 0) causes a CPU interrupt request to be generated. When DIE1 is 0, the channel 1 DMA termination interrupt is disabled. DIE1 is cleared to 0 during RESET.

2 DIE0 DMA Interrupt Enable Channel 0 — When DIE0 is set

to 1, the termination channel 0 of DMA transfer (indicated when DE0 is 0) causes a CPU interrupt request to be generated. When DIE0 is 0, the channel 0 DMA termination interrupt is disabled. DIE0 is cleared to 0 during RESET. Bit Position Bit/Field R/W Value Description

DMA Mode Register (DMODE) DMODE is used to set the addressing and transfer mode for channel 0.

0 DME R DMA Main Enable — A DMA operation is only enabled

when its DE bit DE0 for channel 0, DE1 for channel 1) and the DME bit are set to 1. When NMI occurs, DME is reset to 0, thus disabling DMA activity during the NMI interrupt service routine. To restart DMA, DE0 and/or DE1 must be written with 1 (even if the contents are already 1). This action automatically sets DME to 1, allowing DMA operations to continue. DME cannot be directly written. It is cleared to 0 by NMI or indirectly set to 1 by setting DE0 and/or DE1 to 1.DME is cleared to 0 during RESET. DMA Mode Register (DMODE: 31H) Bit 7 6 5 4 3 2 1 0 Bit/Field ? DM1 DM0 SM1 SM0 MMOD ? R/W ? R/W R/W R/W R/W R/W ? Reset ? 0 0 0 0 0 ? Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 5– 4 DM1:0 R/W Destination Mode Channel 0 — Specifies whether the destination for channel 0 transfers is memory, I/O or memory mapped I/O and the corresponding address modifier. Reference Table12. Bit Position Bit/Field R/W Value Description

mapped I/O and the corresponding address modifier.

1 MMOD R/W DMA Memory Mode Channel 0 — When channel 0 is

cycle until the transfer is completed. Table 12. Channel 0 Destination

12 combinations are available. Table 13. Channel 0 Source Table 14. Transfer Mode Combinations

memory to/from I/O transfers. Note: *: includes memory mapped I/O.

DMA/WAIT Control Register (DCNTL: 32H) Bit 7 6 5 4 3 2 1 0 Bit/Field MWI1 MWI0 IWI1 IWI0 DMS1 DMS0 DIM1 DIM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7– 6 MWI1– 0 R/W Memory Wait Insertion —Specifies the number of wait states introduced into CPU or DMAC memory access cycles. MWI1 and MWI0 are set to 1 during RESET. See section on Wait State Generator for details. 5– 4 IWI1– 0 R/W Wait Insertion — Specifies the number of Wait States introduced into CPU or DMAC I/O access cycles. IWI1 and IWI0 are set to 1 during RESET. See section on Wait State Generator for details. 3– 2 DMS1– 0 R/W DMA Request Sense — Specifies the DMA request sense for channel 0 ( DREQ0 ) and channel 1 ( DREQ1) respectively. When reset to 0, the input is level-sense. When set to 1, the input is edge-sense. 1– 0 DIM1– 0 R/W DMA Channel 1 I/O and Memory Mode — Specifies the source/destination and address modifier for channel 1 memory to/from I/O transfer modes. Reference Table15.

Table 15. Channel 1 Transfer Mode

7 R/W

6 R/W Currently selected DMA channel when Bit 7 = 1

5– 4 Reserved R/W 0 Reserved. Must be 0.

3 R/W 0

This bit must be set to 1 only when both DMA channels are set to take their requests from the same device. If this bit is 1 (it resets to 0), the TEND output of DMA channel o sets a flip-flop, so that thereafter the device’s request is visible to channel 1, but not visible to channel 0. The internal TEND signal of channel 1 clears the FF, so that thereafter, the device’s request is visible to channel 0, but no visible to channel 1. If DMA request are from differing sources, DMA channel 0 request is forced onto DMA channel 1 after TEND output of DMA channel 0 sets the flop-flop to alternate. Bit 6 When both DMA channels are programmed to take their requests from the same device, this bit (FF mentioned in the previous paragraph) controls which channel the device’s request is presented to: 0 = DMA0, 1 = DMA l. When Bit 7 is 1, this bit is automatically toggled by the channel end output of the channels. 2-0 R/W 000 001 010 011 111 DMA1 ext TOUT/DREQ DMA1 ASCI0 DMA1 ASCI1 DMA1 ESCC DMA1 PIA27-20 (P1284) Bit Position Bit/Field R/W Value Description

Bits 5–3 Reserved. Must be 0. Bits 2–0 With DIM1, bit 1 of DCNTL, these bits control which request is presented to DMA channel 1, as described below: DMA Operation This section discusses the three DMA operation modes for channel 0:

• Memory to/from memory
• Memory to/from I/O
• Memory to/from memory mapped I/O DIM1 IAR18–16 Request Routed to DMA Channel 1 000 001 010 011 10X 1X0 111 DREQ1 ASCI0 Tx ASCI1 Tx ext CKA0/ DREQ0 Reserved Reserved Reserved 000 001 010 011 10X 1X0 111 ext DREQ1 ASCI0 Rx ASCI1 Rx ext CKA0/ DREQ0 Reserved Reserved Reserved

In addition, the operation of channel 0 DMA with the on-chip ASCI (Asynchronous Serial Communication Interface) as well as Channel 1 DMA are described. Memory to Memory—Channel 0 For memory to/from memory transfers, the external DREQ0 input is not used for DMA transfer timing. Rather, the DMA operation is timed in one of two programmable modes – BURST or CYCLE STEAL. In both modes, the DMA operation automatically proceeds until termination (shown by byte count-BCR0) = 0. In BURST mode, the DMA operation proceeds until termination. In this case, the CPU cannot perform any program execution until the DMA operation is completed. In CYCLE STEAL mode, the DMA and CPU operation are alternated after each DMA byte transfer until the DMA is completed. The sequence:

• 1 CPU Machine Cycle
• DMA Byte Transfer is repeated until DMA is completed. Figure 46 describes CYCLE STEAL mode DMA timing.

Figure 46. DMA Timing Diagram-CYCLE STEAL Mode

1. Load the memory source and destination address into SAR0 and DAR0
2. Specify memory to/from memory mode and address increment/

decrement in the SM0 SM1, DM0 and DM1 bits of DMODE.

1. Load the number of bytes to transfer in BCR0.
2. Specify burst or cycle steal mode in the MMOD bit of DCNTL.
3. Program DE0 = 1 (with DWE0 = 0 in the same access) in DSTAT

occurs at the same time, the DIE0 bit must be set to 1.

memory mapped I/O. transfers, the CKA0/ DREQ0 pin automatically functions as input pin or output pin even if it has been programmed as output pin for CKA0. And the CKA1/ TEND0 pin functions as an input or an output pin for TEND0 by setting CKA1D to 1 in CNTLA1. To initiate memory to/from I/O (and memory to/from memory mapped I/O) DMA transfer for channel 0, perform the following operations: 1. Load the memory and I/O or memory mapped I/O source and destination addresses into SAR0 and DAR0. I/O addresses (not memory mapped I/O are limited to 16 bits (A0– A15). Make sure that bits A16, A17 and A19 are 0 (A18 is a don't care) to correctly enable the external DREQ0 input. 2. Specify memory to/from I/O or memory to/from memory mapped I/O mode and address increment/decrement in the SM0, SM1, DM0 and DM1 bits of DMODE. 3. Load the number of bytes to transfer in BCR0. 4. Specify whether DREQ0 is edge- or level-sense by programming the DMS0 bit of DCNTL. 5. Enable or disable DMA termination interrupt with the DIE0 bit in DSTAT. 6. Program DE0: = 1 (with DWEO = 0 in the same access) in DSTAT and the DMA operation begins under the control of the DREQ0 input. Memory to ASCI - Channel 0 Channel 0 has extra capability to support DMA transfer to/from the on- chip two channel ASCI. In this case, the external DREQ0 input is not used for DMA timing. Rather, the ASCI status bits are used to generate an internal DREQ0 The TDRE (Transmit Data Register Empty) bit and the RDRF (Receive Data Register Full) bit are used to generate an internal

1. Load the source and destination addresses into SAR0 and DAR0

transmitter or receiver (I/O addresses 6H-9H). b. Bits A8–A15 must equal 0. Table 16. DMA Transfer Request

1. Specify memory ↔ I/O transfer mode and address increment/ decrement in the SM0, SM1, DM0 and DM1 bits of DMODE. 3. Load the number of bytes to transfer in BCR0 4. The DMA request sense mode (DMS0 bit in DCNTL) must be specified as edge sense. 5. Enable or disable DMA termination interrupt with the DIE0 bit in DSTAT. 6. Program DE0 =1 (with DWE0 = 0 in the same access) in DSTAT and the DMA operation with the ASCI begins under control of the ASCI generated internal DMA request. The ASCI receiver or transmitter using DMA is initialized to allow the first DMA transfer to begin. The ASCI receiver must be empty as shown by RDRF = 0. The ASCI transmitter must be full as shown by TDRE = 0. Thus, the first byte is written to the ASCI Transmit Data Register under program control. The remaining bytes are transferred using DMA. Channel 1 DMA DMAC Channel 1 performs memory to/from I/O transfers. Except for different registers and status/control bits, operation is exactly the same as described for channel 0 memory to/from I/O DMA. To initiate a DMA channel 1 memory to/from I/O transfer, perform the following operations: 1. Load the memory address (20 bits) into MAR1. 2. Load the I/O address (16 bits) into IAR1. 3. Program the source/destination and address increment/decrement mode using the DIM1 and DIM0 bits in DCNTL.

1. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in DCNTL. 5. Enable or disable DMA termination interrupt with the DIE1 bit in DSTAT. 6. Program DE1 = 1 (with DWE1 = 0 in the same access) in DSTAT and the DMA operation with the external I/O device begins using the external DREQ1 input and TEND1 output. DMA Bus Timing When memory (and memory mapped I/O) is specified as a source or destination, MREQ goes Low during the memory access. When I/O is specified as a source or destination, IORQ goes Low during the I/O access. When I/O (and memory mapped I/O) is specified as a source or destination, the DMA timing is controlled by the external DREQ input and the TEND output indicates DMA termination External I/O devices may not overlap addresses with internal I/O and control registers, even using DMA. For I/O accesses, one Wait State is automatically inserted. Additional Wait States can be inserted by programming the on-chip wait state generator or using the external WAIT input. For memory mapped I/O accesses, this automatic I/O Wait State is not inserted. For memory to memory transfers (channel 0 only), the external DREQ0 input is ignored. Automatic DMA timing is programmed as either BURST or CYCLE STEAL. When a DMA memory address carry/borrow between bits A15 and A16 of the address bus occurs (crossing 64KB boundaries), the minimum bus Note: Note:

cycle is extended to 4 clocks by automatic insertion of one internal Ti state. DMAC Channel Priority For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority over channel 1. When channel 0 is performing a memory to/from memory transfer, channel 1 cannot operate until the channel 0 operation has terminated. If channel 1 is operating, channel 0 cannot operate until channel 1 releases control of the bus. DMAC and BUSREQ, BUSACK The BUSREQ and BUSACK inputs allow another bus master to take control of the Z8X180 bus. BUSREQ and BUSACK take priority over the on-chip DMAC and suspends DMAC operation. The DMAC releases the bus to the external bus master at the breakpoint of the DMAC memory or I/O access. Since a single byte DMAC transfer requires a read and a write cycle, it is possible for the DMAC to be suspended after the DMAC read, but before the DMAC write. Hence, when the external master releases the Z8X180 bus (BUSREQ High), the on-chip DMAC correctly continues the suspended DMA operation.

The key functions for ASCI on Z80180, Z8S180 and Z8L180 class processors are listed below. Each channel is independently programmable.

• Full-duplex communication
• 7- or 8-bit data length
• Program controlled 9th data bit for multiprocessor communication
• 1 or 2 stop bits
• Odd, even, no parity
• Parity, overrun, framing error detection
• Programmable baud rate generator, /16 and /64 modes
• Modem control signals – Channel 0 contains DCD0, CTS0 and RTS0; Channel 1 contains CTS1
• Programmable interrupt condition enable and disable
• Operation with on-chip DMAC ASCI Block Diagram for the Z8S180/Z8L180-Class Processors Figure 52 illustrates the ASCI block diagram.

Figure 52. ASCI Block Diagram Transmit Data Register (TDR), the data is shifted out to the TXA pin.

When transmission is completed, the next byte (if available) is automatically loaded from TDR into TSR and the next transmission starts. If no data is available for transmission, TSR idles by outputting a continuous High level. The TSR is not program-accessible. ASCI Transmit Data Register 0, 1(TDR0,1:I/O Address = 06H, 07H) Data written to the ASCI Transmit Data Register is transferred to the TSR as soon as TSR is empty. Data can be written while TSR is shifting out the previous byte of data. Thus, the ASCI transmitter is double buffered. Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation is not affected by this read operation. ASCI Transmit Data Register Ch. 0 (TDR0: 06H) Bit 7 6 5 4 3 2 1 0 Bit/Field ASCI Transmit Channel 0 R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable ASCI Transmit Data Register Ch. 1 (TDR1: 07H) Bit 7 6 5 4 3 2 1 0 Bit/Field ASCI Transmit Channel 1 R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable

ASCI Receive Shift Register 0,1(RSR0, 1) This register receives data shifted in on the RXA pin. When full, data is automatically transferred to the ASCI Receive Data Register (RDR) if it is empty. If RSR is not empty when the next incoming data byte is shifted in, an overrun error occurs. The RSR is not program-accessible. ASCI Receive Data Register 0,1 (RDR0, 1: I/O Address = 08H, 09H) When a complete incoming data byte is assembled in RSR, it is automatically transferred to the RDR if RDR is empty. The next incoming data byte can be shifted into RSR while RDR contains the previous received data byte. Thus, the ASCI receiver on Z80180 is double- buffered. On the Z8S180 and Z8L180-class processors are quadruple buffered. The ASCI Receive Data Register is a read-only register. However, if RDRF = ASCI Receive Data Register Ch. 0 (RDR0: 08H) Bit 7 6 5 4 3 2 1 0 Bit/Field ASCI Receive Channel 0 R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable ASCI Receive Data Register Ch. 1 (RDR1: 09H) Bit 7 6 5 4 3 2 1 0 Bit/Field ASCI Receive Channel 1 R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable

0, data can be written into the ASCII Receive Data Register, and the data can be read. ASCI Status Register 0, 1 (STAT0, 1) Each channel status register allows interrogation of ASCI communication, error and modem control signal status, and enabling or disabling of ASCI interrupts. ASCI Status Register 0 (STAT0: 04H) Bit 7 6 5 4 3 2 1 0 Bit/Field RDRF OVRN PE FE RIE DCD0 TDRE TIE R/W R R R R R/W R R R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 RDRF R Receive Data Register Full — RDRF is set to 1 when an

incoming data byte is loaded into RDR. If a framing or parity error occurs, RDRF remains set and the receive data (which generated the error) is still loaded into RDR. RDRF is cleared to 0 by reading RDR, when the DCD0 input is High, in IOSTOP mode, and during RESET.

6 OVRN R Overrun Error — OVRN is set to 1 when RDR is full

and RSR becomes full. OVRN is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET.

5 PE R Parity Error — PE is set to 1 when a parity error is

detected on an incoming data byte and ASCI parity detection is enabled (the MOD1 bit of CNTLA is set to 1). PE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET.

4 FE R Framing Error — If a receive data byte frame is

delimited by an invalid stop bit (that is, 0, should be 1), FE is set to 1. FE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET.

3 RIE R/W Receive Interrupt Enable — RIE must be set to 1 to

enable ASCI receive interrupt requests. When RIE is 1, if any of the flags RDRF, OVRN, PE, or FE become set to 1, an interrupt request is generated. For channel 0, an interrupt is also generated by the transition of the external DCD0 input from Low to High.

2 DCD0 R Data Carrier Detect — Channel 0 has an external

DCD0 input pin. The DCD0 bit is set to 1 when the DCD0 input is HIGH. It is cleared to 0 on the first read of (STAT0, following the DCD0 input transition from HIGH to LOW and during RESET. When DCD0 is 1, receiver unit is reset and receiver operation is inhibited.

1 TDRE R Transmit Data Register Empty — TDRE = 1 indicates

that the TDR is empty and the next transmit data byte is written to TDR. After the byte is written to TDR, TDRE is cleared to 0 until the ASCI transfers the byte from TDR to the TSR and then TDRE is again set to 1. TDRE is set to 1 in IOSTOP mode and during RESET. When the external CTS input is High, TDRE is reset to 0. Bit Position Bit/Field R/W Value Description

0 TIE R/W Transmit Interrupt Enable — TIE must be set to 1 to

enable ASCI transmit interrupt requests. If TIE is 1, an interrupt is requested when TDRE is 1. TIE is cleared to 0 during RESET. Bit Position Bit/Field R/W Value Description

ASCI Control Register A0, 1 (CNTLA0, 1) Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Status Register 1 (STAT1: 05H) Bit 7 6 5 4 3 2 1 0 Bit/Field RDRF OVRN PE FE RIE CTS1E TDRE TIE R/W R R R R R/W R/W R R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description incoming data byte is loaded into RDR. Note that if a framing or parity error occurs, RDRF is still set and the receive data (which generated the error) is still loaded into RDR. RDRF is cleared to 0 by reading RDR, when the DCD0 input is High, in IOSTOP mode, and during RESET. and RSR becomes full. OVRN is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET. detected on an incoming data byte and ASCI parity detection is enabled (the MOD1 bit of CNTLA is set to 1). PE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET.

delimited by an invalid stop bit (that is, 0, should be 1), FE is set to 1. FE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET. enable ASCI receive interrupt requests. When RIE is 1, if any of the flags RDRF, OVRN, PE, or FE become set to 1, an interrupt request is generated. For channel 0, an interrupt is also generated by the transition of the external DCD0 input from Low to High.

2 CTS1E R/W Channel 1 CTS Enable — Channel 1 has an external

CTS1 input which is multiplexed with the receive data pin (RXS) for the CSI/O (Clocked Serial I/O Port). Setting CTS1E to 1 selects the CTS1 function and clearing CTS1E to 0 selects the RXS function. that the TDR is empty and the next transmit data byte is written to TDR. After the byte is written to TDR, TDRE is cleared to 0 until the ASCI transfers the byte from TDR to the TSR and then TDRE is again set to 1. TDRE is set to 1 in IOSTOP mode and during RESET. When the external CTS input is High, TDRE is reset to 0. enable ASCI transmit interrupt requests. If TIE is 1, an interrupt is requested when TDRE is 1. TIE is cleared to 0 during RESET. Bit Position Bit/Field R/W Value Description

ASCI Control Register A0, 1 (CNTLA0, 1) Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Control Register A 0 (CNTLA0: 00H) Bit 7 6 5 4 3 2 1 0 Bit/Field MPE RE TE RTS0 MPBR/ EFR MOD2 MOD1 MOD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 X 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 MPE R/W Multi-Processor Mode Enable — The ASCI has a

multiprocessor communication mode which utilizes an extra data bit for selective communication when a number of processors share a common serial bus. Multiprocessor data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE has no effect. If multiprocessor mode is selected, MPE enables or disables the wakeup feature as follows. If MPE is set to 1, only received bytes in which the MPB (multiprocessor bit) is 1 can affect the RDRF and error flags. Effectively, other bytes (with MPB is 0) are ignored by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the RDRF and error flags.

6 RE R/W Receiver Enable — When RE is set to 1, the ASCI

receiver is enabled. When RE is reset to 0, the receiver is disabled and any receive operation in progress is interrupted. However, the RDRF and error flags are not reset and the previous contents of RDRF and error flags are held. RE is cleared to 0 in IOSTOP mode, and during RESET.

5 TE R/W Transmitter Enable — When TE is set to 1, the ASCI

transmitter is enabled. When TE is reset to 0, the transmitter is disabled and any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode, and during RESET.

4 RTS0

R/W Request to Send Channel 0 — When RTS0 is reset to 0, the RTS0 output pin goes Low. When RTS0 is set to 1, the RTS0 output immediately goes High.

3 MPBR/

R/W Multiprocessor Bit Receive/Error Flag Reset — When multiprocessor mode is enabled (MP in CNTLB is 1), MPBR, when read, contains the value of the MPB bit for the last receive operation. When written to 0, the EFR function is selected to reset all error flags (OVRN, FE and PE) to 0. MPBR/EFR is undefined during RESET. Bit Position Bit/Field R/W Value Description

2– 0 MOD2– 0 R/W ASCI Data Format Mode 2, 1, 0 — These bits program the ASCI data format as follows. MOD2 0: 7 bit data 1: 8 bit data MOD1 0: No parity 1: Parity enabled MOD0 0: 1 stop bit 1: 2 stop bits The data formats available based on all combinations of MOD2, MOD1 and MOD0 are described in Table17. Bit Position Bit/Field R/W Value Description

ASCI Control Register A 1 (CNTLA1: 01H) Bit 7 6 5 4 3 2 1 0 Bit/Field MPE RE TE CKA1D MPBR/ EFR MOD2 MOD1 MOD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 X 0 0 0 R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description multiprocessor communication mode which utilizes an extra data bit for selective communication when a number of processors share a common serial bus. Multiprocessor data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE has no effect. If multiprocessor mode is selected, MPE enables or disables the wakeup feature as follows. If MPE is set to 1, only received bytes in which the MPB (multiprocessor bit) is 1 can affect the RDRF and error flags. Effectively, other bytes (with MPB = 0) are ignored by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the RDRF and error flags. receiver is enabled. When RE is reset to 0, the receiver is disabled and any receive operation in progress is interrupted. However, the RDRF and error flags are not reset and the previous contents of RDRF and error flags are held. RE is cleared to 0 in IOSTOP mode, and during RESET.

transmitter is enabled. When TE is reset to 0, the transmitter is disabled and any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode, and during RESET.

4 CKA1D R/W CKA1 Clock Disable — When CKA1D is set to 1, the

function. When CKA1 D is 0, the pin is used as CKA1, an external data dock input/output for channel 1 R/W Multiprocessor Bit Receive/Error Flag Reset — When multiprocessor mode is enabled (MP in CNTLB is 1), MPBR, when read, contains the value of the MPB bit for the last receive operation. When written to 0, the EFR function is selected to reset all error flags (OVRN, FE and PE) to 0. MPBR/EFR is undefined during RESET. Bit Position Bit/Field R/W Value Description

2– 0 MOD2– 0 R/W ASCI Data Format Mode 2, 1, 0 — These bits program the ASCI data format as follows. MOD2 0: 7 bit data 1: 8 bit data MOD1 0: No parity 1: Parity enabled MOD0 0: 1 stop bit 1: 2 stop bits The data formats available based on all combinations of MOD2, MOD1 and MOD0 are described in Table17. Bit Position Bit/Field R/W Value Description

parity and baud rate selection. Table 17. Data Formats

ASCI Control Register B 0 (CNTLB0: 02H) ASCI Control Register B 1 (CNTLB1: 03H) Bit 7 6 5 4 3 2 1 0 Bit/Field MPBT MP CTS/PS PE0 DR SS2 SS1 SS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset X 0 0 0 0 1 1 1 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 MPBT R/W Multiprocessor Bit Transmit — When multiprocessor

communication format is selected (MP bit is 1), MPBT is used to specify the MPB data bit for transmission. If MPBT is 1, then MPB = 1 is transmitted. If MPBT is 0, then MPBT = 0 is transmitted. MPBT state is undefined during and after RESET.

6 MP R/W Multiprocessor Mode — When MP is set to 1, the data

format is configured for multiprocessor mode based on the MOD2 (number of data bits) and MOD0 (number of stop bits) bits in CNTLA. The format is as follows. Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits Multiprocessor (MP = 1) format has no provision for parity. If MP is 0, the data format is based on MOD0 MOD1, MOD2, and may include parity. The MP bit is cleared to 0 during RESET.

The external ASCI channel 0 data clock pins are multiplexed with DMA control lines (CKA0/ DREQ and CKA1/ TEND0). During RESET, these

5 CTS/PS R/W Clear to Send/Prescale — When read, CTS/PS reflects

the state of the external CTS input. If the CTS input pin is High, CTS/PS is read as 1. When the CTS input pin is High, the TDRE bit is inhibited (that is, held at 0). For channel 1, the CTS1 input is multiplexed with RXS pin (Clocked Serial Receive Data). Thus, CTS/PS is only valid when read if the channel 1 CTS1E bit is 1 and the CST1 input pin function is selected. The read data of CTS /PS is not affected by RESET. When written, CT /PS specifies the baud rate generator prescale factor. If CTS/PS is set to 1, the system clock is prescaled by 30 while if CTS/PS is cleared to 0, the system clock is prescaled by 10.CTS/PS is cleared to 0 during RESET. 4 PEO R/W Parity Even Odd — PE0 selects even or odd parity. PE0 does not affect the enabling/disabling of parity (MOD1 bit of CNTLA). If PE0 is cleared to 0, even parity is selected. If PE0 is set to 1, odd parity is selected.PE0 is cleared to 0 during RESET.

3 DR R/W Divide Ratio — DR specifies the divider used to obtain

baud rate from the data sampling clock If DR is reset to 0, divide by 16 is used, while if DR is set to 1, divide by 64 is used. DR is cleared to 0 during RESET. 2– 0 SS2– 0 R/W Source/Speed Select — Specifies the data clock source (internal or external) and baud rate prescale factor. SS2, SS1, and SS0 are all set to 1 during RESET. Table18 describes the divide ratio corresponding to SS2, SS1 and SS0 Bit Position Bit/Field R/W Value Description

regardless of SS2, SS1, SS0 programming. parity and baud rate selection. Table 18. Divide Ratio

ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class Processors Only) Bit 7 6 5 4 3 2 1 0 Bit/Field RDRF Int Inhibit DCD0 Disable CTS0 Disable X1 Bit Clk ASCI0 BRG0 Mode Break Feature Enable Break Detect (RO) Send Break R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

7 RDRF

RDRF Interrupt Inhibit Off

6 DCD0

5 CTS0

4 X1 Bit

3 BRG0

2 Break

1 Break

(RO) R/W 0 Break Detect On Break Detect Off

Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection.

0 Send

ASCI1 Extension Control Register (I/O Address: 13H) (Z8S180/L180-Class Processors Only) Bit 7 6 5 4 3 2 1 0 Bit/Field RDRF Int Inhibit Reserved X1 Bit Clk ASCI1 BRG1 Mode Break Feature Enable Break Detect (RO) Send Break R/W R/W ? R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description RDRF Interrupt Inhibit Off 6–5 Reserved ? 0 Reserved. Must be 0

3 BRG1

Position Bit/Field R/W Value Description

Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection. (RO) R/W 0 Break Detect On Break Detect Off ASCI0 Time Constant Low Register (I/O Address: 1AH) (Z8S180/L180-Class Processors Only) Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable ASCI0 Time Constant High Register (I/O Address: 1BH) (Z8S180/L180-Class Processors Only) Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description

ASCI channel 0 has CTS0, DCD0 and RTS0 external modem control signals. ASCI channel 1 has a CTS1 modem control signal which is multiplexed with Clocked Serial Receive Data (RXS). CTS0: Clear to Send 0 (Input) The CTS0 input allows external control (start/stop) of ASCI channel 0 transmit operations. When CTS0 is High, the channel 0 TDRE bit is held at 0 whether or not the TDR0 (Transmit Data Register) is full or empty. When CTS0 is Low, TDRE reflects the state of TDR0. The actual transmit operation is not disabled by CT High, only TDRE is inhibited: DCD0: Data Carrier Detect 0 (Input) The DCD0 input allows external control (start/stop) of ASCI channel 0 receive operations. When DCD0 is High, the channel 0 RDRF bit is held at 0 whether or not the RDR0, (Receive Data Register) is full or empty. ASCI1 Time Constant Low Register (I/O Address: 1CH) (Z8S180/L180-Class Processors Only) Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable ASCI1 Time Constant High Register (I/O Address: 1DH) (Z8S180/L180-Class Processors Only) Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable

other ASCI registers or flags. Modem control signal timing is depicted in Figure 53 and Figure 54. Figure 53. DCD0 Timing Diagram

DMAC be correctly configured to use the ASCI flags as DMA request signals. defined in the individual register descriptions. the sampling rate ( ÷16/÷64) as depicted in Figure 56. Figure 56. ASCI Clock

Table 19. ASCI Baud Rate Selection

The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes. Table 19. ASCI Baud Rate Selection (Continued)

allows a common baud rate of up to 512 Kbps to be selected. The BRG can also be disabled in favor of an external clock on the CKA pin. The Receiver and Transmitter subsequently divide the output of the BRG (or the signal from the CKA pin) by 1, 16, or 64, under the control of the DR bit in the CNTLB register, and the X1 bit in the ASCI Extension Control REgister. To compute baud rate, use the following formulas: Where: BRG mode is bit 3 of the ASEXT register PS is bit 5 of the CNTLB register TC is the 16-bit value in the ASCI Time Constant register If ss2.1.0 = 111, baud rate - fCKA/Clock mode else if BRG mode baud rate = fPHI/(2*(TC+2)*Clock mode) else baud rate -fPHI/((10 + 20*PS) * 2^ss*Clock mode) The TC value for a given baud rate is: TC = (fPHI/*2*baud rate*Clock mode)) -2 Clock mode depends on bit 4 in ASEXT and bit 3 in CNTLB, as described in Table20. Table 20.Clock Mode Bit Values X1 DR Clock Mode Reserved, do not use

The ASCIs require a 50% duty cycle when CKA is used as an input. Register to the RX FIFO. The FIFO provides a margin against overruns. Table 21. 2^ss Values

causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0, DCD) continue to request RX interrupt if the RIE bit is 1. The Rx DMA request is inhibited if PE or FE or OVRN is set, so that software can detect where an error occurred. When the RIE bit is 0, as it is after a Reset, RDRF causes an ASCI interrupt if RIE is 1. Clocked Serial I/O Port (CSI/O) The Z8X180 includes a simple, high-speed clock, synchronous serial I/O port. The CSI/O includes transmit/receive (half-duplex), fixed 8-bit data, and internal or external data clock selection. High-speed operation (baud rate 200Kbps at fC = 4 MHz) is provided. The CSI/O is ideal for implementing a multiprocessor communication link between multiple Z8X180s. These secondary devices may typically perform a portion of the system I/O processing, (that is, keyboard scan/decode, LDC interface, for instance). CSI/O Block Diagram The CSI/O block diagram is illustrated in Figure 57. The CSI/O consists of two registers–the Transmit/Receive Data Register (TRDR) and Control Register (CNTR).

Figure 57. CSI/O Block Diagram

Position Bit/Field R/W Value Description

7 EF R End Flag — EF is set to 1 by the CSI/O to indicate

completion of an 8-bit data transmit or receive operation. If EIE (End Interrupt Enable) bit = 1 when EF is set to 1, a CPU interrupt request is generated. Program access of TRDR only occurs if EF is 1. The CSI/O clears EF to 0 when TRDR is read or written. EF is cleared to 0 during RESET and IOSTOP mode.

6 EIE R/W End Interrupt Enable — EIE is set to 1 to enable EF = 1

to generate a CPU interrupt request. The interrupt request is inhibited if EIE is reset to 0. EIE is cleared to 0 during RESET.

5 RE R/W Receive Enable — A CSI/O receive operation is started

by setting RE to 1. When RE is set to 1, the data clock is enabled. In internal clock mode, the data clock is output from the CKS pin. In external dock mode, the dock is input on the CKS pin. In either case, data is shifted in on the RXS pin in synchronization with the (internal or external) data clock. After receiving 8 bits of data, the CSI/O automatically clears RE to 0, EF is set to 1, and an interrupt (if enabled by EIE = 1) is generated. RE and TE are never both set to 1 at the same time. RE is cleared to 0 during RESET and ISTOP mode. RXS is multiplexed with CTS1 modem control input of ASCI channel 1. In order to enable the RXS function, the CTS1E bit in CNTA1 must be reset to 0.

CSI/O Transmit/Receive Data Register (TRDR: I/O Address = 0BH). TRDR is used for both CSI/O transmission and reception. Thus, the system design must insure that the constraints of half-duplex operation are met (Transmit and receive operation cannot occur simultaneously). For example, if a CSI/O transmission is attempted while the CSI/O is receiving data, the CSI/O does not work. TRDR is not buffered. Attempting to perform a CSI/O transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, thereby corrupting the transmit operation in progress. Similarly, reading TRDR during a transmit or receive must be avoided.

4 TE R/W Transmit Enable — A CSI/O transmit operation is

started by setting TE to 1. When TE is set to 1, the data clock is enabled. When in internal clock mode, the data clock is output from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either case, data is shifted out on the TXS pin synchronous with the (internal or external) data clock. After transmitting 8 bits of data, the CSI/O automatically clears TE to 0, EF is set to 1, and an interrupt (if enabled by EIE = 1) is generated. TE and RE are never both set to 1 at the same time. TE is cleared to 0 during RESET and IOSTOP mode. 2– 0 SS2– 0 R/W Speed Select — Selects the CSI/O transmit/receive clock source and speed. SS2, SS I and SS0 are all set to 1 during RESET. Table22 shows CSI/O Baud Rate Selection. Bit Position Bit/Field R/W Value Description

The CSI/O interrupt request circuit is shown in Figure 58. Table 22. CSI/O Baud Rate Selection Note: () indicates the baud rate (BPS) at Phi = 4 MHz.

Figure 58. CSI/O Interrupt Request Generation The CSI/O is operated using status polling or interrupt driven algorithms.

• Transmit–Polling a. Poll the TE bit in CNTR until TE = 0. b. Write the transmit data into TRDR. c. Set the TE bit in CNTR to 1. d. Repeat steps 1 to 3 for each transmit data byte.
• Transmit–Interrupts a. Poll the TE bit in CNTR until TE = 0. b. Write the first transmit data byte into TRDR. c. Set the TE and EIE bits in CNTR to 1. d. When the transmit interrupt occurs, write the next transmit data byte into TRDR. e. Set the TE bit in CNTR to 1. f. Repeat steps 4 and 5 for each transmit data byte.
• Receive –Polling a. Poll the RE bit in CNTR until RE = 0. b. Set the RE bit in CNTR to 1. EF EIE IEF1 CSI/O Interrupt Request

c. Poll the RE bit in CNTR until RE = 0. d. Read the receive data from TRDR. e. Repeat steps 2 to 4 for each receive data byte.

• Receive–Interrupts a. Poll the RE bit in CNTR until RE is 0. b. Set the RE and EIE bits in CNTR to 1. c. When the receive interrupt occurs read the receive data from TRDR. d. Set the RE bit in CNTR to 1. e. Repeat steps 3 and 4 for each receive data byte. CSI/O Operation Timing Notes
• Transmitter clocking and receiver sampling timings are different from internal and external clocking modes. Figure 59 to Figure 62 illustrate CSI/O Transmit/Receive Timing.
• The transmitter and receiver is disabled TE and RE = 0) when initializing or changing the baud rate. CSI/O Operation Notes
• Disable the transmitter and receiver (TE and RE = 0) before initializing or changing the baud rate. When changing the baud rate after completion of transmission or reception, a delay of at least one bit time is required before baud rate modification.
• When RE or TE is cleared to 0 by software, a corresponding receive or transmit operation is immediately terminated. Normally, TE or RE is only cleared to 0 when EF is 1.
• Simultaneous transmission and reception is not possible. Thus, TE and RE are not both 1 at the same time.

Figure 59. Transmit Timing Diagram –Internal Clock

Figure 60. Transmit Timing–External Clock

Figure 61. CSI/O Receive Timing–Internal Clock

Figure 62. CSI/O Receive Timing–External Clock The Z8X180 contains a two channel 16-bit Programmable Reload Timer.

Figure 63. PRT Block Diagram 14H). PRT0 and PRT1 each contain 16-bit timer Data Registers (TMDR). TMDR0 and TMDR1 are set to FFFFH. TMDR is read and written by software using the following procedures.

return accurate data without requiring the timer to be stopped. The write procedure requires the PRT to be stopped. For reading (without stopping the timer), TMDR is read in the order of lower byte - higher byte (TMDRnL, TMDRnH). The lower byte read (TMDRnL) stores the higher byte value in an internal register. The following higher byte read (TMDRnH) accesses this internal register. This procedure insures timer data validity by eliminating the problem of potential 16-bit timer updating between each 8-bit read. Specifically, reading TMDR in higher byte–lower byte order may result in invalid data. Note the implications of TMDR higher byte internal storage for applications which may read only the lower and/or higher bytes. In normal operation all TMDR read routines must access both the lower and higher bytes, in that order. For writing, the TMDR down counting must be inhibited using the TDE (Timer Down Count Enable) bits in the TCR (Timer Control Register). Then, any or both higher and lower bytes of TMDR can be freely written (and read) in any order. CSI/O Transmit/Receive Data Register (TRDR: I/O Address = 0BH). TRDR is used for both CSI/O transmission and reception. Thus, the system design must insure that the constraints of half-duplex operation are met (Transmit and receive operation cannot occur simultaneously). For example, if a CSI/O transmission is attempted while the CSI/O is receiving data, the CSI/O does not work. TRDR is not buffered. Attempting to perform a CSI/O transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, thereby corrupting the transmit operation in progress. Similarly, reading TRDR during a transmit or receive must be avoided.

Timer Reload Register (RLDR: I/O Address = CH0: 0EH, 0FH, CHI, 16H, 17H) PRT0 and PRT1 each contain 16-bit Timer Reload Registers (RLDR). RLDR0 and RLDR1 are each accessed as low and high byte registers (RLDR0H, RLDR0L and RLDR1H, RLDR1L). During RESET, RLDR0 and RLDR1 are set to FFFFH When the TMDR counts down to 0, it is automatically reloaded with the contents of RLDR. Timer Data Register 0L (TMDR0L: 0CH) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Data Register 0H (TMDR0H: 0DH) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable

Timer Reload Register Channel 0L (RLDR0L: 0EH) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Reload Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Reload Register Channel 0H (RLDR0L: 0FH) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Reload Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Data Register 1L (TMDR1L: 14H) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Data Register 1H (TMDR1H: 15H) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable

Timer Control Register (TCR) TCR monitors both channels (PRT0, PRT1) TMDR status. It also controls enabling and disabling of down counting and interrupts along with controlling output pin A18/TOUT for PRT1. Timer Reload Register Channel 1L (RLDR1L: 16H) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Reload Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Reload Register Channel 1H (RLDR1H: 17H) Bit 7 6 5 4 3 2 1 0 Bit/Field Timer Reload Data R/W R/W Reset 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable Timer Control Register (TCR: 10H) Bit 7 6 5 4 3 2 1 0 Bit/Field TIF1 TIF0 TIE1 TIE0 TOC1 TOC0 TDE1 TDE0 R/W R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read W = Write X = Indeterminate ? = Not Applicable

Position Bit/Field R/W Value Description 7– 6 TIF1– 0 R TIF1: Timer Interrupt Flag — When TMDR1 decrements to 0, TIF1 is set to 1. This generates an interrupt request if enabled by TIE1 = 1. TIF1 is reset to 0 when TCR is read and the higher or lower byte of TMDR1 is read. During RESET, TIF1 is cleared to 0. When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and the higher or lower byte of TMDR0 is read. During RESET, TIF0 is cleared to 0. 5– 4 TIE1– 0 R/W Timer Interrupt Enable — When TIE1 is set to 1, TIF1 = 1 generates a CPU interrupt request. When TIE1 is reset to 0, the interrupt request is inhibited. During RESET, TIE1 is cleared to 0. When TIE0 is set to 1, TIF0 = 1 generates a CPU interrupt request. When TIE0 is reset to 0, the interrupt request is inhibited. During RESET, TIE0 is cleared to 0. 3– 2 TOC1– 0 R/W Timer Output Control — TOC1, and TOC0 control the output of PRT1 using the multiplexed A18/TOUT pin as shown in Table23. During RESET, TOC1 and TOC0 are cleared to 0. This selects the address function for A18/ TOUT. By programming TOC1 and TOC0 the A18/ TOUT pin can be forced HIGH, LOW, or toggled when TMDR1 decrements to 0. Reference Table23. 1– 0 TDE1– 0 R/W Timer Down Count Enable — TDE1 and TDE0 enable and disable down counting for TMDR1 and TMDR0 respectively. When TDEn (n = 0, 1) is set to 1, down counting is executed for TMDRn. When TDEn is reset to 0, down counting is stopped and TMDRn is freely read or written. TDE1 and TDE0 are cleared to 0 during RESET and TMDRn does not decrement until TDEn is set to 1.

• TMDR data is accurately read without stopping down counting by reading the lower (TMDRnL*) and higher (TMDRnH*) bytes in that order. Also, TMDR is read or written by stopping the down counting. 1 Take care to ensure that a timer reload does not occur during or between lower (RLDRnL*) and higher (RLDRnH*) byte writes. This may be guaranteed by system design/timing or by stopping down counting (with TMDR containing a non-zero value) during the RLDR updating. Similarly, in applications where TMDR is written at each TMDR overflow, the system/software design must guarantee that RLDR can be updated before the next overflow occurs. Otherwise, time base inaccuracy occurs.
• During RESET, the multiplexed A18/TOUT pin reverts to the address output. By reprogramming the TOC1 and TOC0 bits, the timer output function for PRT channel 1 is selected. The following paragraph describes the initial state of the TOUT pin after TOC1 and TOC0 are programmed to select the PRT channel 1 timer output function. PRT (channel 1) has not counted down to 0. If the PRT has not counted down to 0 (timed out), the initial state of TOUT depends on the programmed value in TOC1 and TOC0. Secondary Bus Interface E clock Output Timing The Z8X180 also has a secondary bus interface that allows it to easily interface with other peripheral families. 1. *n = 0, 1

Figure 70 define E clock output timing. read/write cycles which extend the duration of E clock output High. chip I/O register accesses), E does not go High. Table 24. E Clock Timing in Each Condition

Figure 69. E Clock Timing in SLEEP Mode and SYSTEM STOP Mode corresponds with a system clock rate of 4 MHz.

the clock rate) must exhibit a 50% ± 10% duty cycle. Figure 70. External Clock Interface and 72 specify circuit board design rules. Table 25. Z8X180 Operating Frequencies

2 Open

Figure 73. Example of Board Design Circuit Board design should observe the following parameters.

• Locate the crystal and load capacitors as close to the IC as physically possible to reduce noise.
• Signal lines must not run parallel to the clock oscillator inputs. In particular, the clock input circuitry and the system clock output (pin 64) must be separated as much as possible.
• VCC power lines must be separated from the clock oscillator input circuitry.
• Resistivity between XTAL or EXTAL and the other pins must be greater than 10M ohms. Signal line layout must avoid areas marked with the shaded area of Figure 73. Signal line layout must avoid shaded areas 20 mm max 20 mm max Crystal CL CL 642 GND Z8X180 Phi Top View Note: Pin mumbers valid only for DIP configuration

Free Running Counter (I/O Address = 18H) If data is written into the free running counter, the interval of DRAM refresh cycle and baud rates for the ASCI and CSI/O are not guaranteed. In IOSTOP mode, the free running counter continues counting down. It is initialized to FFH during RESET. Free Running counter (FRC: 18H) Bit 7 6 5 4 3 2 1 0 Bit/Field Counting Data R/W R Reset ? Note: R = Read W = Write X = Indeterminate ? = Not Applicable

Programming Manual for further details. Table 26. Instruction Set Summary

The MLT performs unsigned multiplication on two 8-bit numbers yielding a 16-bit result. MLT may specify BC, DE, HL, or SP registers. The 8-bit operands are loaded into each half of the 16-bit register and the 16-bit result is returned in that register. OTIM, OTIMR, OTDM, OTDMR - Block I/O The contents of memory pointed to by HL is output to the I/O address in (C). The memory address (HL) and I/O address (C) are incremented in OTIM and OTIMR and decremented in OTDM and OTDMR, respectively. The B register is decremented. The OTIMR and OTDMR variants repeat the above sequence until register B is decremented to 0. Since the I/O address (C) is automatically incremented or decremented, these instructions are useful for block I/O (such as Z80180 on-chip I/O) initialization. When I/O is accessed, 00H is output in high-order bits of address automatically. TSTIO m - Test I/O Port The contents of the I/O port addressed by C are ANDed with immediately specified 8-bit data and the status flags are updated. The I/O port contents are not written (non-destructive AND). When I/O is accessed, 00H is output in higher bits of address automatically. TST g - Test Register Perform an AND instruction on the contents of the specified register with the accumulator (A) and the status flags are updated. The accumulator and specified register are not changed (non-destructive AND). TST m - Test Immediate Perform an AND instruction on the contents of the immediately specified 8-bit data with the accumulator (A) and the status flags are updated. The accumulator is not changed (non-destructive AND).

TST (HL) - Test Memory The contents of memory pointed to by HL are ANDed with the accumulator (A) and the status flags are updated. The memory contents and accumulator are not changed (non-destructive AND). INO g, (m) - Input, Immediate I/O address The contents of immediately specified 8-bit I/O address are input into the specified register. When I/O is accessed, 00H is output in high-order bits of the address automatically. OUTO (m), g - Output, Immediate I/O address The contents of the specified register are output to the immediately specified 8-bit I/O address. When I/O is accessed, 00H is output in high- order bits of the address automatically. CPU REGISTERS The Z80180 CPU registers consist of Register Set GR, Register Set GR' and Special Registers. The Register Set GR consists of 8-bit Accumulator (A), 8-bit Flag Register (F), and three General Purpose Registers (BC, DE, and HL) which may be treated as 16-bit registers (BC, DE, and HL) or as individual 8-bit registers (B, C, D, E, H, and L) depending on the instruction to be executed. The Register Set GR' is alternate register set of Register Set GR and also contains Accumulator (A'), Flag Register (F') and three General Purpose Registers (BC', DE', and HL'). While the alternate Register Set GR' contents are not directly accessible, the contents can be programmably exchanged at high speed with those of Register Set GR. The Special Registers consist of 8-bit Interrupt Vector Register (I), 8-bit R Counter (R), two 16-bit Index Registers (IX and IY), 16-bit Stack Pointer (SP), and 16-bit Program Counter (PC)

Figure74 depicts CPU register configurations. Figure 74. CPU Register Configurations logical, and I/O instructions.

Flag Registers (F, F') The flag registers store status bits (described in the next section) resulting from executed instructions. General Purpose Registers (BC, BC', DE, DE', HL, HL') The General Purpose Registers are used for both address and data operation. Depending on the instruction, each half (8 bits) of these registers (B, C, D, E, H, and I) may also be used. Interrupt Vector Register (I) For interrupts that require a vector table address to be calculated ( INT0 Mode 2, INT1, INT2, and internal interrupts), the Interrupt Vector Register (I) provides the most significant byte of the vector table address. I is cleared to 00H during reset. R Counter (R) The least significant seven bits of the R counter (R) count the number of instructions executed by the Z80180. R increments for each CPU Op Code fetch cycle (each M 1 cycle). R is cleared to 00H during reset. Index Registers (IX, and IY) The Index Registers are used for both address and data operations. For addressing, the contents of a displacement specified in the instruction are added to or subtracted from the Index Register to determine an effective operand address.

Stack Pointer (SP) The Stack Pointer (SP) contains the memory address based LIFO stack. SP is cleared to 0000H during reset. Program Counter (PC) The Program Counter (PC) contains the address of the instruction to be executed and is automatically updated after each instruction fetch. PC is cleared to 0000H during reset. Flag Register (F) The Flag Register stores the logical state reflecting the results of instruction execution. The contents of the Flag Register are used to control program flow and instruction operation. Flag Register Bit 7 6 5 4 3 2 1 0 Bit/Field S Z Not Used H Not Used P/V N C R/W R/W R/W ? R/W ? R/W R/W R/W Reset 0 0 ? 0 ? 0 0 0 R = Read W = Write X = Indeterminate ? = Not Applicable Bit Position Bit/Field R/W Value Description 7 S R/W 0 Sign. S stores the state of the most significant bit (bit 7) of the result. This is useful for operations with signed numbers in which values with bit 7 = 1 are interpreted as negative.

6 Z R/W 0 Zero. Z is set to 1 when instruction execution produces 0 result. Otherwise, Z is reset to 0. 5 Not Used ? ? Not used 4 H R/W 0 Half Carry. H is used by the DAA (Decimal Adjust Accumulator) instruction to reflect borrow or carry from the least significant 4 bits and thereby adjust the results of BCD addition and subtraction. 3 Not Used ? ? Not used. 2 P/V R/W 0 P/V: Parity/Overflow . P/V serves a dual purpose. For logical operations P/V is set to 1 if the number of 1 bit in the result is even and P/V is reset to 0 if the number of 1 in the result is odd. For two complement arithmetic, P/V is set to 1 if the operation produces a result which is outside the allowable range (+ 127 to -128 for 8-bit operations, + 32767 to - 32768 for 16-bit operations). 1 N R/W 0 Negative. N is set to 1 if the last arithmetic instruction was a subtract operation (SUB, DEC, CP, etc.) and N is reset to 0 if the last arithmetic instruction was an addition operation (ADD, INC, etc.). 0 C R/W 0 Carry. C is set to 1 when a carry (addition) or borrow (subtraction) from the most significant bit of the result occurs. C is also affected by Accumulator logic operations such as shifts and rotates. Bit Position Bit/Field R/W Value Description

The Z80180 instruction set includes eight addressing modes.

• Implied Register
• Register Direct
• Register Indirect
• Indexed
• Extended
• Immediate
• Relative
• IO Implied Register (IMP) Certain Op Codes automatically imply register usage, such as the arithmetic operations that inherently reference the Accumulator, Index Registers, Stack Pointer, and General Purpose Registers. Register Direct (REG) Many Op Codes contain bit fields specifying registers used for operation. The exact bit field definitions vary depending on instruction depicted in Figure75.

IO (I/O) IO addressing mode is used only by I/O instructions. This mode specifies I/O address ( IORQ is 0) and outputs them as follows. 1. An operand is output to A0 – A7. The contents of accumulator is output to A8 – A15. 2. The contents of Register B is output to A0 – A7. The contents of Register C is output to A8 – A15. 3. An operand is output to A0 – A7. 00H is output to A8 – A15 (useful for internal I/O register access) 4. The contents of Register C is output to A0– A7. 00H is output to A8– A15 (useful for internal I/O register access).

absolute maximum rating for these products. Permanent IC damage may occur if maximum ratings are exceeded. these conditions are exceeded, it could affect reliability of IC. Table 27. Absolute Maximum Rating

Table 28. Z80180 DC Characteristics

VCC = 5V ± 10%, VSS = OV, Ta = 0° to +70°C, unless otherwise noted. Table 29. Z8S180 DC Characteristics Table 28. Z80180 DC Characteristics (Continued)

Table 29. Z8S180 DC Characteristics (Continued)

Table 30. Z8L180 DC Characteristics

Table 30. Z8L180 DC Characteristics (Continued)

2.7 3.0 3.3 VDD (Volts) ICC Active (mA.) Typical ICCA at 4 MHz Z8L180 2 3 4 VDD (Volts) ICC Active (mA.) Typical ICCA at 20 MHz Z8S180

absolute maximum rating for these products. Table 31. Z8S180 AC Characteristic s VDD = 5V ±10% or VDD = 3.3V

Table 31. Z8S180 AC Characteristic s (Continued) V DD = 5V ±10% or

51 PWEH E Pulse Width (High) 25 — 20 — ns

52 PWEL E Pulse Width (Low) 50 — 40 — ns

Figure 81. AC Timing Diagram 1

Figure 82. AC Timing Diagram 2

Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle, I/O Write Cycle)

Figure 84. DMA Control Signals *TDRQS and TDRQH are specified for the rising edge of the clock followed by T3. **TDRQS and TDRQH are specified for the rising edge of the clock.

Figure 89. SLP Execution Cycle Timing Diagram

referenced to the 10% and 90% points). to the Literature List for additional documentation. Figure 93. Test Setup

This section explains the symbols in the instruction set. describes the correspondence between symbols and registers. 8-bit of the 16-bit register respectively. b specifies a bit to be manipulated in the bit manipulation instruction. Table33 indicates the correspondence between b and bits. Table 32. Register Values

000 B 00 BC 00 BC 00 BC 00 BC

001 C 01 DE 01 DE 01 DE 01 DE

010 D 10 HL 10 IX 10 IY 10 HL

011 E 11 SP 11 SP 11 SP 11 AF

describes the correspondence between f and conditions. Table 33. Bit Values Table 34. Instruction Values

000 NZ Nonzero

001 Z Zero

010 NC Non Carry

011 C Carry

100 PO Parity Odd

101 PE Parity Even

110 P Sign Plus

111 M Sign Minus

between v and restart addresses. The symbols listed in Table36 indicate the flag conditions. Table 35. Address Values Table 36. Flag Conditions

• Not Affected ­ Affected x Undefined S Set to 1 R Reset to 0 P Parity V Overflow

Table37 lists the operations mnemonics. Table 37. Operations Mnemonics

• AND operation + OR operation ⊕ EXCLUSIVE OR operation ** Added new instructions to Z80

Table 38. Arithmetic and Logical Instructions (8-bit)

Table 38. Arithmetic and Logical Instructions (8-bit) (Continued)

01 WWI

Table 39. Rotate and Shift Instructions

Table 39. Rotate and Shift Instructions (Continued)

Table 40. Arithmetic Instructions (16-bit)

Table 41. 8-Bit Load

(1) In the case of R1 and Z Mask, interrupts are not sampled at the end of LD A, I or LD A,R. Table 42. 16-Bit Load Table 41. 8-Bit Load (Continued)

Table 42. 16-Bit Load (Continued)

Table 43. Block Transfer

10100001 BCR-1→BCR

• • R R R • 10 111 000 12(BCR = 0) Repeat Q until BCR = 0 (2) LDI 11 101 101 S/D 2 12 (HL)M→DE)R • • R ­ R • 10 100 000 BCR-1→BCR DER + 1→DER HLR + 1→HLR LDIR 11 101 101 S/D 2 14(BCR≠0) (HL)M→(DE)M Q BC R-1→BCR DER + 1→DER HLR + 1→HLR
• • R R R • 10 110 000 12(BCR = 0) Repeat Q until BCR = 0 P/V = 1:BC R-1 ≠ 0 (3)Z = 1:Ar = (HL) M Z = 0 :Ar ≠ (HL)M

Table 43. Block Transfer (Continued)

Table 44. Stock and Exchange

Table 44. Stock and Exchange (Continued)

Table 45. Program Control Instructions

01001101 ZZ(z) (SP + 1)M→PCHr

Table 45. Program Control Instructions (Continued)

Table 46. I/O Instructions

Table 46. I/O Instructions (Continued)

Table 47. Special Control Instructions 7) Interrupts are not sampled at the end of DI or EI.

** : Added new instructions to Z80 MNEMONICS Bytes Machine Cycles States ADC A,m 2 2 6 ADC A,g 1 2 4 ADC A, (HL) 1 2 6 ADC A, (IX+d) 3 6 14 ADC A, (IY+d) 3 6 14 ADD A,m 2 2 6 ADD A,g 1 2 4 ADD A, (HL) 1 2 6 ADD A, (IX+d) 3 6 14 ADD A, (IY+d) 3 6 14 ADC HL,ww 2 6 10 ADD HL,ww 1 5 7 ADD IX,xx 2 6 10 ADD IY,yy 2 6 10 AND m 2 2 6 AND g 1 2 4 AND (HL) 1 2 6 AND (IX+d) 3 6 14 AND (IY+d) 3 6 14 BIT b, HU 2 3 9 BIT b, (IX+d) 4 5 15 BIT b, (IY+d) 4 5 15 BIT b,g 2 2 6 CALL f,mn 3 2 6 (If condition is false)

(If condition is true) CALL mn 3 6 16 CCF 1 1 3 CPD 2 6 12 CPDR 2 8 14 (If BC R ≠ 0 and Ar ≠ (HL)M 2 6 12 (If BC R = 0 or Ar = (HL) M CP (HL) 1 2 6 CPI 2 6 12 CPIR 2 8 14 (If BC R ≠ 0 and Ar ≠ (HL)M 2 6 12 (If BCR = 0 or Ar = (HL) M CP (IX+d) 3 6 14 CP (IY+d) 3 6 14 CPL 1 1 3 CP m 2 2 6 CP g 1 2 4 DAA 1 2 4 DEC (HL) 1 4 10 DEC IX 2 3 7 DEC IY 2 3 7 DEC (IX+d) 3 8 18 DEC (IY+d) 3 8 18 DEC g 1 2 4 DEC ww 1 2 4 DI 1 1 3 DJNZ j 2 5 9 (if Br ≠ 0) MNEMONICS Bytes Machine Cycles States

2 3 7 (if Br = 0) EI 1 1 3 EX AF,AF' 1 2 4 EX DE,HL 1 1 3 EX (SP),HL 1 6 16 EX (SP)I,IX 2 7 19 EX (SP),IY 2 7 19 EXX 1 1 3 HALT 1 1 3 IM 0 2 2 6 IM 1 2 2 6 IM 2 2 2 6 INC g 1 2 4 INC (HL) 1 4 10 INC (IX+d) 3 8 18 INC (IY+d) 3 8 18 INC ww 1 2 4 INC IX 2 3 7 INC IY 2 3 7 IN A,(m) 2 3 9 IN g,(C) 2 3 9 INI 2 4 12 INIR 2 6 14 (if Br ≠ 0) 2 4 12 (If Br = 0) IND 2 4 12 INDR 2 6 14 (If Br ≠ 0) INDR 2 4 12 (If Br = 0) IN0 g,(m)** 3 4 12 JP f,mn 3 2 6 (If f is false) MNEMONICS Bytes Machine Cycles States

(If f is true) JP (HL) 1 1 3 JP (IX) 2 2 6 JP (IY) 2 2 6 JP mn 3 3 9 JR j 2 4 8 JR C,j 2 2 6 (If condition is false) 2 4 8 (If condition is true) JR NC,j 2 2 6 (if condition is false) 2 4 8 (If condition is true) JR Z,j 2 2 6 (If condition is false) 2 4 8 If condition is true) JR NZ,j 2 2 6 (If condition is false) 2 4 8 (If condition is true) LD A, (BC) 1 2 6 LD A, (DE) 1 2 6 LD A,I 2 2 6 LD A, (mn) 3 4 12 LD A,R 2 2 6 LD (BC),A 1 3 7 LDD 2 4 12 MNEMONICS Bytes Machine Cycles States

LD (DE),A 1 3 7 LD ww,mn 3 3 9 LD ww,(mn) 4 6 18 LDDR 2 6 14 (If BC R ≠ 0) 2 4 12 (If BC R = 0 LD (HL),m 2 3 9 LD HL,(mn) 3 5 15 LD (HL),g 1 3 7 LDI 2 4 12 LDI,A 2 2 6 LDIR 2 6 14 (If BC R ≠ 0) 2 4 12 (If BC R = 0) LD IX,mn 4 4 12 LID IX,(mn) 4 6 18 LD (IX+d),m 4 5 15 LD (IX+ d),g 3 7 15 LD IY,mn 4 4 12 LD IY,(mn) 4 6 18 LD (IY+d),m 4 5 15 LD (IY+d),g 3 7 15 LD (mn),A 3 5 13 LD (mn),ww 4 7 19 LD (mn),HL 3 6 16 LD (mn),IX 4 7 19 LD (mn),IY 4 7 19 LD R,A 2 2 6 LD g,(HL) 1 2 6 LD g,(IX+d) 3 6 14 LD g,(IY+d) 3 6 14 LD g,m 2 2 6 MNEMONICS Bytes Machine Cycles States

LD g,g' 1 2 4 LD SP,HL 1 2 4 LD SP,IX 2 3 7 LD SP,IY 2 3 7 MLT ww" 2 13 17 NEG 2 2 6 NOP 1 1 3 OR (HL) 1 2 6 OR (IX+d) 3 6 14 OR (IY+d) 3 6 14 OR m 2 2 6 OR g 1 2 4 OTDM 2 6 14 OTDMR 2 8 16 (If Br ≠ 0) 2 6 14 (If Br = 0) OTDR 2 6 14 (If Br ≠ 0) 2 4 12 (If Br = 0 OTIM 2 6 14 OTIMR 2 8 16 (If Br ≠ 0) 2 6 14 (If Br = 0) OTIR 2 6 14 (If Br ≠ 0) 2 4 12 (If Br = 0) OUTD 2 4 12 OUTI 2 4 12 OUT (m),A 2 4 10 OUT (C),g 2 4 10 OUT0 (m),g ** 3 5 13 POP IX 2 4 12 POP IY 2 4 12 POP zz 1 3 9 MNEMONICS Bytes Machine Cycles States

RES b,(HL) 2 5 13 RES b,(IX+d) 4 7 19 RES b,(IY+d) 4 7 19 RES b,g 2 3 7 RET 1 3 9 RET f 1 3 5 (If condition is false) 1 4 10 (If condition is true) RETI 2 4 (R0, R1) 12 (R0, R1) 10 (Z) 22 (Z) RETN 2 4 12 RLA 1 1 3 RLCA 1 1 3 RLC (HL) 2 5 13 RLC (IX-1-dl 4 7 19 RLC (IY+d) 4 7 19 RLC g 2 3 7 RLD 2 8 16 RL (HL) 2 5 13 RL (IX+d) 4 7 19 RL (IY+d) 4 7 19 RL g 2 3 7 RRA 1 1 3 RRCA 1 1 3 RRC (HL) 2 5 13 RRC (IX+d) 4 7 19 MNEMONICS Bytes Machine Cycles States

RRC (IY+d) 4 7 19 RRC g 2 3 7 RRD 2 8 16 RR (HL) 2 5 13 RR (IX+d) 4 7 19 RR (IY+d) 4 7 19 RR g 2 3 7 RST v 1 5 11 SBC A,(HL) 1 2 6 SBC A, (IX+d) 3 6 14 SBC A,(IY+d) 3 6 14 SBC A,m 2 2 6 SBC A,g 1 2 4 SBC HL,ww 2 6 10 SCF 1 1 3 SET b,(HL) 2 5 13 SET b,(IX+d) 4 7 19 SET b,(IY+d) 4 7 19 SET b,g 2 3 7 SLA (HL) 2 5 13 SLA (IX+d) 4 7 19 SLA (IY+d) 4 7 19 SLA g 2 3 7 SLP** 2 2 8 SRA (HL) 2 5 13 SRA (IX+d) 4 7 19 SRA (IY+d) 4 7 19 SRA g 2 3 7 SRL (HL) 2 5 13 SRL (IX+d) 4 7 19 MNEMONICS Bytes Machine Cycles States

SRL (IY+d) 4 7 19 SRL g 2 3 7 SUB (HL) 1 2 6 SUB (IX+d) 3 6 14 SUB (IY+d) 3 6 14 SUB m 2 2 6 SUB g 1 2 4 TSTIO m 3 4 12 TST g 2 3 7 TST m 3 3 9 TST (HL) 2 4 10 XOR (HL) 1 2 6 XOR (IX+d) 3 6 14 XOR (IY+d) 3 6 14 XOR m 2 2 6 XOR g 1 2 4 MNEMONICS Bytes Machine Cycles States

Table 48. 1st Op Code Map Instruction Format: XX

Note 1: (HL) replaces g. Note 2: (HL) replaces s. Note 3: If DDH is supplemented as first Op Code for the instructions which have HL or (HL) as an operand in Table48, the instructions are executed replacing HL with IX and (HL) with (IX+d). ex. 22H : LD (mn), HL DDH 22H : LD (mn), IX If FDH is supplemented as 1st Op Code for the instructions which have HL or (HL) as an operand in Table48, the instructions are executed replacing HL with IY and (HL) with (IY+d). ex. 34H : INC (HL) FDH 34H : INC (IY+d) However, JP (HL) and EX DE, HL are exceptions and note the following.

• If DDH is supplemented as 1st Op Code for JP (HL), (IX) replaces (HL) as operand and JP (IX) is executed
• If FDH is supplemented as 1st Op Code for JP (HL), (IY) replaces (HL) as operand and JP (IY) is executed
• Even if DDH or FDH is supplemented as 1st Op Code for EX DE, HL, HL is not replaced and the instruction is regarded as illegal instruction.

Table 49. 2nd Op Code Map Instruction Format: CB XX

1110 E NOTE

Table 50. 2nd Op Code Map Instruction Format: ED XX

1010 A ADC HL,ww IND INDR A

1011 B LD ww, (mn) OTD

1100 C TST g MLT ww C

1101 D RETI D

1110 E IM 2 E

1111 F LDR,

Table 51. Bus and Control Signal Condition in Each Machine Cycle

Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)

• 1 Interrupt request is not sampled.

*3 Interrupt request is not sampled.

*4 In the case of R1 and Z MASK, interrupt request is not sampled.

when IOC = 1 and IOC = 0 respectively.

Table 52. Interrupts

Table 52. Interrupts (Continued)

Table 53. Request Acceptances in Each Operating Mode

The Z80180 features three types of requests. Type 1, Type 2, and Type 3 requests priority as follows.

• Highest priority Type 1 > Type 2 > Type 3 lowest priority
• Each request priority in Type 2 is shown as follows. highest priority Bus Req. > Refresh Req. > DMA Request lowest priority Internal I/O Interrupt acceptable NMI ­ ­ ­ Not acceptable Interrupt acknowledge cycle precedes. NMI is accepted after executing Acceptable DMA cycle stops Acceptable Return from SYSTEM STOP mode to normal operation Note: * Not acceptable when DMA Request is in level-sense. ­: Same as above. MC: Machine Cycle

Table 54. The Z80180 Types of Requests

Note: If Bus Request and Refresh Request occur simultaneously, Bus Request is accepted but Refresh Request is cleared. OPERATION MODE TRANSITION NORMAL *1 HALT SLEEP IOSTOP SYSTEM STOP RESET IOSTOP = 1 IOSTOP = 0 RESET = 0 RESET = 0RESET = 0 RESET = 0 RESET = 0 RESET = 0 HALT Instruction Interrupt SLP Instruction Interrupt SLP Instruction Interrupt

Figure 94. Operation Mode Transition

• 1. NORMAL: CPU executes instructions normally in NORMAL mode.
• 2. DMA request: DMA is requested in the following cases.

– DREQ0, DREQ1 = 1 memory to/from (memory mapped) I/O DMA transfer – BCR0, BCR1 = 0000H (all DMA transfers) – NMI = 0 (all DMA transfers) OTHER OPERATION MODE TRANSITIONS The following operation mode transitions are also possible. 1. HALT DMA REFRESH BUS RELEASE IOSTOP DMA REFRESH BUS RELEASE 2. SLEEP BUS RELEASE SYSTEM STOP BUS RELEASE { } { }

Table55 describes pin outputs in each operating mode. Table 55. Pin Outputs in Each Operating Mode

• 1 : High
• 0 : Low
• A : Programmable
• Z : High Impedance
• IN : Input
• OUT : Output
• * : Invalid PIN STATUS Tables56 describes the status of each ping during RESET and LOW POWER OPERATION modes. Internal DMA Memory Read 1 0 1 0 1 1 * 1 0 A IN Memory Write 1 0 1 1 0 1 * 1 0 A OUT I/O Read 1 1 0 0 1 1 * 1 0 A IN I/O Write 1 1 0 1 0 1 * 1 0 A OUT RESET 1 1 1 1 1 1 1 1 1 Z IN

Table 55. Pin Outputs in Each Operating Mode (Continued)

Table 56. Pin Status During RESET and LOW POWER OPERATION Modes

Table 56. Pin Status During RESET and LOW POWER OPERATION Modes (Continued)

• 1: HIGH 0: LOW A: Programmable Z: High Impedance
• IN (A): Input (Active) IN (N): Input (Not active) OUT: Output
• H: Holds the previous state
• ← : same as the left MREQ — 1 1 OUT 1 E — 0 E Clock Output ← ← M1 — 1 1 OUT 1 WR — 1 1 OUT 1 RD — 1 1 OUT 1 Phi — Phi Clock Output ← ← ←

Table 57. Internal I/O Registers

Table 57. Internal I/O Registers (Continued)

• CTS: Depending on the condition 0f CTS Pin.

• DCD0: Depending on the condition of DCD0 Pin.

ORDERING INFORMATION

• Package P = Plastic Dip V = Plastic Chip Carrier F = Quad Flat Pack
• Temperature S = 0°C to +70°C E = -40°C to 100°C
• Speed 06 = 6 MHz 08 = 8 MHz 10 = 10 MHz
• Environmental C = Plastic Standard
• Example Z8018008PSC is an 80180 8 MHz, Plastic DIP, 0 °C to 70°C, Plastic Standard Flow. Z 80180 08 P S C Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix

A AC characteristics 197 Address generation, physical 64 Address map I/O 44 I/O address translation 57 Logical examples 55 Logical memory organization 58 Logical space configuration 59 Physical address transition 56 Addressing Extended 182 I/O 184 Indexed 182 Indirect 181 Architecture 12 ASCI Baud rate selection 142 Block diagram 117 Clock diagram 141 Control register A0 125 Control register A1 128 Control register B 131 Functions 116 Interrupt request circuit diagram 140 Register descriptions 117 Status register 0 120 Status register 1 123 Asynchronous serial communications interface (ASCI) 14 B Baud rate selection ASCI 142 CSI/O 150 Block diagram 6 ASCI 117 CSI/O 146 DMAC 92 MMU 56 PRT 157 Bus state controller 13 C Central processing unit (CPU) 14 Circuit diagram, ASCI interrupt request 140 Clock generator 13 Clocked serial I/O (CSI/O) 14 CPU register configurations 176 CPU timing Basic instruction 23 BUSREQ/BUSACK Bus Exchange 25 HALT and Low Power modes 31 I/O data read/write 22 Internal I/O registers 41 MMU register description 60 Op Code fetch timing 18 Operand and data read/write 20 RESET 25 Wait state generator 27

Control/Status register 147, 150, 159, 160, 161, 172 External clock receivetiming diagram 156 External clock transmit timing diagram 154 Internal clock receivetiming diagram 155 Internal clock transmit timing diagram 153 interrupt request generation 151 Operation 151 Receive/Transmit timing diagram 204 Timer initialization, count down and reload timing diagram 163 Timer output control 163 Timer output timing diagram 164 Cycle timing 87 D Data formats 131 DC characteristics Absolute maximum ratings 185 Z80180 186 Z8L180 189 Z8S180 187 DCD0 timing diagram 139 Description, general 1 Design rules, circuit board 170 Direct register bit field definitions 181 Divide ratio 134 DMA Controller (DMAC) 90 CYCLE STEAL mode timing diagram 106 Edge-sense timing diagram 108 Interrupt request generation 114 Level-sense timing diagram 107 Mode register (DMODE) 97 Operation 104 Status register (DSTAT) 95 TEND0 output timing diagram 108 Transfer request 110 WAIT control register 100 DMAC Block diagram 92 Register 93 DRAM refresh intervals 89 Dynamic RAM refresh control 86 E E clock BUS RELEASE, SLEEP and SYSTEM STOP modes timing diagram 201 Memory and I/O R/W cycles timing dia- gram 201 Minimum timing example of PWEL and PWEH timing diagram 202 Timing conditions 166 Timing diagram (R/W and INTACK cy-

cles) 167 Timing diagram (SLEEP and SYSTEM STOP modes) 168 Extended addressing 182 External clock rise and fall time 204 F Features 1 H HALT mode 31 I I/O Addressing 184 Control register (ICR) 42 I/O control register 42 Immediate addressing Addressing Immediate 183 Indexed addressing 182 Indirect addressing 181 Input ris and fall time (except EXTAL and RE- SET) timing diagram 204 Instruction set CPU registers 175 Flag register 178 Summary 173 INT0 Interrupt mode 2 timing 80 Mode 1 interrupt sequence 77 Mode 1 timing 78 INT0 mode 0 timing 76 Interrupt Acknowledge cycle timings 82 Control registers and flags 65 Controller 13 CSI/O request generation 151 DMA request generation 114 Enable (ITE) 68 INT/TRAP control register (ITC) 67 Maskable interrupt 0 (INT0) 75 Non-maskable 72 PRT request generation 164 Sources 65 Sources during reset 83 TRAP 70 Vector register (I) 66 IOSTOP mode 35 L Level-sense programming 109 Logical memory organization 58 M M1 temporary enable timing 16 Maskable interrupt level 0 75

Memory and I/O Wait state insertion 29 Memory management unit (MMU) 13 Memory to ASCI 109 Memory to memory 105 MMU Register description 60 Mode HALT 31 IOSTOP 35 SLEEP 33 SYSTEM STOP 35 Modem control signals 138 N NMI and DMA operation timing diagram 115 Use 74 Non-maskable interrupt 72 O On-chip clock generator Circuit board design rules 170 External clock interface 169 Operating frequencies 168 Operation modes Control register 84 CPU timing 18 IOC 16 M1 Enable 15 M1 temporary enable 16 P Pin description A0 through CTS1 7 BUSREQ through RFSH 9 D0 through INT2 8 RTS0 through TEND1 10 TEST through XTAL 10 Pin package 64-pin DIP 3 68-pin PLCC 4 80-pin QFP 5 Programmable reload timer (PRT) 14 Programming Level-sense 109 PRT Block diagram 157 Bus release mode timing diagram 167 Interrupt request generation 164 Timer control register 161 R Refresh 87 Control register 88 Register ASCI Control A0 125 ASCI Control A1 128 ASCI Control B 131 ASCI Status 0 120 ASCI Status 1 123

CSI/O control/status 147, 150, 159, 160, 161, 172 Direct bit field definitions 181 DMA mode (DMODE) 97 DMA status 95 DMA/WAIT control 100 Flag 178 I/O Control 42 I/O control (ICR) 42 Indirect addressing 181 INT/TRAP control (ITC) 67 Interrupt Vector (I) 66 MMU bank base (BBR) 62 MMU common bank area (CBAR) 60 MMU common base (CBR) 61 Operation mode control 15, 84 PRT timer control register 161 Refresh control 88 Relative addressing Addressing Relative 183 RETI control signal states 85 Instruction sequence 84 RTS0 timing diagram 140 S Secondary bus interface 165 SLEEP mode 33 SLP execution cycle timing diagram Timing diagram SLP execution cycle 203 Status summary table 10 SYSTEM STOP mode 35 T Test conditions, standard 205 Timer initialization, count down and reload 163 Timer output timing diagram Timing diagram Timer output 202 Timing diagram 163 AC 197 Bus Exchange Timing During CPU Inter- nal Operation 27 Bus Exchange Timing During Memory Read 26 CPU (I/O Read/Write cycles) 199 CSI/O external clock receive 156 CSI/O external clock transmit 154 CSI/O internal clock receive 155 CSI/O internal clock transmit 153 CSI/O receive/transmit 204 CSI/O timer output 164 DCD0 139 DMA control signals 200 DMA CYCLE STEAL mode 106 DMA edge-sense 108 DMA level-sense 107

E clock (memory and I/O R/W cycles) 201 E clock (R/W and INTACK cycles) 167 E clock (SLEEP and SYSTEM STOP modes) 168 E clock BUS RELEASE, SLEEP and SYS- TEM STOP modes) 201 E clock minimum timing example of PWEL and PWEH) 202 External clock rise and fall 204 HALT 33 I/O Read and Write cycles with IOC = 0 17 I/O read and write cycles with IOC=1 17 I/O read/write timing 23 Input rise and fall time 204 Instruction 24 INT0 interrupt mode 2 80 INT0 mode 0 76 INT0 mode 1 78 INT1, INT2 and Internal interrupts 86 M1 temporary enable 16 Memory read/write timing (with Wait state) 22 Memory read/write timing (without Wait state) 21 NMI and DMA operation 115 Op Code Fetch timing (with Wait state) 20 Op Code Fetch timing (without Wait state) PRT bus release mode 167 Refresh cycle 87 RESET 25 RTS0 140 SLEEP 35 TRAP timing - 2nd Op Code Undefined 71 TRAP timing - 3rd Op Code Undefined 72 WAIT 28 TRAP 68 Interrupt 70 Timing 71 U Undefined Fetch Object (UFO) 68 V Vector acquisition INT0 mode 2 79 INT1, INT2 81 Vector table 82 W Wait state generation I/O Wait insertion 29 Memory and 29 Programmable Wait state insertion 28 Wait input and reset 30 Wait state insertion 30