Z8F1681

Z8F1681 ZILOG | Alldatasheet

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High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F6482 Series Copyright ©2021 Zilog®, Inc. All rights reserved. www.zilog.com Product Specification

PS029413-0921 P R E L I M I N A R Y Foreword Z8 Encore! XP® F6482 Series Product Specification ii DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2021 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. Zilog, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. Zilog ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, and ZMOTION are registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. Warning:

Z8 Encore! XP® F6482 Series Product Specification iii

Revision History

Each instance in the following revision history table reflects a change to this document from its previous version. For more details, refer to the corresponding pages or appropriate links provided in the table. Date Revision Level Description Page Aug 2021 13 Updated FLLEN (FLL enable) bit to be disable by System Reset. Clarified that PortD0/RESET is not a Stop Mode Recovery source. Enhanced UART noise filter description. Corrected Noise Filter Operation figure. Updated USB Bulk Out Transfers Section to include information and a caution regarding USB buffer space accesses. Updated ADC Starting and Stopping Conversions Section. Clarified ADC offset compensation and updated ADC gain compensation formula. Added Development System Overview Section. Updated DAC Offset Error parameter. Added Comparator hysteresis definition. Updated Op Amp Input Offset and Gain Tolerance parameters. Dropped DCO tempco, DCO voltco, and FLL Lock TIme parameters. Corrected typos and updated logo. , 110, 120 57, 90 255 349 445 451 561 612 614 617 626 various Jun 2018

12 Removed Z8F6481AT024XK2247 (80-pin LQFP) from the ZMOTION

Library Series Ordering Information table. 636

Z8 Encore! XP® F6482 Series Product Specification iv Apr 2017 11 Corrected typos in pins 9 and 10 of the 32-pin QFN pinout. Corrected RTC_DOW, RTC_DOM, RTC_ADOW, RTC_ADOM addresses. Added information regarding IRQE in Stop Mode. Updated description of PWRCTL1[3:2] regarding control of the ADC and ADC voltage reference. Clarified SEEDSEL usage for DCO. Corrected R/W capability of the TxNFC registers. Corrected counter mode descriptions for RTC_DOW, RTC_DOM, RTC_ADOW, RTC_ADOM. Updated Event In power line selection Added I2C baud rate generator information for the case of the I2C configured as a general purpose timer Clarified stopping ADC conversions when SCAN, CONTCONV or AVE are set. Updated description of ADC wake-up Changed minimum ADC ST value from 1 clock to 2 clocks. Described the effect of setting Op Amp A or Op Amp B OPOWER bit. Clarified OCD block diagram. Removed VBO and LVD pulse rejection periods. Updated DCO resolution and DCO control word resolution. Add ZMOTION ordering part numbers 28-29 109, 121 186 211, 217, 226, 227 212, 228 334 445 447, 449 461 476, 482, 484 560 606, 619 626 636 May 2016

10 Added information about Exter nal Pad on the QFN package and

clarification about AVDD and AVSS power supply in Table 4. 21, 22 Apr 2016 09 Corrected part number typos in Table 356. 633 Mar 2016

08 Added 44-pin QFN package infor mation to Table 16, Table 356, and

Table 358. 55, 633, 638 Jan 2016 07 Corrected Figure 6, 80-pin LQFP. 17 Dec 2015 06 Clarified the 64-pin pack age size (10 mm x 10 mm). 632

Z8 Encore! XP® F6482 Series Product Specification v Nov 2015 05 Added 44-pin Quad Flat No Lead (QFN) packaging option. RTC. Changed LSB in counter mode to DOW. Clarified INPCAP functionality in Dual Input Triggered One-Shot Mode and Gated Mode. Updated 14-bit ADC conversion to be recommended for differential mode only. Indicated that the Op Amp B IRESSEL = 11 setting is not recommended for AV DD < 3V. ADC electrical parameters. Added RESOLUT=1 (14-bit resolution) INL/ DNL specs. Reduced maximum INMODE=0x ADC Clock frequency to 2MHz.Reduced maximum RESOLUT=1 ADC Clock frequency to 2MHz. Added ST and SST parameters for INMODE=1x at POWER=10 (low) Corrected typos. 12, 14, 632 211, 217, 218 155, 165, 180 441, 445, 608 479, 484, 608 various Oct 2014

04 Corrected pin 10 to ESOUT1 from ESOUT0, Figure 2; corrected “P3”

values for pins 32 and 33 to “PE”, Figure 3; corrected PB3 value for Pin 53 to PB4, Figure 6; modified description in System Clock Source Switching and PCLK Source Switching sections; clarified description for the ADCREF bit, Table 15; corrected subscripted terms in Frequency Locked Loop and Phase Locked Loop sections; corrected Figure 24 timer output values to T4CH0, T4CH1; clarified description in WDT Interrupt in Normal Operation, WDT Interrupt in Stop Mode, and WDT Reset in Stop Mode sections; clarified IEC definition, DALI Protocol Mode section; modified Bit 7 description, Table 204; corrected overline issue to depict active status of Timers 0, 1, and 2, Table 217; added note, Channel Scanning section; modified description, Starting and Stopping Conversions section and the Automatic and Manual Wake-Up subsections of the Starting and Stopping Conversions section; modified description, ADC Timing section; modified description, ADC Wake-up, Sampling, and Settling section; clarified description, Calibration and Compensation section; modified offset calibration description for bits 7:6, Table 236; modified GAIN values, bits 7:4, Table 253; modified VBIAS descriptions, Reference System Operation section; modified description of Bit 7, Table 257; corrected ADC Output (Hex) value for 0°C from BC1 to B1C, Table 262; modified TWAKE_AR parameter description and TWAKE_ADC conditions, Table 337; modified GAINTOL values and conditions, Table 342. 13, 14, 17, 54, 100, 102, 109, 112, 194, 207, 243, 400, 413, 444, 445, 447, 449, 451, 452, 482, 491, 494, 501, 608, 617 Dec 2013

03 Updated UART-LDD, USB, Option Bits, and Electrical Characteristics

chapters. 230 , 340, 542, 601 May 2013 02 Corrected to include PRELIMINA RY in footer per Zilog style. n/ a May 2013 01 Original issue. n/a

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification vi Table of Contents Revision History iii Table of Contents vi List of Figures xxii List of Tables xxvi 1.4.14. Master/Slave I

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification vii 5.3.1. Stop-Mode Recovery Using Watchdog Timer Time-Out . 46 5.3.2. Stop-Mode Recovery Using Timer, Comparator, RTC, or LVD Interrupt 46

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification viii 7.10.7. Port A–G Stop-Mode Recovery Source Enable Subregisters

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification ix

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification x

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xi 11.7.6. Multi-Channel Timer Contro l 0 and Control 1 Registers 1 99 11.7.7. Multi-Channel Timer Channe l Status 0 and Status 1 Registers 202 11.7.9. Multi-Channel Timer Ch annel-y High and Low Byte Registers 205 12.2.1. Watchdog Timer Reload Hig h and Low Byte Registers . 208

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xii

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xiii 14.3.12. UART-LDD 0–1 Baud Rate High and Low Byte Registers . 276

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xiv

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xv

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xvi 18.3.9. DMA 0–3 Linked List D escriptor Address High and Low Subregisters 410

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xvii

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xviii

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xix 27.2.3. Flash Code Protection Ag ainst Accidental Program and Erasure 533 29.2.4. Optimizing NVDS Memory Usage for Execution Speed 559

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xx

PS029413-0921 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F6482 Series Product Specification xxi 33.4.20. Digitally Controlled Oscillator and Frequency-Locked Loop 626 Index 639 Customer Support 659

Table 29. Port A–G Stop-Mode Recovery Source Enable Subregisters (PxSMRE) . . 90

Table 123. UART-LDD 0–1 Status 0 Registers, Standard UART Mode (UxSTAT0) 259

Table 143. ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . 285 Table 165. Determining USB Endpoint Buffer Memory Allocation with All Endpoints Table 166. Determining USB Endpoint Buffer Memory Allocation with Only Endpoints

Table 176. USB OUT Endpoint 1–3 Start Address Subregisters (USBOxADDR) . . . 364

Table 215. DMA 0–3 Linked List Descriptor Address High Subregister (DMAxLAH) . . Table 216. DMA 0–3 Linked List Descriptor Address Low Subregister (DMAxLAL) . .

PS029413-0921 P R E L I M I N A R Y Overview Z8 Encore! XP® F6482 Series Product Specification Chapter 1. Overview Zilog’s F6482 Series MCUs, members of the Z8 Encore! XP® family, are based on Zilog’s advanced 8-bit eZ8 CPU core. This microcontroller is optimized for low-power and wire- less applications, and supports 1.8 V to 3.6 V low-voltage operation with extremely low Active, Halt and Stop Mode currents, plus it offers an assortment of speed and low-power options. In addition, the feature-rich analog and digital peripherals of the F6482 Series makes it suitable for a variety of applications including safety and security, utility meter- ing, digital power supervisory, hand-held electronic devices, and general motor control. 1.1. Features Key features of the F6482 Series MCU include:

• 24 MHz eZ8 CPU core
• 16 KB, 32 KB, 60 KB or 64 KB Flash memory with in-circuit programming capability
• 2 KB or 3.75 KB internal RAM
• 128 B Non-Volatile Data Storage (NVDS)
• Up to 17-Channel, 12-bit Analog-to-Digital Converter (ADC) that can be configured for internal or external voltage reference and single-ended or differential inputs
• 12-bit Digital-to-Analog Converter (DAC)
• Integrated LCD driver with blinking and contrast control for up to 96 segments
• 128-bit Advanced Encryption Standard (AES) encryption/decryption hardware accel- erator according to FIPS PUB 197
• Real-Time Clock (RTC) supporting both Counter and Clock modes
• On-Chip Temperature Sensor
• Two on-chip analog comparators (32-pin and 64-pin with LCD packages contain only one)
• Two on-chip, low-power operational amplifiers (32-pin and 64-pin with LCD packages contain only one)
• 8 Channel Event System provides communication between peripherals for autonomous triggering
• Full-Speed Universal Serial Bus (USB 2.0) device supporting eight endpoints with in- tegrated USB-PHY (not available on 64-pin package with LCD)

PS029413-0921 P R E L I M I N A R Y Part Selection Guide Z8 Encore! XP® F6482 Series Product Specification

• Two full-duplex 9-bit UART ports with the support of Local Interconnect Network (LIN) and Digital Addressable Lighting Interface (DALI) protocols (32-pin and 64-pin with LCD packages contain only one)
• RS-485 Multidrop Mode up to 250 kbit/sec (DMX Support) integrated with UARTs
• Two Enhanced Serial Peripheral Interface (SPI) controllers (32-pin and 44-pin packag- es contain only one)
• I2C controller which supports Master/Slave modes
• Four-channel DMA controller
• Three enhanced 16-bit timers with Capture, Compare, and PWM capability
• Two additional basic 16-bit timers with interrupt (shared as UART Baud Rate Gener- ator)
• 16-bit Multi-Channel Timer which supports four Capture/Compare/PWM modules (not available on 32-pin and 64-pin with LCD packages)
• Watchdog Timer (WDT)
• 26 to 67 General-Purpose Input/Output (GPIO) pins, depending upon package
• Up to 41 interrupt sources with up to 30 interrupt vectors
• On-Chip Debugger (OCD)
• Power-On Reset (POR) and Voltage Brown-Out (VBO) protection
• Built-in Low-Voltage Detection (LVD) with programmable voltage threshold
• Low Frequency Crystal Oscillator (LFXO) operating at 32.768 kHz with low power consumption
• Internal clock sources and clock multiplication including: Internal Precision Oscillator (IPO), Digitally Controlled Oscillator (DCO), Watchdog Timer Oscillator (WTO), Fre- quency Locked Loop (FLL) and Phase Locked Loop (PLL)
• High Frequency Crystal Oscillator (HFXO) operating in the 1–24 MHz range
• Wide operation voltage range: 1.8 V–3.6 V
• 32-, 44-, 64-, and 80-pin packages
• –40°C to +85°C (extended) operating temperature range 1.2. Part Selection Guide Table 1 shows basic features and package styles available for each device within the F6482 Series product line.

Table 1. F6482 Series Family Part Selection Guide

Figure 1 shows a block diagram of the F6482 Series architecture. Figure 1. F6482 Series Block Diagram

2 Op Amps

2 Comparators

PS029413-0921 P R E L I M I N A R Y eZ8 CPU and Peripheral Overview Z8 Encore! XP® F6482 Series Product Specification 1.4. eZ8 CPU and Peripheral Overview Zilog’s 8-bit eZ8 CPU meets the continuing demand for faster and more code-efficient microcontrollers. It executes a superset of the original Z8 instruction set. The key features of the eZ8 CPU are:

• Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required Program Memory
• Software stack allows greater depth in subroutine calls and interrupts more than hardware stacks
• Compatible with existing Z8 code
• Expanded internal Register File allows access up to 4 KB
• New instructions improve execution efficiency for code developed using higher-level programming languages including C
• Pipelined instruction fetch and execution
• New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT and SRL
• New instructions support 12-bit linear addressing of the register file
• Up to 12 MIPS operation
• C Compiler-friendly
• 2 to 9 clock cycles per instruction To learn more about the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is available free for download from the Zilog website. 1.4.1. General-Pu rpose Input/Output The F6482 Series features 26 to 67 port pins (Ports A–J) for general purpose input/output (GPIO). The number of GPIO pins available is a function of package. Each pin is individ- ually programmable. 1.4.2. Flash Controller The Flash Controller is used to program and erase Flash memory, and supports protection against accidental program and erasure. 1.4.3. Non-Volatile Data Storage The Non-V olatile Data Storage (NVDS) uses a hybrid hardware/software scheme to implement a byte-programmable data memory and is capable of over 100,000 write cycles.

PS029413-0921 P R E L I M I N A R Y eZ8 CPU and Peripheral Overview Z8 Encore! XP® F6482 Series Product Specification 1.4.4. Clock System The clock system generates a System Clock, a low-frequency Peripheral Clock, and the Watchdog Timer Oscillator. It is comprised of:

• Watchdog Timer Oscillator (WTO).
• 32.768 kHz Internal Precision Oscillator (IPO).
• Low Frequency Crystal Oscillator (LFXO) which is a low-power oscillator optimized for use with a 32.768 kHz watch crystal. The IPO and LFXO can be used as clock sources for the Real-Time Clock (RTC), Liquid Crystal Display (LCD) and Timers in any mode, and as the reference clock for the Frequency Locked Loop (FLL).
• High Frequency Crystal Oscillator (HFXO) that provides highly accurate clock fre- quencies using an external crystal or ceramic resonator.
• Phase Locked Loop (PLL) which is clocked by the HFXO and can be selected as a sys- tem clock and/or as the USB clock.
• Digitally Controlled Oscillator (DCO).
• Frequency Locked Loop (FLL). The reference clock for the FLL can be either an Inter- nal Precision Oscillator (IPO) or a Low Frequency Crystal Oscillator. The FLL, in con- junction with the DCO can be configured to generate system clock frequencies from 1 to 24 MHz. 1.4.5. 12-Bit Analo g-to-Digital Converter The Analog-to-Digital Converter (ADC) converts an analog input signal to a 12-bit binary number. The ADC supports up to eight analog input sources multiplexed with GPIO ports. It is configurable for internal or external voltage reference and single-ended or differential inputs. 1.4.6. 12-Bit Digital-to-Analog Converter The Digital-to-Analog Converter (DAC) converts a 12-bit digital code to an analog output voltage The DAC supports both internal and external references. 1.4.7. Low-Power Opera tional Amplifiers Two low-power operational amplifiers (Op Amps) are provided: Op Amp A and Op Amp B. Op Amp A is a low-power, general-purpose operational amplifier with optional internal programmable gain settings. Op Amp B is a low-power, general-purpose operational amplifier that can optionally be internally configured as a current source/sink. Each Op Amp output can be internally routed to the ADC, a comparator, or an output pin. These op amps can function in all operating modes, including Stop Mode.

PS029413-0921 P R E L I M I N A R Y eZ8 CPU and Peripheral Overview Z8 Encore! XP® F6482 Series Product Specification 1.4.8. Analog Comparators The analog comparators compare the signal at an input pin or at other internal signal sources with either an internal programmable voltage reference, an internal fixed refer- ence, the DAC output or a second input pin. The comparator outputs are used to either drive an output pin, the Event System, or to generate an interrupt. The comparators can function in all operating modes including Stop Mode. 1.4.9. Temperature Sensor The temperature sensor produces an analog output proportional to the device temperature. The signal is sent either to the ADC or to the analog comparators. The temperature sensor can function in all operating modes including Stop Mode. 1.4.10. Low-Voltage Detector The low-voltage detector generates an interrupt when the supply voltage drops below a user-programmable level. 1.4.11. USB 2.0 The Full-Speed Universal Serial Bus (USB 2.0) device provides eight endpoints supporting bulk, control, and interrupt transfers. It contains an integrated USB-PHY and a PLL for trans- mit clocking. 1.4.12. Enhanced SPI The enhanced SPI is a full-duplex, buffered, synchronous character-oriented channel which supports a four-wire interface. 1.4.13. UART with LIN, DALI, and DMX A full-duplex 9-bit UART provides serial, asynchronous communication, and supports the Local Interconnect Network (LIN) and Digital Addressable Lighting Interface (DALI) serial communications protocols as well as Asynchronous Serial Digital Data Transmis- sion Standard for Controlling Lighting Equipment and Accessories (DMX). The UART supports 8-bit and 9-bit data modes, selectable parity, and an efficient bus transceiver Driver Enable signal for controlling a multi-transceiver bus, such as a RS-485. The LIN bus is a cost-efficient, single-master, multiple-slave organization which supports speed up to 20 kilobits. Manchester encoding is supported for the DALI protocol. 1.4.14. Master/Slave I2C The inter-integrated circuit (I2C) controller makes the F6482 Series products compatible with the I2C protocol. The I2C controller consists of two bidirectional bus lines:

• Serial data (SDA) line

PS029413-0921 P R E L I M I N A R Y eZ8 CPU and Peripheral Overview Z8 Encore! XP® F6482 Series Product Specification

• Serial clock (SCL) line This I2C controller also supports Master, Slave, and Multi-Master operations. 1.4.15. Liquid Crystal Display The Liquid Crystal Display (LCD) provides direct drive for shows containing up to 96 segments and supports static display, as well as multiplexing by 2, 3 and 4. Dedicated buf- fers store the LCD image, and an integrated charge pump is available to provide consistent drive levels despite varying supply voltage. In addition, the LCD is capable of contrast control and the automated blinking of individual segments. 1.4.16. Advanced Encryption Standard The hardware accelerator for 128-bit Advanced Encryption Standard (AES) performs encryp- tion and decryption according to FIPS PUB 197. The conversion throughput for each 128- bit block is 160 clock cycles for encryption and 176 clock cycles for decryption. 1.4.17. Timers Three enhanced 16-bit reloadable timers are used for timing/counting events or motor con- trol operations. These timers provide a 16-bit programmable reload counter and operate in One-Shot, Triggered One-Shot, Dual Input Triggered One-Shot, Continuous, Counter, PWM Single Output, PWM Dual Output, Capture, Capture Restart, Compare, Gated, Cap- ture and Compare, and Demodulation modes. In addition to these three enhanced 16-bit timers, there are two basic 16-bit timers with interrupt functionality. The two timers are used as Baud Rate Generators (BRGs) when the UART is enabled, and configured as basic 16-bit timers when the UART is disabled. 1.4.18. Multi-Channel Timer The multi-channel timer has a 16-bit up/down counter and a 4-channel Capture/Compare/ PWM channel array. This timer enables the support of multiple synchronous Capture/ Compare/PWM channels based on a single timer. 1.4.19. Real-Time Clock The Real-Time Clock (RTC) supports both Counter and Clock modes. Alarms are available for seconds, minutes, hours, day of the week, and day of the month. The format for all count and alarm registers is selectable between binary and binary-coded decimal (BCD). Preconfigured dividers exist for 32.768 kHz and 50/60 Hz clock sources and a provision for calibrating a 32.768 kHz clock source is provided.

reset source as well as a reset indicator. munication with an external host. transfer of data between peripherals and/or memories without CPU intervention. This document references the acronyms and expansions listed in Table 2. Table 2. Acronyms and Expansions

Table 2. Acronyms and Expansions (Continued)

Table 3 lists the package styles available for each device in the F6482 Series product line. Series. For signal descriptions, see Table 4 on page 18. erwise. At power-up, the Port D0 pin defaults to the RESET alternate function. Table 3. F6482 Series Package Options

It is recommended to connect the QFN bottom pad to VSS. Figure 2. Z8F6481, Z8F6081, Z8F3281 and Z8F1681 MCUs, 32-Pin Quad Flat No Lead (QFN) Package

It is recommended to connect the QFN bottom pad to VSS. Figure 3. Z8F6481, Z8F6081, Z8F3281 & Z8F1681 MCUs, 44-Pin Quad Flat No Lead (QFN) and Low-

Figure 4. Z8F6481, Z8F6081 Z8F3281 & Z8F1681 MCUs, 64-Pin Low-Profile Quad Flat Package (LQFP)

Figure 5. Z8F6482, Z8F6082, Z8F3282 & Z8F1682 MCUs, 64-Pin Low-Profile Quad Flat Package (LQFP)

Figure 6. Z8F6482, Z8F6082, Z8F3282 & Z8F1682 MCUs, 80-Pin Low-Profile Quad Flat Package (LQFP)

cific package style, see the Pin Configurations section on page 12. Table 4. Signal Descriptions PA[7:0] I/O Port A: These pins are used for general-purpose I/O. PB[7:0] I/O Port B: These pins are used for GPIO. PC[7:0] I/O Port C: These pins are used for GPIO. PD[7:0] I/O Port D: These pins are used for GPIO. PD0 is output only. PE[6:0] I/O Port E: These pins are used for GPIO. PF[7:0] I/O Port F. These p ins are used for GPIO. PG[7:0] I/O Port G. These pins are used for GPIO. PH[7:0] I/O Port H. These pins are used for GPIO. PJ[3:0] I/O Port J. These pins are used for GPIO. These signals are the transmit output from the UART0/1. These signals are the receive input for the UART0/1. These signals are the flow control input for the UART0/1. external RS-485 driver is enabled when data is transmitted by the UART0/1. enable the SDA function, this pin is open-drain.

is the SPI 0–1 slave, SS0/SS1 is the input slave select. data input to the SPI 0–1 slave device. output from the SPI 0–1 slave device. Liquid Crystal Display (LCD) segment outputs. Liquid Crystal Display (LCD) common outputs. decoupled with a 1 µF capacitor. These signals are output from the timers. These signals are output from the timers in PWM Dual Output Mode. T1IN/T2IN signal is multiplexed with T0OUT/T1OUT/T2OUT signals. Table 4. Signal Descriptions (Continued)

These are the output from the comparator 0 and the comparator 1. If enabled, this pin is driven by the on-chip, low-power Operational Amplifier. be connected between the pin and the XOUT pin to form the oscillator. be connected between it and the XIN pin to form the oscillator.

clock and/or as System Clock. This signal is the control and data input and output of the On-Chip Debugger. resistor to ensure proper operation. open-drain and features an enabled internal pull-up resistor. AVDD I Analog Power Supply. AV DD must be at the same potential as VDD. AVSS I Analog Ground. AV SS must be at the same potential as VSS. VCORE I/O Regulated core power supply (ex ternal current loading not permitted).

this table is sorted alphabetically by pin symbol mnemonic. Table 5. Pin Characteristics

Table 5. Pin Characteristics (Continued)

PS029413-0921 P R E L I M I N A R Y Address Space Z8 Encore! XP® F6482 Series Product Specification Chapter 3. Address Space The eZ8 CPU can access the following three distinct address spaces:

• The Register File contains addresses for general-purpose registers, eZ8 CPU, peripher- als, and GPIO port control registers
• The Program Memory contains addresses for all memory locations having executable code and/or data
• The Data Memory contains addresses for all memory locations that contain data only These three address spaces are covered briefly in the following sections. To learn more about the eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual (UM0128), which is available free for download from the Zilog website. 3.1. Register File The Register File address space in the Z8 Encore!® MCU is 4 KB (4096 bytes). The Reg- ister File is composed of two sections: control registers and general-purpose registers. When instructions are executed, registers defined as sources are read, and registers defined as destinations are written. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4 KB Register File address space are reserved for control of the eZ8 CPU, on-chip peripherals, and the input/output ports. These registers are located in the F00h to FFFh address range. Some of the addresses within the 256 B control register sections are reserved; i.e., unavailable. Reading from a reserved Register File address returns an undefined value. Zilog does not recommend writing to the reserved Register File addresses because doing so can produce unpredictable results. On-chip Register RAM always begins at address 000h in the Register File address space. F6482 Series devices contain 2 KB or 3.75 KB of on-chip Register RAM. 3.2. Program Memory The eZ8 CPU supports 64 KB of Program Memory address space. The F6482 Series devices contain 16 KB to 64 KB of on-chip Flash memory in the Program Memory address space, depending on the device.

effect. Table 6 lists the Program Memory maps for the F6482 Series products. Table 6. F6482 Series Program Memory Maps Note: *See Table 51 on page 128 for a list of interrupt vectors and traps.

F6482 Series MCUs do not use the eZ8 CPU’s 64 KB Data Memory address space. gram Memory data. Access to the Flash Information Area is read-only. Table 7. F6482 Series Flash Memory Information Area Map FC00–FC3F Zilog option bits. FC60–FC7F Zilog calibration data. Table 6. F6482 Series Program Memory Maps (Continued) Note: *See Table 51 on page 128 for a list of interrupt vectors and traps.

devices and package styles in the F6482 Series support the LCD or all of the GPIO Ports. Consider registers for unimplemented peripherals as Reserved. Table 8. Register File Address Map

Table 8. Register File Address Map (Continued)

PS029413-0921 P R E L I M I N A R Y Reset, Stop-Mode Recovery and Low-Volt age Z8 Encore! XP® F6482 Series Product Specification Chapter 5. Reset, Stop-Mode Recovery and Low-Voltage Detection The Reset Controller within the F6482 Series MCU controls Reset and Stop-Mode Recov- ery operations and provides indication of low-voltage supply conditions. During the oper- ation, the following events cause a Reset:

• Power-On Reset (POR)
• Voltage Brown-Out (VBO) protection
• Watchdog Timer (WDT) time-out (when configured by the WDT_RES Flash option bit to initiate a Reset)
• External RESET pin assertion (when the alternate function, RESET, is enabled by the GPIO register)
• On-Chip Debugger initiated Reset (OCDCTL[0] set to 1) When the device is in Stop Mode, a Stop-Mode Recovery can be initiated by each of the following triggers:
• Watchdog Timer time-out
• GPIO Port input pin transition on an enabled Stop-Mode Recovery source
• Interrupt from a timer, comparator, Low Voltage Detection or RTC operating in Stop Mode The low-voltage detection circuitry on the device offers the following features:
• The low-voltage detection threshold level is user-defined
• It generates an interrupt when the supply voltage drops below a user-defined level 5.1. Reset Types The F6482 Series MCU provides multiple types of Reset operation. Stop-Mode Recovery is considered a form of Reset. Table 9 lists the types of Reset and their operating charac- teristics.

the Clock System chapter on page 96. port reset, after which the user code can reconfigure this pin as a general-purpose output. sion Oscillator (IPO) continues to function. Table 9. Reset, Stop-Mode Recovery Characteristics and Latency

cution begins at the Reset vector address. ble. Use software to wait until it is stable before using it as a clock source. Table 10 lists the possible sources of a System Reset. Table 10. System Reset Sources and Resulting Reset Type RESET pin assertion Reset de lay begins after RESET pin assertion. Characteristics chapter on page 601. Reset delay begins upon OCDCTL[0] set to 1. RESET pin assertion Reset de lay begins after RESET pin assertion. Characteristics chapter on page 601.

the supply voltage reaches a safe circuit operating level when the device is powered on. VDD must be greater than both VPOR and VVBO to exit the Reset state. age. Figure 8 on page 42 shows this POR behavior. After the F6482 Series MCU exits the POR state, the eZ8 CPU fetches the Reset vector. Following this POR, the POR/VBO status bit in the Reset Status Register is set to 1. Characteristics chapter on page 601. Figure 7. Power-On Reset Operation

1. Internal Reset and POR Reset are Low active.

acteristics chapter on page 601. subsequently controlled by VBOCTL upon exit from System Reset. Figure 8. Power-On Reset Behavior

set to signify that the reset was initiated by the WDT. Figure 9. Voltage Brown-Out Reset Operation Note: this figure is not to scale.

PS029413-0921 P R E L I M I N A R Y Stop-Mode Recovery Z8 Encore! XP® F6482 Series Product Specification through the System Reset sequence. Because of possible asynchronicity of the system clock and reset signals, the required reset duration can be as short as three clock periods and as long as four. A reset pulse three clock cycles in duration could trigger a Reset; a pulse four cycles in duration always triggers a Reset. While the RESET input pin is asserted Low, the F6482 Series MCU remains in the Reset state. If the RESET pin is held Low beyond the System Reset time-out, the device exits the Reset state on the system clock rising edge following RESET pin deassertion. Following a System Reset initiated by the external RESET pin, the EXT status bit in the RSTSTAT Register is set to 1. 5.2.5. External Reset Indicator During System Reset, or when enabled by the GPIO logic (see the Port A–J Control Reg- isters section on page 87), the RESET pin functions as an open-drain (active Low) reset mode indicator in addition to the input functionality. This Reset output feature allows the F6482 Series MCU to reset other components to which it is connected, even if that reset is caused by internal sources such as POR, VBO, or WDT events. After an internal Reset event occurs, the internal circuitry begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry until the appropriate delay (listed in Table 9 on page 39) has elapsed. 5.2.6. On-Chip Debugger Initiated Reset A POR can be initiated using the OCD by setting the RST bit in the OCD Control Regis- ter. The OCD block is not reset, but the remainder of the chip goes through a normal Sys- tem Reset. The RST bit automatically clears during the system reset. Following the System Reset the POR bit in the Reset Status Register is set. 5.3. Stop-Mode Recovery Stop Mode is entered by execution of a STOP instruction by the eZ8 CPU. For detailed Stop Mode information, see the Low-Power Modes section on page 50. Stop-Mode Recovery does not affect on-chip registers other than the Reset Status (RSTSTAT), Clock Control 0 (CLKCTL0), Clock Control 5 (CLKCTL5) and Interrupt Control (IRQCTL) registers. During Stop-Mode Recovery, the DCO is configured with the most recent DCO delay con- trol code, and is selected as System Clock with the FLL disabled. If the FLL or another system clock source is required, the Stop-Mode Recovery code must reconfigure the Clock System such that the desired system clock source is enabled and selected. To learn more, see the Clock System chapter on page 96.

PS029413-0921 P R E L I M I N A R Y Stop-Mode Recovery Z8 Encore! XP® F6482 Series Product Specification After a System Reset or Stop-Mode Recovery, an external crystal oscillator may become unstable. Use software to wait until it is stable before using this crystal as a clock source. The IPO, LFXO, or external clock drive, when enabled, can be configured to remain operating during Stop Mode (PCKSM = 1 in the CLKCTL1 Register) or to be nonoperating during Stop Mode (PCKSM = 0 in the CLKCTL1 Register). If enabled and configured to to be nonoperat- ing during Stop Mode, the clock source will become operational during Stop-Mode Recovery. The FLL is always disabled by entry into Stop Mode and, if required during Normal Opera- tion, must be enabled by software after Stop-Mode Recovery. Stop-Mode Recovery latency is a function of FRECOV in the Power Control Register 0 (PWRCTL0, see the Power Control Register Definitions section on page 52), If FRECOV is set, the Stop-Mode Recovery latency is 6 System Clock cycles. If FRECOV is cleared, the Stop-Mode Recovery latency is the Stop-Mode Recovery Delay plus 6 System Clock cycles. To learn more, see Stop-Mode Recovery Delay in the Electrical Characteristics chapter on page 601. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002h and 0003h and loads that value into the Program Counter. Program execution begins at the Reset vec- tor address. Following Stop-Mode Recovery, the STOP bit in the Reset Status Register is set to 1 and the IRQE bit in the IRQCTL Register is cleared disabling interrupts. Software can enable interrupts by setting the IRQE bit or by issuing the EI instruction. Interrupt capable peripherals running in Stop Mode can initiate a Stop-Mode Recovery only if enabled as an interrupt source. Table 11 lists the Stop-Mode Recovery sources and result- ing actions. The text following provides more information about each of the Stop-Mode Recovery sources. Note:

lowed by a call of the desired WDT interrupt code. CPU services the corresponding interrupt request. Table 11. Stop-Mode Recovery Sources and Resulting Action

PS029413-0921 P R E L I M I N A R Y Low-Voltage Detection Z8 Encore! XP® F6482 Series Product Specification 5.3.3. Stop-Mode Recovery Using GPIO Port Pin Transition Many of the GPIO Port pins can be configured as a Stop-Mode Recovery input source. Which GPIO can be configured as a Stop-Mode Recovery input source is described in the General-Purpose Input/Output chapter on page 55. On any GPIO pin enabled as a Stop- Mode Recovery source, a change in the input pin value (from High to Low or from Low to High) initiates Stop-Mode Recovery. In the Reset Status Register, the STOP bit is set to 1. If the GPIO is also configured as an interrupt source, an interrupt will occur once inter- rupts are reenabled. In Stop Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input Data registers record the Port transition only if the signal stays on the Port pin until the end of the Stop-Mode Recovery delay. As a result, short pulses on the Port pin can ini- tiate Stop-Mode Recovery without being written to the Port Input Data Register or with- out initiating an interrupt (if enabled for that pin). 5.3.4. Stop-Mode Recovery Using External RESET Pin When the F6482 Series MCU is in Stop Mode and the external RESET pin is driven Low, a System Reset occurs. Because of a glitch filter operating on the RESET pin, the Low pulse must be greater than the minimum width specified, or it is ignored. For details, see the Electrical Characteristics chapter on page 601. 5.4. Low-Voltage Detection In addition to the VBO Reset described earlier, it is also possible to generate an interrupt when the supply voltage drops below a user-selected value. To learn more about the avail- able Low-V oltage Detection (LVD) threshold levels, see the Flash Option Bits chapter on page 542. When the supply voltage drops below the LVD threshold, the LVD bit of the RSTSTAT Register is set to 1. This bit remains 1 until the low-voltage condition elapses. Reading or writing this bit does not clear it. The LVD circuit can also generate an interrupt when enabled; see the Interrupt Controller chapter on page 127. The LVD is not latched, so enabling the interrupt is the only way to guarantee detection of a transient low-voltage event. The LVD circuit is either enabled or disabled by the Power Control Register bit 4. To learn more, see the Power Control Register Definitions section on page 52. Caution:

time-out. Reading this register resets the upper 4 bits to 0. Table 12. Reset Status Register (RSTSTAT) out or Stop-Mode Recovery occurs. This bit is also reset to 0 when the register is read. register also resets this bit. register resets this bit. This read must occur to clear the WDT interrupt. These bits are reserved and must be programmed to 000. threshold. This value is not latched but is a real-time indicator of the supply voltage level.

Table 13. Reset Status Per Event

PS029413-0921 P R E L I M I N A R Y Low-Power Modes Z8 Encore! XP® F6482 Series Product Specification Chapter 6. Low-Power Modes The F6482 Series products have power-saving features. The highest level of power reduc- tion is provided by the Stop Mode. The next lower level of power reduction is provided by the Halt Mode. Further power savings can be implemented by disabling individual peripheral blocks while in Normal Mode. 6.1. Stop Mode Executing the eZ8 CPU’s Stop instruction places the device into Stop Mode. In Stop Mode, the operating characteristics are:

• IRQE in the IRQCTL Register is cleared.
• The High Frequency Crystal Oscillator (HFXO) is stopped and the Phase Locked Loop (PLL) is disabled (PLLEN is cleared); XIN and XOUT (if previously enabled) are dis- abled and PA0/PA1 reverts to the states programmed by the GPIO registers.
• The FLL is disabled (FLLEN is cleared) and the DCO is stopped; upon recovering from Stop Mode, the FLL remains disabled and the DCO is enabled, see the Clock System chapter on page 96 to learn more.
• If enabled and selected as the Peripheral Clock (PCKSEL in the Clock Control 1 Reg- ister), a PCLK source can be configured to operate in Stop Mode, as follows: – Internal Precision Oscillator (IPO): PCKSM = 1 in the Clock Control 1 Register and FRECOV = 1 in the Power Control 0 Register – Low Frequency Crystal Oscillator (LFXO): PCKSM = 1 in the Clock Control 1 Register – External clock drive: PCKSM = 1 in the Clock Control 1 Register
• If enabled, the RTC continues to operate with the selected RTC clock source.
• System Clock is stopped.
• eZ8 CPU is stopped.
• Program counter (PC) stops incrementing.
• If enabled, the Watchdog Timer (WDT) logic continues operating.
• If enabled for operation in Stop Mode, the Timer logic continues to operate with the selected Timer clock source.

PS029413-0921 P R E L I M I N A R Y Halt Mode Z8 Encore! XP® F6482 Series Product Specification

• If enabled for operation in Stop Mode by the associated Flash option bits, the VBO pro- tection circuit continues operating; the LVD circuit continues to operate if enabled by the Power Control Register 0.
• Operational Amplifiers, comparators, and Temperature Sensor continue to operate if both enabled by the Power Control Register 0 and FRECOV = 1.
• LCD continue to operate if enabled by the Power Control Register 0.
• All other on-chip peripherals are idle. To minimize current in Stop Mode, all GPIO pins which are configured as digital inputs must be driven to one of the supply rails (VDD or GND). The device is brought out of Stop Mode using Stop-Mode Recovery. To learn more about Stop-Mode Recovery, see the Reset, Stop-Mode Recovery and Low-V oltage Detection chapter on page 38. 6.2. Halt Mode Executing the eZ8 CPU’s Halt instruction places the device into Halt Mode. In Halt Mode, the operating characteristics are:
• Any enabled crystal oscillator continues to operate
• System clock is enabled and continues to operate
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• If enabled, the WDT continues to operate
• All other on-chip peripherals continue to operate The eZ8 CPU can be brought out of Halt Mode by any of the following operations:
• Interrupt
• Watchdog Timer time-out (Interrupt or Reset)
• Power-On Reset
• Voltage Brown-Out Reset
• External RESET pin assertion To minimize current in Halt Mode, all GPIO pins which are configured as inputs must be driven to one of the supply rails (VDD or GND).

the F6482 Series devices. Disabling a given peripheral minimizes its power consumption. clock input or by removing power from the block. disable it. Failure to perform this task results in Stop Mode currents greater than specified. Table 14. Power Control Register 0 (PWRCTL0) 1 = Op Amp B is enabled (this applies even in Stop Mode if FRECOV = 1). 1 = Op Amp A is enabled (this applies even in Stop Mode if FRECOV = 1). 1 = LCD is enabled (this applies even in Stop Mode).

PS029413-0921 P R E L I M I N A R Y Power Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification [4] LVD Low-Voltage Detection Enable 0 = LVD disabled. 1 = LVD enabled (this applies even in Stop Mode). [3] TEMP Temperature Sensor Enable 0 = Temperature Sensor disabled. 1 = Temperature Sensor enabled (this applies even in Stop Mode if FRECOV = 1). [2] FRECOV Fast Recovery 0 = Fast Recovery disabled. 1 = Fast Recovery enabled. Fast Recovery provides for the shortest Stop-Mode recovery latency at the expense of higher Stop Mode current consumption. See the Reset, Stop-Mode Recovery and Low- Voltage Detection chapter on page 38 to learn more. In addition, this bit must be set for certain peripherals to remain active during Stop Mode as described in this chapter. [1] COMP0 Comparator 0 Enable 0 = Comparator 0 is disabled. 1 = Comparator 0 is enabled (this applies even in Stop Mode if FRECOV = 1). [0] COMP1 Comparator 1 Enable 0 = Comparator 1 is disabled). 1 = Comparator 1 is enabled (this applies even in Stop Mode if FRECOV = 1). Bit Description (Continued)

Table 15. Power Control Register 1 (PWRCTL1) This bit is reserved and must be programmed to 0. TWAKE_ADC, is incurred prior to the conversion starting. This bit is reserved and must be programmed to 0.

port pin is individually programmable. Table 16 lists the port pins available with each device and package type. Table 16. Port Availability by Device and Package Type

PS029413-0921 P R E L I M I N A R Y Shared Reset Pin Z8 Encore! XP® F6482 Series Product Specification The crystal oscillator and the 32 kHz secondary oscillator functionalities are not controlled by the GPIO block. When the crystal oscillator or the 32 kHz secondary oscillator is enabled in the clock system block, the GPIO functionality of PA0 and PA1, or PA2 and PA3, is overridden. In such a case, those pins function as input and output for the crystal oscillator. 7.4. Shared Reset Pin On all devices, the Port D0 pin shares a function with a bidirectional reset pin. Unlike all other I/O pins, this pin does not default to GPIO pin on power-up. This pin acts as a bidi- rectional, open-drain reset with pull-up until user software reconfigures it. The Port D0 pin is output-only when in GPIO Mode and does not function as a Stop-Mode Recovery source. 7.5. High Frequency Crystal Oscillator Override For systems using the High Frequency Crystal Oscillator (HFXO), PA0 and PA1 are used to connect the crystal. When the HFXO is enabled, the GPIO settings are overridden and PA0 and PA1 is disabled; see the Clock Control 2 Register (CLKCTL2) on page 117. 7.6. Low Frequency Crystal Oscillator Override For systems using the Low Frequency Crystal Oscillator (LFXO), PA2 and PA3 are used to connect a watch crystal. When the LFXO is enabled, the GPIO settings are overridden and PA2 and PA3 is disabled; see the Clock Control 1 Register (CLKCTL1) on page 116. 7.7. External Clock Setup For systems using an external TTL drive, PA0 is the clock source for the PLL and the sys- tem clock selection multiplexer, and PA2 is the clock source for PCLK. For systems using an external clock drive of the PLL and a system clock source multiplexer, configure PA0 for alternate function CLKIN and write to the Clock Control C Register (CLKCTLC) (see Table 50 on page 126) to select the External Clock Drive. For systems using an external clock drive for PCLK, configure PA2 for alternate function CLK2IN and write the Clock Control 1 Register (see page 116) to select the External Clock Drive.

through 21 indicate the port alternate function mapping. Table 17. Port Alternate Function Mapping, 32-Pin Parts

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

Table 17. Port Alternate Function Mapping, 32-Pin Parts (Continued)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1 PD0 RESET External Reset AFS1[0]: 0

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

Table 18. Port Alternate Function Mapping (44-Pin Parts)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

Table 18. Port Alternate Function Mapping (44-Pin Parts) (Continued)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D and E, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

Table 19. Port Alternate Function Mapping (Z8Fxx81 64-Pin Parts)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E and F, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

Table 19. Port Alternate Function Mapping (Z8Fxx81 64-Pin Parts) (Continued)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E and F, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E and F, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E and F, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E and F, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E and F, the Alternate

Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

Table 20. Port Alternate Function Mapping (Z8Fxx82 64-Pin Parts)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, F, G and H, the Alter-

the Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there is only a single alternate function for each Port J pin, the Alternate Function Set registers are not

Subregisters (see page 88 ), must also be enabled.

Table 20. Port Alternate Function Mapping (Z8Fxx82 64-Pin Parts) (Continued)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, F, G and H, the Alter-

the Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there is only a single alternate function for each Port J pin, the Alternate Function Set registers are not

Subregisters (see page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, F, G and H, the Alter-

the Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there is only a single alternate function for each Port J pin, the Alternate Function Set registers are not

Subregisters (see page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, F, G and H, the Alter-

the Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there is only a single alternate function for each Port J pin, the Alternate Function Set registers are not

Subregisters (see page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, F, G and H, the Alter-

the Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there is only a single alternate function for each Port J pin, the Alternate Function Set registers are not

Subregisters (see page 88 ), must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, F, G and H, the Alter-

the Port A–J Alternate Function Subregisters (see page 88 ), must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ), must also be enabled.

1. Because there is only a single alternate function for each Port J pin, the Alternate Function Set registers are not

Subregisters (see page 88 ), must also be enabled.

Table 21. Port Alternate Function Mapping, 80-Pin Parts

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

Table 21. Port Alternate Function Mapping, 80-Pin Parts (Continued)

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

rupt Controller chapter on page 127. Four registers for each port provide access to GPIO control, input data, and output data. to provide access to their subregisters for port configuration and control. Table 22. GPIO Port Registers and Subregisters

1. Because there are at most two choices of alternate function for some pins of Ports A, B, D, E, F and G, the Alter-

Port A–J Alternate Function Subregisters (see page 88 ) must also be enabled.

1. The alternate function selection for Port C, as described in the Port A–J Alternate Function Subregisters (see

page 88 ) must also be enabled.

1. Because there is only a single alternate function for each pin in ports H and J, the Alternate Function Set subreg-

Alternate Function Subregisters (see page 88 ) must also be enabled.

vide access to all GPIO Port controls, see Table 23. Table 23. Port A–J GPIO Address Registers (PxADDR) 00h: No function; provides some protection against accidental port reconfiguration. 03h: Output Control (Open-Drain). 05h: Stop-Mode Recovery Source Enable. 07h: Alternate Function Set 1. 08h: Alternate Function Set 2. Table 22. GPIO Port Registers and Subregisters (Continued)

or written to by a Port A–J Control Register transaction. A–J Control Register by writing 01h to the Port A–J Address Register. Table 24. Port A–J Control Registers (PxCTL) Table 25. Port A–J Data Direction Subregisters (PxDD) overrides the Data Direction Register setting. 0: Output. Data in the Port A–J Output Data Register is driven onto the port pin. 1: Input. The port pin is sampled and the value written into the Port A–J Input Data Register. The output driver is tristated.

1 Subregisters section on page 92 and the Alternate function selection on the port pins

port pin, see the GPIO Alternate Functions section on page 56. alternate function. Failure to follow this guideline results in unpredictable operation. Table 26. Port A–J Alternate Function Subregisters (PxAF) determines the direction of the pin. 1 : The alternate function selected through Alternate Function set subregisters are enabled. Port pin operation is controlled by the alternate function.

affects the pins directly and, as a result, alternate functions are also affected. Table 27. Port A–J Output Control Subregisters (PxOC) The drains are enabled for any output mode (unless overridden by the alternate function). 1 : The drain of the associated pin is disabled (open-drain mode). Table 28. Port A–J High Drive Enable Subregisters (PxHDE) 0: The port pin is configured for standard output current drive. 1: The port pin is configured for high output current drive.

Table 29. Port A–G Stop-Mode Recovery Source Enable Subregisters (PxSMRE) during Stop Mode do not initiate a Stop-Mode Recovery. pin during Stop Mode initiates a Stop-Mode Recovery. Note: PortD0/RESET does not function as a Stop-Mode Recovery source.

Table 30. Port A–J Pull-Up Enable Subregisters (PxPUE) 0: The weak pull-up on the port pin is disabled. 1: The weak pull-up on the port pin is enabled.

through the Port A–G Control Register by writing 07h to the Port A–G Address Register. the GPIO Alternate Functions section on page 56. A–J Alternate Function Subregisters section on page 88. Table 31. Port A–G Alternate Function Set 1 Subregisters (PxAFS1) Alternate Functions section on page 56. Alternate Functions section on page 56.

through 21 in the GPIO Alternate Functions section on page 56. Alternate Function Subregisters section on page 88. Table 32. Port C Alternate Function Set 2 Subregisters (PxAFS2) Alternate Functions section on page 56. Alternate Functions section on page 56.

values from the corresponding port pins. The Port A–J Input Data registers are read-only. packages other than the 80-pin package. Table 33. Port A–J Input Data Registers (PxIN) Sampled data from the corresponding port pin input. 0: Input data is logical 0 (Low). 1: Input data is logical 1 (High).

Table 34. Port A–J Output Data Register (PxOUT) the corresponding Port Output Control Register bit to 1.

PS029413-0921 P R E L I M I N A R Y Clock System Z8 Encore! XP® F6482 Series Product Specification Chapter 8. Clock System The F6482 Series devices use seven possible clock sources, each user-selectable:

• On-chip Internal Precision Oscillator (IPO)
• On-chip Digitally Controlled Oscillator (DCO)
• On-chip High Frequency Crystal Oscillator (HFXO) using off-chip crystal or resonator
• On-chip Low Frequency Crystal Oscillator (LFXO) using off-chip crystal
• Two external clock drives
• On-chip Watchdog Timer Oscillator (WTO) Two internal clock multiplication systems are available:
• An on-chip Frequency Locked Loop (FLL) which locks the DCO to Peripheral Clock (PCLK, an internal clock)
• An on-chip Phase Locked Loop (PLL) which can clock the USB and/or source System Clock and locks to either the HFXO or external clock drive Four internal clocks exist and are configured to the clock sources as follows:
• System Clock (SYSCLK) is the clock input to the CPU as well as other system func- tions. The five possible clock sources for System Clock are: – Peripheral Clock (PCLK), a derived clock – DCO which can be locked to PCLK using the FLL – HFXO or External clock drive (based on PLL clock source select) – PLL clock sourced by the HFXO or external clock drive – WTO
• Peripheral Clock (PCLK) is the 32.768 kHz clock input to the DCO and can be selected to clock certain peripherals. The three possible clock sources for PCLK are: – IPO – LFXO – External clock 2 drive
• The WTO is the clock input to the Watchdog Timer (WDT) and can be selected to clock certain peripherals

PS029413-0921 P R E L I M I N A R Y Architecture Z8 Encore! XP® F6482 Series Product Specification

• The PLL Clock (PLLCLK) is driven by the on-chip PLL and it can clock the USB and/ or System Clock. The two possible sources for the PLL are: – HFXO – External clock drive In addition, F6482 Series devices contain:
• A clock failure detection and recovery circuitry allowing continued operation despite a failure of the System Clock source
• A clock failure detection circuitry allowing detection of a failure of the Watchdog Tim- er Oscillator (WTO)
• A divider circuit to reduce the frequency of the selected System Clock source. The di- vider selection can be altered dynamically to quickly increase or decrease System Clock frequency to manage performance and power consumption 8.1. Architecture This chapter discusses the oscillator control system including clock sources such as oscil- lators, clock multiplication, selection of clock sources for internal clocks and oscillator failure detection. A diagram of the oscillator control system is shown in Figure 11.

Clock sources can be selected for System Clock, Peripheral Clock, and PLL Clock. Figure 11. Clock System Block Diagram

Table 35. System Clock Configuration and Selection

• Frequency range 1–24MHz
• No external components required
• Unlock the Clock Control registers and configure the DCO
• Switch System Clock sources as described in the System Clock Source Switching section on page 100 Running with FLL
• Performs clock multiplication
• Frequency range 1–24 MHz
• Accuracy 0.25% (vs. PCLK)
• No external components required
• Unlock the Clock Control registers
• Configure Peripheral Clock (PCLK)
• Configure the FLL
• Switch System Clock sources as described in the System Clock Source Switching section on page 100 Peripheral Clock • See Table 36 on page 101 • Unlock the Cloc k Control registers and configure Peripheral Clock (PCLK)
• Switch System Clock sources as described in the System Clock Source Switching section on page 100 High Frequency Crystal/Oscillator (HFXO)
• 1MHz to 24 MHz
• Very high accuracy (dependent on crystal or resonator used)
• External components required
• Unlock the Clock Control registers and configure the HFXO control bits for correct external oscillator mode
• Switch System Clock sources as described in the System Clock Source Switching section on page 100 External Clock Drive
• 0 to 24 MHz
• Accuracy dependent on external clock source
• Unlock the Clock Control registers and configure the HFXOBAND for correct external clock drive frequency
• Write GPIO registers to configure PA0 pin for external clock function, CLKIN
• Apply external clock signal to GPIO
• Switch System Clock sources as described in the System Clock Source Switching section on page 100

control block employs a register unlocking/locking scheme.

1. Unlock the clock control registers.
2. Write to the appropriate clock control registers to configure the desired clock source.
3. Enable the desired clock source.
4. Wait for the newly enabled cl ock source to stabilize by polling the appropriate ready
5. Write CLKCTL0 to select System Clock. The byte written to CLK CTL0 should have

CSTAT set if it desired to leave the system clock registers unlocked.

1. After the System Clock source has been switched, disable any unnecessary clock
2. The clock control registers can be locked by clearing CSTAT.

• 10 to 48 MHz
• Performs clock multiplication
• Very high accuracy (dependent on clock source used)
• External components if using HFXO as clock source
• Enable the desired PLL clock source and wait until it is ready
• Unlock the Clock Control registers and configure the PLL
• Switch System Clock sources as described in the System Clock Source Switching section on page 100 Internal WDT Oscillator (WTO)
• 10 kHz nominal
• ± 40% accuracy; no external components required
• Low power consumption
• Switch System Clock sources as described in the System Clock Source Switching section on page 100

Table 35. System Clock Configuration and Selection (Continued)

Clock frequency to manage performance and power consumption. peripheral that is clocked by PCLK. Table 36 summarizes peripheral clock sources and usage. Table 36. Peripheral Clock Sources and Usage

• Optimized for use with a 32.768 kHz Watch Crystal
• Very high accuracy
• Dedicated XTAL pins
• External components required
• Unlock the Clock Control registers
• Enable the LFXO
• Switch System Clock sources as described in the PCLK Source Switching section on page 102
• Select PCLK as the clock source for any desired peripheral(s) in the appropriate peripheral control register(s)

1. Unlock the clock control registers.
2. Write to the appropriate clock control registers to configure the desired clock source.
3. Enable the desired clock source.
4. Wait for the newly enabled clock source to stabilize.
5. Write CLKCTL1 to select PCLK.
6. After the System Clock source has been switched, disable any unnecessary clock
7. The clock control registers can be locked by clearing CSTAT.

PLL are the High Frequency Crystal Oscillator (HFXO) and the External Clock Drive.

• 32.768 kHz nominal
• ± 2% accuracy with factory trim
• No external components required
• Unlock the Clock Control registers
• Enable the IPO
• Switch System Clock sources as described in the PCLK Source Switching section on page 102
• Select PCLK as the clock source for any desired peripheral(s) in the appropriate peripheral control register(s) External Clock 2 Drive • 32.768 kHz when used as PCLK source
• Accuracy dependent on external clock source
• Write GPIO registers to configure PA2 pin for external clock function, CLK2IN
• Apply external clock signal to GPIO
• Unlock the Clock Control registers
• Switch System Clock sources as described in the PCLK Source Switching section on page 102
• Select PCLK as the clock source for any desired peripheral(s) in the appropriate peripheral control register(s)

PS029413-0921 P R E L I M I N A R Y Clock Failure Detection and Recovery Z8 Encore! XP® F6482 Series Product Specification 103 Clock source selection is performed with PLLSEL and the source selected by PLLSEL is available both to the PLL and as a System Clock source selectable using SCKSEL. The PLL should be enabled only when the selected clock source is ready. When using the USB, the PLL must be enabled to provide a 48 MHz clock to the USB. 8.2.4. Clock System Control R egister Unlocking/Locking Before writing a clock system control register (CLKCTLx), the clock control registers must be unlocked by making two writes to the CLKCTL0 Register with the value E7h fol- lowed by the value 18h. Successful unlocking sets CSTAT. When unlocked, one or more CLKCTLx registers can be written. The clock control registers can be again locked by clearing CSTAT in CLKCTL0. Any other sequence of clock system control register writes has no effect. The values written to unlock the register must be ordered correctly, but are not necessarily consecutive. It is possible to write to or read from other registers within the unlocking/locking operation. To remain unlocked when writing CLKCTL0, the byte writ- ten to CLKCTL0 must have CSTAT set. Before writing the unlock sequence, check that CSTAT is cleared. If the unlock sequence is written while CSTAT is set, the CLKCTL0 Register will be loaded with the unlock sequence values. When selecting a new clock source, the System Clock failure detection circuitry and the Watchdog Timer oscillator failure circuitry must be disabled. If SCKFEN and WTOFEN are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a failure of either oscillator. The Failure detection circuitry can be enabled anytime after a successful write of SCKSEL in the CLKCTL0 Register. 8.3. Clock Failure Detection and Recovery Clock failure detection and recovery features are provided for the System Clock. A clock failure detection feature is provided for the Watchdog Timer oscillator. 8.3.1. System Clock Failure The F6482 Series devices can generate nonmaskable interrupt-like events when the Sys- tem Clock source fails. To maintain system function in this situation, when SCKFEN=1, the clock failure recovery circuitry automatically forces the Watchdog Timer Oscillator (WTO) to drive System Clock. The WTO is enabled automatically to allow the recovery. Although this oscillator runs at a much slower speed than the original system clock, the CPU continues to operate allowing execution of a clock failure vector and software rou- Note:

PS029413-0921 P R E L I M I N A R Y High Frequency Crystal Oscillator Z8 Encore! XP® F6482 Series Product Specification 104 tines that either remedy the oscillator failure or issue a failure alert. This automatic switch- over is not available if WTO is the System Clock source. The System Clock source failure detection circuitry asserts if the System Clock frequency drops below 1 kHz ±50%. If an external signal is selected as the System Clock source, it is possible that a very slow but nonfailing clock can generate a failure condition. Under these conditions, do not enable the System Clock failure circuitry (SCKFEN should be cleared). 8.3.2. Watchdog Timer Failure In the event of a Watchdog Timer Oscillator (WTO) failure, a similar nonmaskable inter- rupt-like event is issued. This event does not trigger an attendant clock switch-over, but alerts the CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a System Clock failure. The failure detection circuitry does not function if the Watchdog Timer is used as the System Clock. In this case, it is necessary to disable the detection circuitry by clearing WTOFEN. The WTO failure-detection circuit counts system clocks while looking for a Watchdog Timer clock. The logic counts 8004 system clock cycles before determining that a failure has occurred. The system clock rate determines the speed at which the Watchdog Timer failure can be detected. A very slow system clock results in very slow detection times. 8.4. High Frequency Crystal Oscillator The products in the F6482 Series contain an on-chip High Frequency Crystal Oscillator (HFXO) for use with external crystals with 1 MHz to 24 MHz frequencies. HFXO features include:

• Optimized for low current consumption
• Selectable as System Clock
• Selectable as the PLL reference clock, which in turn, can generate System Clock and/ or generate clocking for the USB Alternatively, the XIN input pin can also accept a 1 MHz–24MHz CMOS-level clock input signal. If an external clock generator is used, the XOUT pin must be left unconnected. Although the XIN pin can be used as an main system clock input for an external clock gener- ator, configuring PA0 as CLKIN is better suited for such use. To learn more, see the System Clock Selection section on page 98). Note:

PS029413-0921 P R E L I M I N A R Y High Frequency Crystal Oscillator Z8 Encore! XP® F6482 Series Product Specification 105 8.4.1. Operating Modes The HFXO and external clock drive support three frequency bands:

• Low gain for use with medium frequency crystals, ceramic resonators or external clock drive (1 MHz to 8 MHz)
• Medium gain for use with medium frequency crystals, ceramic resonators or external clock drive (> 8 MHz to 16 MHz)
• Maximum gain for use with high-frequency crystals or external clock drive (> 16 MHz to 24 MHz) The HFXO and external clock drive band is selected using HXFOBAND in the CLKCTL2 Register. 8.4.2. HFXO Operation HFXOEN in the CLKCTL2 Register controls whether the HFXO is enabled. During System Reset, HFXOEN is cleared, disabling the HFXO. When user code sets HFXOEN to enable the crystal oscillator, it should also check that the HFXO is stable, by reading HFXORDY , before using it as the PLL clock source or selecting the HFXO as System Clock. HFXORDY is cleared when the HFXO is disabled. Figure 12 shows a recommended configuration for connection with external load capaci- tors and a fundamental-mode, parallel-resonant crystal operating. See the Electrical Char- acteristics chapter on page 601 for additional details regarding the characteristics of the HFXO. Printed circuit board layout should minimize crystal pin parasitic capacitance.

• On-chip RC oscillator that does not require external components
• Elimination of crystals in applications for which high timing accuracy is not required
• 32.768 kHz nominal frequency
• Accuracy: ± 2% over operational temperature and voltage range 8.6.1. Operation IPOEN in the CLKCTL1 Register controls whether the IPO is enabled. During System Reset, IPOEN is set, enabling the IPO. If the IPO is disabled, user code can set IPOEN to enable the IPO, it should also check that the IPO is stable, by reading IPORDY , before selecting the IPO as PCLK. The IPO is an RC relaxation oscillator that offers low sensitivity to power supply and tem- perature variation. At System Reset, the IPO is enabled and selected as PCLK which, in turn, is selected as input to the FLL. If the IPO is not required, it can be disabled by clear- ing IPOEN in CLKCTL1 to reduce system power consumption.

Figure 13. Recommended 32.768 kHz Crystal Oscillator Configuration

PS029413-0921 P R E L I M I N A R Y Watchdog Timer Oscillator Z8 Encore! XP® F6482 Series Product Specification 108 8.7. Watchdog Timer Oscillator The Watchdog Timer Oscillator (WTO) can be selected as System Clock, the clock source for several peripheral, and is the clock source for the Watchdog Timer.The WTO is auto- matically enabled whenever it is needed. 8.8. Digitally Controlled Oscillator The Digitally Controlled Oscillator (DCO) can be selected as System Clock and can be adjusted to oscillate over a wide frequency range. DCO features include:

• Can be locked to PCLK using the FLL or can free run
• When free running, the oscillation frequency is adjusted via the DCO control words, DCOCTLH and DCOCTLL
• When using the FLL, the DCO is locked to a multiple of PCLK determined by FLLN- DIVL and FLLNDIVH
• When locked, the FLL can remain enabled so that the DCO control words continue to converge, tracking any changes in operating conditions, or the FLL can be disabled to free run with the current DCO control words
• The converged DCO control words can be saved for later use in rapid frequency chang- ing 8.8.1. Operating Modes The DCO supports two operating modes:
• Free running (FLLEN = 0 in CLKCTL5)
• Locked to PCLK using the FLL (FLLEN = 1 in CLKCTL5) 8.8.2. DCO Operation DCOEN in the CLKCTL5 Register controls whether the DCO is enabled. During System Reset, DCOEN is set, enabling the DCO. After setting DCOEN to enable the DCO, the DCO will oscillate at a frequency determined by the DCO control words as well as device characteristics and operating conditions. A particular set of DCO control words may not provide exactly the same oscillation frequency on all units, or at differing operating condi- tions for any particular unit. To achieve a desired DCO operating frequency, the appropriate control word values for a particular unit at its current operating conditions can be determined by enabling the FLL to lock the DCO to PCLK. FLLRDY will be set after the convergence of the DCO control words is completed. The FLL can remain enabled so that the DCO control words continue

PS029413-0921 P R E L I M I N A R Y Frequency Locked Loop Z8 Encore! XP® F6482 Series Product Specification 109 to converge to track any changes in operating conditions, or the FLL can be disabled to run with the current DCO control words. The converged DCO control words, DCOCTLCL and DCOCTLCH, for a particular fre- quency can be saved for later use in rapid frequency changes by writing the saved values to the DCO control words, DCOCTLL and DCOCTLH. While the FLL is disabled (FLLEN = 0), to rapidly switch the DCO from its current frequency to a previously saved, converged frequency, observe the following procedure: 1. Set SEEDSEL=1 so that the DCO responds to the DCOCTLL/DCOCTLH registers. 2. Write the value stored from DCO CTLCL to DCOCTLL. The new DCOCTLL value will not be applied to the DCO until DCOCTLH is written 3. Write the value stored from DCOCTLCH to DCOCTLH. Writing DCOC TLH applies both DCOCTLL and DCOCTLH to the DCO. To learn more about changing DCO frequency while the FLL is enabled, see the Fre- quency Locked Loop section on page 109. Use caution when free running the DCO, as changes to operating temperature and operat- ing voltage can result in a DCO frequency that differs from the frequency at the time the DCO control word values were converged. 8.9. Frequency Locked Loop The Frequency Locked Loop (FLL) is used to lock the DCO to a frequency multiple of PCLK. FLL features include:

• Converges DCO control words to achieve frequency lock
• Employs both fast locking and linear locking algorithms
• Locks with or without stored values (seed) for the DCO control words 8.9.1. Operating Modes The FLL supports two locking modes:
• A fast locking algorithm is initiated when FLLDIVH is written and SEEDSEL = 0. It is well-suited to locking without initial values (seed) for the DCO control words. The fast locking algorithm is also initiated automatically during a System Reset.
• A linear locking algorithm is initiated when FLLDIVH is written and SEEDSEL = 1. It is well-suited to locking to available values (seed) for the DCO control words. The linear locking algorithm is also initiated whenever FLLEN is set.

diagram of the FLL with connections to the DCO is shown in Figure 14.

• If there are no desired stored values for the DCO control words, and if any previous fast lock activity is completed, new DCO control word values can be converged using a fast locking algorithm. To initiate the fast locking algorithm, observe the following proce- dure: a. Set SEEDSEL = 0 to indicate that the existing DCO control words should not be used during the locking process. Also set FLLEN = 1.

Figure 14. FLL Block Diagram

PS029413-0921 P R E L I M I N A R Y Frequency Locked Loop Z8 Encore! XP® F6482 Series Product Specification 111 b. Write FLLNDIVL with the least significant byte of the desired frequency divisor. c. Write FLLNDIVH with the most si gnificant byte of the desired frequency divisor. Writing to FLLNDIVH will trigger the fast locking algorithm.

• If stored values for the DCO control words are available, They can be used to seed FLL convergence using a linear locking algorithm. To initiate the linear locking algorithm, observe the following procedure: a. Set SEEDSEL = 1 to indicate that loaded values for the DCO co ntrol words should be used during the locking process. Also set FLLEN = 1. b. Write the value stored from DCOCTLCL to DCOCTLL. c. Write the value stored fr om DCOCTLCH to DCOCTLH. d. Write FLLNDIVL with the least significant byte of the desired frequency divisor. e. Write FLLNDIVH with the most si gnificant byte of the desired frequency divisor. Writing to FLLNDIVH will trigger the linear locking algorithm. Three bits, FLLRDY , FLLLL, and FLADONE, are provided in the CLKCTL5 Register to describe the FLL status. When the FLL has achieved lock status, FLLRDY is set. If the FLL loses lock status, FLLLL is set, and FLLRDY is cleared. If the FLL is disabled, both FLLRDY and FLLLL are cleared. If the lock is lost while the FLL is enabled, a system clock fail trap occurs if the FLLIRQE bit in the CLKCTL5 Register is set. The FLADONE bit is set when the fast locking algorithm has completed. The setting of the FLLRDY bit precedes the setting of FLADONE. The fast locking algorithm should not be interrupted by entering Stop Mode, clearing the FLLEN bit, or by changing the FLL divider value. After the fast locking algorithm has been initiated, always check to determine that it has completed (as evidenced by FLADONE = 1) before entering Stop Mode, clearing the FLLEN bit, or by changing the FLL divider value. The fast locking algorithm is always initiated automatically during System Reset. While the FLL is enabled, it continues to converge the DCO control codes, as required, to maintain frequency lock. Although the DCO has fine resolution, the resolution is finite and the FLL operation can result in dithering between two values of the DCO control words. If such dither is undesirable, the FLL can be disabled for dither-free operation and enabled periodically to again converge the DCO control words and therefore account for environmental changes. Upon being enabled, the FLL will converge the DCO control words based on the divisor values in FLLNDIVL and FLLNDIVH, achieve lock using the linear algorithm, and set FLLRDY . Immediately after Stop-Mode Recovery, the DCO is enabled and operates with the DCO control words existing upon entry into Stop Mode. In addition, the FLL is disabled and Note:

lock using the linear algorithm. When locked, FLLRDY will be set.

• Fully integrated PLL
• Programmable input, feedback and output dividers
• Provides an accurate, low jitter clock suitable for USB applications
• PLL ready flag 8.10.1. Operation The PLL consists of an input clock multiplexer, a 4-bit reference divider, the PLL core including a V oltage Controlled Oscillator (VCO), a 3-bit output divider and a 8-bit feed- back divider. A block diagram of the PLL is shown in Figure 15. PLLEN in the CLKCTLC Register controls whether the PLL is enabled. During System Reset, PLLEN is cleared, disabling the PLL. Before setting PLLEN to enable the PLL, user software should check that the PLL clock source is stable. Prior to enabling the USB or selecting the PLL as a system clock, user software should check that the PLL is ready by reading PLLRDY . The input clock selection is controlled by PLLSEL in CLKCTLC which can select either the HXFO or External Clock Drive as input to the 4-bit reference divider that ultimately provides the reference clock input to the PLL core. The reference divider prescales the input clock and is controlled by PLLRDIV in CLKCTLB.

Figure 15. PLL Block Diagram

• PLLCLKIN: 0.3125 MHz–24 MHz
• Reference divider output frequency (PLL core input clock): 0.3125–24 MHz, 1.5 MHz – the recommended minimum for when clocking the USB
• PLL VCO frequency (input to output divider): 80 MHz–384 MHz
• PLLCLK (PLL output): 48 MHz max. If PLLCLK is >25 MHz and is selected as the source for System Clock, SCKDIV must be configured such that System Clock does not exceed 24 MHz. Table 37 lists common PLL configurations to generate a 48 MHz PLLCLK for the USB that satisfy the 2500 ppm data rate requirement. PLLCLK = PLLCLKIN x (PLLNDIV+1) (PLLRDIV +1) (PLLODIV+1)

Table 37. Common PLL Configurations for 48 MHz PLLCLK

CLKCTLA and CLKCTLB only when the PLL is disabled. Clock, Peripheral Clock, and PLL clock. Table 37. Common PLL Configurations for 48 MHz PLLCLK (Continued)

Clock System Control Register Unlocking/Locking section on page 103. Table 38. Clock Control 0 Register (CLKCTL0) Note: *SMR = Effect of Stop-Mode Recovery. written to CLKCTL0 must have CSTAT set. 0: Failure detection of the System Clock is disabled. 1: Failure detection of the System Clock is enabled. selected as System Clock) and SCKFEN is set. is selected as System Clock) and SCKFEN is set. or WTO is selected as System Clock) and SCKFEN is set.

Register Unlocking/Locking section on page 103. : Digitally Controlled Oscillator (DCO). 001: Peripheral Clock (PCLK). on PLL Clock Source Select (PLLSEL). 011 : Phase Locked Loop (PLL). 100: Watchdog Timer Oscillator (WTO). Table 39. Clock Control 1 Register (CLKCTL1) This bit is reserved and must be programmed to 0. 0: Failure detection of Watchdog Timer Oscillator is disabled. 1: Failure detection of Watchdog Timer Oscillator is enabled.

System Control Register Unlocking/Locking section on page 103. : Internal Precision Oscillator (IPO). 01: Low Frequency Crystal Oscillator (LFXO). 10: External clock drive, CLK2IN on PA2. 0: Enabled PCLK sources do not operate during Stop Mode. Table 40. Clock Control 2 Register (CLKCTL2) These bits are reserved and must be programmed to 000.

PS029413-0921 P R E L I M I N A R Y Clock System Register Definitions Z8 Encore! XP® F6482 Series Product Specification 118 8.11.4. Clock Control 3 Register The Clock Control 3 (CLKCTL3) Register, shown in Table 41, selects the FLL N-Divider High byte. Before writing CLKCTL3, the clock control registers must be unlocked as described in the Clock System Control Register Unlocking/Locking section on page 103. [3:2] HFXOBAND High Frequency Crystal Oscillator (HFXO) Frequency Band 00: The HFXO or external clock drive is in the 1MHz to 8MHz frequency band. 01: The HFXO or external clock drive is in the > 8MHz to 16MHz frequency band. 10: The HFXO or external clock drive is in the > 16MHz to 24MHz frequency band. 11: Reserved. [1] Reserved This bit is reserved and must be programmed to 0. [0] HFXOEN High Frequency Crystal Oscillator (HFXO) Enable 0: HFXO is disabled. 1: HFXO is enabled. In Stop Mode, this bit is overridden such that the HFXO is disabled. Bit Description (Continued)

System Control Register Unlocking/Locking section on page 103. Table 41. Clock Control 3 Register (CLKCTL3) 4 Register section on page 119 to learn more about FLL N-divider settings. Table 42. Clock Control 4 Register (CLKCTL4) These bits are reserved and must be programmed to 000000.

described in the Clock System Control Register Unlocking/Locking section on page 103. should not be less than 01Fh (1 MHz) nor exceed 2DCh (24 MHz). Table 43. Clock Control 5 Register (CLKCTL5) Notes: *STOP = Effect of entering Stop Mode; SMR = Effect of Stop-Mode Recovery. This bit is reserved and must be programmed to 0.

Locking section on page 103. 0: The FLL lost lock condition (FLLLL) does not generate an interrupt request. 0: The FLL has not lost lock. 0: The FLL is not ready (unlocked). 1: The FLL is ready (locked). enter Stop Mode, clear FLLEN or change FLL divider value until this bit is set. 1: The FLL fast locking algorithm is done. 0: DCO seed is internally computed when locking the FLL. 0: FLL is disabled. The FLLRDY and FLLLL status bits are cleared when the FLL is disabled. Table 44. Clock Control 6 Register (CLKCTL6)

ing/Locking section on page 103. Locking section on page 103. The most-significant bits of the DCO control word, bits 15:8. Table 45. Clock Control 7 Register (CLKCTL7) implemented but not used by the FLL, allowing for future capability expansion. Table 46. Clock Control 8 Register (CLKCTL8)

Locking section on page 103. The most-significant bits of the DCO converged control word, bits 15:8. Table 47. Clock Control 9 Register (CLKCTL9) The least-significant bits of the DCO converged control word, bits 7:0. Table 48. Clock Control A Register (CLKCTLA)

PS029413-0921 P R E L I M I N A R Y Clock System Register Definitions Z8 Encore! XP® F6482 Series Product Specification 124 Bit Description [7:0] PLLNDIV Phase Locked Loop (PLL) Feedback Division Ratio Disable the PLL by clearing PLLEN prior to changing PLLNDIV. 00h : 1. 01h: 2. 02h: 3. 03h: 4. FCh : 253. FDh: 254. FEh: 255. FFh: 256.

Control Register Unlocking/Locking section on page 103. Table 49. Clock Control B Register (CLKCTLB) Disable the PLL by clearing PLLEN prior to changing PLLRDIV. This bit is reserved and must be programmed to 0.

System Control Register Unlocking/Locking section on page 103. Table 50. Clock Control C Register (CLKCTLC) This bit is reserved and must be programmed to 0. 0: High Frequency Crystal Oscillator (HFXO). 1: External clock drive, CLKIN on PA0.

PS029413-0921 P R E L I M I N A R Y Interrupt Controller Z8 Encore! XP® F6482 Series Product Specification 127 Chapter 9. Interrupt Controller The interrupt controller on the F6482 Series products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The interrupt controller includes the following features:

• Forty-one interrupt sources using thirty unique interrupt vectors – 16 GPIO port pin interrupt sources (nine interrupt vectors are shared, see Table 51) – 25 on-chip peripheral interrupt sources (five interrupt vectors are shared, see Table 51)
• Flexible GPIO interrupts – Twelve selectable rising and falling edge GPIO interrupts – Four dual-edge interrupts
• Three levels of individually programmable interrupt priority
• WDT can be configured to generate an interrupt Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the CPU and the interrupting peripheral. When the service routine is com- pleted, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information about interrupt servicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is available free for download from the Zilog website. 9.1. Interrupt Vector Listing Table 51 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most-significant byte (MSB) at the even Program Memory address and the least-significant byte (LSB) at the following odd Program Memory address.

rupt sources are unavailable on devices not containing those peripherals. Table 51. Trap and Interrupt Vectors in Order of Priority

setting. See the Interrupt Vectors and Priority section on page 131 to learn more. Table 51. Trap and Interrupt Vectors in Order of Priority (Continued)

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 131

• Stop-Mode Recovery
• Execution of a Disable Interrupt (DI) instruction
• Writing 0 to the IRQE bit in the interrupt control register
• eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
• Execution of a Trap instruction
• Illegal Instruction Trap
• Primary Oscillator Fail Trap
• Watchdog Oscillator Fail Trap 9.3.2. Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of the interrupts are enabled with identical interrupt priority (for example, all as Level 2 interrupts), the interrupt priority is assigned from highest to lowest as specified in Table 51 on page 128. Level 3 interrupts are always assigned higher priority than Level 2 interrupts which, in turn, always are assigned higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 51 on page 128. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail Trap, Watchdog Timer Oscillator Fail Trap, and Illegal Instruction Trap always have highest (Level 3) priority. 9.3.3. Interrupt Assertion Interrupt sources assert their interrupt requests for only a single-system clock period (sin- gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond- ing bit in the Interrupt Request Register is cleared until the next interrupt occurs. Writing 0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt request. Zilog recommends not using a coding style that clears bits in the Interrupt Request reg- isters. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 1, which follows. Example 1. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 Caution:

PS029413-0921 P R E L I M I N A R Y Interrupt Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 132 To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt Request 0 Register: Example 2. Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK 9.3.4. Software Interrupt Assertion Program code can generate interrupts directly. Writing 1 to the correct bit in the Interrupt Request Register triggers an interrupt (assuming that interrupt is enabled). When the inter- rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request Register is automatically cleared to 0. Zilog recommends not using a coding style to generate software interrupts by setting bits in the Interrupt Request registers. All incoming interrupts received between execu- tion of the first LDX command and the final LDX command are lost. See Example 3, which follows. Example 3. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt Request registers. Example 4. Good coding style that avoids lost-interrupt requests: ORX IRQ0, MASK 9.4. Interrupt Control Register Definitions For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail Trap, and the Watchdog Oscillator Fail Trap, the Interrupt Control registers enable individ- ual interrupts, set interrupt priorities, and indicate interrupt requests. 9.4.1. Interrupt Request 0 Register The Interrupt Request 0 (IRQ0) Register, shown in Table 52, stores the interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt con- troller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 Caution:

Interrupt Request 0 Register to determine if any interrupt requests are pending. Table 52. Interrupt Request 0 Register (IRQ0) 0: No interrupt request is pending for Timer 2. 1: An interrupt request from Timer 2 is awaiting service. 0: No interrupt request is pending for Timer 1. 1: An interrupt request from Timer 1 is awaiting service. 0: No interrupt request is pending for Timer 0. 1: An interrupt request from Timer 0 is awaiting service. 0: No interrupt request is pending for the UART 0 receiver. 1: An interrupt request from the UART 0 receiver is awaiting service. 0: No interrupt request is pending for the UART 0 transmitter. 1: An interrupt request from the UART 0 transmitter is awaiting service. 0: No interrupt request is pending for the USB. 1: An interrupt request from the USB is awaiting service. 0: No interrupt request is pending for USB Resume. 1: An interrupt request for USB Resume is awaiting service. 0: No interrupt request is pending for the I2C. 1: An interrupt request from I2C is awaiting service.

Request 1 Register to determine if any interrupt requests are pending. Table 53. Interrupt Request 1 Register (IRQ1) 0: No interrupt request is pending for the SPI 1. 1: An interrupt request from the SPI 1 is awaiting service. 0: No interrupt request is pending for the DAC. 1: An interrupt request from the DAC is awaiting service. 0: No interrupt request is pending for DMA x. 0: No interrupt request is pending for the ADC. 1: An interrupt request from the ADC is awaiting service. 0: No interrupt request is pending for the SPI 0. 1: An interrupt request from the SPI 0 is awaiting service. 0: No interrupt request is pending for the LCD. 1: An interrupt request from the LCD is awaiting service. 0: No interrupt request is pending for the RTC. 1: An interrupt request from the RTC is awaiting service.

Request 2 Register to determine if any interrupt requests are pending. Table 54. Interrupt Request 2 Register (IRQ2) 0: No interrupt request is pending for GPIO Port A7 or LVD. 1: An interrupt request from GPIO Port A7 or LVD. 0: No interrupt request is pending for GPIO Port A6 or Comparator 0. 1: An interrupt request from GPIO Port A6 or Comparator 0. 0: No interrupt request is pending for GPIO Port A5 or Comparator 1. 1: An interrupt request from GPIO Port A5 or Comparator 1. 1: An interrupt request from GPIO Port Ax or Port Dx is awaiting service. Register 0 section on page 146. 0: No interrupt request is pending for GPIO Port A0. 1: An interrupt request from GPIO Port A0 is awaiting service.

Request 3 Register to determine if any interrupt requests are pending. Table 55. Interrupt Request 3 Register (IRQ3) 0: No interrupt request is pending for the AES. 1: An interrupt request from the AES is awaiting service. 0: No interrupt request is pending for multi-channel timer. 1: An interrupt request from multi-channel timer is awaiting service. 0: No interrupt request is pending for the UART 1 receiver. 1: An interrupt request from the UART 1 receiver is awaiting service. 0: No interrupt request is pending for the UART 1 transmitter. 1: An interrupt request from the UART 1 transmitter is awaiting service. 0: No interrupt request is pending for GPIO Port Cx or DMA x. specific GPIO Port C bit or DMA number (3–2). 0: No interrupt request is pending for GPIO Port C pin x. GPIO Port C pin number (1–0).

Interrupt Request 0 Register. Priority is generated by setting bits in each register. Table 56. IRQ0 Enable and Priority Encoding Note: x indicates register bits from 0–7. Table 57. IRQ0 Enable High Bit Register (IRQ0ENH)

Table 58. IRQ0 Enable Low Bit Register (IRQ0ENL)

Request 1 Register. Priority is generated by setting bits in each register. Table 59. IRQ1 Enable and Priority Encoding Note: x indicates register bits from 0–7. Table 60. IRQ1 Enable High Bit Register (IRQ1ENH) x indicates the specific DMA bit (5–4).

Request 2 Register. Priority is generated by setting bits in each register. Table 61. IRQ1 Enable Low Bit Register (IRQ1ENL) x indicates the specific DMA bit (5–4). Table 62. IRQ2 Enable and Priority Encoding Note: x indicates the register bits from 0–7.

Table 63. IRQ2 Enable High Bit Register (IRQ2ENH) Port A or Port D as the interrupt source. See Table 69 on page 146for a selection of either Port A or Port D as the interrupt source. Table 64. IRQ2 Enable Low Bit Register (IRQ2ENL)

Interrupt Request 3 Register. Priority is generated by setting bits in each register. x indicates the specific PAD bit (4–1). Table 65. IRQ3 Enable and Priority Encoding Note: x indicates register bits from 0–7. Table 66. IRQ3 Enable High Bit Register (IRQ3ENH)

PS029413-0921 P R E L I M I N A R Y Interrupt Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 143 [4] U1TENH UART1 Transmit Interrupt Request Enable High Bit [3:2] CxENH/ DMAyENH Port Cx or DMAy Interrupt Request Enable High Bit x indicates the specific Port C bit (3–2); y indicates the specific DMA bit (3–2). [1:0] CxENH Port Cx (x = 0–1) Interrupt Request Enable High Bit x indicates the specific Port C bit (1–0). Bit Description (Continued)

Table 67. IRQ3 Enable Low Bit Register (IRQ3ENL) x indicates the specific Port C bit (3–2); y indicates the specific DMA bit (3–2). x indicates the specific Port C bit (1–0).

Table 68. Interrupt Edge Select Register (IRQES) Note: x indicates the specific GPIO port bit number (7–0).

A and alternate sources for the individual interrupts. Table 69. Shared Interrupt Select Register 0 (IRQSS0) 0: PA7 is used for the interrupt for PA7VS interrupt request. 1: The LVD is used for the interrupt for PA7VS interrupt request. 0: PA6 is used for the interrupt for PA6CS interrupt request. 1: The Comparator 0 is used for the interrupt for PA6CS interrupt request. 0: PA5 is used for the interrupt for PA5CS interrupt request. 1: The Comparator 1 is used for the interrupt for PA5CS interrupt request. x indicates the specific Port A bit number (4–1). 0: PAx is used for the interrupt for PAx/PDx interrupt request. 1: PDx is used for the interrupt for PAx/PDx interrupt request. This bit is reserved and must be programmed to 0.

Port C and DMA for the individual interrupts. Table 70. Shared Interrupt Select Register 1 (IRQSS1) These bits are reserved and must be programmed to 0000. x indicates the specific Port C bit/DMA channel number (3–2). 0 = PCx is used for the interrupt for PCx/DMAx interrupt request. 1 = DMAx is used for the interrupt for PCx/DMAx interrupt request. These bits are reserved and must be programmed to 00.

Table 71. Interrupt Control Register (IRQCTL) Note: *SMR = Effect of Stop-Mo de Recovery; NC = No Change. a 0 to this bit, eZ8 CPU acknowledgement of an interrupt request, or by a trap. These bits are reserved and must be programmed to 0000000.

PS029413-0921 P R E L I M I N A R Y Timers Z8 Encore! XP® F6482 Series Product Specification 149 Chapter 10. Timers The F6482 Series products contain three 16-bit reloadable timers that can be used for tim- ing, event counting, or generation of pulse-width modulated signals. The timers’ features include:

• 16-bit reload counter
• One-shot timer
• Programmable prescaler with prescale values ranging from 1 to 128
• PWM output generation
• Capture and compare capability
• Two independent capture/compare channels which reference the common timer
• DMA support
• Event System and external input pin for timer input, clock gating, or capture signal. Ex- ternal input pin signal frequency is limited to a maximum of one-fourth the timer clock frequency
• Timer output to Event System and external pin
• Timer interrupt
• Noise Filter on Timer Input 0 signal
• Operation in any mode with PCLK or WTO; operation in Normal Mode and Halt Mode with SYSCLK, PCLK, or WTO In addition to the timers described in this chapter, the Baud Rate Generator (BRG) of unused serial port peripherals can also be used to provide basic timing functionality. For more information about using the Baud Rate Generators as additional timers, see the Elec- trical Characteristics chapter on page 601, the Enhanced Serial Peripheral Interface chap- ter on page 281 and the I2C Master/Slave Controller chapter on page 306. Furthermore, the RTC Counter Mode can be used to provide basic timing functionality. To learn more regarding the use of RTC Counter Mode, see the Real-Time Clock chapter on page 210.

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 151 When the timer is operating on PCLK or the WTO, the timer clock is asynchronous to System Clock. To ensure error-free operation, disable the timer before modifying its op- eration (including changing the timer clock source). When the Timer uses PCLK or the WTO and the Timer is enabled, any read from TxH or TxL is not recommended, because results can be unpredictable. Disable the Timer first, then read it. If capture, capture/compare, Capture Restart or demodulation mode is selected, any read from TxPWM0H, TxPWM0L, TxPWM1H, TxPWM1L, or TxSTAT must be done after capture interrupt occurs, or results can be unpredictable. INPCAP in the Timer Control 0 Register has the same characteristics as these PWM registers. When the Timer clock selection is System Clock, registers can be written/read at any time. 10.1.2. Low-Power Modes Timers can operate in both Halt Mode and Stop Mode. This section discusses each of these low-power modes. 10.1.2.1. Operation in Halt Mode When the eZ8 CPU enters Halt Mode, the Timer will continue to operate if enabled. To minimize current in Halt Mode, the Timer can be disabled by clearing the TEN control bit. The Noise Filter, if enabled, will also continue to operate in Halt Mode and rejects any noise on the Timer Input 0. 10.1.2.2. Operation in Stop Mode When the eZ8 CPU enters Stop Mode, the Timer continues to operate if enabled and PCLK or the WTO is selected as the timer clock. In Stop Mode, the timer interrupt (if enabled) automatically initiates a Stop-Mode Recovery and generates an interrupt request. In the Reset Status Register, the stop bit is set to 1. Also, timer interrupt request bit in Interrupt Request 0 Register is set. Following completion of the Stop-Mode Recovery, if interrupts are enabled, the CPU responds to the interrupt request by fetching the timer interrupt vector. The Noise Filter, if enabled, will also continue to operate in Stop Mode and rejects any noise on the Timer Input 0. If System Clock is chosen as the timer clock, the Timer ceases to operate as System Clock is disabled in Stop Mode. In this case the registers are not reset and operation will resume after Stop-Mode Recovery occurs. 10.1.2.3. Power Reduction During Operation Clearing TEN will inhibit clocking of the Timer. The CPU can still read/write registers when TEN is cleared. Caution:

described in this section where indicated in Table 72. starting the timer, configure TPOL to the opposite bit value.

1. Write to the Timer Control 1 Register to:

Table 72. Timer Operating Modes

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 153 – Disable the timer – Configure the timer for One-Shot Mode – Set the prescale value – If using the Timer Output alternate function or the Event System, set the initial output level (High or Low) and configure the output behavior (OUTCTL) 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value. 5. Write to the Timer Reload High and Low Byte registers to set the reload value. 6. If required, enable the timer i nterrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. If using the Event System, configure it to route the Timer Output to the desired destination. 8. Write to the Timer Control 1 Re gister to enable the timer and initiate counting. In One-Shot Mode, the timer clock always provides the timer input. The timer period is calculated using the following equation: 10.1.3.2. Triggered One-Shot Mode In Triggered One-Shot Mode (TMODE = 1011), the Timer Input 0 signal triggers counting. Two timer output options and four interrupt options are available. Timer Input 1 can be used in the interrupt control to signal that a trigger event occurred while counting. If a trig- ger event occurs while counting, INPCAP is set to indicate that the interrupt is due to the trigger event. If a reload occurs, INPCAP is cleared to indicate that the interrupt is not due to a trigger event. The timer operates in the following sequence: 1. The Timer idles until a trigge r is received. The Timer trigger, the Input 0 signal, is taken from the GPIO port pin timer input alternate function or from the Event System. If required, enable the Noise Filter and set the Noise Filter control by writing to the relevant bits in the Noise Filter Control Register. The TPOL bit in the Timer Control 1 Register selects whether the triggering occurs on the rising edge or the falling edge of the timer Input 0 signal. Note that when OUTCTL = 1, falling edge triggering is not available, and should therefore not be selected. ONE-SHOT Mode Time-Out Period (s) Reload Value - Start Value )xPrescale

1. Following the trigger event, th e Timer counts timer clocks up to the 16-bit reload

value stored in the Timer Reload High and Low Byte registers.

1. The timer output polarity is se lected by TPOL and timer output behavior is selected in

– OUTCTL = 1: Pulse from start to reload; only TPOL = 0 is allowed.

1. Timer interrupt behavior is sel ected by TICONFIG to occur upon one of the follow-
2. Upon reaching the reload value , the timer resets the count value in the Timer High and

One-Shot Mode and initiating operation. Table 73. Triggered One-Shot Mode Initialization Example T0CTL0 E0h TMODE[3:0] = 1011b selects Triggered One-Shot Mode. TICONFIG[1:0] = 11b enables interrupts on Timer reload only. PWMD[2:0] = 000b has no effect. OUTCTL = 0b selects a single clock output pulse upon timer reload. = 000b sets prescaler to divide by 1. TCLKS = 10b selects PCLK as the Timer clock source.

1. The Timer idles until a trigge r is received. Due to the assertion of an input, both inputs

T0H 00h Timer starting value = 0001h. T0RH ABh Timer reload value = ABCDh. PAADDR 02h Selects Port A Alte rnate Function Register. Alternate Function Set 1 Register. Alternate Function Set 1 Register. PAADDR 07h Selects Port A Alter nate Function Set 1 Register. PACTL[1:0] 00b PACTL[0] enables Time r 0 Input Alternate function. PACTL[1] enables Timer 0 Output Alternate function. ESDADDR 10h Selects the Timer 0 In put 0 Event System Destination. ESDCTL 00h Disconnects the Event System Input0 to Timer 0. IRQ0ENH[5] 0b Disables th e Timer 0 interrupt. = 1 enables the timer. All other bits remain in their appropriate settings.

1. Count ABCDh timer clocks.
2. Upon Timer 0 reload, generate a single clock cycle active High output pulse on the Timer 0 Output.
3. Wait for the next input trigger event.

Table 73. Triggered One-Shot Mode Initialization Example (Continued)

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 156 trigger occurs on the rising edge or the falling edge of the timer Input 0 signal. Note that when OUTCTL = 1, falling edge triggering is not available, and should therefore not be selected. 2. Following the trigger event, th e Timer counts timer clocks up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. 3. The timer output polarity is se lected by TPOL and timer output behavior is selected in OUTCTL to be one of the following: – OUTCTL = 0: Pulse at reload lasting one timer clock – OUTCTL = 1: Pulse from start to reload; only TPOL = 0 is allowed 4. Timer interrupt behavior is sel ected by TICONFIG to occur upon one of the follow- ing: – TICONFIG = 00: All reload events and all trigger events while counting – TICONFIG = 01: Only on same input trigger events while counting – TICONFIG = 10: Only on opposite input trigger events while counting – TICONFIG = 11: Only on reload events 5. Upon reaching the reload value , the timer resets the count value in the Timer High and Low Byte registers to 0001h. The Timer now idles until the next timer Input 0 or Input 1 trigger event. In Dual Input Triggered One-Shot Mode, the timer clock always provides the timer input. The timer period is shown in the following equation: 10.1.3.4. Continuous Mode In Continuous Mode (TMODE = 0001), the timer counts timer clocks up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. Also, the Timer Output changes state (from Low to High or High to Low) on timer reload. The Timer Output can be con- nected to the Event System and, if the Timer Output alternate function is enabled, to the Timer Output pin. Observe the following steps to configure a timer for Continuous Mode and initiate the count: 1. Write to the Timer Control 1 Register to: – Disable the timer Triggered ONE-SHOT Mode Time-Out Period (s) Reload Value - Start Value() Prescale×

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 157 – Configure the timer for Continuous Mode – Set the prescale value – If using the Timer Output Alternate Function or the Event System, set the initial output level (High or Low) 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt-configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001h). This value only affects the first pass in Continuous Mode. After the first timer reload in Continuous Mode, counting always begins at the reset value of 0001h. 5. Write to the Timer Reload High and Low Byte registers to set the reload value. 6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. If using the Event System, configure it to route the Timer Output to the desired destination. 8. Write to the Timer Control 1 Re gister to enable the timer and initiate counting. In Continuous Mode, the timer clock always provides the timer input. The timer period is calculated using the following equation: If an initial starting value other than 0001h is loaded into the Timer High and Low Byte registers, the One-Shot Mode equation must be used to determine the first time-out period. 10.1.3.5. Counter Mode In Counter Mode (TMODE = 0010), the timer counts timer Input 0 signal transitions. The timer Input 0 signal is taken from the GPIO Port pin Timer Input alternate function or from the Event System Input 0. The TPOL bit in the Timer Control 1 Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input 0 signal. In Counter Mode, the prescaler is disabled. The input frequency of the Timer Input signal must not exceed one-fourth the timer clock frequency. CONTINUOUS Mode Time-Out Period (s) Reload Value Prescale× Caution:

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 158 Upon reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. Also, the Timer Output pin changes state (from Low to High or High to Low) at timer reload. The Timer Output can be connected to the Event System and, if the Timer Output alternate function is enabled, to the Timer Output pin. Observe the following steps to configure a timer for Counter Mode and initiate the count: 1. Write to the Timer Control 1 Register to: – Disable the timer. – Configure the timer for Counter Mode. – Select either the rising edge or falling edge of the Timer Input 0 signal for the count. This also sets the initial logic level (High or Low) for the Timer Output Alternate Function. However, the Timer Output function is not required to be enabled. 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value. This value only affects the first pass in Counter Mode. After the first timer reload in Coun- ter Mode, counting always begins at the reset value of 0001h. Generally, in Counter Mode the Timer High and Low Byte registers should be written with the value 0001h. 5. Write to the Timer Reload High and Low Byte registers to set the reload value. 6. If required, enable the timer i nterrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. If required, enable the Noise Filter and set the Noise Filter control by writing to the relevant bits in the Noise Filter Control Register. 8. Configure the associated GPIO po rt pin for the Timer Input alternate function or con- figure the desired Event System Timer Input 0. 9. When using the Timer Output, c onfigure the associated GPIO port pin for the Timer Output alternate function or configure the Event System to route the Timer Output to the desired destination. 10. Write to the Timer Control 1 Register to enable the timer. In Counter Mode, the number of Timer Input 0 transitions since the timer start is calcu- lated using the following equation: COUNTER Mode Timer Input Transitions Current Count Value - Start Value=

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 159 10.1.3.6. PWM Single Output Mode In PWM Single Output Mode (TMODE = 0011), the timer outputs a Pulse Width Modula- tor output signal through a GPIO Port pin and/or to the Event System. The Timer counts timer clocks up to the 16-bit reload value. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM0 High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. If the TPOL bit in the Timer Control 1 Register is set to 1, the Timer Output signal begins as High (1) and then transitions to Low (0) when the timer value matches the PWM value. The Timer Output signal returns to High (1) after the timer reaches the reload value and is reset to 0001h. If the TPOL bit in the Timer Control 1 Register is set to 0, the Timer Output signal begins as Low (0) and then transitions to High (1) when the timer value matches the PWM value. The Timer Output signal returns to Low (0) after the timer reaches the reload value and is reset to 0001h. Observe the following steps to configure a timer for PWM Single Output Mode and initi- ate PWM operation: 1. Write to the Timer Control 1 Register to: – Disable the timer – Configure the timer for PWM Mode – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output Alternate Function 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value (typi- cally 0001h). This value only affects the first pass in PWM Mode. After the first timer reset in PWM Mode, counting always begins at the reset value of 0001h. 5. Write to the Timer PWM0 High an d Low Byte registers to set the PWM value. 6. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 7. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers.

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 160 8. Configure the associated GPIO po rt pin for the Timer Output alternate function and/or the Event System to route the Timer Output to the desired destination. 9. Write to the Timer Control 1 Re gister to enable the timer and initiate counting. The PWM period is calculated using the following equation: If an initial starting value other than 0001h is loaded into the Timer High and Low Byte registers, the One-Shot Mode equation must be used to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is calculated using the following equation: If TPOL is set to 1, the ratio of the PWM output High time to the total period is calculated using the following equation: 10.1.3.7. PWM Dual Output Mode In PWM Dual Output Mode (TMODE = 1000), the timer outputs a Pulse Width Modulator output signal and also its complement through two GPIO Port pins and/or to the Event System. The timer first counts up to 16-bit PWM match value stored in the Timer PWM0 High and Low Byte registers. When the timer count value matches the PWM value, the Timer Outputs (TOUT and TOUT) toggle. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and TOUT and TOUT toggles again and counting resumes. If the TPOL bit in the Timer Control 1 Register is set to 1, the Timer Output signal begins as High (1) and then transitions to Low (0) when the timer value matches the PWM value. The Timer Output signal returns to High (1) after the timer reaches the reload value and is reset to 0001h. If the TPOL bit in the Timer Control 1 Register is set to 0, the Timer Output signal begins as Low (0) and then transitions to High (1) when the timer value matches the PWM value. The Timer Output signal returns to Low (0) after the timer reaches the reload value and is reset to 0001h. PWM Period (s) Reload Value Prescale× PWM Output High Time Ratio (%) Reload Value - PWM Value PWM Output High Time Ratio (%) PWM Value

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 161 The timer also generates a second PWM output signal, Timer Output Complement (TOUT). TOUT is the complement of the Timer Output PWM signal (TOUT). A program- mable deadband delay can be configured to set a time delay (0 to 128 timer clock cycles) when one PWM output transitions from High to Low and the other PWM output transi- tions from a Low to High. This configuration ensures a time gap between the removal of one PWM output and the assertion of its complement. Observe the following steps to configure a timer for PWM Dual Output Mode and initiate the PWM operation: 1. Write to the Timer Control 1 Register to: – Disable the timer – Configure the timer for PWM Dual Output Mode. Setting the mode also involves writing to TMODE[3] bit in the TxCTL0 Register – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output Alternate Function 2. Write to the Timer High and Low Byte registers to set the starting count value (typi- cally 0001h). This value only affects the first pass in PWM Mode. After the first timer reset in PWM Mode, counting always begins at the reset value of 0001h. 3. Write to the Timer PWM0 High an d Low Byte registers to set the PWM value. 4. Write to the Timer Control 0 Register: – To set the PWM deadband delay value – To choose the timer clock source 5. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 6. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 7. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 8. Configure the associated GPIO po rt pin for the Timer Output and Timer Output Com- plement alternate functions and/or the Event System to route the Timer Output to the desired destination. 9. Write to the Timer Control 1 Re gister to enable the timer and initiate counting. The PWM period is calculated using the following equation: PWM Period (s) Reload Value Prescale×

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 162 If an initial starting value other than 0001h is loaded into the Timer High and Low Byte registers, the One-Shot Mode equation must be used to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is calculated using the following equation: If TPOL is set to 1, the ratio of the PWM output High time to the total period is calculated using the following equation: 10.1.3.8. Capture Mode In Capture Mode (TMODE = 0100), the current timer count value is recorded when the appropriate external Timer Input 0 transition occurs. The Capture count value is written to the Timer PWM0 High and Low Byte registers. The Timer counts timer clocks up to the 16-bit reload value. The TPOL bit in the Timer Control 1 Register determines if the Cap- ture occurs on a rising edge or a falling edge of the Timer Input 0 signal. When the Cap- ture event occurs, an interrupt is generated and the timer continues counting. The INPCAP bit in Timer Control 0 Register is set to indicate the timer interrupt is due to an input cap- ture event. The timer continues counting up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an inter- rupt and continues counting. The INPCAP bit in Timer Control 0 Register is cleared to indicate the timer interrupt is not due to an input capture event. Observe the following steps to configure a timer for Capture Mode and initiate the count: 1. Write to the Timer Control 1 Register to: – Disable the timer – Configure the timer for Capture Mode – Set the prescale value – Set the Capture edge (rising or falling) for the Timer Input 0 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value (typi- cally 0001h). PWM Output High Time Ratio (%) Reload Value - PWM Value PWM Output High Time Ratio (%) PWM Value

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 163 5. Write to the Timer Reload High and Low Byte registers to set the reload value. 6. Clear the Timer PWM High and Low Byte registers to 0000h. This allows user soft- ware to determine if interrupts were generated by either a capture event or a reload. If the PWM0 High and Low Byte registers still contain 0000h after the interrupt, then the interrupt was generated by a Reload. 7. If required, enable the timer i nterrupt and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt will be generated for both input capture and reload events. If required, configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the Timer Control 0 Register. 8. Configure the associated GPIO po rt pin for the Timer Input alternate function or con- figure the desired Event System Timer Input 0. 9. Write to the Timer Control 1 Re gister to enable the timer and initiate counting. In Capture Mode, the elapsed time from timer start to Capture event can be calculated using the following equation: 10.1.3.9. Capture Restart Mode In Capture Restart Mode (TMODE = 1001), the current timer count value is recorded when the appropriate external Timer Input 0 transition occurs. The Capture count value is writ- ten to the Timer PWM0 High and Low Byte registers. The Timer counts timer clocks up to the 16-bit reload value. The TPOL bit in the Timer Control 1 Register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input 0 signal. When the Capture event occurs, an interrupt is generated and the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. The INPCAP bit in Timer Control 0 Register is set to indicate the timer interrupt is due to an input capture event. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. The INPCAP bit in Timer Control 0 Register is cleared to indicate the timer interrupt is not due to an input capture event. Observe the following steps to configure a timer for Capture Restart Mode and initiate the count: 1. Write to the Timer Control 1 Register to: – Disable the timer – Configure the timer for Capture Restart Mode. Setting the mode also involves writing to TMODE[3] bit in the TxCTL0 Register Capture Elapsed Time (s) Capture Value - Start Value() Prescale×

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 164 – Set the prescale value – Set the Capture edge (rising or falling) for the Timer Input 0 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value (typi- cally 0001h). 5. Write to the Timer Reload High and Low Byte registers to set the reload value. 6. Clear the Timer PWM High and Low Byte registers to 0000h. This allows user soft- ware to determine if interrupts are generated by either a Capture Event or a Reload. If the PWM0 High and Low Byte registers still contain 0000h after the interrupt, then the interrupt is generated by a Reload. 7. If required, enable the timer i nterrupt and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt will be generated for both input capture and reload events. If required, configure the timer interrupt to be generated only at the Input Capture event or the reload event by setting TICONFIG field of the Timer Control 0 Register. 8. Configure the associated GPIO po rt pin for the Timer Input alternate function or con- figure the desired Event System Timer Input 0. 9. Write to the Timer Control 1 Re gister to enable the timer and initiate counting. In Capture Mode, the elapsed time from Timer start to Capture event can be calculated using the following equation: 10.1.3.10.Compare Mode In Compare Mode (TMODE = 0101), the timer counts timer clocks up to the 16-bit maxi- mum Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001h). Also, the Timer Output changes state (from Low to High or from High to Low) on Compare. The Timer Output can be connected to the Event System and, if the Timer Output alternate function is enabled, to the Timer Output pin. If the Timer reaches FFFFh, the timer rolls over to 0000h and continues counting. Observe the following steps to configure a timer for Compare Mode and initiate the count: 1. Write to the Timer Control 1 Register to: – Disable the timer Capture Elapsed Time (s) Capture Value - Start Value() Prescale×

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 165 – Configure the timer for Compare Mode – Set the prescale value – Set the initial logic level (High or Low) for the Timer Output, if required 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field, TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value. 5. Write to the Timer Reload High and Low Byte registers to set the Compare value. 6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 7. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. If using the Event System, configure it to route the Timer Output to the desired destination. 8. Write to the Timer Control 1 Re gister to enable the timer and initiate counting. In Compare Mode, the timer clock always provides the timer input. The Compare time is calculated using the following equation: 10.1.3.11.Gated Mode In Gated Mode (TMODE = 0110), the timer counts only when the Timer Input 0 signal is in its active state (asserted) as determined by the TPOL bit in the Timer Control 1 Register. When the Timer Input 0 signal is asserted, counting begins. A Timer Interrupt is generated when the Timer Input 0 signal is deasserted or a timer reload occurs. The INPCAP bit in Timer Control 0 Register is set to indicate the timer interrupt is due to the Timer Input sig- nal. The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers using the timer clock. When reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes (assuming the Timer Input 0 signal is still asserted). Also, the Timer Output changes state (from Low to High or from High to Low) at timer reset. The Timer Output can be connected to the Event System and, if the Timer Output alternate function is enabled, to the Timer Output pin. Observe the following steps to configure a timer for Gated Mode and initiate the count: 1. Write to the Timer Control 1 Register to: COMPARE Mode Time (s) Compare Value - Start Value() Prescale×

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 166 – Disable the timer – Configure the timer for Gated Mode – Set the prescale value 2. Write to the Timer Control 2 Register to choose the timer clock source. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value. This value only affects the first pass in Gated Mode. After the first timer reset in Gated Mode, counting always begins at the reset value of 0001h. 5. Write to the Timer Reload High and Low Byte registers to set the reload value. 6. If required, enable the timer i nterrupt and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt will be generated for both input deassertion and reload events. If required, configure the timer interrupt to be generated only at the Input Deassertion event or the Reload event by setting TICONFIG field of the Timer Control 0 Register. 7. Configure either the associated GPIO port pin for the Timer Input alternate function or the Event System Timer Input 0. 8. Write to the Timer Control 1 Register to enable the timer. 9. Assert the Timer Input 0 signal to initiate the counting. 10.1.3.12.Capture/Compare Mode In Capture/Compare Mode (TMODE = 0111), the timer begins counting on the first exter- nal Timer Input 0 transition. The appropriate transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control 1 Register. The Timer counts timer clocks up to the 16-bit reload value. Every subsequent appropriate transition (after the first) of the Timer Input 0 signal cap- tures the current count value. The Capture value is written to the Timer PWM0 High and Low Byte registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. The INPCAP bit in Timer Control 0 Register is set to indicate the timer interrupt is due to an input capture event. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h and counting resumes. The INPCAP bit in Timer Control 0 Register is cleared to indicate the timer interrupt is not due to an input capture event.

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 167 Observe the following steps to configure a timer for Capture/Compare Mode and initiate the count: 1. Write to the Timer Control 1 Register to: – Disable the timer – Configure the timer for Capture/Compare Mode – Set the prescale value – Set the Capture edge (rising or falling) for the Timer Input 0 2. Write to the Timer High and Low Byte registers to set the starting count value (typi- cally 0001h). 3. Write to the Timer Control 2 Register to choose the timer clock source. 4. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 5. Write to the Timer Reload High and Low Byte registers to set the Compare value. 6. If required, enable the timer interrupt and set the timer-int errupt priority by writing to the relevant interrupt registers. By default, the timer interrupt will be generated for both input capture and reload events. If required, configure the timer interrupt to be generated only at the input Capture event or the Reload event by setting TICONFIG field of the Timer Control 0 Register. 7. Configure the associated GPIO po rt pin for the Timer Input alternate function or con- figure the desired Event System Timer Input 0. 8. Write to the Timer Control 1 Register to enable the timer. 9. Counting begins on the first transition of the Timer Input 0 signal. No interrupt is gen- erated by this first edge. In Capture/Compare Mode, the elapsed time from timer start to Capture event is calcu- lated using the following equation: 10.1.3.13.Demodulation Mode In Demodulation Mode (TMODE = 1100), the timer begins counting on the first external Timer Input 0 transition. The appropriate transition (rising edge or falling edge or both) is set by the TPOL bit in the Timer Control 1 Register and TPOLHI bit in the Timer Control 2 Register. The Timer counts timer clocks up to the 16-bit reload value. Every subsequent appropriate transition (after the first) of the Timer Input 0 signal cap- tures the current count value. The Capture value is written to the Timer PWM0 High and apture Elapsed Time (s) Capture Value - Start Value() Prescale×

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 168 Low Byte registers for rising input edges of the Timer Input 0 signal. For falling edges the capture count value is written to the Timer PWM1 High and Low Byte registers. The TPOL bit in the Timer Control 1 Register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input 0 signal. If the TPOLHI bit in the Timer Control

2 Register is set, a Capture is executed on both the rising and falling edges of the input sig-

nal. Whenever the Capture event occurs, an interrupt is generated and the timer continues counting. The corresponding event flag bit in the Timer Status Register, PWMxEF, is set to indicate that the timer interrupt is due to an input Capture event. The timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h, and counting resumes. The RTOEF event flag bit in the Timer Status Register is set to indicate that the timer interrupt is due to a Reload event. Software can use this bit to determine if a Reload occurred prior to a Capture. Observe the following steps to configure a timer for Demodulation Mode and initiate the count: 1. Write to the Timer Control 1 Register to: – Disable the timer. – Configure the timer for Demodulation Mode. Setting the mode also involves writ- ing to the TMODEHI bit in the TxCTL0 Register. – Set the prescale value. – Set the TPOL bit to set the Capture edge (rising or falling) for the Timer Input 0. This setting applies only if the TPOLHI bit in the TxCTL2 Register is not set. 2. Write to the Timer Control 2 Register to: – Choose the timer clock source. – Set the TPOLHI bit if the Capture is required on both edges of the input signal. 3. Write to the Timer Control 0 Re gister to set the timer interrupt configuration field TICONFIG . 4. Write to the Timer High and Low Byte registers to set the starting count value (typi- cally 0001h). 5. Write to the Timer Reload High and Low Byte registers to set the reload value. 6. Clear the Timer T xPWM0 and TxPWM1 High and Low Byte registers to 0000h. 7. If required, enable the Noise Filter and set the Noise Filter control by writing to the relevant bits in the Noise Filter Control Register.

1. If required, enable the timer i nterrupt and set the timer interrupt priority by writing to

field of the Timer Control 0 Register.

1. Configure the associated GPIO Po rt pin for the Timer Input alternate function or con-

figure the desired Event System Timer Input 0.

1. Write to the Timer Control 1 Register to enable the timer. Counting will start on the

occurrence of the first external input transition. lation Mode and initiating operation. Table 74. Demodulation Mode Initialization Example T0CTL0 C0h TMODE[3:0] = 1100b selects Demodulation Mode. TICONFIG[1:0] = 10b enables interrupt only on Capture events. PWMD[2:0] = 000b has no effect. PRES[2:0] = 000b sets prescaler to divide by 1. T0H 00h Timer starting value = 0001h.

1. Start counting on the timer clock.
2. Upon receiving a Timer 0 Input 0 rising edge, save the Capture value in the T0PWM0 registers, generate an

interrupt, and continue to count.

1. Upon receiving a Timer 0 Input 0 falling edge, save the Capture value in the T0PWM1 registers, generate an

interrupt, and continue to count.

1. After the timer count to ABCD clocks, set the reload event flag and reset the Timer count to the start value.

ister is read, the contents of the Timer Low Byte Register are placed in a holding register. returns the actual value in the counter. PAADDR 02h Selects Port A Alternat e Function control register. PACTL[1:0] 11b PACTL[0] enables Time r 0 Input alternate function. PACTL[1] enables Timer 0 Output alternate function. PAADDR 07h Selects Port A Alter nate Function Set 1 Register. PACTL[1:0] 00b PACTL[0] enables Time r 0 Input Alternate function. PACTL[1] enables Timer 0 Output Alternate function. ESDCTL 00h Disconnects the Event System Input 0 to Timer 0. IRQ0ENH[5] 0b Disables th e Timer 0 interrupt. T0CTL1 84h TEN = 1 enables the timer. All other bits remain in their appropriate settings. Table 74. Demodulation Mode Initialization Example (Continued)

1. Start counting on the timer clock.
2. Upon receiving a Timer 0 Input 0 rising edge, save the Capture value in the T0PWM0 registers, generate an

interrupt, and continue to count.

1. Upon receiving a Timer 0 Input 0 falling edge, save the Capture value in the T0PWM1 registers, generate an

interrupt, and continue to count.

1. After the timer count to ABCD clocks, set the reload event flag and reset the Timer count to the start value.

PS029413-0921 P R E L I M I N A R Y Timer Operation Z8 Encore! XP® F6482 Series Product Specification 171 page 155. Use TICONFIG to select whether interrupts are generated due to reload, capture or input triggering events. An interrupt request that is pending when the Timer is disabled is not automatically cleared. DMA request behavior is a function of mode. For all modes except those pertaining to capture and demodulate, DMA request is asserted whenever an interrupt request is asserted. Each Timer DMA request results in a single-byte DMA transfer. This provides a mechanism for DMA transfers to be triggered by the Timer. DMA request is cleared when the DMA services the request or whenever the counter is disabled. Zilog does not recom- mend DMA for One-Shot Mode, because upon a channel interrupt, the channel is dis- abled, thereby clearing its DMA request. For capture modes (TMODE = 0100, 0111, 1100) and demodulate mode ( T M O D E = 1 1 0 0 ) , DMA request is asserted whenever an interrupt is asserted due to capture. Reload inter- rupts do not cause DMA request to be asserted. DMA request is cleared whenever the Timer PWM0 or PWM1 Low Byte Register is read by the DMA or software or whenever the counter is disabled. For capture modes, the DMA is typically configured to have fixed- word address control for the DMA source address and the source address is configured to be the Timer PWM0 High Byte Register address. 10.1.6. Timer Output Signal Operation The Timer Outputs, TOUT and TOUT, are available as GPIO Port pin alternate functions and a sources to the Event System. TOUT is the complement of TOUT in all timer modes with the special case of DUAL PWM Mode in which the complementary behavior includes deadband insertion. Generally, the Timer Outputs are toggled every time the counter is reloaded. For One-Shot, Triggered One-Shot, and Dual Input Triggered One- Shot modes, the timer output waveforms are controlled by OUTCTL. Output connectivity to Event System destinations is controlled by the Event System registers. GPIO connectiv- ity is controlled by the GPIO alternate function registers. 10.1.7. Timer Input Path and Noise Filter The timer input path develops two timer inputs from three input signals as followings: Input 0 is an OR function of a GPIO alternate function (TIN) and Event System Timer Input 0. The result is optionally polarity-adjusted and filtered. Input 1 is Event System Timer Input 1. A noise filter from another timer can be assigned to this input. A noise filter circuit is included which filters noise on the Timer Input 0 signal before it reaches the Timer. The noise filter features the following elements:

• Synchronizes the input signal to the timer clock.

This section describes the following Timer registers.

• Timer 0–2 High and Low Byte Registers – see page 175
• Timer Reload High and Low Byte Registers – see page 176
• Timer 0–2 PWM0 High and Low Byte Registers – see page 177
• Timer 0–2 PWM1 High and Low Byte Registers – see page 178
• Timer 0–2 Control Registers – see page 179
• Timer 0–2 Status Registers – see page 185

Figure 20. Noise Filter Operation

• Timer 0–2 Noise Filter Control Registers – see page 186 10.1.1. Timer 0–2 High and Low Byte Registers The Timer 0–2 High and Low Byte (TxH and TxL) registers, shown in Tables 75 and 76, contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TxL always returns this temporary register when the timers are enabled. When the timer is dis- abled, reading from the TxL reads the register directly. Zilog does not recommend writing to the Timer High and Low Byte registers when the timer is enabled. There are no temporary holding registers available for write operations; therefore simultaneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low Byte) at the next clock edge. The counter continues counting from the new value.

Table 75. Timer 0–2 High Byte Registers (TxH) Note: x references bits in the range [2:0]. Table 76. Timer 0–2 Low Byte Registers (TxL) Note: x references bits in the range [2:0]. These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.

the 16-bit timer reload value. Table 77. Timer 0–2 Reload High Byte Registers (TxRH) Note: x references bits in the range [2:0]. Table 78. Timer 0–2 Reload Low Byte Registers (TxRL) Note: x references bits in the range [2:0]. bytes form the 16-bit Compare value.

registers is delayed until a timer reload to 0001h occurs; i.e., unless PWM0UE = 1. Table 79. Timer 0–2 PWM0 High Byte Registers (TxPWM0H) Note: x references bits in the range [2:0]. Table 80. Timer 0–2 PWM0 Low Byte Registers (TxPWM0L) Note: x references bits in the range [2:0]. operating in Capture, Capture/Compare and Demodulation modes.

in Tables 81 and 82, store Capture values for Demodulation Mode. Table 81. Timer 0–2 PWM1 High Byte Registers (TxPWM1H) Note: x references bits in the range [2:0]. Table 82. Timer 0–2 PWM1 Low Byte Registers (TxPWM1L) Note: x references bits in the range [2:0].

This subsection describes the three timer control registers. status bit to identify if the last timer interrupt is due to an input capture event. Table 83. Timer 0–2 Control 0 Registers (TxCTL0) Note: x references bits in the range [2:0]. learn more, see the description of the Timer 0–2 Control 1 Registers section on page 180. This field configures timer interrupt definition. This bit is a function of TMODE. 11: Timer Interrupt only on Reload/Compare Events available in the selected mode. 00: All Reload Events and Trigger while counting. 01: Only on timer Input 0 Trigger Events while counting. 10: Only on timer Input 1 Trigger Events while counting. 00: All Reload and Trigger while counting Events. 01: Only on same input Trigger Events while counting. 10: Only on input Trigger Events while counting by the input that did not trigger counting.

timers, set the prescaler value, and determine the timer operating mode. before the Timer Output and the Timer Output Complement is forced to their active state. This bit should be ignored when TICONFIG=1x. Table 84. Timer 0–2 Control 1 Registers (TxCTL1) Note: x references bits in the range [2:0]. Operation of this field is a function of the current operating modes of the timer. timer is enabled, the Timer Output signal is complemented upon timer reload.

PS029413-0921 P R E L I M I N A R Y Timer Register Definitions Z8 Encore! XP® F6482 Series Product Specification 181 [6] TPOL (cont’d) Continuous Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer reload. Counter Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer reload. : Count occurs on the rising edge of the Timer Input 0 signal. 1: Count occurs on the falling edge of the Timer Input 0 signal. PWM Single Output Mode 0: Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) on PWM count match and forced Low (0) on Reload. 1: Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) on PWM count match and forced High (1) on Reload. Capture Mode 0: Count is captured on the rising edge of the Timer Input 0 signal. 1: Count is captured on the falling edge of the Timer Input 0 signal. Compare Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented on timer reload. Gated Mode 0: Timer counts when the Timer Input 0 signal is High (1) and interrupts are generated on the falling edge of the Timer Input 0 signal. 1: Timer counts when the Timer Input 0 signal is Low (0) and interrupts are generated on the rising edge of the Timer Input 0 signal. Capture/Compare Mode 0: Counting is started on the first rising edge of the Timer Input 0 signal. The current count is captured on subsequent rising edges of the Timer Input 0 signal. 1: Counting is started on the first falling edge of the Timer Input 0 signal. The current count is captured on subsequent falling edges of the Timer Input 0 signal. Bit Description (Continued)

PS029413-0921 P R E L I M I N A R Y Timer Register Definitions Z8 Encore! XP® F6482 Series Product Specification 182 [6] TPOL (cont’d) PWM Dual Output Mode : Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. When enabled, the Timer Output Complement is forced Low (0) upon PWM count match and forced High (1) upon Reload. The PWMD field in Timer Control 0 Register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to High (1). 1: Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. When enabled, the Timer Output Complement is forced High (1) upon PWM count match and forced Low (0) upon Reload. The PWMD field in Timer Control 0 Register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to Low (0). Capture Restart Mode 0: Count is captured on the rising edge of the Timer Input 0 signal. 1: Count is captured on the falling edge of the Timer Input 0 signal. Comparator Counter Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer reload. Triggered One-Shot Mode and Dual Input Triggered One-Shot Mode OUTCTL = 0 : Timer counting is triggered on the rising edge of the Timer Input 0 signal. 1: Timer counting is triggered on the falling edge of the Timer Input 0 signal. OUTCTL = 1 0: Timer counting is triggered on the rising edge of the Timer Input 0 signal. 1: Reserved. Demodulation Mode This functionality applies only if TPOLHI bit in Timer Control 2 Register is 0. If TPOLHI bit is 1 then timer counting is triggered on any edge of the Timer Input 0 signal and the current count is captured on both edges. The current count is captured into PWM0 registers on rising edges and PWM1 registers on falling edges of the Timer Input 0 signal. : Timer counting is triggered on the rising edge of the Timer Input 0 signal. The current count is captured into PWM0 High and Low byte registers on subsequent rising edges of the Timer Input 0 signal. 1: Timer counting is triggered on the falling edge of the Timer Input 0 signal. The current count is captured into PWM1 High and Low byte registers on subsequent falling edges of the Timer Input 0 signal. Bit Description (Continued)

PS029413-0921 P R E L I M I N A R Y Timer Register Definitions Z8 Encore! XP® F6482 Series Product Specification 183 [5:3] PRES Prescale Value The timer input clock is divided by 2PRES; PRES can be set from 0 to 7. The prescaler is reset each time the Timer is disabled. This insures proper clock division each time the Timer is restarted. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 [2:0] TMODE[2:0] Timer Mode This field, along with the TMODE[3] bit in the TxCTL0 Register, determines the operating mode of the timer. TMODE[3:0] selects among the following modes: 0000 = One-Shot Mode. 0001 = Continuous Mode. 0010 = Counter Mode. 0011 = PWM Single Output Mode. 0100 = Capture Mode. 0101 = Compare Mode. 0110 = Gated Mode. 0111 = Capture/Compare Mode. 1000 = PWM Dual Output Mode. 1001 = Capture Restart Mode. 1010 = Dual Input Triggered One-Shot Mode. 1011 = Triggered One-Shot Mode. 1100 = Demodulation Mode. Bit Description (Continued)

clock source and control of timer input polarity in Demodulation Mode. Table 85. Timer 0–2 Control 2 Registers (TxCTL2) Note: x references bits in the range [2:0]. These bits are reserved and must be programmed to 00. affect on a timer reload to 0001h. 1: Writes to the Channel High and Low Byte registers are not buffered when TEN = 1. This bit determines if timer count is triggered and captured on both edges of the input signal. This applies only to Demodulation Mode. determined by TPOL bit in the TxCTL1 Register. Input signal in Demodulation Mode. This bit is reserved and must be programmed to 0. and Dual Input Triggered One-Shot modes. 0: Pulse at reload lasting one timer clock. 1: Pulse from start to reload. Use only when TPOL = 0. 01: Reserved. Defaults to System Clock.

pare event occurrences, overrun errors, noise event occurrences and reload time-out status. Table 86. Timer 0–2 Status Register (TxSTAT) did not match the average data value. This bit is reserved and must be programmed to 0. PWMxEF bit in the TxSTAT Register clears this bit. 1: Capture/Compare Event Flag Overrun. interrupt is due to a reload event. 0: No Reload Time-Out event occurred. 1: A Reload Time-Out event occurred. This bit is reserved and must be programmed to 0. independent of the setting of the timer interrupt enable bit. 0: No Capture/Compare Event occurred for this PWM channel. 1: A Capture/Compare Event occurred for this PWM channel.

able the Timer Noise Filter and set noise filter control. Table 87. Timer 0–2 Noise Filter Control Registers (TxNFC) Note: x references bits in the range [2:0]. 1: Noise Filter is reassigned to Timer(x+1) and filters Event System Timer(x+1) Input 1. designated timer and uses its timer clock. This bit is reserved and must be programmed to 0.

PS029413-0921 P R E L I M I N A R Y Multi-Channel Timer Z8 Encore! XP® F6482 Series Product Specification 187 Chapter 11. Multi-Channel Timer The Multi-Channel timer has a 16-bit up/down counter and a 4-channel Capture/Compare/ PWM channel array. This timer provides multiple synchronous Capture/Compare/PWM channels based on a single timer. The Multi-Channel Timer features include:

• 16-bit up/down timer counter with programmable prescale
• Selectable clock source (system clock or external input pin)
• Count Modulo and Count up/down counter modes
• Four independent capture/compare channels which reference the common timer
• Channel modes: – One-Shot Compare Mode – Continuous Compare Mode – PWM Output Mode –C a p t u r e M o d e
• Event System and external input pin for timer input
• DMA request source 11.1. Architecture Figure 21 shows the Multi-Channel Timer architecture.

Counter registers MCTH and MCTL can be read/written by software. tem input, refer to the Event System chapter on page 411. Figure 21. Multi-Channel Timer Block Diagram

refer to the Event System chapter on page 411. setting the Reload Register to 0. The timer will then stop when the counter next reaches 0. Writing a nonzero value to the Reload Register restarts the timer counting. Register. The timer modes are described below in Table 88. Table 88. Timer Count Modes reset to 0000h and counting resumes.

01 Reserved

10 Count Up/Down Timer counts up to Reload and then counts down to

0000h. The Count up/down cycle continues.

11 Reserved

PS029413-0921 P R E L I M I N A R Y Captur e/Compare Channel Operation Z8 Encore! XP® F6482 Series Product Specification 191 11.3. Capture/Compare Channel Operation The Multi-Channel timer supports four Capture/Compare channels: CHA, CHB, CHC, and CHD. Each channel has the following features:

• A 16-bit Capture/Compare Register (MCTCHyH and MCTCHyL registers) used to capture input event times or to generate time intervals. Any user software update of the Capture/Compare Register value when the timer is running takes effect only at the end of the counting cycle, not immediately. The end of the counting cycle is when the counter transitions from the reload value to 0 (Count Modulo Mode) or from 1 to 0 (Count Up/Down Mode).
• A dedicated bidirectional GPIO pin (T4CHA, B, C, or D) and Event System input/ output that can be configured for the input capture function or to generate an output compare match or one-shot pulse. Each channel is configured to operate in either One-Shot Compare, Continuous Compare, PWM Output, or Capture Mode. 11.3.1. One-Shot Compare Operation In One-Shot Compare operation, a channel interrupt is generated when the channel com- pare value matches the timer count. The channel event flag, CHyEF, is set in the Channel Status 1 Register (MCTCHS1) to identify the responsible channel. Then the channel is automatically disabled. The timer continues counting according to the programmed mode. The channel output (TOutA, B, C, or D) changes state for one system clock cycle (from Low to High then back to Low or High to Low then back to High as determined by the CHPOL bit) on match. 11.3.2. Continuous Compare Operation In Continuous Compare operation, a channel interrupt is generated when the channel com- pare value matches the timer count. The channel event flag (CHyEF) is set in the Channel Status1 Register (MCTCHS1) and the channel remains enabled. The timer continues counting according to the programmed mode. The channel output (TOutA, B, C, or D) changes state (from Low to High then back to Low, or High to Low then back to High as determined by the CHPOL bit) on match. For proper operation, configure the CHPOL bit prior to setting the CHEN bit. 11.3.3. PWM Output Operation In PWM Output operation, the timer generates a PWM output signal on the channel output (TOutA, B, C, or D). The channel output toggles whenever the timer count matches the channel compare value (defined in the MCTCHyH and MCTCHyL) registers. In addition, a channel interrupt is generated and the channel event flag is set in the status register. The timer continues counting according to its programmed mode.

PS029413-0921 P R E L I M I N A R Y Multi-Channel Timer Interrupts and DMA Z8 Encore! XP® F6482 Series Product Specification 192 The channel output signal begins with the output value = CHPOL and then transitions to CHPOL when timer value matches the PWM value. If the timer mode is Count Modulo Mode, the channel output signal returns to output = CHPOL when timer reaches the reload value and is reset. If the timer mode is Count Up/Down Mode, channel output signal returns to output = CHPOL when the timer count matches the PWM value again (when counting down). For proper operation, configure the CHPOL bit prior to setting the CHEN bit. 11.3.4. Capture Operation In Capture operation, the current timer count is recorded when the selected transition occurs on TInA, B, C or D. The Capture count value is written to the Channel High and Low Byte registers. In addition, a channel interrupt is generated and the channel event flag (CHyEF) is set in the Channel Status Register. The CHPOL bit in the Channel Control Register determines if the Capture occurs on a rising edge or a falling edge of the Channel Input signal. The timer continues counting according to the programmed mode. 11.4. Multi-Channel Timer Interrupts and DMA The Multi-Channel Timer provides a single interrupt which has five possible sources. These sources are the internal timer and the four timer channels. 11.4.1. Timer Interrupt If enabled by TCIEN bit of the MCTCTL0 Register, the timer interrupt will be generated when the timer completes a count cycle. This occurs during transition from counter = reload register value to counter = 0 in Count Modulo Mode, and occurs during transition from counter = 1 to counter = 0 in Count Up/Down Mode. 11.4.2. Channel Interrupts If enabled by the CHIEN bit of the MCTCHyCTL Register, a channel interrupt is gener- ated when the channel compare value matches the timer count while in one of the follow- ing channel modes: One-Shot Compare, Continuous Compare, or PWM Output. In Capture operation, a channel interrupt is generated whenever there is a successful Cap- ture Event on the Timer Channel. 11.4.3. DMA DMA request is asserted whenever the MCT asserts interrupt request due to a channel interrupt. This provides a mechanism for DMA transfers to be triggered by the Timer. Each MCT DMA request results in a single-byte DMA transfer. DMA request is cleared when the DMA services the request or whenever the MCT channel is disabled. Zilog does

PS029413-0921 P R E L I M I N A R Y Low-Power Modes Z8 Encore! XP® F6482 Series Product Specification 193 not recommend DMA for One-Shot Compare operation, because upon a channel interrupt, the channel is disabled, thereby clearing its DMA request.

• DMA request behavior is a function of channel mode. The behavior in the first paragraph under DMA would pertain to all modes except Capture Mode. 11.5. Low-Power Modes 11.5.1. Operation in Halt Mode When the eZ8 CPU is operating in Halt Mode, the Multi-Channel Timer will continue to operate if enabled. To minimize current in Halt Mode, the Multi-Channel Timer must be disabled by clearing the TEN control bit. 11.5.2. Operation in Stop Mode When the eZ8 CPU is operating in Stop Mode, the Multi-Channel Timer ceases to operate as the System Clock is stopped. The registers are not reset and operation will resume after Stop-Mode Recovery occurs. 11.5.3. Power Reduction During Operation Deassertion of the TEN bit will inhibit clocking of the entire Multi-Channel Timer block. Deassertion of the CHEN bit of individual channels will inhibit clocking of channel spe- cific logic to minimize power consumption of unused channels. The CPU can still read/ write registers when the enable bit(s) are deasserted. 11.6. Multi-Channel Timer Application Examples 11.6.1. PWM Programmable Deadband Generation The Count Up/Down Mode supports motor control applications that require dead time between output signals. Figure 24 shows dead-time generation between two channels operating in Count Up/Down Mode.

tus 0, Channel Status 1, Channel-y Control, Channel-y High- and Low-Byte registers. ters can be directly accessed. Figure 25. Count Max Mode with Channel Compare Table 89. Multi-Channel Timer Address Map

counting from the new value.

0 Timer Control 0

1 Channel Status 0

2 Channel A Capture/Compare High

3 Channel B Capture/Compare High

4 Channel C Capture/Compare High

5 Channel D Capture/Compare High

0 Timer Control 1

1 Channel Status 1

2 Channel A Capture/Compare Low

3 Channel B Capture/Compare Low

4 Channel C Capture/Compare Low

0 Reserved

1 Reserved

2 Channel A Control

3 Channel B Control

4 Channel C Control

5 Channel D Control

Table 89. Multi-Channel Timer Address Map (Continued)

MCT High and Low Byte registers are not reset when TEN = 0. reaches the end of the count cycle. operation allows simultaneous updates of the 16-bit MCT reload value. Table 90. MCT High Byte Register (MCTH) Table 91. MCT Low Byte Register (MCTL) These 2 bytes, {MCTH[7:0], MCTL[7:0]}, contain the current 16-bit MCT count value.

access the subregister by writing or reading subregisters 0, 1, or 2. Table 92. MCT Reload High Byte Register (MCTRH) Table 93. MCT Reload Low Byte Register (MCTRL) the MCT period in the Modulo and Up/Down Count modes. Table 94. MCT Subaddress Register (MCTSA)

selects the subregister to be written to or read from. Table 95. MCT Subregister x (MCTSRx) Note: x references bits in the range [2:0]. Table 96. Multi-Channel Timer Control 0 Register (MCTCTL0) 0: Timer count cycle is not complete. 1: Timer count cycle is complete.

PS029413-0921 P R E L I M I N A R Y Multi-Channel Timer Control Register D efinitions Z8 Encore! XP® F6482 Series Product Specification 200 The input frequency of the timer input signal must not exceed one-fourth of the system clock frequency. [6] CHST Channel Status This bit indicates if a channel Capture/Compare event occurred. This bit is the logical OR of the CHyEF bits in the MCTCHS1 Register. This bit is cleared when TEN = 0. 0: No channel capture/compare event has occurred. 1: A channel capture/compare event has occurred. One or more of the CHDEF, CHCEF, CHBEF, and CHAEF bits in the MCTCHS1 Register are set. [5] TCIEN Timer Count Interrupt Enable This bit enables generation of timer count interrupt. A timer count interrupt is generated whenever the timer completes a count cycle: counting up to Reload Register value or counting down to zero depending on whether the time r mode is Count Modulo or Count up/ down. 0: Timer Count Interrupt is disabled. 1: Timer Count Interrupt is enabled. [4:3] Reserved These bits are reserved and must be programmed to 00. [2:0] TCLKS Timer Clock Source 000: System Clock (prescaling enabled). 001: Reserved. 010: System Clock gated by active High Timer Input signal (Prescaling enabled). 011: System Clock gated by active Low Timer Input signal (Prescaling enabled). 100: Timer input rising edge (Prescaler disabled). 101: Timer input falling edge (Prescaler disabled). 110: Reserved. 111: Reserved. Bit Description (Continued) Note:

Table 97. Multi-Channel Timer Control 1 Register (MCTCTL1) 0: Timer is disabled and the counter is reset. 1: Timer is enabled to count. This bit is reserved and must be programmed to 0. applied when the alternate function input pin is selected as the timer clock source. This bit is reserved and must be programmed to 0. 0000h. The count up and count down cycles continue.

Table 98. Multi-Channel Timer Channel Status 0 Register (MCTCHS0) These bits are reserved and must be programmed to 0000. TEN = 0 (TEN is the MSB of MCTCTL1). 1: Capture/Compare Event Flag Overrun. Table 99. Multi-Channel Timer Channel Status 1 Register (MCTCHS1) These bits are reserved and must be programmed to 0000.

enable channel interrupts, and select the channel mode of operation. (TEN is the MSB of MCTCTL1). 0: No Capture/Compare event occurred for this channel. 1: A Capture/Compare event occurred for this channel. Table 100. Multi-Channel Timer Channel Control Register (MCTCHyCTL)

PS029413-0921 P R E L I M I N A R Y Multi-Channel Timer Control Register D efinitions Z8 Encore! XP® F6482 Series Product Specification 204 [6] CHPOL Channel Input/Output Polarity Operation of this bit is a function of the current operating mode of the channel. For Continuous Compare and PWM Output operation, configure this bit prior to setting the CHEN bit. One-Shot Operation When the channel is disabled, the Channel Output signal is set to the value of this bit. When the channel is enabled, the Channel Output signal toggles for one system clock on reaching the Channel Capture/Compare Register value. Continuous Compare Operation When the channel is disabled, the Channel Output signal is set to the value of this bit. When the channel is enabled, the Channel Output signal toggles (from Low to High or High to Low) on reaching the Channel Capture/Compare Register value. PWM Output Operation 0: Channel Output is forced Low when the channel is disabled. When enabled, the Channel Output is forced High on Channel Capture/Compare Register value match and forced Low on reaching the Timer Reload Register value (Modulo Mode) or counting down through the channel Capture/Compare register value (Count Up/Down Mode). 1: Channel Output is forced Low when the channel is disabled. When enabled, the Channel Output is forced High on Channel Capture/Compare Register value match and forced Low on reaching the Timer Reload Register value (Modulo Mode) or counting down through the channel Capture/Compare register value (Count Up/Down Mode). Capture Operation 0: Count is captured on the rising edge of the Channel Input signal. 1: Count is captured on the falling edge of the Channel Input signal. [5] CHIEN Channel Interrupt Enable This bit enables generation of channel interrupt. A channel interrupt is generated whenever there is a capture/compare event on the Timer Channel. 0: Channel interrupt is disabled. 1: Channel interrupt is enabled. [4] CHUE Channel Update Enable This bit determines whether writes to the Channel High and Low Byte registers are buffered when TEN = 1. Writes to these registers are not buffered when TEN = 0 regardless of the value of this bit. 0: Writes to the Channel High and Low Byte registers are buffered when TEN = 1, and only take affect on the next end-of-cycle count. 1: Writes to the Channel High and Low Byte registers are not buffered when TEN = 1. [3] Reserved This bit is reserved and must be programmed to 0. Bit Description (Continued) Note: y = A, B, C, D.

and loading of the registers is delayed till the next timer end count, unless CHUE = 1. modes, see the Count Up/Down Mode section on page 190. Table 101. Multi-Channel Timer Channel-y High Byte Registers (MCTCHyH) Table 102. Multi-Channel Timer Channel-y Low Byte Registers (MCTCHyL) desired Channel Input transition occurs.

• Clocked by the Watchdog Timer Oscillator (WTO)
• A selectable time-out response: System Reset or Interrupt
• 16-bit programmable time-out value 12.1. Operation The WDT is a retriggerable one-shot timer that resets or interrupts the F6482 Series MCU when the WDT reaches its terminal count. The WDT uses the Watchdog Timer Oscillator (WTO) as its clock source. The WDT has only two modes of operation: ON and OFF. After it is enabled, the WDT always counts and must be retriggered to prevent a time-out. An enable can be performed by executing the WDT instruction or by writing the WDT_AO option bit to 0. When 0, The WDT_AO bit enables the WDT to operate contin- uously, even if a WDT instruction has not been executed. The WDT is a 16-bit reloadable downcounter that uses two 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is calculated using the following equation: In the above equation, the WDT reload value is computed using {WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC Oscillator frequency is 10 kHz. Users must consider system requirements when selecting the time-out delay. Table 103 indicates the approximate time-out delays for the default and maximum WDT reload values.

Table 103. Watchdog Timer Approximate Time-Out Delays 0400 1024 102 ms Reset default value time-out delay. FFFF 65,536 6.55 s Maximum time-out delay.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 207 12.1.1. Watchdog Timer Retrigger When first enabled, the WDT is loaded with the value in the WDT Reload registers. The WDT then counts down to 0000h unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT reload value stored in the WDT Reload registers. Counting resumes following the reload operation. When the eZ8 CPU is operating in DEBUG Mode (through the OCD), the WDT is contin- uously retriggered to prevent unnecessary WDT time-outs. 12.1.2. Watchdog Timer Time-Out Response The WDT times out when the counter reaches 0000h. A time-out of the WDT generates either an interrupt or a System Reset. The WDT_RES option bit determines the time-out response of the WDT. To learn more about programming the WDT_RES option bit, see the Flash Option Bits chapter on page 542. 12.1.2.1. WDT Interrupt in Normal Operation If it is configured to generate an interrupt when a time-out occurs, the WDT issues an interrupt request to the Interrupt Controller. The WDT status bit in the Reset Status Regis- ter is set. The eZ8 CPU responds to the request by fetching the corresponding interrupt vector and executing code from the vector address. After time-out and interrupt genera- tion, the WDT rolls over and continues counting. To clear the WDT interrupt, clear the WDT bit in the Reset Status Register. 12.1.2.2. WDT Interrupt in Stop Mode The WDT automatically initiates a Stop-Mode Recovery and generates an interrupt request if configured to generate an interrupt when a time-out occurs and the CPU is in Stop Mode. Both the WDT status bit and the STOP bit in the Reset Status Register are set to 1 following a WDT time-out in Stop Mode. After time-out and interrupt generation, the WDT rolls over and continues counting. Upon completion of the Stop-Mode Recovery, the eZ8 CPU responds to the interrupt request by fetching the corresponding interrupt vector and executing code from the vector address. To clear the WDT interrupt, clear the WDT bit in the Reset Status Register. 12.1.2.3. WDT Reset in Normal Operation The WDT forces the device into the Reset state if it is configured to generate a System Reset when a time-out occurs; the WDT status bit is set to 1 (for details, see the Reset Sta- tus Register (RSTSTAT) on page 48). For more information about System Reset and the WDT status bit, see the Reset, Stop-Mode Recovery and Low-V oltage Detection chapter on page 38. Following a System Reset, the WDT Counter is initialized with its reset value.

PS029413-0921 P R E L I M I N A R Y Watch dog Timer Register Definitions Z8 Encore! XP® F6482 Series Product Specification 208 12.1.2.4. WDT Reset in Stop Mode If enabled in Stop Mode and configured to generate a System Reset when a time-out occurs and the device is in Stop Mode, the WDT initiates a Stop-Mode Recovery. Both the WDT status bit and the STOP bit in the Reset Status Register (RSTSTAT) (see page 48) are set to 1 following a WDT time-out in Stop Mode. For more information, see the Reset, Stop-Mode Recovery and Low-V oltage Detection section on page 38. 12.1.3. Watchdog Timer Reload Unlock Sequence Writing the unlock sequence to the Watchdog Timer Reload High (WDTH) Register address unlocks the two Watchdog Timer Reload registers (WDTH and WDTL) to allow changes to the time-out period. These write operations to the WDTH Register address pro- duce no effect on the bits in the WDTH Register. The locking mechanism prevents unwar- ranted writes to the Reload registers. The following sequence is required to unlock the Watchdog Timer Reload registers (WDTH and WDTL) for write access. 1. Write 55h to the Watchdog Timer Reload High Register (WDTH). 2. Write AAh to the Watchdog Timer Reload High Register (WDTH). 3. Write the appropriate value to the Watchdog Timer Reload High Register (WDTH). 4. Write the appropriate value to the Watchdog Timer Reload Low Register (WDTL). When this write occurs, the Watchdog Timer Reload registers are again locked. All steps of the WDT Reload Unlock sequence must be written in the order defined above. The values in these WDT Reload registers are loaded into the counter every time a WDT instruction is executed. 12.2. Watchdog Timer Register Definitions The two Watchdog Timer Reload registers (WDTH and WDTL) are described in the fol- lowing tables. 12.2.1. Watchdog Timer Reload High and Low Byte Registers The Watchdog Timer Reload High and Low Byte (WDTH, WDTL) registers, shown in Tables 104 and 105, form the 16-bit reload value that is loaded into the Watchdog Timer when a WDT instruction executes; this 16-bit reload value is {WDTH[7:0], WDTL[7:0]}. Writing to these registers following the unlock sequence sets the appropriate reload value. Reading from these registers returns the current WDT count value.

Table 104. Watchdog Timer Reload High Byte Register (WDTH = FF2h) Table 105. Watchdog Timer Reload Low Byte Register (WDTL = FF3h)

The Real-Time Clock (RTC) provides both Calendar Mode and Counter Mode operation.

• Selectable Calendar Mode or Counter Mode
• Four selectable clock sources
• Clock prescaler with optional automatic prescaler configuration for clock sources at 32.768 kHz, 60 Hz, and 50 Hz 13.3. Architecture A simplified block diagram of the RTC is shown in Figure 26.

Figure 26. Real-Time Clock Block Diagram

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 211 13.4. Operation 13.4.1. Calendar Mode Operation In Calendar Mode (MODE = 0), The Real-Time Clock maintains time by keeping count of seconds, minutes, hours, day-of-the-week, day-of-the-month, month and year. The current time is kept in a 24-hour format. The format for all count and alarm registers is selectable between binary and binary-coded decimal (BCD) operations. The calendar operation maintains the correct day-of-the-month. Compensation for leap year must be performed by software. 13.4.2. Counter Mode Operation In Counter Mode (MODE = 1), four of the RTC counter registers are cascaded to form a 32-bit counter. An alarm can be configured by loading the RTC alarm registers with the appropriate alarm values and by selecting which counter bytes are enabled for matching in the RTC Alarm Control Register. The counter registers that are utilized in Counter Mode are: RTC_SEC (Byte 3, MSB), RTC_MIN (Byte 2), RTC_HRS (Byte 1), and RTC_DOM (Byte 0, LSB). The corresponding alarm registers that are utilized in Counter Mode are: RTC_ASEC (Byte 3, MSB), RTC_AMIN (Byte 2), RTC_AHRS (Byte 1), and RTC_ADOM (Byte 0, LSB). 13.4.3. Real-Time Clock Alarm The clock is programmed to generate an alarm condition when the current count matches the alarm set-point registers. In Calendar Mode (MODE = 0), alarm registers are available for seconds, minutes, hours, day-of-the-week, and day-of-the-month. In Counter Mode (MODE = 1), alarms are available for each of the 4 bytes that comprise the 32-bit counter. Each alarm is independently enabled. To generate an alarm condition, the current time must match all enabled alarm values. For example, if the day-of-the-week and hour alarms are both enabled, the alarm only occurs at a specified hour on a specified day. The alarm triggers an interrupt if configured to do so in the Interrupt Controller. The alarm status, ALARM, is set if the alarm condition is currently met. Alarm value registers and alarm control registers are written at any time. Alarm conditions are generated when the count value matches the alarm value. The comparison of alarm and count values occurs whenever the RTC count increments. With automatically configured prescaling (FREQ_SEL) of 32,768 kHz, 50 Hz, or 60 Hz, the RTC count increments one time every second. The RTC is also forced to perform a comparison at any time by writing a 1 to the RTC_LOCK bit (the RTC_LOCK bit is not required to be changed to a 0 first). 13.4.4. Real-Time Clock Source Selection The RTC can be driven by four possible clock sources: PCLK (CLK_SEL = 00). Selecting the 32.768 kHz clock source (FREQ_SEL = 00) automat- ically configures the clock prescaler for this frequency.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 212 W T O ( C L K _ S E L = 0 1 ) . When WTO is selected, the RTC is typically run in Counter Mode (MODE = 1) with selectable clock prescaler setting (FREQ_SEL = 11). SYSCLK (CLK_SEL = 10). When SYSCLK is selected, the RTC is typically run in Coun- ter Mode (MODE = 1) with selectable clock prescaler setting (FREQ_SEL = 11). Event In (CLK_SEL = 11). The Event System can be configured to connect Event In to a GPIO that serves as a 50 Hz or 60 Hz power-line clock source via an Event System chan- nel. Automatic configuration of the clock prescaler for a power-line clock source is pro- vided via FREQ_SEL= 01 or 10. The clock source and clock frequencies are selected in the RTCTIM Register. This register is read/write when the RTC is unlocked (RTC_LOCK = 0) and read-only when the RTC is locked (RTC_LOCK = 1). 13.4.5. Synchronous Reading of the Real Time Clock Counts With an automatically-configured prescaling (FREQ_SEL) of 32,768 kHz, 50 Hz, or 60Hz, the RTC count increments one time every second. To read counts while the RTC is enabled (RTC_LOCK = 1), the sync bit should be consulted. If SYNC = 0, counts are static and safe to read. If SYNC = 1, counts may not be static. When the prescaler is configured directly (FREQ_SEL = 11) and the RTC is enabled (RTC_LOCK = 1), the sync bit is set (SYNC = 1). In this case, to validate the reading of counts, a second read should be compared with the initial read. When the RTC is disabled (RTC_LOCK = 0) and counting has ceased, the sync bit is reset ( S Y N C = 0 ) . 13.4.6. Real-Time Clock Recommended Operation Following a Power-On Reset (POR), the counter values of the RTC are undefined and all alarms are disabled. Zilog recommends initializing the Real-Time Clock:

• Write to RTC_CTRL to clear RTC_LOCK to disable the RTC counter; while unlocked, the clock prescaler is reset
• Write values to the Real Time Clock Timing Register (RTC_TIM) to select clock source and frequency
• Write values to the RTC count registers to set the current time
• Write values to the RTC alarm registers to set the appropriate alarm conditions
• Write to RTC_CTRL to set RTC_LOCK; setting RTC_LOCK enables the clock pres- caler 13.4.7. Real-Time Clock Enable and Count Register Writing The RTC_LOCK control bit controls enabling RTC counting as well as write access to the RTC count registers and the RTC Timing Register (RTC_TIM). When unlocked

The Real-Time Clock control registers are defined in this section. locked, and read/write if the RTC is unlocked. Table 106. Real-Time Clock Seconds Register (RTC_SEC) Note: *X = undefined; R/W = read-only if RTC is locked, read/write if RTC is unlocked. 0: This bit is reserved and must be programmed to 0. Values 0–5 represent the tens digit of the current seconds count. Values 0–9 represent the ones digit of the current seconds count.

locked, and read/write if the RTC is unlocked. These bits are reserved and must be programmed to 00. Values 00h–3Bh represent the current seconds count. Values 00h–FFh represent Counter byte 3 (MSB). Table 107. Real-Time Clock Minutes Register (RTC_MIN) Note: X = undefined; R/W = read-only if RTC locked, read/write if RTC unlocked. This bit is reserved and must be programmed to 0. Values 0–5 represent the tens digit of the current minutes count.

PS029413-0921 P R E L I M I N A R Y Real-Tim e Clock Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 215 13.5.3. Real-Time Clock Hours Register This register contains the current hours count. The value in the RTC_HRS Register, shown in Table 108, is unchanged by a Power-On Reset (POR). The current setting of BCD_EN determines whether the values in this register are binary (BCD_E N = 0 ) o r b i n a r y - c o d e d decimal (BCD_EN = 1). Access to this register is read-only if the RTC is locked, and read/ write if the RTC is unlocked. [3:0] MIN Current Minutes Ones Values 0–9 represent the ones digit of the current minutes count. Binary Operation (BCD_EN = 0, MODE = 0) [7:6] Reserved These bits are reserved and must be programmed to 00. [5:0] MIN Current Minutes Values 00h–3Bh represent the current minutes count. Counter Mode Operation (BCD_EN = X, MODE = 1) [7:0] MIN Minutes Count Values 00h–FFh represent Counter byte 2. Bit Description (Continued) Binary-Coded Decimal Operation (BCD_EN = 1, MODE = 0) (Continued)

Table 108. Real-Time Clock Hours Register (RTC_HRS) Note: X = undefined; R/W = read-only if RTC locked, read/write if RTC unlocked. These bits are reserved and must be programmed to 00. Values 0–2 represent the tens digit of the current hours count. Values 0–9 represent the ones digit of the current hours count. These bits are reserved and must be programmed to 000. Values 00h–17h represent the current hours count. Values 00h–FFh represent Counter byte 1.

Table 109. Real-Time Clock Day-of-the-Month Register (RTC_DOM ) Note: X = undefined; R/W = read-only if RTC locked, read/write if RTC unlocked. These bits are reserved and must be programmed to 00. Values 0–3 represent the tens digit of the current day-of-the-month count. Values 0–9 represent the ones digit of the current day-of-the-month count. These bits are reserved and must be programmed to 000. Values 01h–1Fh represent the current day-of-the-month count. Values 00h–FFh represent Counter byte 0 (LSB).

register is read-only if the RTC is locked, and read/write if the RTC is unlocked. Table 110. Real-Time Clock Day-of-the-Week Register (RTC_DOW) Note: X = undefined; R = read-only; R/W = read-only if RTC locked, read/write if RTC unlocked. These bits are reserved and must be programmed to 00000. Values 1–7 represent the current day-of-the-week count. These bits are reserved and must be programmed to 00000. Values 01h–07h represent the current day-of-the-week count.

to this register is read-only if the RTC is locked, and read/write if the RTC is unlocked. Table 111. Real-Time Clock Month Register (RTC_MON ) Note: X = undefined; R/W = read-only if RTC locked, read/write if RTC unlocked. These bits are reserved and must be programmed to 000. Values 0–1 represent the tens digit of the current month count. Values 0–9 represent the ones digit of the current month count. These bits is reserved and must be programmed to 0000. Values 1h–Ch represent the current month count.

write if the RTC is unlocked. Table 112. Real-Time Clock Year Register (RTC_YR ) Note: X = undefined; R/ W = read-only if RTC locked, read/write if RTC unlocked. Values 0–9 represent the tens digit of the current year count. Values 0–9 represent the ones digit of the current year count. This bit is reserved and must be programmed to 0. Values 00h–63h represent the current year count.

binary-coded decimal (BCD_EN = 1). Table 113. Real-Time Clock Alarm Seconds Register (RTC_ASEC ) Note: X = undefined; R/W = read/write. This bit is reserved and must be programmed to 0. Values 0–5 represent the tens digit of the alarm seconds value. Values 0–9 represent the ones digit of the alarm seconds value. These bits are reserved and must be programmed to 00. Values 00h–3Bh represent the alarm seconds value. Values 00h–FFh represent the most-significant byte of Counter Mode Alarm, Byte 3.

binary-coded decimal (BCD_EN = 1). Table 114. Real-Time Clock Alarm Minutes Register (RTC_AMIN) Note: X = undefined; R/W = read/write. This bit is reserved and must be programmed to 0. Values 0–5 represent the tens digit of the alarm minutes value. Values 0–9 represent the ones digit of the alarm minutes value. These bits are reserved and must be programmed to 00. Values 00h–3Bh represent the alarm minutes value. Values 00h–FFh represent Counter Mode Alarm Byte 2.

binary-coded decimal (BCD_EN = 1). Table 115. Real-Time Clock Alarm Hours Register (RTC_AHRS ) Note: X = undefined; R/W = read/write. These bits are reserved and must be programmed to 00. Values 0–2 represent the tens digit of the alarm hours value. Values 0–9 represent the ones digit of the alarm hours value. These bits are reserved and must be programmed to 000. Values 00h–17h represent the alarm hours value. Values 00h–FFh represent Counter Mode Alarm Byte 1.

Table 116. Real-Time Clock Alarm Day-of-the-Month Register (RTC_ADOM) Note: X = undefined; R = read-only; R/W = read/write. These bits are reserved and must be programmed to 00. Values 0–3 represent the tens digit of the alarm day-of-the-month value. Values 0–9 represent the ones digit of the alarm day-of-the-month value. These bits are reserved and must be programmed to 000. Values 00h–1Eh represent the alarm date. Values 00h–FFh represent the least-significant byte of Counter Mode Alarm, Byte 0.

Table 117. Real-Time Clock Alarm Day-of-the-Week Register (RTC_ADOW ) Note: X = undefined; R = read-only; R/W = read/write. These bits are reserved and must be programmed to 00000. Values 1–7 represent the alarm day-of-the-week value. These bits are reserved and must be programmed to 00000. Values 01h–07h represent the alarm day-of-the-week.

Clock. This register is cleared by a Power-On Reset (POR). Table 118. Real-Time Clock Alarm Control Register (RTC_ACTRL ) These bits are reserved and must be programmed to 000. 0: The day-of-the-month alarm is disabled. 1: The day-of-the-month alarm is enabled. 0: The day-of-the-week alarm is disabled. 1: The day-of-the-week alarm is enabled. 0: The hours alarm is disabled. 1: The hours alarm is enabled. 0: The minutes alarm is disabled. 1: The minutes alarm is enabled. 0: The seconds alarm is disabled. 1: The seconds alarm is enabled.

PS029413-0921 P R E L I M I N A R Y Real-Tim e Clock Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 227 13.5.14.Real-Time Clock Timing Register The RTC_TIM Register, shown in Table 119, contains timing control for the Real-Time Clock. This register is cleared by a Power-On Reset (POR). Access to this register is read- only if the RTC is locked and read/write if the RTC is unlocked. The CLK_SEL bits select the RTC clock source. Note that the clock source is enabled sep- arately; see the Clock System chapter on page 96 to learn more. If the 32.768 kHz clock frequency option is selected (CLK_FRQ = 00), the internal prescaler is set to divide by 32768. If the power-line frequency option is selected, the prescale value is set according to the selected frequency. Counter Mode Operation (MODE = 1) [7:5] Reserved These bits are reserved and must be programmed to 000. [4] ADOM_EN Byte 0 Alarm Day Of Month Enable 0: The Byte0 alarm is disabled. 1: The Byte0 alarm is enabled. [3] Reserved This bit is reserved and must be programmed to 0. [2] AHRS_EN Byte 1 Alarm Hours Enable 0: The Byte1 alarm is disabled. 1: The Byte1 alarm is enabled. [1] AMIN_EN Byte 2 Alarm Minutes Enable 0: The Byte2 alarm is disabled. 1: The Byte2 alarm is enabled. [0] ASEC_EN Byte 3 Alarm Seconds Enable 0: The Byte3 alarm is disabled. 1: The Byte3 alarm is enabled. Bit Description (Continued)

updated by setting (locking) the RTC_LOCK bit or by an increment of the RTC count. all registers including the alarm set points. Table 119. Real-Time Clock Timing Register (RTC_TIM ) Note: X = undefined; R = read-only; R/W = read/write. This bit is reserved and must be programmed to 0. PRESCALE is utilized only if FREQ_SEL = 11. 00: 32.768kHz. The prescaler is automatically configured for this frequency.

Table 120. Real-Time Clock Control Register (RTC_CTRL ) Note: X = undefined; R = read-only; R/W = read/write. 0: Counts are static and safe to read. be compared with the initial read. This bit is reserved and must be programmed to 0. 0: RTC count and alarm value registers are binary. This bit is reserved and must be programmed to 0. that use DST. No action is performed by the RTC when setting or clearing this bit. 0: Suggested value for Daylight Savings Time not selected. 1: Suggested value for Daylight Savings Time selected. and the clock prescaler is cleared. 1: RTC count registers are locked to prevent write access. RTC counter is enabled. When enabled, the RTC runs in all operating modes, including Stop Mode.

PS029413-0921 P R E L I M I N A R Y UART-LDD Z8 Encore! XP® F6482 Series Product Specification 230 Chapter 14. UART-LDD The Local Interconnect Network Universal Asynchronous Receiver/Transmitter (UART- LDD) is a full-duplex communication channel capable of handling asynchronous data transfers in standard UART applications and providing LIN, DALI, and DMX protocol support. The UART-LDD is a superset of the standard F6482 Series MCU UART, provid- ing all of its standard features, LIN/DALI/DMX protocol support and a digital noise filter. UART-LDD includes the following features:

• 8-bit asynchronous data transfer
• Selectable even- and odd-parity generation and checking
• Option of 1 or 2 stop bits
• Selectable Multiprocessor (9-bit) Mode with three configurable interrupt schemes
• Separate transmit and receive interrupts
• Framing, parity, overrun and break detection
• 16-bit baud rate generator (BRG) which can function as a general-purpose timer with interrupt
• Driver Enable output for external bus transceivers
• LIN protocol support for both Master and Slave modes: – Break generation and detection – Selectable slave autobaud – Check Tx vs. Rx data when sending
• DALI protocol support for both Master and Slave modes: – Biphase data encoding – Slave address matching
• DMX protocol support for both Master and Slave modes: – Slave address matching – Automatic break generation
• Configuring a digital-noise filter on the Receive Data line
• DMA support

Noise Filter. Figure 27 shows the UART-LDD architecture. Figure 27. UART-LDD Block Diagram

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 233 5. Write to the UART-LDD Control 0 Register to: a. Set the Transmit Enable (TEN) bit to enable the UART-LDD for data transmis- sion. b. If parity is appropriate and Multiprocessor Mode is not enabled, set the parity enable (PEN) bit and select either even-or-odd parity (PSEL). c. Set or clear the CTSE bit to enable or disable control from t he remote receiver using the CTS pin. 6. Check the TDRE bit in the UART-LDD Status 0 Register to determine if the Transmit Data Register is empty (indicated by a 1); if empty, continue to Step 7. If the Transmit Data Register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data Register becomes available to receive new data. 7. If operating in Multiprocessor Mode, write to the UART-LDD Control 1 Register to select the outgoing address bit. – Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte; clear it if sending a data byte. 8. Write the data byte to the UAR T-LDD Transmit Data Register. The transmitter auto- matically transfers the data to the Transmit Shift Register and transmits the data. 9. If appropriate – and if Multip rocessor Mode is enabled – changes can be made to the Multiprocessor Bit Transmitter (MPBT) value. 10. To transmit additional bytes, return to Step 5. 14.1.3. Transmitting Data Using Interrupt-Driven Method The UART-LDD Transmitter interrupt indicates the availability of the Transmit Data Reg- ister to accept new data for transmission. Observe the following steps to configure the UART-LDD for interrupt-driven data transmission: 1. Write to the UART-LDD Baud Rate High and Low Byte registers to set the appropri- ate baud rate. 2. Enable the UART-LDD pin functions by configuring the associat ed GPIO port pins for alternate function operation. 3. Execute a DI instructio n to disable interrupts. 4. Write to the interrupt control r egisters to enable the UART-LDD Transmitter interrupt and set the appropriate priority. 5. If Multiprocessor Mode is approp riate, write to the UART-LDD Control 1 Register to enable Multiprocessor (9-bit) Mode functions. 6. Set the Multiprocessor Mode S elect (MPEN) bit to enable Multiprocessor Mode. 7. Write to the UART-LDD Control 0 Register to: a. Set the transmit enable (TEN) bit to enable the UART-LDD for data transmission.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 234 b. If Multiprocessor Mode is not en abled, then enable parity if appropriate and select either even or odd parity. c. Set or clear the CTSE bit to enable or disable control from t he remote receiver via the CTS pin. 8. Execute an EI instruc tion to enable interrupts. The UART-LDD is now configured for interrupt-driven data transmission. Because the UART-LDD Transmit Data Register is empty, an interrupt is generated immediately. When the UART-LDD Transmit interrupt is detected and there is transmit data ready to send, the associated interrupt service routine (ISR) performs the following: 1. If in Multiprocessor Mode, writes to the UART-LDD Control 1 Register to select the outgoing address bit: – Sets the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clears it if sending a data byte. 2. Writes the data byte to the UAR T-LDD Transmit Data Register. The transmitter auto- matically transfers the data to the Transmit Shift Register and transmits the data. 3. Executes the IRET instruction to return from the interrupt-se rvice routine and wait for the Transmit Data Register to again become empty. If a transmit interrupt occurs and there is no transmit data ready to send, the interrupt ser- vice routine executes the IRET instruction. When the application does have data to trans- mit, software can set the appropriate interrupt request bit in the Interrupt Controller to initiate a new transmit interrupt. Another alternative would be for the software to write the data to the Transmit Data Register instead of invoking the interrupt service routine. 14.1.4. Receiving Data Using Polled Method Observe the following steps to configure the UART-LDD for polled data reception: 1. Write to the UART-LDD Baud Rate High and Low Byte registers to set the appropri- ate baud rate. 2. Enable the UART-LDD pin functions by configuring the associat ed GPIO port pins for alternate function operation. 3. If Multiprocessor Mode is approp riate, write to the UART-LDD Control 1 Register to enable Multiprocessor (9-bit) Mode functions. 4. Write to the UART-LDD Control 0 Register to: a. Set the Receive Enable (REN) bi t to enable the UART-LDD for data reception.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 235 b. If Multiprocessor Mode is not en abled, then enable parity (if appropriate), and select either even or odd parity. 5. Check the RDA bit in the UART-LDD Status 0 Register to determ ine if the Receive Data Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indi- cate available data, continue to Step 6. If the Receive Data Register is empty (indi- cated by a 0), continue to monitor the RDA bit that is awaiting reception of the valid data. 6. Read data from the UART-LDD Receive Data Register. If operating in Multiprocessor (9-bit) Mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0]. 7. Return to Step 5 to receive additional data. 14.1.5. Receiving Data Using the Interrupt-Driven Method The UART-LDD Receiver interrupt indicates the availability of new data (as well as error conditions). Observe the following steps to configure the UART-LDD receiver for inter- rupt-driven operation: 1. Write to the UART-LDD Baud Rate High and Low Byte registers to set the appropri- ate baud rate. 2. Enable the UART-LDD pin functions by configuring the associat ed GPIO port pins for alternate function operation. 3. Execute a DI instructio n to disable interrupts. 4. Write to the Interrupt Control registers to enable the UART-L DD Receiver interrupt and set the appropriate priority. 5. Clear the UART-LDD Receiver in terrupt in the applicable Interrupt Request Register. 6. Write to the UART-LDD Control 1 Register to enable Multiproce ssor (9-bit) Mode functions, if appropriate. a. Set the Multiprocessor Mode S elect (MPEN) bit to enable Multiprocessor Mode. b. Set the Multiprocessor Mode Bits , MPMD[1:0] to select the appropriate address matching scheme. c. Configure the UART-LDD to inte rrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a DMA block). 7. Write the device address to th e Address Compare Register (automatic Multiprocessor modes only). 8. Write to the UART-LDD Control 0 Register to: a. Set the receive enable (REN) b it to enable the UART-LDD for data reception.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 236 b. If Multiprocessor Mode is not en abled, then enable parity (if appropriate) and select either even or odd parity. 9. Execute an EI instruc tion to enable interrupts. The UART-LDD is now configured for interrupt-driven data reception. When the UART- LDD Receiver interrupt is detected, the associated ISR performs the following: 1. Checks the UART-LDD Status 0 Reg ister to determine the source of the interrupt- error, break, or received data. 2. If the interrupt is due to data available, read the data from the UART-LDD Receive Data Register. If operating in Multiprocessor (9-bit) Mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0]. 3. Execute the IRET instruction to return from the ISR and await more data. 14.1.6. Clear To Send Operation The Clear To Send (CTS) pin, if enabled by the CTSE bit of the UART-LDD Control 0 Register, performs flow control on the outgoing transmit data stream. The Clear To Send (CTS) input pin is sampled one system clock before any new character transmission begins. To delay transmission of the next data character, an external receiver must reduce CTS at least one system clock cycle before a new data transmission begins. For multiple character transmissions, this operation is typically performed during the stop bit transmis- sion. If CTS stops in the middle of a character transmission, the current character is sent completely. 14.1.7. External Driver Enable The UART-LDD provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated using a GPIO pin to control the trans- ceiver when communicating on a multitransceiver bus, such as RS-485. Driver Enable is a programmable polarity signal which envelopes the entire transmitted data frame including parity and stop bits, as illustrated in Figure 30. The Driver Enable signal asserts when a byte is written to the UART-LDD Transmit Data Register. The Driver Enable signal asserts at least one bit period, and no greater than two bit periods, before the start bit is transmitted. This assertion allows a set-up time to enable the trans- ceiver. The Driver Enable signal deasserts one system clock period after the last stop bit is transmitted. This system clock delay allows both time for data to clear the transceiver before disabling it, as well as the ability to determine if another character follows the cur- rent character. In the event of back-to-back characters (new data must be written to the Transmit Data Register before the previous character is completely transmitted), the DE signal is not deasserted between characters. The DEPOL bit in the UART-LDD Control Register 1 sets the polarity of the Driver Enable signal.

• Multiprocessor Mode
• LIN Mode
• DALI Mode
• DMX Mode The UART-LDD features a common control register (Control 0) that has a unique register address and several mode-specific control registers (Multiprocessor Control, Noise Filter Control, LIN Control, DALI Control, and DMX Control) that share a common register address (Control 1). When the Control 1 address is read or written, the MSEL[2:0] (Mode Select) field of the Mode Select and Status Register determines which physical register is accessed. Similarly, there are mode-specific status registers, one of which is returned when the Status 0 Register is read, depending on the MSEL field. 14.1.9. Multiprocessor Mode The UART-LDD features a Multiprocessor (9-bit) mode that uses an extra (9th) bit for selective communication when a number of processors share a common UART bus. In Multiprocessor Mode (also referred to as 9-bit mode), the multiprocessor (MP) bit is trans-

Figure 30. UART-LDD Driver Enable Signal Timing with One Stop Bit and Parity

• Interrupt on all address bytes
• Interrupt on matched address bytes and correctly framed data bytes
• Interrupt only on correctly framed data bytes These modes are selected with MPMD[1:0] in the UART-LDD Control 1 Register. For all Multiprocessor modes, the MPEN bit of the UART-LDD Control 1 Register must be set to The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine checks the address byte which triggered the interrupt. If it matches the UART-LDD address, the software clears MPMD[0]. At this point, each new incoming byte interrupts the CPU. The software determines the end of the frame and checks for it by reading the MPRX bit of the UART-LDD Status 1 Register for each incoming byte. If

Figure 31. UART-LDD Asynchronous Multiprocessor Mode Data Format

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 239 MPRX = 1, a new frame begins. If the address of this new frame is different from the UART-LDD’s address, then MPMD[0] must be set to 1 by software, causing the UART- LDD interrupts to go inactive until the next address byte. If the new frame’s address matches the UART-LDD’s address, then the data in the new frame is also processed. The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART- LDD’s address into the UART-LDD Address Compare Register. This mode introduces more hardware control, interrupting only on frames that match the UART-LDD’s address. When an incoming address byte does not match the UART-LDD’s address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an interrupt is issued and further interrupts occur on each successive data byte. The first data byte in the frame has NEWFRM = 1 in the UART-LDD Status 1 Register. When the next address byte occurs, the hardware compares it to the UART-LDD’s address. If there is a match, the interrupt occurs and the NEWFRM bit is set to the first byte of the new frame. If there is no match, the UART-LDD ignores all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART- LDD’s address into the UART-LDD Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame remains accompanied by a NEWFRM assertion. 14.1.10. LIN Protocol Mode The Local Interconnect Network (LIN) protocol, as supported by the UART-LDD module, is defined in Revision 2.0 of the LIN Specification Package. The LIN protocol specifica- tion covers all aspects of transferring information between LIN master and slave devices using message frames, including error detection and recovery, SLEEP Mode and wake up from SLEEP Mode. The UART-LDD hardware in LIN Mode provides character transfers to support the LIN protocol including break transmission and detection, wake-up trans- mission and detection and slave autobauding. Part of the error detection of the LIN proto- col is for both master and slave devices to monitor their receive data when transmitting. If the receive and transmit data streams do not match, the UART-LDD asserts the PLE bit (i.e., the physical layer error bit in the Status 0 Register). The message frame time-out aspect of the protocol depends on software requiring the use of an additional general-pur- pose timer. The LIN Mode of the UART-LDD does not provide any hardware support for computing/verifying the checksum field or verifying the contents of the identifier field. These fields are treated as data and are not interpreted by hardware. The checksum calcu- lation/verification can easily be implemented in software via the Add with Carry (ADC) instruction. The LIN bus contains a single Master and one or more slaves. The LIN master is responsi- ble for transmitting the message frame header which consists of the Break, Synch and Identifier fields. Either the master or one of the slaves transmits the associated response section of the message which consists of data characters followed by a checksum charac- ter.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 240 In LIN Mode, the interrupts defined for normal UART operation still apply with the fol- lowing changes:

• A Parity Error (i.e., the PE bit in the Status 0 Register) is redefined as the Physical Lay- er Error (PLE) bit. The PLE bit indicates that receive data does not match transmit data when the UART-LDD is transmitting. This definition applies to both Master and Slave operating modes.
• The Break Detect interrupt (i.e., the BRKD bit in the Status 0 Register) indicates when a break is detected by the slave (i.e., a break condition for at least 11 bit times). Soft- ware can use this interrupt to start a timer checking for message frame time-out. The duration of the break can be read in the RxBreakLength[3:0] field of the Mode Select and Status Register.
• The Break Detect interrupt (BRKD bit in Status 0 Register) indicates when a wake-up message has been received, if the UART-LDD is in a LIN Sleep state.
• In LIN Slave Mode, if the BRG counter overflows while measuring the autobaud peri- od (from the start bit to the beginning of bit 7 of the autobaud character), an Overrun Error is indicated (OE bit in the Status 0 Register). In this case, software sets the Lin- State field back to 10b, where the slave ignores the current message and waits for the next break. The Baud Reload High and Low registers are not updated by hardware if this autobaud error occurs. The OE bit is also set if a data overrun error occurs. 14.1.10.1. LIN System Clock Requirements The LIN Master provides the timing reference for the LIN network and is required to have a clock source with a tolerance of ± 0.5%. A slave with autobaud capability is required to have a baud clock matching the master oscillator within ±14%. The slave nodes autobaud to lock onto the master timing reference with an accuracy of ±2%. If a slave does not con- tain autobaud capability, it must include a baud clock which deviates from the masters by not more than ±1.5%. These accuracy requirements must include the effects such as volt- age and temperature drift during operation. Before sending/receiving messages, the Baud Reload High/Low registers must be initial- ized. Unlike standard UART modes, the Baud Reload High/Low registers must be loaded with the baud interval rather than 1/16 of the baud interval. To autobaud with the required accuracy, the LIN slave system clock must be at least 100 times the baud rate. 14.1.10.2. LIN Mode Initialization and Operation LIN Protocol Mode is selected by setting either the LIN Master (LMST) or LIN Slave (LSLV) and, optionally (for the LIN slave), the Autobaud Enable (ABEN) bits in the LIN Control Register. To access the LIN Control Register, the Mode Select (MSEL) field of the UART-LDD Mode Select/Status Register must be = 010b. The UART-LDD Control 0 Register must be initialized with TEN = 1, REN = 1 and all other bits = 0.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 241 In addition to the LMST, LSLV and ABEN bits in the LIN Control Register, a Lin- State[1:0] field exists which defines the current state of the LIN logic. This field is initially set by software. In the LIN Slave Mode, the LinState field is updated by hardware as the slave moves through the Wait For Break, AutoBaud and Active states. 14.1.10.3. LIN Master Mode Operation LIN Master Mode is selected by setting LMST = 1, LSLV = 0, ABEN = 0 a n d LinState[1:0] = 11b. If the LIN bus protocol indicates the bus is required go into the LIN Sleep state, the LinState[1:0] bits must be set to 00b by software. The break is the first part of the message frame transmitted by the master, consisting of at least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master, the duration (in bit times) of the break is written to the TxBreakLength field of the LIN Control Register. The transmission of the break is performed by setting the SBRK bit in the Control 0 Register. The UART-LDD starts the break after the SBRK bit is set and any character transmission currently underway has completed. The SBRK bit is deasserted by hardware until the break is completed. If it is necessary to generate a break longer than 15 bit times, the SBRK bit can be used in normal UART Mode, in which software times the duration of the break. The Synch character is transmitted by writing a 55h to the Transmit Data Register (TDRE must = 1 before writing). The Synch character is not transmitted by the hardware until the break is complete. The identifier character is transmitted by writing the appropriate value to the Transmit Data Register (TDRE must = 1 before writing). If the master is sending the response portion of the message, these data and checksum characters are written to the Transmit Data Register when the TDRE bit asserts. If the Transmit Data Register is written after TDRE asserts, but before TXE asserts, the hard- ware inserts one or two stop bits between each character as determined by the stop bit in the Control 0 Register. Additional idle time occurs between characters, if TXE asserts before the next character is written. If the selected slave is sending the response portion of the frame to the master, each receive byte will be signalled by the receive data interrupt (the RDA bit will be set in the Status 0 Register). If the selected slave is sending the response to a different slave, the master can ignore the response characters by deasserting the REN bit in the Control 0 Reg- ister until the frame time slot is completed. 14.1.10.4. LIN Sleep Mode While the LIN bus is in the sleep state, the CPU can either be in low-power Stop Mode, in Halt Mode, or in normal operational state. Any device on the LIN bus can issue a wake-up message if it requires the master to initiate a LIN message frame. Following the wake-up message, the master wakes up and initiates a new message. A wake-up message is accom-

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 242 plished by pulling the bus Low for at least 250 µs but less than 5 ms. Transmitting a 00h character is one way to transmit the wake-up message. If the CPU is in Stop Mode, the UART-LDD is not active and the wake-up message must be detected by a GPIO edge detect Stop-Mode Recovery. The duration of the Stop-Mode Recovery sequence can preclude making an accurate measurement of the wake-up mes- sage duration. If the CPU is in a halt or operational mode, the UART-LDD (if enabled) times the duration of the wake-up and provides an interrupt following the end of the break sequence if the duration is ≥ 3 bit times. The total duration of the wake-up message in bit times can be obtained by reading the RxBreakLength field in the Mode Select and Status Register. After a wake-up message has been detected, the UART-LDD can be placed (by software) either into LIN Master or LIN Slave Wait for Break states, as appropriate. If the break duration exceeds 15 bit times, the RxBreakLength field contains the value Fh. If the UART-LDD is disabled, wake-up message is detected via a port pin interrupt and timed by software. If the device is in Stop Mode, the High to Low transition on the port pin will bring the device out of Stop Mode. The LIN Sleep state is selected by software setting LinState[1:0] = 00. The decision to move from an active state to sleep state is based on the LIN messages as interpreted by software. 14.1.10.5. LIN Slave Operation LIN Slave Mode is selected by setting LMST = 0, LSLV = 1, ABEN = 1 or 0 and LinState[1:0] = 01b (Wait for Break state). The LIN slave detects the start of a new mes- sage by the break which appears to the slave as a break of at least 11 bit times in duration. The UART-LDD detects the break and generates an interrupt to the CPU. The duration of the break is observable in the RxBreakLength field of the Mode Select and Status Register. A break of less than 11 bit times in duration does not generate a break interrupt when the UART-LDD is in a Wait for Break state. If the break duration exceeds 15 bit times, the RxBreakLength field contains the value Fh. Following the break, the UART-LDD hardware automatically transits to the Autobaud state, where it autobauds by timing the duration of the first 8 bit times of the Synch char- acter as defined in the LIN standard. The duration of the autobaud period is measured by the BRG Counter which will update every 8th system clock cycle between the start bit and the beginning of bit 7 of the autobaud sequence. At the end of the autobaud period, the duration measured by the BRG counter (auto baud period divided by 8) is automatically transferred to the Baud Reload High and Low registers if the ABEN bit of the LIN Control Register is set. If the BRG Counter overflows before reaching the start of bit 7 in the auto- baud sequence the Autobaud Overrun Error interrupt occurs, the OE bit in the Status 0 Register is set and the Baud Reload registers are not updated. To autobaud within 2% of the master’s baud rate, the slave system clock must be a minimum of 100 times the baud rate. To avoid an autobaud overrun error, the system clock must not be greater than 219

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 243 times the baud rate (16 bit counter following 3-bit prescaler when counting the 8 bit times of the Autobaud sequence). Following the Synch character, the UART-LDD hardware transits to the Active state, in which the identifier character is received and the characters of the response section of the message are sent or received. The slave remains in this Active state until a break is received or software forces a state change. After it is in an Active state (i.e., autobaud has completed), a break of 10 or more bit times is recognized and causes a transition to the Autobaud state. If the identifier character indicates that this slave device is not participating in the mes- sage, the software sets the LinState[1:0] = 01b (Wait for Break state) to ignore the remain- der of the message. No further receive interrupts will occur until the next break. 14.1.11. DALI Protocol Mode The Digital Addressable Lighting Interface (DALI) protocol, as supported by the UART- LDD module, is defined in IEC62386-201. This DALI protocol specification covers all aspects of transferring information between DALI master and DALI slave devices. The UART-LDD hardware provides character transfers to support the DALI protocol, includ- ing biphase encoding and decoding, message formation, and slave message address extraction for matching with the comparison address (COMP_ADDR). Forward messages from a DALI master to a DALI slave are typically19-bit messages con- sisting of a start bit, an 8-bit address, 8-bit data, and 2 stop bits. The start bit, address byte, and data byte are biphase encoded; stop bits are not biphase encoded. Backward messages from a slave to a master are typically 11 bits consisting of 1 start bit, 8 data bits and 2 stop bits. The slave transmits only upon the request of the master. The DALI start bit is encoded as a logical 1 (a Low to High transition) and the stop bits are High levels. The DALI standard frames and biphase bit encoding are shown in Figure 32.

• A Parity Error (i.e., the PE bit in the Status 0 Register) is replaced with a biphase error, BPE, which indicates that there was a biphase encode error
• The Break Detect interrupt (i.e., the BRKD bit in the Status 0 Register) is not set
• Framing error checking occurs only for single-byte transfers (i.e, MULTRXE = 0 in the DALI Control Register) 14.1.11.1. DALI Clock Requirements Both the DALI master and DALI slaves are required to have a nominal 1.2 kbit/s bit rate with a tolerance of ±10%. Before sending/receiving messages, the Baud Reload High/Low registers must be initial- ized. Unlike standard UART modes, the Baud Reload High/Low registers must be loaded with 1/32 of the baud interval rather than 1/16 of the baud interval.

Figure 32. UART-LDD DALI Standard Frames and Biphase Bit Encoding

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 245 14.1.11.2. DALI Mode Initialization and Operation DALI Protocol Mode is selected by setting either the MULTTXE (multiple-byte transmit enable) or MULTRXE (multiple-byte receive enable) in the DALI Control Register. To access the DALI Control Register, the MSEL (Mode Select) field of the UART-LDD Mode Select/Status Register must be = 100b. The UART-LDD Control 0 Register must be initialized. For DALI transmit operation, configure TEN = 1, STOP = 1 and all other bits = 0. For DALI receive operation, configure REN = 1, STOP = 1 and all other bits = 0. In the DALI Control Register, several bits affect both transmit and receive operation: Biphase Encoding Enable (BPEN). BPEN should be set for DALI operation. DALI Biphase Encoding (BPENC). BPENC has an effect only if BPEN = 1. When BPENC = 0, DALI encoding is performed such that logic 0 is encoded as biphase 1 → 0 and logic 1 is encoded as biphase 0 → 1. When BPENC = 1, alternate encoding is per- formed such that logic 0 is encoded as biphase 0 → 1 and logic 1 is encoded as biphase 1 → 0. Start Bit Polarity (STRTPOL). The start bit value, logic 0 or logic 1, matches the value of this bit. STRTPOL is typically set for DALI. Bit Order (BITORD). Standard UART bit order is selected when BITORD = 0 and the LSB (TxD[0]/RxD[0]) is transmitted/received first. DALI bit order is selected when BITORD = 1 and the MSB (TxD[7]/RxD[7]) is transmitted/received first. DALI Control Register bits that affect only transmit or receive operations are described in the following sections. 14.1.11.3. DALI Transmit Operation The UART-LDD Control 0 Register must be initialized. For DALI transmit operation, configure TEN = 1, STOP = 1 and all other bits = 0. When the MSEL= 100b (Mode Select) in the DALI Control Register, DALI transmit operation can be configured for single-byte or multiple-byte transmission. If MULTTXE = 0 in the DALI Control Register, single-byte transmit is selected and stop bits will be transmitted after each transmitted byte. This set- ting is typically selected for DALI slave response messages that are transmitted to the master. If MULTTXE = 1 in the DALI Control Register, multiple-byte transmit is selected and stop bits will be transmitted only after the last transmitted byte. This setting is typically selected for DALI master operation to send an address byte, followed by one or more data bytes. When the UART-LDD Transmit Data Register is written, the UART-LDD will send a start bit, followed by the 8 bits in the UART-LDD Transmit Data Register. As the data is transmitted, the UART-LDD will assert an interrupt request for the next data byte. If the Transmit Data Register is written after TDRE asserts – but before TXE asserts – the hard- ware will transmit the character in the Transmit Data Register without the intervening stop bits. If TXE asserts before the next character is written in the Transmit Data Register, the DALI Master will transmit two stop bits after the last data bit.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 246 Collision detection is enabled by setting CLSNE in the DALI Control Register. This set- ting is useful for DALI masters in systems with more than one master, because it is possi- ble for more than one master to start a transmission at the same time. When CLSNE is set, the UART-LDD monitors its own transmission. Because Low (i.e., 0) is the dominant state on the DALI bus, collision detection effectively checks to determine if High (i.e., 1) state transmissions are not corrupted. If a collision is detected, CLSN is set in the Status Regis- ter and an interrupt request is generated. 14.1.11.4. DALI Receive Operation The UART-LDD Control 0 Register must be initialized. For DALI receive operation, con- figure REN = 1, STOP = 1 and all other bits = 0. When the MSEL= 100b (Mode Select) in the DALI Control Register, DALI receive operation can be configured for single-byte or multiple-byte reception. If MULTRXE = 0 in the DALI Control Register, single-byte receive is selected, and stop bits will be expected after each transmitted byte. This setting is typically selected for a DALI master that will receive a slave response message. Address match checking is not performed when MULTRXE = 0. If MULTRXE = 1 in the DALI Control Register, multiple-byte receive is selected, and stop bits will be received to signal the end of the transmission. This setting is typically selected for DALI slave operation to receive an address byte followed by one or more data bytes. If PARTRXE is set, and if a partial byte has been received, it will be loaded into the UART-LDD Receive Data Register upon receiving the number of stop bits selected by STOP in the UART-LDD Control 0 Register. Software should determine which bits in the received byte are valid. When MULTRXE = 1 in the DALI Control Register, the start bit is detected as the begin- ning of a new message. The UART-LDD decodes the first byte received as an address, and a status is provided with MODESTAT in the UART-LDD Mode Select and Status Regis- ter, as follows: 0–7Fh. Short address, each DALI slave is assigned a short address (MODESTAT = 001). 80–9Fh. Group address (MODESTAT = 010). A0–FDh. Special or unrecognized command (MODESTAT = 101). FE–FFh. Broadcast (MODESTAT = 100). Address matching for short addresses is performed by hardware, which compares the short address in the received address byte to the value of COMP_ADDR[5:0] stored in the Comparison Address Register. If a short address is received that does not match the value of COMP_ADDR[5:0], the message is ignored. Each DALI slave can belong to as many as 4 groups of the 16 available groups. Software should determine whether the slave belongs to the group for which the message is intended, and whether to process the message.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 247 Except for cases in which messages with short addresses do not match the value of COMP_ADDR[5:0], when each byte is received including the first byte, RDA is set in the UART-LDD Status Register, and an interrupt request is generated. 14.1.11.5. DALI Receive During Stop Mode While the DALI bus is idle, the DALI receiver can either be in low-power Stop Mode, in Halt Mode, or in a normal operational state. While the receiver is in Stop Mode, the UART-LDD is not active, and the start bit must be detected by a GPIO edge-detect Stop- Mode Recovery. A High-to-Low transition on the port pin can be used to bring the device out of Stop Mode. When Stop-Mode Recovery is completed, and if enabled, the UART- LDD will recognize the start bit. The duration of the Stop-Mode Recovery sequence can preclude recognizing the start bit. 14.1.12. DMX Protocol Mode The Asynchronous Serial Digital Data Transmission Standard for Controlling Lighting Equipment and Accessories (DMX) protocol, as supported by the UART-LDD module, is defined in ANSI E1.11-2008. This DMX protocol specification covers all aspects of trans- ferring information from a DMX master to DMX slave devices. The UART-LDD hard- ware provides character transfers to support the DMX protocol, including break transmission and detection, mark after break transmission and detection, and tracking by the DMX slave of the received data slot number for matching with the comparison address (COMP_ADDR). The DMX mode of the UART-LDD also provides hardware support for recognizing a null start code. The DMX bus contains a single master and one or more slaves. The DMX protocol con- sists of a reset sequence followed by up to 512 data slots. The DMX master is responsible for transmitting the reset sequence, which consists of the break, a mark after break, and a start code. The Master then transmits up to 512 DMX data slots. When the start code is the null start code, data values from 0 to 255 are valid. Furthermore, each slave must be con- figured to identify the data slot(s) containing data intended for it. After transmitting the appropriate number of data slots, the DMX master asserts a mark before break. The DMX frame and data slot are shown in Figure 33.

• A Parity Error (i.e., the PE bit in the Status 0 Register) is not applicable. Parity Enable (i.e., the PEN bit in the Control 0 Register) is ignored in DMX Mode.
• Framing error checking is not performed; therefore, the framing error status bit (i.e., the FE bit in the Status 0 Register) is reserved in DMX Mode.
• The Break Detect interrupt (i.e, the BRKD bit in the Status 0 Register) indicates when a break is detected by the slave (a break condition for at least 22 bit times). Software can use this interrupt to start a timer checking for lost data input (loss of data tolerance). 14.1.12.1. DMX Clock Requirements Both a DMX Master and DMX slaves are required to have a nominal 250 kbit/s bit rate with a tolerance of ±2%. Before sending/receiving messages, the Baud Reload High/Low registers must be initialized.

Figure 33. UART-LDD DMX Frame and Data Slot *Minimum of 22.668 ms if all 512 channel slots are sent.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 249 14.1.12.2. DMX Mode Initialization and Operation DMX Protocol Mode is selected by setting either the DMXMST (DMX master) or DMX- SLV (DMX slave) in the DMX Control Register. To access the DMX Control Register, the Mode Select (MSEL) field of the UART-LDD Mode Select/Status Register must be = 101b. The UART-LDD Control 0 Register must be initialized. For DMX Master Mode operation, configure TEN = 1, STOP = 1, and all other bits = 0. For DMX slave oper- a t i o n , c o n f i g u r e R E N = 1 , S T O P = 1 , a n d a l l o t h e r b i t s = 0 . 14.1.12.3. DMX Master Mode Operation When the MSEL= 101b (Mode Select) in the DMX Control Register, DMX Master Mode is selected by setting DMXMST = 1 and DMXSLV = 0 in the DMX Control Register. The break is the first part of the DMX protocol transmitted by the master. Hardware can be selected to generate a break consisting of 24 bit periods of logical zero on the DMX bus by first setting AUTOBRK in the DMX Control Register with SBRK in the Control 0 Register cleared. The duration of the break is timed by hardware, and AUTOBRK is deasserted by hardware when the break is completed. Alternatively, if it is necessary to generate a break longer than 24 bit times, a break can be sent manually by first clearing AUTOBRK in the DMX Control Register, then setting SBRK in the Control 0 Register, waiting the appropriate duration, then clearing SBRK. In both cases, UART-LDD starts the break after AUTOBRK or SBRK is set, and any character transmission currently underway has completed. The mark after break is transmitted automatically for four bit times at the conclusion of the break. The start code should be written to the Transmit Data Register prior to the conclusion of a mark after break transmission. The start code can be written while generating either the mark before break, the break, or the mark after break, as long as TDRE = 1 before writing. If the Transmit Data Register is written after TDRE asserts but before TXE asserts, the hardware will transmit the character in the Transmit Data Register during the next slot. During each slot, the DMX master will insert a start bit prior to transmitting the character, and will insert two stop bits between each character if STOP = 1 in the Control 0 Register. If TXE asserts before the next character is written in the Transmit Data Register, the DMX Master will transmit a mark before break. 14.1.12.4. DMX Slave Operation When the MSEL= 101b (Mode Select) in the DMX Control Register, DMX Slave Mode is selected by setting DMXMST = 0 and DMXSLV = 1. The DMX slave detects the start of a new message by the break which appears to the slave as a break of at least 22 bit times in duration. Following the break, the UART-LDD hardware automatically checks for a mark after a break lasting at least one bit time. When a mark after this break is detected, hardware will wait for the first slot to be transmitted, which commences with the start bit of the start code. The UART-LDD will also check for the break condition.

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 250 The UART-LDD DMX slave decodes the start code and, if it is the null start code, the UART-LDD counts data slots received until the received data slot number matches the value of COMP_ADDR stored in the Comparison Address Register and the DMX Control Register. The slave then receives the data slots. While the REN bit in the UxCLT0 Regis- ter remains set, the slave receives data slots until a mark before the break is received, and also receives the first byte of the break. After receiving the data slots assigned to the slave, clearing the REN bit in the UxCTL0 Register and then setting REN prevents further data reception and associated interrupts until after the next valid break. DMX receive status information is provided in the MODESTAT field of the UART-LDD Mode Select and Sta- tus Register. The UART-LDD can be configured to generate an interrupt upon all received characters, or only upon characters received in data slots equal to or greater than the COMP_ADDR. When the characters in the data slots assigned to the slave have been received, a Wait for Break (WFBRK) can be set to inhibit further receive interrupts until after the next break. To learn more about DMX slave interrupt options, see the Receiver Interrupts section on page 251. Even if WFBRK is set, the Receive Data Register will continue to receive if the REN bit was not temporarily cleared after receiving the data slots assigned to the slave. In this case, a software handler based on the mode status bits in the UxMDSTAT Register should discard the Receive Data Register contents between the time the DMX break con- dition is detected and the reception of a start code is indicated. 14.1.12.5. DMX Slave During Stop Mode While the DMX bus is in a mark after break condition, the DMX slave can either be in low-power Stop Mode, in Halt Mode, or in a normal operational state. While the slave is in Stop Mode, the UART-LDD is not active, and the break condition must be detected by a GPIO edge-detect Stop-Mode Recovery. A High-to-Low transition on the port pin can be used to bring the device out of Stop Mode. When Stop-Mode Recovery is completed, if enabled, the UART-LDD will time the duration of the break. If the UART-LDD is dis- abled, the duration of the break can be timed by software. The duration of the Stop-Mode Recovery sequence can preclude making an accurate measurement of a break duration. 14.1.13. UART-LDD Interrupts The UART-LDD features separate interrupts for the transmitter and receiver. In addition, when the UART-LDD primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability. 14.1.13.1. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty (TDRE) bit is set to 1. This interrupt indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs when the transmitter is initially enabled, and after the Transmit Shift Register has shifted out the first bit of a character. At this point, the Transmit Data Register can be written with the next character to send. As a

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 251 result of this write, 7 bit periods of latency are provided to load the Transmit Data Register before the Transmit Shift Register completes shifting the current character. Writing to the UART-LDD Transmit Data Register clears the TDRE bit to 0. In addition, and while transmitting, the UART-LDD can detect a physical layer error (PLE) for LIN Protocol Mode and a collision error (CLSN) for DALI Protocol Mode. The UART-LDD will generate an interrupt if PLE is detected and if CLSN is detected while CLSNE is set. 14.1.13.2. Receiver Interrupts The receiver generates an interrupt when any one of the following issues occur:

• A data byte has been received and is available in the UART-LDD Receive Data Reg- ister. This interrupt can be disabled independently of the other receiver interrupt sourc- es via the RDAIRQ bit in the Multiprocessor Control Register, and is useful when using DMA to transfer UART-LDD data. The received data interrupt occurs after the receive character has been placed in the Receive Data Register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error. In Multiprocessor Mode (MPEN = 1), the receive-data interrupts are dependent on the mul- tiprocessor configuration and the most recent address byte.
• A break is received
• A receive data overrun or LIN slave autobaud overrun error is detected
• A data framing error is detected
• A parity error is detected (e.g., if a physical layer error in LIN Mode occurs, software must disable parity error checking for DMX Mode)
• In DALI Mode, a collision error is detected while CLSNE is set in the DALI Control Register
• In DMX Mode, the following slave receive data interrupt events as selected by DMX- SIRQ while RDAIRQ is set and WFBRK is cleared: – Interrupt following each received byte. – Interrupt following each received byte in a slot ≥ the slave address only if the first received byte was the null start. – Interrupt following the start code. – Interrupt following the start code and each received byte in a slot ≥ the slave address only if the first received byte was the null start. If the first received byte was not the null start, interrupt following each received byte. Note:

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 252 14.1.13.3. UART-LDD Overrun Errors When an overrun error condition occurs, the UART-LDD prevents overwriting of the valid data currently in the Receive Data Register. The break detect and overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the OE bit of the Status 0 Register is updated to indicate the overrun condition (and break detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data Register contains a data byte. However, because the overrun error occurred, this byte cannot contain valid data, and must be ignored. A BRKD bit indicates if the overrun is caused by a break condition on the line. After reading a status byte indicating an overrun error, the Receive Data Register must be read again to clear the error bits in the UART-LDD Status 0 Register. In LIN Mode, an overrun error is signalled for receive-data overruns as described above, and in the LIN slave if the BRG Counter overflows during the autobaud sequence (the ATB bit will also be set in this case). There is no data associated with the autobaud overflow interrupt; however the Receive Data Register must be read to clear the OE bit. In this case, software must write a 10b to the LinState field, forcing the LIN slave back to a Wait for Break state. 14.1.13.4. UART-LDD Data- and Error-Handling Procedure Figures 34 shows the recommended procedure for use in UART-LDD receiver interrupt service routines.

LDD receiver functionality is not employed. The transmitter can be enabled in this mode. Figure 34. UART-LDD Receiver Interrupt Service Routine Flow

PS029413-0921 P R E L I M I N A R Y UART-LDD Architecture Z8 Encore! XP® F6482 Series Product Specification 254 14.1.14. UART-LDD and DMA Support The UART-LDD will assert DMA RX request whenever receive data is available (RDA = 1) and will deassert DMA RX request whenever the Receive Data Register is read by the DMA or software. When using DMA, it can be desirable to clear RDAIRQ so that interrupts occur on receive errors but not upon receive data. The UART-LDD will assert DMA TX request whenever the Transmit Data Register is empty (TDRE = 1) and will deassert DMA TX request whenever the Transmit Data Regis- ter is written by the DMA or software. 14.1.15. UART-LDD Baud Rate Generator The UART-LDD Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART-LDD Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data-transmission rate (baud rate) of the UART-LDD. The UART-LDD data rate for normal UART operation and DMX operation is calculated using the following equation: The UART-LDD data rate for LIN Mode UART operation is calculated using the follow- ing equation: The UART-LDD data rate for DALI Mode operation is calculated using the following equation: When the UART-LDD is disabled, the BRG functions as a basic 16-bit timer with interrupt on time-out. To configure the BRG as a timer with interrupt on time-out, follow the proce- dure below: 1. Disable the UART-LDD receiver by clearing the REN bit in the UART-LDD Control 0 Register to 0 (i.e., the TEN bit can be asserted; transmit activity can occur). 2. Load the appropriate 16-bit co unt value into the UART-LDD Baud Rate High and Low Byte registers. UART Data Rate (bits/s) = System Clock Frequency (Hz) 16 x UART Baud Rate Divisor Value UART Data Rate (bits/s) = System Clock Frequency (Hz) UART Baud Rate Divisor Value UART Data Rate (bits/s) = System Clock Frequency (Hz) 32 x UART Baud Rate Divisor Value

PS029413-0921 P R E L I M I N A R Y Noise Filter Z8 Encore! XP® F6482 Series Product Specification 256 14.2.2. Operation Figure 36 shows the operation of the noise filter both with and without noise. The noise filter in this example is a 2-bit up/down counter which saturates at 00b and 11b. A 2-bit counter is shown for convenience; the operation of wider counters is similar. The output of the filter switches from 1 to 0, when the counter counts down from 01b to 00b; this output switches from 0 to 1 when the counter counts up from 10b to 11b. In this 2-bit counter example, the noise filter delays the receive data by three System Clock cycles. The receive data delay induced by the noise filter is a function of the counter width: Filter delay= 2n - 1 System Clock cycles, where n is the counter width value selected by NFCTL. The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit time. The presence of noise (FiltSatB = 1 at the center of the bit time) does not mean that the sampled data is incorrect; instead, the filter is not in its saturated state of all ones or all zeroes. If FiltSatB = 1, then RxD is sampled during a receive character and the NE bit in the ModeStatus[4:0] field is set. By observing this bit, an indication of the level of noise in the network can be obtained.

Figure 36. Noise Filter Operation

The UART-LDD control registers support the UART-LDD and the noise filter. the read-only UART-LDD 0–1 Receive Data Register. with the write-only UART-LDD 0–1 Transmit Data Register. Table 121. UART-LDD 0–1 Transmit Data Registers (UxTXD) Note: W = Write; X = undefined; x = 0,1. UART-LDD transmitter data byte to be shifted out through the TxD pin. Table 122. UART-LDD 0–1 Receive Data Registers (UxRXD) Note: R = read; X = undefined; x = 0,1. UART-LDD receiver data byte from the RxD pin.

uration and status. Table 123 describes the Status 0 registers for standard UART Mode. Table 125, and for DMX Mode in Table 126. Table 123. UART-LDD 0–1 Status 0 Registers, Standard UART Mode (UxSTAT0) Note: R = read; X = undefined; x = 0,1. UART-LDD Receive Data Register clears this bit. 0: The UART-LDD Receive Data Register is empty. 1: There is a byte in the UART-LDD Receive Data Register. : No overrun error occurred. 1: An overrun error occurred. This bit indicates that a framing error (no stop bit following data reception) was detected. Reading the Receive Data Register clears this bit. 0: No framing error occurred. 1: A framing error occurred. are all zeroes, then this bit is set to 1. Reading the Receive Data Register clears this bit.

This bit indicates that the Transmit Data Register is empty and ready for additional data. Writing to the Transmit Data Register resets this bit. 0: Do not write to the Transmit Data Register. 1: The Transmit Data Register is ready to receive an additional byte for transmission. : Data is currently transmitting. 1: Transmission is complete. mode. CTS only affects transmission if the CTSE bit = 1. Table 124. UART-LDD 0–1 Status 0 Registers, LIN Mode (UxSTAT0) : The Receive Data Register is empty. 1: There is a byte in the Receive Data Register. simultaneously. Reading the Status 0 Register or the Receive Data Register clears this bit. 0: Transmit and Receive data match. 1: Transmit and Receive data do not match.

PS029413-0921 P R E L I M I N A R Y UART-LDD Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 261 [5] OE Receive Data and Autobaud Overrun Error This bit is set just as in normal UART operation if a receive data overrun error occurs. This bit is also set during LIN slave autobaud if the BRG counter overflows before the end of the autobaud sequence. This indicates that the receive activity is not an autobaud character or the master baud rate is too slow. The ATB status bit will also be set in this case. This bit is cleared by reading the Receive Data Register. 0: No autobaud or data overrun error occurred. 1: An autobaud or data overrun error occurred. [4] FE Framing Error This bit indicates that a framing error (no stop bit following data reception) is detected. Reading the Receive Data Register clears this bit. 0: No framing error occurred. 1: A framing error occurred. [3] BRKD Break Detect This bit is set in LIN Mode if:

• It is in LIN Sleep state and a break of at least 4 bit times occurred (wake-up event) or
• It is in Slave Wait Break state and a break of at least 11 bit times occurred (break event) or
• It is in Slave Active state and a break of at least 10 bit times occurs. Reading the Status 0 Register or the Receive Data Register clears this bit. : No LIN break occurred. 1: LIN break occurred. [2] TDRE Transmitter Data Register Empty This bit indicates that the Transmit Data Register is empty and ready for additional data. Writing to the Transmit Data Register resets this bit. 0: Do not write to the Transmit Data Register. 1: The Transmit Data Register is ready to receive an additional byte for transmission. [1] TXE Transmitter Empty This bit indicates that the Transmit Shift Register is empty and character transmission is completed. : Data is currently transmitting. 1: Transmission is complete. [0] ATB LIN Slave Autobaud Complete This bit is set in LIN Slave Mode when an autobaud character is received. If the ABIEN bit is set in the LIN Control Register, then a receive interrupt is generated when this bit is set. Reading the Status 0 Register clears this bit. This bit will be 0 in LIN Master Mode. Bit Description (Continued)

Table 125. UART-LDD 0–1 Status 0 Registers, DALI Mode (UxSTAT0 ) Note: R = read; X = undefined; x = 0,1. UART-LDD Receive Data Register clears this bit. 0: The UART-LDD Receive Data Register is empty. 1: There is a byte in the UART-LDD Receive Data Register. : No biphase error occurred. same value. This bit is set only if BPEN = 1. : No overrun error occurred. 1: An overrun error occurred. Register). Reading the Receive Data Register clears this bit. 0: No framing error occurred. 1: A framing error occurred. : No collision was detected. 1: A collision was detected. This bit indicates that the Transmit Data Register is empty and ready for additional data. Writing to the Transmit Data Register resets this bit. 0: Do not write to the Transmit Data Register. 1: The Transmit Data Register is ready to receive an additional byte for transmission.

This bit indicates that the Transmit Shift Register is empty and character transmission is finished. 0: Data is currently transmitting. 1: Transmission is complete. mode. CTS only affects transmission if the CTSE bit = 1. Table 126. UART-LDD 0–1 Status 0 Registers, DMX Mode (UxSTAT0 ) Note: R = read; X = undefined; x = 0,1. UART-LDD Receive Data Register clears this bit. 0: The UART-LDD Receive Data Register is empty. 1: There is a byte in the UART-LDD Receive Data Register. This bit is reserved and must be programmed to 0. : No overrun error occurred. 1: An overrun error occurred. This bit is reserved and must be programmed to 0. bits are zero) then this bit is set to 1. Reading the Receive Data Register clears this bit.

This bit indicates that the Transmit Data Register is empty and ready for additional data. Writing to the Transmit Data Register resets this bit. 0: Do not write to the Transmit Data Register. 1: The Transmit Data Register is ready to receive an additional byte for transmission. This bit indicates that the Transmit Shift Register is empty and character transmission is finished. 0: Data is currently transmitting. 1: Transmission is complete. mode. CTS only affects transmission if the CTSE bit = 1. Table 127. UART-LDD 0–1 Mode Select and Status Registers (UxMDSTAT) Note: R = read; R/W = read/write; x = 0,1. status is returned in the Mode Status field when reading this register. 000: Multiprocessor and normal UART control/status. 001: Noise filter control/status. 010: LIN protocol control/status.

This read-only field returns status corresponding to one of four modes selected by MSEL. These four modes are described in Table 128 on page 265. : Multiprocessor Mode status = {NE,0,0,NEWFRM, MPRX}. 001: Noise filter status = {NE,0,0,0,0}. 010: LIN Mode status = {NE, RxBreakLength}. Table 128. Mode Status Fields Data Register resets this bit to 0. 0: The current byte is not the first data byte of a new frame. 1: The current byte is the first data byte of a new frame. UART-LDD Receive Data Register resets this bit to 0. See the NE description in this table for Multiprocessor Mode Status Field. See description in this table for Multiprocessor Mode Status Field. the break. If the break exceeds 15 bit times the value saturates at 1111b.

This bit is identical to RDA in the UART-LDD Status 0 Register. This bit is identical to CLSN in the UART-LDD Status 0 Register in DALI Mode. 101: Special or unrecognized command. All other bits are reserved. This bit is identical to RDA in the UART-LDD Status 0 Register. reception of the frame ends. reception of the frame ends. reception of the frame ends. This bit is asserted while the Mark Before/After Break Condition is detected.

Table 129. UART-LDD 0–1 Control 0 Registers (UxCTL0) Note: R/W = read/write; x = 0,1. and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is enabled. This bit enables or disables the receiver. 0: The CTS signal has no effect on the transmitter. 1: The UART-LDD recognizes the CTS signal as an enable control for the transmitter. (MSEL = 101) modes. Even or odd is determined by the PSEL bit. 0: Parity is disabled. This bit is overridden by the MPEN bit. 0: Even parity is sent as an additional parity bit for the transmitter/receiver. 1: Odd parity is sent as an additional parity bit for the transmitter/receiver.

PS029413-0921 P R E L I M I N A R Y UART-LDD Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 268 [2] SBRK Send Break This bit pauses or breaks data transmission. Sending a break interrupts any transmission in progress, so ensure that the transmitter has completed sending data before setting this bit. In standard UART Mode, the duration of the break is determined by how long the software leaves this bit asserted. Also the duration of any required stop bits following the break must be timed by software before writing a new byte to be transmitted to the Transmit Data Register. In LIN Mode, the master sends a break character by asserting SBRK. The duration of the break is timed by hardware and the SBRK bit is deasserted by hardware when the break is completed. The duration of the break is determined by the TxBreakLength field of the LIN Control Register. One or two stop bits are automatically provided by the hardware in LIN Mode, as defined by the stop bit. In DALI Mode and DMX Mode, this bit pauses or breaks data transmission just as in standard UART Mode. In DMX Mode, hardware can time the duration of the break if AUTOBRK is set in the DMX Control Register. : No break is sent. 1: A break is sent (the output of the transmitter is 0). [1] STOP Stop Bit Select 0: The transmitter sends one stop bit. The receiver framing error check expects one stop bit. 1: The transmitter sends two stop bits. The receiver framing error check expects two stop bits. [0] LBEN Loop Back Enable 0: Normal operation. 1: All transmitted data is looped back to the receiver. Bit Description (Continued)

features that can apply to multiple modes. Table 130. Multiprocessor Control 0–1 Registers (UxCTL1 with MSEL = 000b) Note: R = read; R/W = read/write; x = 0,1. 00: The UART-LDD generates an interrupt request on all data and address bytes. 01: The UART-LDD generates an interrupt request only on received address bytes. data bytes until an address mismatch occurs. the most recent address byte matched the value in the Address Compare Register. This bit is used to enable Multiprocessor (9-bit) Mode. 0: Disable Multiprocessor (9-bit) Mode. 1: Enable Multiprocessor (9-bit) Mode. This bit is applicable only when Multiprocessor (9-bit) Mode is enabled. 0: Send a 0 in the multiprocessor bit location of the data stream (9th bit). 1: Send a 1 in the multiprocessor bit location of the data stream (9th bit). 0: DE signal is active High.

PS029413-0921 P R E L I M I N A R Y UART-LDD Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 270 [2] BRGCTL Baud Rate Generator Control This bit causes different UART-LDD behavior depending on whether the UART-LDD receiver is enabled (REN = 1 in the UART-LDD Control 0 Register). When the UART-LDD receiver is not enabled, this bit determines whether the Baud Rate Generator issues interrupts. When the UART-LDD receiver is enabled, this bit allows Reads from the baud rate registers to return the BRG count value instead of the reload value. When the UART-LDD receiver is not enabled: 0: BRG is disabled. Reads from the Baud Rate High and Low Byte registers return the BRG reload value. 1: BRG is enabled and counting. The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART-LDD receiver is enabled: 0: Reads from the Baud Rate High and Low Byte registers return the BRG reload value. 1: Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the timers, there is no mechanism to latch the High Byte when the Low Byte is read. [1] RDAIRQ Receive Data Interrupt 0: Received data and receiver errors generates an interrupt request to the Interrupt controller. Note that RDAIRQ also affects DALI and DMX modes. In DMX Mode, the received data interrupts are governed by DMXSIRQ. 1: Received data does not generate an interrupt request to the Interrupt controller. Only receiver errors generate an interrupt request. [0] Reserved This bit is reserved and must be programmed to 0. Bit Description (Continued)

control for the digital noise filter. Table 131. Noise Filter Control 0–1 Registers (UxCTL1 with MSEL = 001b) Note: R = read; R/W = read/write; x = 0,1. 0: Noise filter is disabled. 1: Noise filter is enabled. Receive data is preprocessed by the noise filter. 110: 10-bit up/down counter. 111: 11-bit up/down counter. These bits are reserved and must be programmed to 0000.

Table 132. LIN Control 0–1 Registers (UxCTL1 with MSEL = 010b) Note: R/W = read/write; x = 0,1. 0: LIN Master Mode not selected. 1: LIN Master Mode selected (if MPEN, PEN, LSLV = 0). 0: LIN Slave Mode not selected. 1: LIN Slave Mode selected (if MPEN, PEN, LMST = 0). 1: Autobaud enabled, if in LIN Slave Mode. 0: Interrupt following autobaud does not occur. after which hardware cycles through the Wait for Break, Autobaud and Active states. configuration, software does not alter the LinState field during operation. 00: Sleep state (either LMST or LSLV can be set). 10: Autobaud state (only valid for LSLV = 1). 11: Active state (either LMST or LSLV can be set).

Used in LIN Mode by the master to control the duration of the transmitted break. Table 133. DALI Control 0–1 Registers (UxCTL1 with MSEL Note: R/W = read/write; x = 0,1. TEN in the UART-LDD Control Register must also be set to enable transmit. 0: Transmit stop bit(s) after each byte transmitted. REN in the UART-LDD Control Register must also be set to enable receive. 0: Stop bit(s) are expected after each byte received. 1: Multiple bytes can be received without stop bit(s) inserted between the bytes. 0: Biphase encoding not enabled. 1: Biphase encoding enabled. BPEN should be set for DALI operation. BPENC has an effect only if BPEN = 1.

for the DMX Mode of operation. 1: Start bit is a logic 1. STRTPOL is typically set for DALI. 0: Standard UART bit order with the LSB (TxD[0]/RxD[0]) transmitted/received first. 1: DALI bit order with the MSB (TxD[7]/RxD[7]) transmitted/received first. 0: Collision detection is disabled. 1: Collision detection is enabled. CLSNE should be set only for DALI master transmissions. Register and an interrupt will be generated. PARTRXE has an effect only when receiving. 0: Partial bytes are not loaded into RXDATA. Table 134. DMX Control 0-1 Registers (UxCTL1 with MSEL Note: R/W = read/write; x = 0,1. 0: DMX Master Mode not selected. 1: DMX Master Mode selected. 0: DMX Slave Mode not selected.

PS029413-0921 P R E L I M I N A R Y UART-LDD Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 275 13.3.11. UART-LDD Address Compare Registers The UART-LDD Address Compare 0–1 registers, shown in Table 135, store the multinode network address of the UART-LDD. When the MPMD[1] bit of the UART-LDD Multipro- cessor Control Register is set, all incoming address bytes are compared to the value stored in this Address Compare Register. Receive interrupts and RDA assertions only occur in the event of a match. In the DMX Control Register, when DMXSLV and RDAIRQ are set and DMXSIRQ = x1, the data slot number is compared to the value of COMP_ADDR is stored in this address compare register and in the DMX Control Register. Interrupts can be configured to occur upon receiving characters in data slots equal to or greater than the COMP_ADDR value. [5:4] DMXSIRQ DMX Slave Interrupt Control DMXSIRQ has an effect only for a DMX slave (DMXSLV = 1) and if both RDAIRQ = 1 and WFBRK = 0. 00: Interrupt following each received byte. 01: Interrupt following each received byte in a slot ≥ the slave address only if the first received byte was the null start. 10: Interrupt following the start code. 11: Interrupt following the start code and each received byte in a slot ≥ the slave address only if the first received byte was the null start. [3] Reserved This bit is reserved and must be programmed to 0. [2] AUTOBRK Automatic Break AUTOBRK has an effect only for a DMX Master (DMXMST = 1). 0: No automatic break transmission. Manually send a break using SBRK 1: Automatic break transmission of 24 bit times (96us at 250 kHz) upon being set. AUTOBRK is cleared by hardware upon completing the break transmission. Clearing AUTOBRK during a break transmission does not terminate the break transmission. [1] WFBRK Wait for Break WFBRK has an effect only for a DMX slave (DMXSLV = 1). 0: Do not wait for break. Continue to generate receive data interrupts as configured by DMXSIRQ and RDAIRQ. 1: Wait for break. Do not generate received data interrupts until the next break is received. Upon receiving a break, WFBRK is cleared by hardware. [0] COMP_AD DR[8] Comparison Address bit 8 COMP_ADDR[8] has an effect only for a DMX slave (MODE = 101, DMXSLV = 1). 0–1: Combined with COMP_ADDR[7:0] in UART-LDD Address Compare Register to form a 9-bit comparison address. For a DMX slave, the comparison address is compared against the received data slot number. Bit Description (Continued)

transmission rate (baud rate) of the UART-LDD. Table 135. UART-LDD 0–1 Address Compare Registers (UxADDR) Note: R/W = read/write; x = 0,1. COMP_ADDR[8] in the DMX Control Register is also used. Table 136. UART-LDD 0-1 Baud Rate High Byte Registers (UxBRH) Note: R/W = read/write; x = 0,1. These bits set the High byte of the baud rate divisor value.

the baud period rather than 1/16th of the baud period. low registers must be written independently. Table 137. UART-LDD 0–1 Baud Rate Low Byte Registers (UxBRL) Note: R/W = read/write; x = 0,1. These bits set the Low Byte of the baud rate divisor value.

Table 138. UART-LDD Baud Rates, 20.0 MHz System Clock

Table 139. UART-LDD Baud Rates, 19.99848 MHz System Clock Table 140. UART-LDD Baud Rates, 10.0 MHz System Clock Table 141. UART-LDD Baud Rates, 7.3728 MHz System Clock

Table 142. UART-LDD Baud Rates, 2.4576 MHz System Clock

PS029413-0921 P R E L I M I N A R Y Enhanced Serial Peripheral Interface Z8 Encore! XP® F6482 Series Product Specification 281 Chapter 15. Enhanced Serial Peripheral Interface The Enhanced Serial Peripheral Interface (ESPI) supports the Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S). ESPI includes the following features:

• Full-duplex, synchronous, character-oriented communication
• Four-wire interface (SS, SCK, MOSI and MISO)
• Transmit and receive buffer registers to enable high throughput
• Master Mode transfer rates up to a maximum of one-half the system clock frequency
• Slave Mode transfer rates up to a maximum of one-eighth the system clock frequency
• Error detection
• Dedicated Programmable Baud Rate Generator
• Data transfer control via polling, interrupt or DMA 15.1. Architecture The ESPI is a full-duplex, synchronous, character-oriented channel that supports a four- wire interface (serial clock, transmit data, receive data and slave select). The ESPI block consists of a shift register, data buffer register, a baud rate (clock) generator, control/status registers and a control state machine. Transmit and receive transfers are in synch because there is a single shift register for both transmitting and receiving data. Figure 37 shows a diagram of the ESPI block.

Figure 37. ESPI Block Diagram

0 Shift Register 7

PS029413-0921 P R E L I M I N A R Y ESPI Signals Z8 Encore! XP® F6482 Series Product Specification 283 15.2. ESPI Signals The four ESPI signals are:

• Master-In/Slave-Out (MISO)
• Master-Out/Slave-In (MOSI)
• Serial Clock (SCK)
• Slave Select (SS) The following paragraphs discuss these signals as they operate in both Master and Slave modes. 15.2.1. Master-In/Slave-Out The Master-In/Slave-Out (MISO) pin is configured as an input in a master device and as an output in a slave device. Data is transferred most significant bit first. The MISO pin of a slave device is placed in a high-impedance state if the slave is not selected. When the ESPI is not enabled, this signal is in a high-impedance state. The direction of this pin is controlled by the MMEN bit of the ESPI Control Register. 15.2.2. Master-Out/Slave-In The Master-Out/Slave-In (MOSI) pin is configured as an output in a master device and as an input in a slave device. Data is transferred most significant bit first. When the ESPI is not enabled, this signal is in a high-impedance state. The direction of this pin is controlled by the MMEN bit of the ESPI Control Register. 15.2.3. Serial Clock The Serial Clock (SCK) synchronizes data movement both in and out of the Shift Register via the MOSI and MISO pins. In Master Mode (MMEN = 1), the ESPI’s Baud Rate Gener- ator creates the serial clock and drives it out on its SCK pin to the slave devices. In Slave Mode, the SCK pin is an input. Slave devices ignore the SCK signal unless their SS pin is asserted. The master and slave are each capable of exchanging a character of data during a sequence of NUMBITS clock cycles; see the ESPI 0-1 Mode Registers (ESPIxMODE) on page 299 for details. In both master and slave ESPI devices, data is shifted on one edge of the SCK, and is sampled on the opposite edge where data is stable. SCK phase and polarity is deter- mined by the PHASE and CLKPOL bits in the ESPI Control Register. 15.2.4. Slave Select The Slave Select signal is a bidirectional framing signal with several modes of operation to support SPI and other synchronous serial interface protocols. Slave Select Mode is

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 284 selected by the SSMD field of the ESPI Mode Register. The direction of the SS signal is controlled by the SSIO bit of the ESPI Mode Register. The SS signal is an input on slave devices, and is an output on the active master device. Slave devices ignore transactions on the bus unless their Slave Select input is asserted. In SPI Master Mode, additional GPIO pins are required to provide Slave Selects if there is more than one slave device. 15.3. Operation During a transfer, data is sent and received simultaneously by both the master and slave devices. Separate signals are required for transmit data, receive data, and the serial clock. When a transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin, and a multi-bit character is simultaneously shifted in on second data pin. An 8-bit shift register in the master and an 8-bit shift register in the slave are connected as a circular buf- fer. The ESPI Shift Register is buffered to support back-to-back character transfers in high-performance applications. Though the hardware is inherently full-duplex during an SPI transaction, software may choose to use the SPI to send only, to receive only, or to both send and receive data. The ESPIEN1 and ESPIEN0 bits in the Control Register are used to enable data movement in transmit and receive directions. Only the data interrupt(s) and DMA request(s) associated with the enabled direction(s) will be asserted. If transmit is enabled by ESPIEN1 = 1, then the TDRE bit in the status register can be set by the SPI and assert the SPI interrupt if DIRQS = 1. If receive is enabled by ESPIEN0 = 1, then the RDRNE bit in the status register can be set by the SPI and will assert the SPI interrupt if DIRQS = 1. The TDRE and RDRNE bits, when set, also generate transmit and receive DMA requests. When using DMA to transfer data, set DIRQS = 0 to prevent data interrupts from TDRE and RDRNE. In this case, error interrupts still occur and must be handled directly by the software. When ESPIEN1 = 0 (transmit is disabled), transmit data will be all 1s and neither a trans- mit interrupt nor a DMA request will be asserted. When ESPIEN0 = 0 (receive is disabled), RDRNE will not be set; therefore, neither a receive interrupt nor a DMA request will be asserted. When both ESPIEN1 and ESPIEN0 are set in Master Mode following a character transfer, both interrupts or DMA requests must be serviced before the next transaction will start. These transmit and receive requests can be serviced in either order. To support back- to-back transfers without an intervening pause, the receive and transmit interrupts must be serviced while the current character is being transferred. The master sources the Serial Clock (SCK) and Slave Select signal (SS) during the trans- fer.

Mode, the transfer will be terminated if new data is not available to send. to allow for synchronization of the SCK input to the internal system clock. clock edge, which provides a half cycle of setup and hold time. Table 143. ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation

This section describes the different modes of data transfer supported by the ESPI block. The mode is selected by the Slave Select Mode (SSMD) field of the Mode Register. transaction. Prior to writing the first transmit data byte, software sets the SSV bit. character is transmitted, the hardware will automatically deassert the SSV and TEOF bits. Figure 39. ESPI Timing when PHASE = 1

devices. Typically, for an SPI master, SSIO = 1 and SSPO = 0. the ESPI configured as an SPI master. Figure 42. ESPI Configured as an SPI Master in a Single Master, Single Slave System

Figure 43. ESPI Configured as an SPI Master in a Single Master, Multiple Slave System

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 293 A transmit underrun sets the TUND bit in the ESPI Status Register to 1. Writing a 1 to TUND clears this error flag. 15.3.5.2. Mode Fault (Multi-Master Collision) A mode fault indicates when more than one master is trying to communicate simultane- ously (i.e., a multi-master collision) in SPI Mode. The mode fault is detected when the enabled master’s SS input pin is asserted. For this assertion to occur, the Control and Mode registers must be configured with MMEN = 1, SSIO = 0 (SS is an input) and SS input = 0. A mode fault sets the COL bit in the ESPI Status Register to 1. Writing a 1 to COL clears this error flag. 15.3.5.3. Receive Overrun A receive overrun error occurs when a transfer completes and the RDRNE bit is still set from the previous transfer. A receive overrun sets the ROVR bit in the ESPI Status Regis- ter to 1. Writing a 1 to ROVR clears this error flag. The Receive Data Register is not over- written and will contain the data from the transfer which initially set the RDRNE bit. Subsequent received data is lost until the RDRNE bit is cleared. In SPI Master Mode, a receive overrun will not occur. Instead, the SCK will be paused until software responds to the previous RDRNE/TDRE requests. 15.3.5.4. Slave Mode Abort In Slave Mode, if the SS pin deasserts before all bits in a character have been transferred, the transaction is aborted. When this condition occurs, the ABT bit is set in the ESPI Sta- tus Register. A slave abort error resets the slave control logic to idle state. A slave abort error is also asserted in Slave Mode if BRGCTL = 1 and a baud rate genera- tor time-out occurs. When BRGCTL = 1 in Slave Mode, the baud rate generator functions as a watchdog timer monitoring the SCK signal. The BRG counter is reloaded every time a transition on SCK occurs while SS is asserted. The Baud Rate Reload registers must be programmed with a value longer than the expected time between the SS assertion and the first SCK edge, between SCK transitions while SS is asserted, and between the last SCK edge and SS deassertion. A time-out indicates that the master is stalled or disabled. Writ- ing a 1 to ABT clears this error flag. 15.3.6. ESPI Interrupts ESPI has a single interrupt output which is asserted when any of the TDRE, TUND, COL, ABT, ROVR or RDRNE bits are set in the ESPI Status Register. The setting of TDRE will only generate an interrupt if transmit is enabled (ESPIEN1 = 1 ). The interrupt is a pulse which is generated when any one of the source bits initially sets. The TDRE and RDRNE interrupts can be enabled/disabled via the Data Interrupt Request Select (DIRQS) bit of the ESPI Control Register. A transmit interrupt is asserted by the TDRE status bit when the ESPI block is enabled and the DIRQS bit is set. The TDRE bit in the status register is cleared automatically when the

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 294 Transmit Data Register is written or the ESPI block is disabled. After the Transmit Data Register is loaded into the Shift Register to start a new transfer, the TDRE bit will be set again, causing a new transmit interrupt. In Master or Slave modes, if information is being received but not transmitted, the transmit interrupts can be eliminated by selecting Receive Only Mode (ESPIEN1,0 = 01). A receive interrupt is generated by the RDRNE status bit when the ESPI block is enabled, the DIRQS bit is set, and a character transfer completes. At the end of the character trans- fer, the contents of the Shift Register are transferred into the Receive Data Register, caus- ing the RDRNE bit to assert. The RDRNE bit is cleared when the Data Buffer is read as empty. If information is being transmitted but not received by the software application, the receive interrupt can be eliminated by selecting Transmit Only Mode (ESPIEN1,0 = 10) in either Master or Slave modes. When information is being sent and received under inter- rupt control, RDRNE and TDRE will both assert simultaneously at the end of a character transfer. In this case, RDRNE and TDRE can be serviced in either order. ESPI error interrupts occur if any of the TUND, COL, ABT and ROVR bits in the ESPI Status Register are set. These bits are cleared by writing a 1. If the ESPI is disabled (ESPIEN1, 0 = 00), an ESPI interrupt can be generated by a Baud Rate Generator time-out. This timer function must be enabled by setting the BRGCTL bit in the ESPICTL Register. This timer interrupt does not set any of the bits of the ESPI Status Register. 15.3.7. ESPI and DMA The ESPI will assert a DMA RX request whenever the receive data register is not empty (RDRNE = 1), and will deassert a DMA RX request whenever the Receive Data Register is read by the DMA or software. The EPSI will assert a DMA TX request whenever the Transmit Data Register is empty (TDRE = 1), and will deassert a DMA TX request whenever the Transmit Data Register is written by the DMA or software. When using DMA, it can be desirable to clear DIRQS so that interrupts occur on errors, but not upon data requests. If the software application is moving data in only one direc- tion, the ESPIEN1,ESPIEN0 bits are set to 10 or 01, allowing a single DMA channel to control the ESPI data transfer. When operating in Receive Only Mode, transmit data will be all 1s. 15.3.8. ESPI Baud Rate Generator In ESPI Master Mode, the Baud Rate Generator creates a lower frequency serial clock (SCK) for data transmission synchronization between the master and the external slave. The input to the Baud Rate Generator is the system clock. The ESPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the ESPI Baud Rate Generator. The ESPI baud rate is calculated using the following equation:

PS029413-0921 P R E L I M I N A R Y ESPI Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 295 The minimum baud rate is obtained by setting BRG[15:0] to 0000h for a clock divisor value of (2 x 65536 = 131072). When the ESPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. Observe the following steps to configure the Baud Rate Gener- ator as a timer with interrupt on time-out: 1. Disable the ESPI by clearing the ESPIEN1,0 bits in the ESPI Control Register. 2. Load the appropriate 16-bit co unt value into the ESPI Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the ESPI Control Register to 1. When configured as a general-purpose timer, the SPI BRG interrupt interval is calculated using the following equation: 15.4. ESPI Control Register Definitions The ESPI control registers are defined in this section. 15.4.1. ESPI 0-1 Data Registers The ESPI 0-1 Data Registers, shown in Table 144, address both the outgoing Transmit Data Registers and the incoming Receive Data Registers. Reads from an ESPI Data Regis- ter return the contents of the Receive Data Register. The Receive Data Register is updated with the contents of the Shift Register at the end of each transfer. Writes to an ESPI Data Register load the Transmit Data Register unless TDRE = 0. Data is shifted out starting with bit 7. The last bit received resides in bit position 0. In either the Master or Slave modes, if TDRE = 0, writes to this register are ignored. When the character length is less than 8 bits (as set by the NUMBITS field in the ESPI Mode Register), the transmit character must be left-justified in the ESPI Data Register. A received character of less than 8 bits is right-justified (i.e., the last bit received is in bit position 0). For example, if the ESPI is configured for 4-bit characters, the transmit char- acters must be written to ESPIDATA[7:4] and the received characters are read from ESPI- DATA[3:0]. SPI Baud Rate bits s⁄() System Clock Frequency Hz() SPI BRG Interrupt Interval (s) Syst em Clock Period (s) BRG[15:0]×=

the SS pin when it is configured as an output (Master Mode). Table 144. ESPI 0-1 Data Registers (ESPIxDATA) Note: x references bits in the range [1:0]. from the ESPIDATA Register return the value of the Receive Data Register. Table 145. ESPI 0-1 Transmit Data Command Registers (ESPIxTDCR) Note: x references bits in the range [1:0]. [7:2] These bits are reserved and must be written to 000000. state, and TEOF will automatically clear. 0: The data in the Transmit Data Register is not the last character in the message. 1: The data in the Transmit Data Register is the last character in the message. see the SSMD field of the ESPI 0-1 Mode Registers section on page 299.

Table 146. ESPI 0-1 Control Registers (ESPIxCTL) Note: x references bits in the range [1:0]. ROVR bits will cause an interrupt. also cause interrupts. Use this setting when controlling data transfer via interrupt handlers. a master is not valid for I2S operation (SSMD = 010). TDRE and RDRNE will be active.

PS029413-0921 P R E L I M I N A R Y ESPI Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 298 [5] BRGCTL Baud Rate Generator Control The function of this bit depends upon ESPIEN1,0. When ESPIEN1,0 = 00, this bit allows enabling the BRG to provide periodic interrupts. If the ESPI is disabled 0: The Baud Rate Generator timer function is disabled. Reading the Baud Rate High and Low registers returns the BRG reload value. 1: The Baud Rate Generator timer function and time-out interrupt is enabled. Reading the Baud Rate High and Low registers returns the BRG Counter value. If the ESPI is enabled: 0: Reading the Baud Rate High and Low registers returns the BRG reload value. If MMEN = 1, the BRG is enabled to generate SCK. If MMEN = 0, the BRG is disabled. 1: Reading the Baud Rate High and Low registers returns the BRG Counter value. If MMEN = 1, the BRG is enabled to generate SCK. If MMEN = 0 the BRG is enabled to provide a Slave SCK time-out. See the error description in the Slave Mode Abort section on page 293. CAUTION: If reading the counter one byte at a time while the BRG is counting, keep in mind that the values will not be in sync. [4] PHASE Phase Select Sets the phase relationship of the data to the clock. For more information about operation of the PHASE bit, see the ESPI Clock Phase and Polarity Control section on page 285. [3] CLKPOL Clock Polarity 0: SCK idles Low (0). 1: SCK idles High (1). [2] WOR Wire OR (Open-Drain) Mode Enabled 0: ESPI signal pins not configured for open-drain. 1: All four ESPI signal pins (SCK, SS, MISO and MOSI) configured for open-drain function. This setting is typically used for multi-master and/or multi-slave configurations. [1] MMEN ESPI Master Mode Enable This bit controls the data I/O pin selection and SCK direction. 0: Data out on MISO, data in on MOSI (used in SPI Slave Mode), SCK is an input. 1: Data out on MOSI, data in on MISO (used in SPI Master Mode), SCK is an output. Bit Description (Continued)

Table 147. ESPI 0-1 Mode Registers (ESPIxMODE) Note: x references bits in the range [1:0]. modes, see the Slave Select section on page 283. frame (after the last RDRNE event), SSV will be automatically deasserted by hardware. In this mode, SCK is active only for data transfer (one clock cycle per bit transferred). provide an asynchronous remote loop back (echo) function. period before the data and will remain in that state until the start of the next frame. triggers the start of a transaction on the next SCK cycle.

PS029413-0921 P R E L I M I N A R Y ESPI Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 300 [4:2] NUMBITS[2:0] Number of Data Bits Per Character to Transfer This field contains the number of bits to shift for each character transfer. To learn more about valid bit positions when the character length is less than 8 bits, see the description of the ESPI 0-1 Data Registers section on page 295. 000: 8 bits. 001: 1 bit. 010: 2 bits. 011: 3 bits. 100: 4 bits. 101: 5 bits. 110: 6 bits. 111: 7 bits. [1] SSIO Slave Select I/O This bit controls the direction of the SS pin. In single Master Mode, SSIO is set to 1 even if a separate GPIO pin is being used to provide the SS output function. In the SPI slave or multi-master configuration, SSIO is set to 0. : SS pin configured as an input (SPI slave and multi-master modes). 1: SS pin configured as an output (SPI single-master mode). [0] SSPO Slave Select Polarity This bit controls the polarity of the SS pin. 0: SS is active Low. (SSV = 1 corresponds to SS = 0). 1: SS is active High. (SSV = 1 corresponds to SS = 1). Bit Description (Continued)

The ESPI 0-1 Status Registers, shown in Table 148, indicate the current state of the ESPI. All bits revert to their Reset state if the ESPI is disabled. Table 148. ESPI 0-1 Status Registers (ESPIxSTAT) Note: *R/W = read access; write a 1 to clear the bit to 0; x references bits in the range [1:0]. 0: Transmit Data Register is full or ESPI is disabled. 1: Transmit Data Register is empty. A write to the ESPI (Transmit) Data Register clears this bit. 0: A Transmit Underrun error has not occurred. 1: A Transmit Underrun error has occurred. 0: A multi-master collision (mode fault) has not occurred. 1: A multi-master collision (mode fault) has occurred. 0: A Slave Mode transaction abort has not occurred. 1: A Slave Mode transaction abort has occurred. 0: A Receive Overrun error has not occurred. 1: A Receive Overrun error has occurred. 0: Receive Data Register is empty. 1: Receive Data Register is not empty.

0: No data transfer is currently in progress. 1: Data transfer is currently in progress. Reading this bit returns the current value of the SS pin. 1: The SS pin input is High. Table 149. ESPI S0-1 tate Registers (ESPIxSTATE) Note: x references bits in the range [1:0]. This bit reflects the state of the serial clock pin. 0: The SCK input pin is Low. 1: The SCK input pin is High. : The serial data input pin is Low. 1: The serial data input pin is High. and are not intended to be used by a software driver.

Table 150 defines the valid ESPI states. Table 150. ESPISTATE Values 00_0011 I 2S Slave Mode start delay. 01_0000 SPI Master Mode start delay. 11_0001 I 2S Master Mode start delay. 11_0010 I 2S Master Mode start delay.

1. Disable the ESPI by setting ESPIEN[1:0] = 00 in the SPI Control Register.
2. Load the appropriate 16-bit co unt value into the ESPI Baud Rate High and Low Byte
3. Enable the BRG timer function and associated interrupt by set ting the BRGCTL bit in

the ESPI Control Register to 1. Table 151. ESPI 0-1 Baud Rate High Byte Registers (ESPIxBRH) Note: x references bits in the range [1:0]. The most significant byte, BRG[15:8], of the ESPI Baud Rate Generator’s reload value.

Table 152. ESPI 0-1 Baud Rate Low Byte Registers (ESPIxBRL) Note: x references bits in the range [1:0]. The least significant byte, BRG[7:0], of the ESPI Baud Rate Generator’s reload value.

PS029413-0921 P R E L I M I N A R Y I 2C Master/Slave Controller Z8 Encore! XP® F6482 Series Product Specification 306 Chapter 16. I2C Master/Slave Controller The I2C Master/Slave Controller ensures that the F6482 Series devices are bus-compatible with the I2C protocol. The I2C bus consists of the serial data signal (SDA) and a serial clock signal (SCL) bidirectional lines. The features of the I2C controller include:

• Operates in MASTER/SLAVE or SLAVE ONLY modes
• Supports arbitration in a multimaster environment (MASTER/SLAVE Mode)
• Supports data rates up to 400 Kbps
• 7-bit or 10-bit slave address recognition (interrupt-only on address match)
• Optional general call address recognition
• Optional digital filter on receive SDA, SCL lines
• Optional interactive receive mode allows software interpretation of each received ad- dress and/or data byte before acknowledging
• Unrestricted number of data bytes per transfer
• Baud Rate Generator can be used as a general-purpose timer with an interrupt if the I2C controller is disabled 16.1. Architecture Figure 45 shows the architecture of the I2C controller.

Table 153 summarizes the I2C Master/Slave controller’s software-accessible registers. Figure 45. I2C Controller Block Diagram Table 153. I2C Master/Slave Controller Registers I2C Data I2CDATA Transmit/receive data register. I2C Interrupt Status I2CISTAT Interrupt status register. I2C Control I2CCTL Control registe r: basic control functions.

cally configured for open-drain operation. I2C Baud Rate High I2CBRH High byte o f baud rate generator initialization value. I2C Baud Rate Low I2CBRL Low byte of baud rate generator initializa tion value. I2C State I2CSTATE State register. configure address recognition, define slave address bits [9:8]. I2C Slave Address I2CSLVAD Defines slave address bits [7:0]. Table 153. I2C Master/Slave Controller Registers (Continued)

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 309 enabled when running in I2C FAST Mode (400 KBps) and can also be used at lower data rates. 16.2.2. I2C Interrupts The I2C controller contains multiple interrupt sources that are combined into one interrupt request signal to the interrupt controller. If the I2C controller is enabled, the source of the interrupt is determined by which bits are set in the I2CISTAT Register. If the I2C control- ler is disabled, the BRG controller is used to generate general-purpose timer interrupts. Each interrupt source, other than the baud rate generator interrupt, features an associated bit in the I2CISTAT Register that automatically clears when software reads the register or performs another task, such as reading/writing the Data Register. 16.2.2.1. Transmit Interrupts Transmit interrupts (i.e., the TDRE bit = 1 in the I2CISTAT Register) occur under the fol- lowing conditions, both of which must be true:

• The Transmit Data Register is empty and the TXI bit = 1 in the I2C Control Register.
• The I2C controller is enabled with one of the following elements: – The first bit of a 10-bit address is shifted out. – The first bit of the final byte of an address is shifted out and the RD bit is deas- serted. – The first bit of a data byte is shifted out. Writing to the I2C Data Register always clears the TRDE bit to 0. 16.2.2.2. Receive Interrupts Receive interrupts (i.e., the RDRF bit = 1 in the I2CISTAT Register) occur when a byte of data has been received by the I2C controller. The RDRF bit is cleared by reading from the I2C Data Register. If the RDRF interrupt is not serviced prior to the completion of the next receive byte, the I2C controller holds SCL Low during the final data bit of the next byte until RDRF is cleared, to prevent receive overruns. A receive interrupt does not occur when a slave receives an address byte or when data bytes following a slave address do not match. An exception is if the Interactive Receive Mode (IRM) bit is set in the I2CMODE Register, in which case receive interrupts occur for all receive address and data bytes in SLAVE Mode. 16.2.2.3. Slave Address Match Interrupts Slave address match interrupts (i.e., the SAM bit = 1 in the I2CISTAT Register) occur when the I2C controller is in SLAVE Mode and a received address matches the unique slave address. The General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized if the GCE bit = 1 in the I2CMODE Register. The software checks the RD

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 310 bit in the I2CISTAT Register to determine if the transaction is a read or write transaction. The General Call Address and STARTBYTE address are also distinguished by the RD bit. The General Call Address (GCA) bit of the I2CISTAT Register indicates whether the address match occurred on the unique slave address or the General Call/STARTBYTE address. The SAM bit clears automatically when the I2CISTAT Register is read. If configured via the MODE[1:0] field of the I2C Mode Register for 7-bit slave address- ing, the most significant 7 bits of the first byte of a transaction are compared against the SLA[6:0] bits of the Slave Address Register. If configured for 10-bit slave addressing, the first byte of the transaction is compared against {11110, SLA[9:8], R/W} and the second byte is compared against SLA[7:0]. 16.2.2.4. Arbitration Lost Interrupts Arbitration Lost interrupts (i.e., the ARBLST bit = 1 in the I2CISTAT Register) occur when the I2C controller is in MASTER Mode and loses arbitration (outputs 1 on SDA and receives 0 on SDA). The I2C controller switches to SLAVE Mode when this instance occurs. This bit clears automatically when the I2CISTAT Register is read. 16.2.2.5. Stop/Restart Interrupts A stop/restart event interrupt (i.e., the SPRS bit = 1 in the I2CISTAT Register) occurs when the I2C controller is in SLAVE Mode and a stop or restart condition is received, indicating the end of the transaction. The RSTR bit in the I2C State Register indicates whether the bit is set due to a stop or restart condition. When a restart occurs, a new transaction by the same master is expected to follow. This bit is automatically cleared when the I2CISTAT Register is read. The stop/restart interrupt occurs only on a selected (address match) slave. 16.2.2.6. Not Acknowledge Interrupts Not Acknowledge interrupts (i.e., the NCKI bit = 1 in the I2CISTAT Register) occur in MASTER Mode when a Not Acknowledge is received or sent by the I2C controller and the start or stop bit is not set in the I2C Control Register. In MASTER Mode, the Not Acknowledge interrupt clears by setting the start or stop bit. When this interrupt occurs in MASTER Mode, the I2C controller waits until it is cleared before performing any action. In SLAVE Mode, the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to data sent. The NCKI bit clears in SLAVE Mode when software reads the I2CISTAT Register. 16.2.2.7. General-Purpose Timer Interrupt from Baud Rate Generator If the I2C controller is disabled (i.e., the IEN bit in the I2CCTL Register = 0) and the BIRQS bit in the I2CCTL Register = 1, an interrupt is generated when the baud rate gener- ator (BRG) counts down to 1. The baud rate generator reloads and continues counting, providing a periodic interrupt. None of the bits in the I2CISTAT Register are set, allowing the BRG in the I2C controller to be used as a general-purpose timer when the I2C control- ler is disabled.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 311 16.2.3. Start and Stop Conditions The master generates the start and stop conditions to start or end a transaction. To start a transaction, the I2C controller generates a start condition by pulling the SDA signal Low while SCL is High. To complete a transaction, the I2C controller generates a stop condi- tion by creating a Low-to-High transition of the SDA signal while the SCL signal is High. These start and stop events occur when the start and stop bits in the I2C Control Register are written by software to begin or end a transaction. Any byte transfer currently under way including the Acknowledge phase finishes before the start or stop condition occurs. 16.2.4. Software Control of I2C Transactions The I2C controller is configured via the I2C Control and I2C Mode registers. The MODE[1:0] field of the I2C Mode Register allows the configuration of the I2C controller for MASTER/SLA VE or SLAVE ONLY Mode, and configures the slave for 7-bit or 10- bit addressing recognition. MASTER/SLA VE Mode can be used for:

• MASTER ONLY operation in a single master/one or more slave I2C system
• MASTER/SLAVE in a multimaster/multislave I2C system
• SLAVE ONLY operation in an I2C system In SLAVE ONLY Mode, the start bit of the I2C Control Register is ignored (i.e., software cannot initiate a master transaction by accident) and operation to SLAVE ONLY Mode is restricted thereby preventing accidental operation in MASTER Mode. The software con- trols I2C transactions by enabling the I2C controller interrupt in the interrupt controller or by polling the I2C Status Register. To use interrupts, the I2C interrupt must be enabled in the interrupt controller and followed by executing an EI instruction. The TXI bit in the I2C Control Register must be set to enable transmit interrupts. An I2C interrupt service routine then checks the I2C Status Register to determine the cause of the interrupt. To control transactions by polling, the TDRE, RDRF, SAM, ARBLST, SPRS and NCKI interrupt bits in the I2C Status Register should be polled. The TDRE bit asserts regardless of the state of the TXI bit. 16.2.5. Master Transactions The following sections describe master read and write transactions to both 7-bit and 10-bit slaves. 16.2.5.1. Master Arbitration If a master loses arbitration during the address byte it releases the SDA line, switches to SLAVE Mode and monitors the address to determine if it is selected as a slave. If a master

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 312 loses arbitration during the transmission of a data byte, it releases the SDA line and waits for the next stop or start condition. The master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the bus in the same bit-time. This loss occurs if more than one master is simultaneously accessing the bus. Loss of arbitration occurs during the address phase (two or more Mas- ters accessing different slaves) or during the data phase, when the masters are attempting to write different data to the same slave. When a master loses arbitration, the software is informed by means of the Arbitration Lost interrupt. The software can repeat the same transaction at a later time. A special case can occur when a slave transaction starts just before the software attempts to start a new master transaction by setting the start bit. In this case, the state machine enters its slave states before the start bit is set and as a result the I2C controller will not arbitrate. If a slave address match occurs and the I2C controller receives/transmits data, the start bit is cleared and an Arbitration Lost interrupt is asserted. The software can minimize the chance of this instance occurring by checking the BUSY bit in the I2CSTATE Register before initiating a master transaction. If a slave address match does not occur, the Arbitra- tion Lost interrupt will not occur and the start bit will not be cleared. The I2C controller will initiate the master transaction after the I2C bus is no longer busy. 16.2.5.2. Master Address-Only Transactions It is sometimes preferable to perform an address-only transaction to determine if a particu- lar slave device is able to respond. This transaction can be performed by monitoring the ACKV bit in the I2CSTATE Register after the address has been written to the I2CDATA Register and the start bit has been set. After the ACKV bit is set, the ACK bit in the I2CSTATE Register determines if the slave is able to communicate. The stop bit must be set in the I2CCTL Register to terminate the transaction without transferring data. For a 10- bit slave address, if the first address byte is acknowledged, the second address byte should also be sent to determine if the preferred slave is responding. Another approach is to set both the stop and start bits (for sending a 7-bit address). After both bits have been cleared (7-bit address has been sent and transaction is complete), the ACK bit can be read to determine if the slave has acknowledged. For a 10-bit slave, set the stop bit after the second TDRE interrupt (which indicates that the second address byte is being sent). 16.2.5.3. Master Transaction Diagrams In the following transaction diagrams, the shaded regions indicate the data that is trans- ferred from the master to the slave, and the unshaded regions indicate the data that is trans- ferred from the slave to the master. The transaction field labels are defined as follows: SS t a r t WW r i t e

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 315 1. The software initializes the MODE field in the I2C Mode Register for MASTER/ SLA VE Mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of slave address types). The MODE field selects the address width for this mode when addressed as a slave (but not for the remote slave). The software asserts the IEN bit in the I2C Control Register. 2. The software asserts the TXI bit of the I 2C Control Register to enable transmit inter- rupts. 3. The I 2C interrupt asserts because the I2C Data Register is empty. 4. The software responds to the TDRE interrupt by writing the fi rst slave address byte (11110xx0). The least-significant bit must be 0 for the write operation. 5. The software asserts the start bit of the I 2C Control Register. 6. The I 2C controller sends a start condition to the I2C slave. 7. The I 2C controller loads the I2C Shift Register with the contents of the I2C Data Reg- ister. 8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt asserts. 9. The software responds by writin g the second byte of address into the contents of the I2C Data Register. 10. The I2C controller shifts the remainder of the first byte of the address and the write bit out via the SDA signal. 11. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next High period of SCL. The I2C controller sets the ACK bit in the I2C Status Register. If the slave does not acknowledge the first address byte, the I2C controller sets the NCKI bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C State Register. The software responds to the Not Acknowledge interrupt by setting the stop bit and clearing the TXI bit. The I2C controller flushes the second address byte from the Data Register, sends a stop condition on the bus, and clears the stop and NCKI bits. The transaction is complete and the following steps can be ignored. 12. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg- ister (2nd address byte). 13. The I2C controller shifts the second address byte out via the SDA signal. After the first bit has been sent, the transmit interrupt asserts. 14. The software responds by writing the data to be written out to the I2C Control Regis- ter. 15. The I2C controller shifts out the remainder of the second byte of the slave address (or ensuring data bytes, if looping) via the SDA signal.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 318 2. The software writes 11110b, followed by the two most-significant address bits and a 0 (write) to the I2C Data Register. 3. The software asserts the start bit of the I 2C Control Register. 4. The I 2C controller sends a start condition. 5. The I 2C controller loads the I2C Shift Register with the contents of the I2C Data Reg- ister. 6. After the first bit has been s hifted out, a transmit interrupt is asserted. 7. The software responds by writin g the least significant eight bits of address to the I2C Data Register. 8. The I 2C controller completes shifting of the first address byte. 9. The I 2C slave sends an Acknowledge by pulling the SDA signal Low during the next High period of SCL. If the slave does not acknowledge the address byte, the I2C controller sets the NCKI bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C State Register. The software responds to the Not Acknowledge interrupt by setting the stop bit. The I2C controller flushes the Transmit Data Register, sends the stop condi- tion on the bus and clears the stop and NCKI bits. The transaction is complete and the following steps can be ignored. 10. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg- ister (the lower byte of the 10-bit address). 11. The I2C controller shifts out the next eight bits of the address. After the first bit shifts, the I2C controller generates a transmit interrupt. 12. The software responds by setting the start bit of the I2C Control Register to generate a repeated start condition. 13. The software writes 11110b, followed by the 2-bit slave address and a 1 (read) to the I2C Data Register. 14. If the user chooses to read-only one byte, the software responds by setting the NAK bit of the I2C Control Register. 15. After the I2C controller shifts out the address bits listed in Step 9 (the second address transfer), the I2C slave sends an Acknowledge by pulling the SDA signal Low during the next High period of SCL. If the slave does not acknowledge the address byte, the I2C controller sets the NCKI bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C State Register. The software responds to the Not Acknowledge interrupt by setting the stop bit. The I2C controller flushes the Transmit Data Register, sends the stop condi- tion on the bus and clears the stop and NCKI bits. The transaction is complete and the following steps can be ignored.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 319 16. The I2C controller sends a repeated start condition. 17. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg- ister (the third address transfer). 18. The I2C controller sends 11110b, followed by the two most-significant bits of the slave read address and a 1 (read). 19. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next High period of SCL. 20. The I2C controller shifts in a byte of data from the slave. 21. The I2C controller asserts the Receive interrupt. 22. The software responds by reading the I2C Data Register. If the next data byte is to be the final byte, the software must set the NAK bit of the I2C Control Register. 23. The I2C controller sends an Acknowledge or Not Acknowledge to the I2C slave, based on the value of the NAK bit. 24. If there are more bytes to transfer, the I2C controller returns to Step 20. 25. The I2C controller generates a NAK interrupt (the NCKI bit in the I2CISTAT Regis- ter). 26. The software responds by setting the stop bit of the I2C Control Register. 27. A stop condition is sent to the I2C slave. 16.2.6. Slave Transactions The following subsections describe read and write transactions to the I2C controller con- figured for 7-bit and 10-bit slave modes. 16.2.6.1. Slave Address Recognition The following two slave address recognition options are supported; a description of each follows.

• Slave 7-Bit Address Recognition Mode
• Slave 10-Bit Address Recognition Mode Slave 7-Bit Address Recognition Mode. If IRM = 0 during the address phase and the controller is configured for MASTER/SLA VE or SLAVE 7-BIT ADDRESS Mode, the hardware detects a match to the 7-bit slave address defined in the I2CSLV AD Register and generates the slave address match interrupt (the SAM bit = 1 in the I2CISTAT Register). The I2C controller automatically responds during the Acknowledge phase with the value in the NAK bit of the I2CCTL Register.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 320 Slave 10-Bit Address Recognition Mode. If IRM = 0 during the address phase and the controller is configured for MASTER/SLA VE or SLAVE 10-BIT ADDRESS Mode, the hardware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLV AD registers and generates the slave address match interrupt (the SAM bit = 1 in the I2CISTAT Register). The I2C controller automatically responds during the Acknowl- edge phase with the value in the NAK bit of the I2CCTL Register. 16.2.6.2. General Call and Start Byte Address Recognition If GCE = 1 and IRM = 0 during the address phase and the controller is configured for mas- ter/slave or slave in either 7- or 10-bit address modes, the hardware detects a match to the General Call Address or the start byte and generates the slave address match interrupt. A General Call Address is a 7-bit address of all zeroes, with the R/W bit = 0. A start byte is a 7-bit address of all zeroes, with the R/W bit = 1. The SAM and GCA bits are set in the I2CISTAT Register. The RD bit in the I2CISTAT Register distinguishes a General Call Address from a start byte which is cleared to 0 for a General Call Address). For a General Call Address, the I2C controller automatically responds during the address acknowledge phase with the value in the NAK bit of the I2CCTL Register. If the software is set to pro- cess the data bytes associated with the GCA bit, the IRM bit can optionally be set follow- ing the SAM interrupt to allow the software to examine each received data byte before deciding to set or clear the NAK bit. A start byte will not be acknowledged – a require- ment of the I2C specification. 16.2.6.3. Software Address Recognition To disable hardware address recognition, the IRM bit must be set to 1 prior to the recep- tion of the address byte(s). When IRM = 1, each received byte generates a receive interrupt (RDRF = 1 in the I2CISTAT Register). The software must examine each byte and deter- mine whether to set or clear the NAK bit. The slave holds SCL Low during the acknowl- edge phase until the software responds by writing to the I2CCTL Register. The value written to the NAK bit is used by the controller to drive the I2C bus, then releasing the SCL. The SAM and GCA bits are not set when IRM = 1 during the address phase, but the RD bit is updated based on the first address byte. 16.2.6.4. Slave Transaction Diagrams In the following transaction diagrams, the shaded regions indicate data transferred from the master to the slave and the unshaded regions indicate the data transferred from the slave to the master. The transaction field labels are defined as follows: SS t a r t WW r i t e A Acknowledge A Not Acknowledge PS t o p

operating as a slave in 7-bit addressing mode and receiving data from the bus master.

1. The software configures the co ntroller for operation as a slave in 7-bit addressing

Mode or MASTER/SLA VE Mode with 7-bit addressing. b. Optionally set the GCE bit. c. Initialize the SLA[6:0] bits in the I 2C Slave Address Register. d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.

1. The bus master initiates a tran sfer, sending the address byte. In SLAVE Mode, the I2C
2. The software responds to the in terrupt by reading the I2CISTAT Register (which

clears the SAM bit). After seeing the SAM bit to 1, the software checks the RD bit. Because RD = 0, no immediate action is required until the first byte of data is received.

1. The master detects the Acknowledge and sends the byte of data .
2. The I 2C controller receives the data byte and responds with an Acknowledge or a Not
3. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1

one more data byte, it sets the NAK bit in the I2CCTL Register.

1. The master and slave loops through Step 4 to Step 6 until the master detects a Not

Acknowledge instruction or runs out of data to send. Figure 50. Data Transfer Format, Slave Receive Transaction with 7-Bit Address

1. The master sends the stop or restart signal on the bus. Either of these signals can cause

the I2C controller to assert a stop interrupt (the stop bit = 1 in the I2CISTAT Register). stop bit in the I2CISTAT Register. operating as a slave in 10-bit addressing mode and receiving data from the bus master.

1. The software configures the co ntroller for operation as a slave in 10-bit addressing

Mode or MASTER/SLA VE Mode with 10-bit addressing. b. Optionally set the GCE bit. d. Set IEN = 1 in the I2CCTL Register. Set NAK = 0 in the I2C Control Register.

1. The master initiates a transfer, sending the first address byte. The I2C controller recog-

available to accept the transaction.

1. The master sends the second a ddress byte. The SLA VE Mode I2C controller detects an
2. The software responds to the interrupt by reading the I2CISTAT Register, which clears

the NAK bit in the I2CCTL Register.

1. The master detects the Acknowl edge and sends the first byte of data.

Figure 51. Data Transfer Format, Slave Receive Transaction with 10-Bit Address

1. The I 2C controller receives the first byte and responds with Acknowledge or Not
2. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1

can accept only one more data byte, it sets the NAK bit in the I2CCTL Register.

1. The master and slave loops through Step 5 to Step 7 until the master detects a Not

Acknowledge instruction or runs out of data to send.

1. The master sends the stop or restart signal on the bus. Either of these signals can cause

operating as a slave in 7-bit addressing mode and transmitting data to the bus master.

1. The software configures the co ntroller for operation as a slave in 7-bit addressing

Mode or MASTER/SLA VE Mode with 7-bit addressing. b. Optionally set the GCE bit. c. Initialize the SLA[6:0] bits in the I 2C Slave Address Register. d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.

1. The master initiates a transfer by sending the address byte. The SLA VE Mode I2C

rupt. The RD bit is set to 1, indicating a read from the slave.

1. The software responds to the in terrupt by reading the I2CISTAT Register, thereby

Figure 52. Data Transfer Format, Slave Transmit Transaction with 7-bit Address

1. SCL is released and the firs t data byte is shifted out.
2. After the first bit of the fir st data byte has been transferred, the I2C controller sets the

TDRE bit, which asserts the transmit data interrupt.

1. The software responds to the tr ansmit data interrupt (TDRE = 1) by loading the next

data byte into the I2CDATA Register, which clears TDRE.

1. After the data byte has been r eceived by the master, the master transmits an Acknowl-

edge instruction (or a Not Acknowledge instruction if this byte is the final data byte).

1. The bus cycles through Step 5 to Step 7 until the final byte has been transferred. If the

Not Acknowledge interrupt to be generated.

1. The software responds to the Not Acknowledge interrupt by clearing the TXI bit in the
2. When the master has completed the final acknowledge cycle, it asserts a stop or restart
3. The slave I2C controller asserts the stop/restart interrupt (i.e., sets the SPRS bit in the
4. The software responds to the stop/restart interrupt by reading the I2CISTAT Register,

operating as a slave in 10-bit addressing mode, transmitting data to the bus master.

1. The software configures the co ntroller for operation as a slave in 10-bit addressing

Figure 53. Data Transfer Format, Slave Transmit Transaction with 10-Bit Address

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 325 a. Initialize the MODE field in the I 2C Mode Register for either SLAVE ONLY Mode or MASTER/SLA VE Mode with 10-bit addressing. b. Optionally set the GCE bit. c. Initialize the SLA[7:0] bits in the I2CSLV AD Register and SLA[9:8] in the I2C MODE Register. d. Set IEN = 1 and NAK = 0 in the I2C Control Register. 2. The master initiates a transfer by sending the first address byte. The SLA VE Mode I2C controller recognizes the start of a 10-bit address with a match to SLA[9:8], and detects R/W bit = 0 (i.e., a write from the master to the slave). The I2C controller acknowledges, indicating it is available to accept the transaction. 3. The master sends the second address byte. The SLA VE Mode I2C controller compares the second address byte with the value in SLA[7:0]. If there is a match, the SAM bit in the I2CISTAT Register is set = 1, causing a slave address match interrupt. The RD bit is set = 0, indicating a write to the slave. If a match occurs, the I2C controller acknowl- edges on the I2C bus, indicating it is available to accept the data. 4. The software responds to the slave address match interrupt by reading the I2CISTAT Register, which clears the SAM bit. Because the RD bit = 0, no further action is required. 5. The master sees the Acknowledge and sends a restart instructi on, followed by the first address byte with R/W set to 1. The SLA VE Mode I2C controller recognizes the restart instruction, follows with the first address byte with a match to SLA[9:8], and detects R/W = 1 (i.e, the master reads from the slave). The slave I2C controller sets the SAM bit in the I2CISTAT Register, which causes the slave address match interrupt. The RD bit is set = 1. The SLA VE Mode I2C controller acknowledges on the bus. 6. The software responds to the interrupt by reading the I2CISTAT Register and clearing the SAM bit. The software loads the initial data byte into the I2CDATA Register and sets the TXI bit in the I2CCTL Register. 7. The master starts the data transfer by asserting SCL Low. Aft er the I2C controller has data available to transmit, the SCL is released and the master proceeds to shift the first data byte. 8. After the first bit of the fir st data byte has been transferred, the I2C controller sets the TDRE bit which asserts the transmit data interrupt. 9. The software responds to the transmit data interrupt by loadi ng the next data byte into the I2CDATA Register. 10. The I2C master shifts in the remainder of the data byte. The master transmits the Acknowledge (or Not Acknowledge, if this byte is the final data byte). 11. The bus cycles through Step 7 to Step 10 until the final byte is transferred. If the soft- ware has not yet loaded the next data byte when the master brings SCL Low to trans-

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 326 fer the most significant data bit, the slave I2C controller holds SCL Low until the Data Register is written. When a Not Acknowledge is received by the slave, the I2C controller sets the NCKI bit in the I2CISTAT Register, causing the NAK interrupt to be generated. 12. The software responds to the NAK interrupt by clearing the TXI bit in the I2CCTL Register and by asserting the FLUSH bit of the I2CCTL Register. 13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a stop or restart condition on the bus. 14. The slave I2C controller asserts the stop/restart interrupt (i.e., sets the SPRS bit in the I2CISTAT Register). 15. The software responds to the stop interrupt by reading the I2CISTAT Register and clearing the SPRS bit. 16.2.7. DMA Control of I2C Transactions The DMA engine is configured to support transmit and receive DMA requests from the I2C Controller. The I2C data interrupt requests must be disabled by setting the DMAIF bit in the I2C Mode Register and clearing the TXI bit in the I2C Control Register. These actions allow error condition interrupts to be handled by software while data movement is handled by the DMA engine. The DMA interface on the I2C Controller is intended to support data transfer but not MASTER Mode address byte transfer. The start, stop, and NAK bits must be controlled by software. A summary of I2C transfer of data using the DMA follows. 16.2.7.1. Master Write Transaction with Data DMA

• Configure the selected DMA channel for I2C transmit. The IEOB bit must be set in the DMAxCTL0 Register for the last buffer to be transferred.
• The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C error conditions. A Not Acknowledge interrupt occurs on the last byte transferred.
• The I2C master/slave must be configured as defined in the sections above describing MASTER Mode transactions. The TXI bit in the I2CCTL Register must be cleared.
• Initiate the I2C transaction, as described in the Master Address-Only Transactions sec- tion on page 312, using the ACKV and ACK bits in the I2CSTATE Register to deter- mine if the slave acknowledges.
• Set the DMAIF bit in the I2CMODE Register.
• The DMA transfers the data, which is to be transmitted to the slave.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 327

• When the DMA interrupt occurs, poll the I2CSTAT Register until the TDRE bit = 1. This polling sequence ensures that the I2C master/slave hardware has commenced transmitting the last byte written by the DMA.
• Set the stop bit in the I2CCTL Register. The stop bit is polled by software to determine when the transaction is actually completed.
• Clear the DMAIF bit in the I2CMODE Register. If the slave sends a Not Acknowledge prior to the last byte, a Not Acknowledge interrupt occurs. Software must respond to this interrupt by clearing the DMAIF bit and setting the stop bit to end the transaction. 16.2.7.2. Master Read Transaction with Data DMA In master read transactions, the master is responsible for the Acknowledge for each data byte transferred. The master software must set the NAK bit after the next to the last data byte has been received, or while the last byte is being received. The DMA supports these actions by setting the DMA watermark to 1, which results in a DMA interrupt when the next-to-the-last byte has been received. A DMA interrupt also occurs when the last byte is received. Otherwise, the sequence is similar to the sequence for the master write transac- tion described in the previous subsection.
• Configure the selected DMA channel for I2C receive. The IEOB bit must be set in the DMAxCTL0 Register for the last buffer to be transferred. Typically, one buffer is de- fined with a transfer length of N, in which N bytes are expected to be read from the slave. The watermark is set to 1 by setting WMCNT to 0001 in the DMAxCNTH Reg- ister.
• The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C error conditions. A Not Acknowledge interrupt occurs on the last byte transferred.
• The I2C master/slave must be configured as defined in a previous section describing MASTER Mode transactions. The TXI bit in the I2CCTL Register must be cleared.
• Initiate the I2C transaction as described in the Master Address-Only Transactions sec- tion on page 312, using the ACKV and ACK bits in the I2CSTATE Register to deter- mine if the slave acknowledges. Do not set the stop bit unless ACKV = 1 and ACK = 0 (i.e., slave did not acknowledge).
• Set the DMAIF bit in the I2CMODE Register.
• The DMA transfers the data to memory as it is received from the slave.
• When the first DMA interrupt occurs indicating the (N–1)st byte has been received, the NAK bit must be set in the I2CCTL Register. Note:

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 328

• When the second DMA interrupt occurs, it indicates that the Nth byte has been re- ceived. Set the stop bit in the I2CCTL Register; this stop bit is polled by software to determine when the transaction is actually completed.
• Clear the DMAIF bit in the I2CMODE Register. 16.2.7.3. Slave Write Transaction with Data DMA In a transaction in which the I2C master/slave operates as a slave that receives data written by a master, the software must set the NAK bit after the (N–1)st byte has been received or during the reception of the last byte. As in the Master Read transaction described previ- ously, the watermark DMA interrupt is used to notify software when the (N–1)st byte has been received.
• Configure the selected DMA channel for I2C receive. The IEOB bit must be set in the DMAxCTL0 Register for the last buffer to be transferred. Typically, one buffer will be defined with a transfer length of N where N bytes are expected to be received from the master. The watermark is set to 1 by setting WMCNT to 0001 in the DMAxCNTH Reg- ister.
• The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C error conditions.
• The I2C master/slave must be configured as defined in a previous section describing SLAVE Mode transactions. The TXI bit in the I2CCTL Register must be cleared.
• When the SAM interrupt occurs, set the DMAIF bit in the I2CMODE Register.
• The DMA transfers the data to memory as it is received from the master.
• When the first DMA interrupt occurs indicating that the (N–1)st byte is received, the NAK bit must be set in the I2CCTL Register.
• When the second DMA interrupt occurs, it indicates that the Nth byte is received. A stop I2C interrupt occurs (SPRS bit set in the I2CSTAT Register) when the master is- sues the stop (or restart) condition.
• Clear the DMAIF bit in the I2CMODE Register. 16.2.7.4. Slave Read Transaction with Data DMA In this transaction the I2C master/slave operates as a slave, sending data to the master.
• Configure the selected DMA channel for I2C transmit. The IEOB bit must be set in the DMAxCTL0 Register for the last buffer to be transferred. Typically, a single buffer with a transfer length of N is defined.
• The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C error conditions. A Not Acknowledge interrupt occurs on the last byte transferred.
• The I2C master/slave must be configured as defined in the sections above describing SLAVE Mode transactions. The TXI bit in the I2CCTL Register must be cleared.

• When the SAM interrupt occurs, set the DMAIF bit in the I2CMODE Register.
• The DMA transfers the data to be transmitted to the master.
• When the DMA interrupt occurs, the last byte is being transferred to the master. The master must send a Not Acknowledge for this last byte, setting the NCKI bit in the I2CSTAT Register and generating the I2C interrupt. A stop or restart interrupt follows (i.e., the SPRS bit is set in the I2CSTAT Register).
• Clear the DMAIF bit in the I2CMODE Register. If the master sends a Not Acknowledge prior to the last byte, software responds to the Not Acknowledge interrupt by clearing the DMAIF bit. 16.3. I 2C Control Register Definitions The I2C Control registers are described in this section. 16.3.1. I2C Data Register The I2C Data Register listed in Table 154 contains the data that is to be loaded into the Shift Register to transmit onto the I2C bus. This register also contains data that is loaded from the Shift Register after it is received from the I2C bus. The I2C Shift Register is not accessible in the Register File address space, but is used only to buffer incoming and out- going data. Writes by the software to the I2CDATA Register are blocked if a slave write transaction is underway (the I2C controller is in SLAVE Mode and data is being received).

Table 154. I2C Data Register (I2CDATA = F50h)

Table 155. I2C Interrupt Status Register (I2CISTAT = F51h) shifting in data during the reception of a byte or when shifting an address and the RD bit is set. This bit clears by writing to the I2CDATA Register. clears by reading the I2CDATA Register. reading the I2CISTAT Register. updated following the first address byte of each transaction.

The I2C Control Register, shown in Table 156, enables and configures I2C operation. The R/W1 bit can be set (written to 1) when IEN = 1, but cannot be cleared (written to 0). interrupt was caused by a stop or restart condition. Table 156. I2C Control Register (I2CCTL) This bit enables the I2C controller.

PS029413-0921 P R E L I M I N A R Y I 2C Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 332 16.3.4. I2C Baud Rate High and Low Byte Registers The I2C Baud Rate High and Low Byte registers, shown in Tables 157 and 158, combine to form a 16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator. [6] START Send Start Condition When set, this bit causes the I2C controller (when configured as the master) to send a start condition. After it is asserted, this bit is cleared by the I2C controller after it sends the start condition or by deasserting the IEN bit. If this bit is 1, it cannot be cleared by writing to the bit. After this bit is set, a start condition is sent if there is data in the I2CDATA or I2C Shift Register. If there is no data in one of these registers, the I2C controller waits until data is loaded. If this bit is set while the I2C controller is shifting out data, it generates a restart condition after the byte shifts and the Acknowledge phase completes. If the stop bit is also set, it waits until the stop condition is sent before the start condition. If start is set while a SLAVE Mode transaction is underway to this device, the start bit will be cleared and ARBLST bit in the Interrupt Status Register will be set. [5] STOP Send Stop Condition When set, this bit causes the I2C controller (when configured as the master) to send the stop condition after the byte in the I2C Shift Register has completed transmission or after a byte is received in a receive operation. When set, this bit is reset by the I2C controller after a stop condition has been sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register. If a stop is set while a SLAVE Mode transaction is underway, the stop bit is cleared by hardware. [4] BIRQS Baud Rate Generator Interrupt Request Select This bit is ignored when the I2C controller is enabled. If this bit is set = 1 when the I2C controller is disabled (IEN = 0), the baud rate generator is used as an additional timer causing an interrupt to occur every time the baud rate generator counts down to one. The baud rate generator runs continuously in this mode, generating periodic interrupts. [3] TXI Enable TDRE Interrupts This bit enables interrupts when the I2C Data Register is empty. [2] NAK Send NAK Setting this bit sends a Not Acknowledge condition after the next byte of data has been received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register. [1] FLUSH Flush Data Setting this bit clears the I2C Data Register and sets the TDRE bit to 1. This bit allows flushing of the I2C Data Register when an NAK condition is received after the next data byte is written to the I2C Data Register. Reading this bit always returns 0. [0] FILTEN I2C Signal Filter Enable Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This function provides the spike suppression filter required in I2C Fast Mode. These filters reject any input pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock cycle latency on the inputs. Bit Description (Continued)

The I2C baud rate is calculated using the following equation. is calculated using the following equation. If BRG = 0000h, then use 10000h in the equation. the current value of the I2C Baud Rate Counter[15:8]. Table 157. I2C Baud Rate High Byte Register (I2CBRH = 53h) The most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value. Table 158. I2C Baud Rate Low Byte Register (I2CBRL = F54h)

the current value of the I2C Baud Rate Counter[7:0]. ler and I2C bus; see Table 161. I2C controller state machine. The least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value. Table 159. I2C State Register (I2CSTATE), Description when DIAG = 1 the internal state machine. Table 161 defines the states for this field.

Table 160. I2C State Register (I2CSTATE), Description when DIAG = 0 by a stop or restart condition. This bit indicates the status of the Acknowledge for the last byte transmitted or received. This bit is set for an Acknowledge and cleared for a Not Acknowledge condition. This bit is active High while the address is being transferred on the I2C bus. This bit is active High while the data is being transferred on the I2C bus. this bit is set. When set, it is Reset after the address has been sent. SDA signals on the I2C bus can be observed via the GPIO Input Register. 0: No activity on the I2C Bus. 1: A transaction is underway on the I2C bus.

Table 161. I2CSTATE_H 0000 Idle I 2C bus is idle or I2C controller is disabled. 0001 Slave Start I 2C controller has received a start condition. 0010 Slave Bystander Address did no t match; ignore remainder of transaction.

0011 Slave Wait Waiting for stop o r restart condition after sending a Not

0100 Master Stop2 Master compl eting stop condition (SCL = 1, SDA = 1). 0101 Master Start/Restart MASTER M ode sending start condition (SCL = 1, SDA = 0). 0110 Master Stop1 Master ini tiating stop condition (SCL = 1, SDA = 0).

0111 Master Wait Master received a Not Acknowledge instruction, w aiting for

software to assert stop or start control bits. 1000 Slave Transmit Data Nine subs tates, one for each data bit and one for the Acknowledge. 1001 Slave Receive Data Nine subst ates, one for each data bit and one for the Acknowledge.

1010 Slave Receive Addr1 Slave rec eiving first address byte (7- and 10-bit addressing) Nine

substates, one for each address bit and one for the Acknowledge.

1011 Slave Receive Addr2 Slave rec eiving second address byte (10-bit addressing) nine

substates, one for each address bit and one for the Acknowledge. 1100 Master Transmit Data Nine sub states, one for each data bit and one for the Acknowledge. 1101 Master Receive Data Nine subs tates, one for each data bit and one for the Acknowledge.

1110 Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing) nine

substates, one for each address bit and one for the Acknowledge.

1111 Master Transmit Addr2 Master sending second address byte (10 -bit addressing) nine

substates, one for each address bit and one for the Acknowledge. Table 162. I2CSTATE_L

0001 Master Restart Master is endin g one transaction and starting a

new one without letting the bus go idle.

ating mode, slave address and diagnostic modes. 1000–1111 0111 Send/Receive bit 7 S ending/Receiving most significant bit.

0110 Send/Receive bit 6

0101 Send/Receive bit 5

0100 Send/Receive bit 4

0011 Send/Receive bit 3

0010 Send/Receive bit 2

0001 Send/Receive bit 1

0000 Send/Receive bit 0 Sending/Re ceiving least significant bit.

1000 Send/Receive

Sending/Receiving Acknowledge. Table 163. I 0: Used when software polling or interrupts are used to move data. transmit DMA request. The assertion of RDRF causes a receive DMA request. 00: MASTER/SLAVE capable (supports multi-master arbitration) with 7-bit slave address. 01: MASTER/SLAVE capable (supports multi-master arbitration) with 10-bit slave address. 10: Slave Only capable with 7-bit address. 11: Slave Only capable with 10-bit address. Table 162. I2CSTATE_L (Continued)

PS029413-0921 P R E L I M I N A R Y I 2C Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 338 [4] IRM Interactive Receive Mode Valid in SLAVE Mode when software must interpret each received byte before acknowledging. This bit is useful for processing the data bytes following a General Call Address or if software wants to disable hardware address recognition. 0: Acknowledge occurs automatically and is determined by the value of the NAK bit of the I2CCTL Register. 1: A receive interrupt is generated for each byte received (address or data). The SCL is held Low during the Acknowledge cycle until software writes to the I2CCTL Register. The value written to the NAK bit of the I2CCTL Register is output on SDA. This value allows software to Acknowledge or Not Acknowledge after interpreting the associated address/ data byte. [3] GCE General Call Address Enable Enables reception of messages beginning with the General Call Address or start byte. 0: Do not accept a message with the General Call Address or start byte. 1: Do accept a message with the General Call Address or start byte. When an address match occurs, the GCA and RD bits in the I2C Status Register indicates whether the address matched the General Call Address/start byte or not. Following the General Call Address byte, the software can set the IRM bit that allows software to examine the following data byte(s) before acknowledging. [2:1] SLA[9:8] Slave Address Bits 9 and 8 Initialize with the appropriate slave address value when using 10-bit slave addressing. These bits are ignored when using 7-bit slave addressing. [0] DIAG Diagnostic Mode Selects read back value of the Baud Rate Reload and State registers. 0: Reading the baud rate registers returns the baud rate register values. Reading the state register returns I2C controller state information. 1: Reading the Baud Rate registers returns the current value of the baud rate counter. Reading the state register returns additional state information. Bit Description (Continued)

order address bits used in 7- and 10-bit slave address recognition. Table 164. I2C Slave Address Register (I2CSLVAD = 57h)

• Full-speed (12 Mbps) USB device
• IN endpoint 0 and OUT endpoint 0 control endpoints
• IN endpoints 1–3 and OUT endpoints 1–3 capable of bulk and interrupt transfers
• USB Suspend, host-initiated Resume, and device-initiated Resume (remote wake-up)
• USB clock of 48 MHz from internal PLL or external clock source; see the Clock Sys- tem chapter on page 96 to learn more
• 512 bytes of dedicated USB endpoint buffer memory; each endpoint buffer memory can be configured as 8, 16, 32, or 64 bytes
• Integrated full-speed USB PHY with integrated pull-up resistor
• Support for two DMA channels 17.1. Architecture The architecture, shown in Figure 54,consists of a USB device, USB endpoint buffer memory, and a USB PHY .

Figure 54. USB Block Diagram

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 341 17.2. Operation The USB Module is a USB 2.0-compliant full-speed device with an integrated PHY and dedicated buffer memory space. The serial data rate for full-speed USB is 12 Mbps. The USB Module performs serial-to-parallel conversion for received data and parallel-to-serial conversion for transmit. USB data flow terminology is relative to the USB host. Data transmitted by the USB host is transmitted to a USB device OUT endpoint. Data to be sent to the USB host by a USB device is placed into a USB device IN endpoint buffer space prior to transmission. These endpoint buffer spaces can be accessed by software or by DMA. The USB Module requires an accurate 48 MHz clock, which can be supplied from the internal PLL or an external clock source, as described in the Clock System chapter on page 96. 17.2.1. Overview of USB Registers and Subregisters Seven registers provide access to the USB Module: three registers for USB special func- tions (SFRs) and endpoint buffer memory, three registers for DMA control and data, and one register for resuming interrupt control. Table 169 on page 356 lists these USB regis- ters. The USB clock must be running to access the USB special function registers (SFRs) or endpoint buffer memory. When ADDRSEL = 0 in the USB Subaddress Register (USBSA), the USBSA provides address selection for subregisters in USB SFR address space. To access a USB Module SFR, write the USBSA Register with the appropriate SFR address, then read or write the USB Subdata Register (USBSD). When ADDRSEL = 1 in the USBSA, the USBSA and the USB Control Register (USBCTL) together provide addressing for endpoint buffer memory. To access the USB Module endpoint buffer space, select an endpoint buffer with the USBCTL Register, write the USBSA Register with the appropriate address within the selected USB endpoint buffer space, then read or write the USBSD Register. In addition, AI in the USBCTL Register controls autoincrementing of endpoint buffer memory accesses. Autoincrementing of endpoint memory buffer accesses is enabled if AI = 0 and disabled if AI = 1. Accesses to SFRs do not autoincrement. The usage of the three DMA registers is described in the DMA section on page 355. The usage of the USB Interrupt Control Register is covered in the Interrupts section on page 355. 17.2.2. USB Endpoint Buffer Memory The USB Module contains a dedicated 512-byte endpoint buffer space that provides up to 64 bytes of endpoint buffer memory for each endpoint. Data transmitted by the USB host is transmitted to a USB Module OUT endpoint buffer space. Data to be transmitted to the

to transmission. These endpoint buffer spaces can be accessed by software or by DMA. the size of each endpoint buffer memory must be configured. endpoint used. The size of an endpoint buffer space is a multiple of 2 bytes. and OUT endpoints 3 are not used. Example register values are shown in Figure 55. Table 165. Determining USB Endpoint Buffer Memory Allocation with All Endpoints Used

Table 166. Determining USB Endpoint Buffer Memory

performed, as described in the following sections. USB OUT Endpoint Valid Subregister (USBOUTV AL). Figure 55. Example Endpoint Buffer Memory Allocation

64 Bytes

16 Bytes

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 345 17.2.4. USB Control Transfers Using Endpoint 0 A control transfer consists of two or three stages:

• Setup stage
• Data stage (optional)
• Status stage The following describes control write and control read transfers, in addition to the associ- ated status and interrupt bit. 17.2.4.1. Control Write In the Setup stage of a control transfer, after receiving a Setup token, the USB Module sets the HSNAK bit in the USB Endpoint 0 Control and Status Subregister (USBEP0CS) and the SUTOKIRQ bit in the USB Protocol Interrupt Request Subregister (USBIRQ). A USB interrupt is generated if the SUTOKIEN bit is set in the USB Protocol Interrupt Enable Subregister (USBIEN). Subsequently, if an 8-byte data packet is received correctly, the USB Module sets the SUDA VIRQ bit in the USBIRQ Subregister and a USB interrupt is generated if the SUDA VIEN bit is set in the USBIEN Subregister. The 8-byte data packet can be accessed from the USB Setup Buffer Byte 0–7 subregisters (USBSUx), as described in the Setup Buffer section on page 347. The Data stage of a control transfer consists of one or more OUT bulk-like transactions. After each correct OUT packet is received during the Data stage, the USB Module sets the OUT0IRQ bit in the USB OUT Interrupt Request Subregister (USBOUTIRQ), and a USB interrupt is generated if the OUT0IEN is set in the USB OUT Interrupt Enable Subregister (USBOUTIEN). The OUT0BC Subregister contains the number of data bytes received in the last OUT transaction. Software should service the interrupt request, then prepare the endpoint for the next transaction by reloading the OUT0BC Subregister with any value, which results in hardware setting the OUTBUSY bit in the USBEP0CS Subregister. Until this preparation task is performed, the USB Controller will NAK subsequent data packets. The Status stage of a control transfer is the final operation in the sequence. Software should clear the HSNAK bit (by writing a 1 to it) to instruct the USB Module to ACK the Status stage. The USB Module sends the STALL handshake when both HSNAK and STALL bits are set. Prior to the Status stage, after the last successful transaction in the Data stage when all expected bytes of the transfer have been received or sent by the USB Module and a STALL handshake is to be sent for any additional data stage tokens, DSTALL is typically set by software. When DSTALL is set, the USB Module will send a STALL handshake if additional data stage tokens are sent and, if this transmission occurs, the STALL bit will be automatically set so that the USB Module will send a STALL hand- shake in the Status stage. If DSTALL is set, a token that indicates a transition to the status stage (e.g., an OUT token for an IN endpoint) will not cause a STALL handshake. A control write transfer example is shown in Figure 56.

Control read transfer is similar to control write transfer. The difference is in the Data stage. Figure 56. Control Write Transfer Example

0 Byte Data

8 Byte Data

USBSUx contains the data packet. the next Data stage transaction. Clear HSNAK to ACK the Status stage.

STALL handshake when both HSNAK and STALL bits are set. USB Module receives a setup data packet. Software clears CHGSET by writing a 1 to it. Software should access the USBSUx subregisters and identify and respond to the request. Figure 57. Control Read Transfer Example USBSUx contains the data packet. the next Data stage transaction. Clear HSNAK to ACK the Status stage.

packet. In the following discussion, x = 1–3. details the USB Module response to the host upon receiving an IN token. Figure 58. Bulk IN Transfer Example endpoint x for the next transaction.

transaction to complete (45us for full-speed USB). during an OUT token or data phase, the USB Module will not return a handshake. Table 168 details the USB Module response to the host upon receiving an OUT token. that all INBUSY bits are cleared. Table 167. USB Module Response to Host upon Receiving an IN Token

function address matches the function address assigned to the USB Module. other buffer via the USB Module. Figure 59. Bulk OUT Transfer Example Table 168. USB Module Response to Host upon Receiving an OUT Token the next OUT endpoint x transaction.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 351 ware should not access the IN endpoint 3 buffer space, the IN3VAL bit, the IN3IEN bit, the IN3IRQ bit, the USBI3BC Subregister, or the USB3ICS Subregister. To begin arming the paired IN endpoints, load the IN endpoint 2 buffer memory space twice. After each load is completed, write the number of bytes loaded to the USBI2BC Subregister to arm the endpoint buffer space. The USB Module readdresses the second IN endpoint 2 buffer memory load to IN endpoint 3 buffer memory. After the second write to the USBI2BC Subregister, both endpoints of the pair are armed and the INBUSY bit in the USB IN 2 Control and Status Subregister (USBIN2CS) is set by hardware. Software should not load new data into the IN endpoint 2 buffer space while INBUSY is set. When one or both of the endpoint buffer spaces of the pair become empty (unarmed), the INBUSY bit is cleared by hardware, and software may fill the IN endpoint 2 buffer mem- ory with new data and again load the USBI2BC Subregister to arm the endpoint for trans- mission. Clearing the INBUSY bit (by writing a 1 to it) causes both of the paired endpoints to unarm. A USB interrupt request is generated after each data packet is cor- rectly sent, independent of the INBUSY bit in the USBIN2CS Subregister. OUT endpoints 2 and 3 are paired by setting PROUT23 in the USBPAIR Subregister. When OUT endpoints 2 and 3 are paired, the OUT endpoint 2 subregisters govern control of the paired endpoints; software should access only the OUT endpoint 2 buffer space. The USB Module manages readdressing, as required, to utilize the OUT endpoint 3 buffer space. Software is not required to configure the OUT endpoint 3 control bits and registers. When paired, software should not access the OUT endpoint 3 buffer space, the OUT3V AL bit, the OUT3IEN bit, the OUT3IRQ bit, the USBO3BC Subregister, or the USBO3CS Subregister. To arm the paired OUT endpoints, load the USBO2BC Subregister twice. After the second write to the USBO2BC Subregister, both endpoints of the pair are armed, and the OUT- BUSY bit in the USB OUT 2 Control and Status Subregister (USBO2CS) is set by hard- ware. When both endpoint buffer spaces of the pair are empty and no data is available, the OUTBUSY bit is set by hardware. When one or both of the buffers contain valid data, the OUTBUSY bit is cleared by hardware. Clearing the OUTBUSY bit (by writing a 1 to it) causes both of the paired endpoints to unarm. A USB interrupt request is generated after each data packet is correctly received, independent of the OUTBUSY bit. 17.2.7. USB Transfer Control The following sections provide USB transfer control information. 17.2.7.1. Toggle Control Data packet synchronization is achieved via the use of a data sequence toggle bit for each endpoint, and for the DATA0/DATA1 Packet IDs (PIDs). The USB Module automatically toggles DATA0/DATA1 PIDs at every bulk transfer. Software can directly set or clear the data toggle bits using the USB Toggle Control Subregister (USBTOGCTL). Software should clear these data toggle bits when the host issues CLEAR_FEATURE or SET_INTERFACE, or selects an alternate setting.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 352 To read a current data toggle bit value, software should perform the following sequence: 1. Write the USBTOGCTL subadd ress to the USBSA Register. 2. Write the USBTOGCTL Subregister EP and IN/OUT fields to select the desired end- point while writing the remaining fields with zeroes. 3. Read the data toggle value, DATA, in the USBTOGCTL Subregiste r. To write a data toggle bit, software should perform the following sequence: 1. Write the USBTOGCTL subadd ress to the USBSA Register. 2. Write the USBTOGCTL Subregister EP and IN/OUT fields to select the desired end- point while writing the remaining fields with zeroes. 3. Repeat the write to the USBTOGCTL Subregister. The value writ ten should be the same as the previous write, with the exception that either TDATA1 should be config- ured to set the toggle data value to 1 or TDATA0 should be configured to clear the tog- gle data value to 0. 17.2.7.2. SOF and USB Frame Number The USB Module copies the received frame count into the USB Frame Count Low and USB Frame Count High subregisters (USBFCL and USBFCH) at every start of frame (SOF). Upon SOF, the SOFIRQ bit is set in the USB Protocol Interrupt Request Subregis- ter (USBIRQ), and a USB interrupt is generated if SOFIEN is set in the USB Protocol Interrupt Enable Subregister (USBIEN). In addition, using an internal timer, the USB Module can detect when an SOF from the host was missed. PLLCLK is the clock source for the internal timer. This feature is enabled by setting the SOFWDOG bit in the USB Control and Status Subregister (USBCS). If the SOF is missed, a USB interrupt is generated, and the SOFIRQ bit is set in the USB Proto- col Interrupt Request Subregister (USBIRQ). 17.2.7.3. USB Reset Bus State When the USB Reset bus state occurs, the USB Module reports the condition by setting the URESIRQ bit in the USBIRQ Subregister. A USB interrupt is generated if the URE- SIEN bit is set in the USBIEN Subregister. In addition, when a USB Reset bus state is detected, the function address in the USB Function Address Subregister (USBFNADDR) is reset to 00h by the USB Module. 17.2.8. Suspend/Resume Suspend is a mechanism for reducing power consumption from the USB (i.e., devices powered via the USB) when there is no traffic. The host initiates a Suspend by idling the USB for at least 3 ms. The Suspend is then detected by the USB Module, which should go into a reduced-power Suspend state. While in the Suspend state, either a USB device (such

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 353 as the USB Module) or the USB host can cause a Resume by changing the bus state to non-idle, after which USB devices can power up. 17.2.8.1. Suspend When the USB detects an idle condition on the bus that lasts for at least 3 ms, the SUS- PIRQ bit is set in the USB Protocol Interrupt Request Subregister (USBIRQ), and a USB interrupt is generated if the SUSPIEN bit is set in the USB Protocol Interrupt Enable Sub- register (USBIEN). When a Suspend is detected, the device should go into a reduced- power Suspend state. The following steps should be performed by software upon a USB interrupt due to a Suspend: 1. Read the USBIRQ Subregister to determine if the interrupt is due to the host signal- ling a Suspend. 2. Write any value to the USBCLKGA TE Subregister to gate off the USB clock and power down the USB PHY . 3. Optional: Disable the USB clock source (e.g., the PLL) if it is not currently selected as the system clock. 17.2.8.2. Device-Initiated Resume (Remote Wake-Up) The USB Module supports device-initiated Resume (i.e., remote wake-up). Software should verify if the device that initiated the Resume is allowed and enabled for the device prior to initiating a Resume. Two methods are available to perform a device-initiated Resume. To perform a device-initiated Resume using the USB Module to time the USB Idle state, observe the following procedure: 1. If it is not already running, configure the USB PLL for a 48 MHz output frequency, then enable the PLL and wait until it is stable. See the Clock System chapter on page 96 to learn more. 2. Set the RIRQE bit in the USBIR QCTL Register to enable both device-initiated and host-initiated Resume interrupt requests. Additionally, set the WAKEUP bit to initiate a Resume. 3. The USB Module will count 0–5 ms and a USB Resume interrupt will be generated after timing 5 ms of continuous USB bus Idle state. In addition, the WAKEUP bit in the USBIRQCTL Register will be cleared by the USB Module. 4. Read the DEVRSUME bit in the U SB Control and Status Subregister (USBCS) to determine if the Resume is device-initiated. 5. Set the SIGRSUME bit in the USB Control and Status Subregister (USBCS) to initiate remote wake-up signaling to the host. To raise the crossover voltage during remote wake-up signalling, software can first write the FORCEJ bit in the USB Control and Status Subregister (USBCS), then clear the FORCEJ bit and set the SIGRSUME bit.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 354 6. Wait 1–15 ms, then clear the SIGRSUME bit. To perform a device-initiated Resume using the software to time the USB Idle state, observe the following procedure: 1. Clear the RIRQE bit in the USBIRQCTL Register so that only a host-initiated Resume generates a USB Resume interrupt. 2. If it is not already running, configure the USB PLL for a 48 MHz output frequency, then enable the PLL and wait until it is stable. See the Clock System chapter on page 96 to learn more. 3. Ensure that the USB bus has b een continuously in the Idle state for a minimum of 5 ms, then set the WAKEUP bit in the USBIRQCTL Register to initiate a Resume. 4. Set the SIGRSUME bit in the USB Control and Status Subregister (USBCS) to initiate remote wake-up signaling to the host. To raise the crossover voltage during remote wake-up signalling by initially forcing the Data J bus state, software can first write to the FORCEJ bit in the USB Control and Status Subregister (USBCS), then clear the FORCEJ bit and set the SIGRSUME bit. 5. Wait 1–15 ms, then clear the SIGRSUME bit. 6. Clear the WAKEUP bit in the USBIRQCTL Register. 17.2.8.3. Host-Initiated Resume While in the Suspend state and not performing a device-initiated Resume, the RIRQE bit in the USBIRQCTL Register should be cleared. When the USB host wishes to wake up a USB device, it drives the Data K bus state on the USB bus for 20 ms. Upon detecting the Data K bus state, the USB Module generates a USB Resume interrupt. Software should perform the following steps to perform a host-initiated Resume:

• If it is not already running, configure the USB PLL for a 48 MHz output frequency, then enable the PLL and wait until it is stable. See the Clock System chapter on page 96 to learn more.
• Optional: When the USB Module recognizes PLLCLK, it will clear the DEVRSUME bit in the USB Control and Status Subregister (USBCS), which can be polled. If the RIRQE bit is set, another USB Resume interrupt request is generated; therefore, the RIRQE bit should be cleared during a host-initiated Resume. 17.2.9. Stop Mode Operation Stop Mode should only be entered when the USB Controller is either:
• Not available on the F6482 Series part number being used
• Unused, as indicated by DISCON = 1 in the USB Control and Status Subregister (USBCS)

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 355

• In the Standby State and no longer requires the USB clock While in Stop Mode, the USB controller can receive Resume signalling from the host, and will assert the USB Resume interrupt request if Resume signalling is received. 17.2.10.USB Module Interrupts and DMA The following sections describe the USB Module interrupts and DMA. 17.2.10.1.Interrupts The USB Module provides two interrupt requests: the USB Resume interrupt request that signals USB Resume, and the USB interrupt request that signals all other USB interrupts. While the RIRQE bit is cleared in the USBIRQCTL Register, the USB Resume interrupt is generated only upon host-initiated Resume. While the RIRQE bit is set, the USB Resume interrupt is generated upon both a host-initiated Resume and a device-initiated Resume. To learn more, see the Suspend/Resume section on page 352. Each USB interrupt request source that shares the USB interrupt request is associated to an interrupt request bit in either the USBINIRQ, USBOUTIRQ or USBIRQ Subregister. Each interrupt request bit has a corresponding interrupt enable bit in the USBINIEN, USBOUTIEN, or USBIEN Subregister which determines whether a particular interrupt request source generates a USB interrupt request. The current USB interrupt request source is furnished by the IID bit in the USB Interrupt Identification Subregister (USBIID). Because more than one USB interrupt request source can be active simultaneously, the contents of the IID bit are prioritized in the order listed in the description of the USB Interrupt Identification Subregister. To learn more, see the USB Interrupt Identification Subregister section on page 368. 17.2.10.2.DMA The USB Module provides USB endpoint buffer memory access for up to two DMA chan- nels. The two DMA channels can be independently configured to access any of the 4 IN or 4 OUT endpoints. In addition to the DMA control registers described in the Direct Mem- ory Access Controller chapter on page 390, the USB Module contains two DMA control registers, USBDMA0CTL and USBDMA1CTL, each providing additional control for a single DMA channel. Both DMA channels access endpoint buffer memory via the single USB DMA Data Reg- ister, USBDMADATA, using DMA fixed addressing. The USB Module performs autoin- crementing of the endpoint buffer memory address, from 0 to 63, at each DMA access. This endpoint buffer memory address is reset to 0 when the USB asserts a DMA request. It is not possible to start a DMA transfer at an endpoint memory buffer address other than 0. The USB DMA Control registers, USBDMA0CTL and USBDMA1CTL, are used to select which endpoint buffer memory is to be accessed by DMA and to initiate assertion of

interrupt to service the IN endpoint indicated by INxIRQ in the USBINIRQ Subregister. Register to select the appropriate IN endpoint and initiate assertion of a DMA request. Table 169. USB Registers and Subregisters Note: *The DMASA bit in the DMASA Register contains the subregister address.

Table 169. USB Registers and Subregisters (Continued) Note: *The DMASA bit in the DMASA Register contains the subregister address.

vide write access to all USB Module controls and buffer memory. and 6 of this register are forced to 0 by hardware. Table 170. USB Subaddress Register (USBSA) 0: Special Function Register (SFR). 1: Endpoint buffer selected by EPSEL in the USBCTL Register.

dress Register section on page 357. Table 171. USB Subdata Register (USBSD) ters that configure the USB operation as selected by the USBSA and USBCTL registers.

Table 172. USB Control Register (USBCTL) This bit is reserved and must be programmed to 0. 0: Accesses to the endpoint buffer selected by EPSEL will auto-increment. 1: Accesses to the endpoint buffer selected by EPSEL will not auto-increment. 000: IN endpoint 0 buffer memory. 001: IN endpoint 1 buffer memory. 010: IN endpoint 2 buffer memory. 011: IN endpoint 3 buffer memory. 100: OUT endpoint 0 buffer memory. 101: OUT endpoint 1 buffer memory. 110: OUT endpoint 2 buffer memory. 111: OUT endpoint 3 buffer memory. These bits are reserved and must be programmed to 000.

dent DMA channels can service the USB. Table 173. USB DMA 0–1 Control Registers (USBDMAxCTL) Note: x references bits in the range [1:0]. This bit is reserved and must be programmed to 00. 000: IN endpoint 0 buffer memory. 001: IN endpoint 1 buffer memory. 010: IN endpoint 2 buffer memory. 011: IN endpoint 3 buffer memory. 100: OUT endpoint 0 buffer memory. 101: OUT endpoint 1 buffer memory. 110: OUT endpoint 2 buffer memory. 111: OUT endpoint 3 buffer memory. This bit is reserved and must be programmed to 00. 0: DMA request is deasserted. DMA transfer completes. Software can also clear this bit to deassert DMA request.

simultaneously and access this register without conflict. pointer will point to the first byte after 64th byte is accessed. Table 174. USB DMA Data Register (USBDMADATA) 00–FF: DMA data value for the currently addressed endpoint buffer memory location.

Resume and to manage Resume interrupts. Table 175. USB Interrupt Control Register (USBIRQCTL) These bits are reserved and must be programmed to 000000. initiated resume interrupt to occur. USB has completed timing the Idle state. See Suspend/Resume on page 352 for details. 0: Do not perform a device-initiated resume. is running. See device-initiated resume (Remote Wake-up) on page 362 for details.

the USBISTADDR Register shown in Table 177, define the size of each OUT endpoint. Table 176. USB OUT Endpoint 1–3 Start Address Subregisters (USBOxADDR) Note: *R0/W = Write but reads back as 0.

address for IN endpoints and stop address for the uppermost OUT endpoint. Table 177. USB IN Endpoints Start Address Subregister (USBISTADDR) This bit is reserved and must be programmed to 0. address [9:0]; therefore the minimum increment of INSTADDR is 4 bytes of buffer memory.

shown in Table 200 on page 388, define the size of each IN endpoint. Table 178. USB IN Endpoint 1–3 Start Address Subregisters (USBIxADDR) Note: *R0/W = Write, but reads back as 0. Memory section on page 341 for details.

The USB Clock Gate Subregister, shown in Table 179, is used to disable the USB clock. USBCLKGATE Register is a write-only register. Table 179. USB Clock Gate Subregister (USBCLKGATE) Note: *R0/W = Write, b ut reads back as 0.

Table 180. USB Interrupt Identification Subregister (USBIID) This bit is reserved and must be programmed to 0. 00000: SUDAVIRQ in the USBIRQ Register. Highest priority. 00001: SOFIRQ in the USBIRQ Register. 00010: SUTOKIRQ in the USBIRQ Register. 00011: SUSPIRQ in the USBIRQ Register. 00100: URESIRQ in the USBIRQ Register. 00110: IN0IRQ in the USBINIRQ Register. 00111: OUT0IRQ in the USBOUTIRQ Register. 01000: IN1IRQ in the USBINIRQ Register. 01001: OUT1IRQ in the USBOUTIRQ Register. 01010: IN2IRQ in the USBINIRQ Register. 01011: OUT2IRQ in the USBOUTIRQ Register. 01100: IN3IRQ in the USBINIRQ Register. 01101: OUT3IRQ in the USBOUTIRQ Register. Lowest priority. These bits are reserved and must be programmed to 00.

corresponding register position. Table 181. USB IN Interrupt Request Subregister (USBINIRQ) Note: *R/W1 = Writing a 1 clears this bit. These bits are reserved and must be programmed to 0000. 0: No interrupt request from IN endpoint 3. 1: Interrupt request from IN endpoint 3. 0: No interrupt request from IN endpoint 2. 1: Interrupt request from IN endpoint 2. 0: No interrupt request from IN endpoint 1. 1: Interrupt request from IN endpoint 1. 0: No interrupt request from IN endpoint 0. 1: Interrupt request from IN endpoint 0.

Table 182. USB OUT Interrupt Request Subregister (USBOUTIRQ) Note: *R/W1 = Writing a 1 clears this bit. These bits are reserved and must be programmed to 0000. 0: No interrupt request from OUT endpoint 3. 1: Interrupt request from OUT endpoint 3. 0: No interrupt request from OUT endpoint 2. 1: Interrupt request from OUT endpoint 2. 0: No interrupt request from OUT endpoint 1. 1: Interrupt request from OUT endpoint 1. 0: No interrupt request from OUT endpoint 0. 1: Interrupt request from OUT endpoint 0.

Table 183. USB Protocol Interrupt Request Subregister (USBIRQ) Note: *R/W1 = Writing a 1 clears this bit. These bits are reserved and must be programmed to 000. 0: No USB Reset bus state detected. 1: USB Reset bus state detected. Write a 1 to this bit to clear the interrupt request. 1: USB suspend detected. Write a 1 to this bit to clear the interrupt request. 0: No USB Setup token received. 1: USB Setup token received. Write a 1 to this bit to clear the interrupt request. 0: No USB Start-of-Frame (SOF) packet received. 0: No error-free setup stage data packet received.

endpoint interrupt requests. Table 184. USB IN Interrupt Enable Subregister (USBINIEN) These bits are reserved and must be programmed to 0000. 0: Interrupts from IN endpoint 3 are disabled. 1: Interrupts from IN endpoint 3 are enabled. 0: Interrupts from IN endpoint 2 are disabled. 1: Interrupts from IN endpoint 2 are enabled. 0: Interrupts from IN endpoint 1 are disabled. 1: Interrupts from IN endpoint 1 are enabled. 0: Interrupts from IN endpoint 0 are disabled. 1: Interrupts from IN endpoint 0 are enabled.

OUT endpoint interrupt requests. Table 185. USB OUT Interrupt Enable Subregister (USBOUTIEN) These bits are reserved and must be programmed to 0000. 0: Interrupts from OUT endpoint 3 are disabled. 1: Interrupts from OUT endpoint 3 are enabled. 0: Interrupts from OUT endpoint 2 are disabled. 1: Interrupts from OUT endpoint 2 are enabled. 0: Interrupts from OUT endpoint 1 are disabled. 1: Interrupts from OUT endpoint 1 are enabled. 0: Interrupts from OUT endpoint 0 are disabled. 1: Interrupts from OUT endpoint 0 are enabled.

of USB protocol interrupt requests. Table 186. USB Protocol Interrupt Enable Subregister (USBIEN) These bits are reserved and must be programmed to 000. 0: No interrupt upon USB bus reset detect. 1: Interrupt upon USB bus reset detected. 0: No interrupt upon USB suspend detected. 1: Interrupt upon USB suspend detected. 0: No interrupt upon USB Setup token received. 1: Interrupt upon USB Setup token received. 0: No interrupt upon USB Start-of-Frame (SOF) packet received. 1: Interrupt upon USB Start-of-Frame (SOF) packet received. 0: No interrupt upon error free Setup data packet received. 1: Interrupt upon error free Setup data packet received.

and status for USB endpoint 0. Table 187. USB Endpoint 0 Control and Status Subregister (USBEP0CS) Note: *R/W1 = Writing a 1 clears this bit. These bits are reserved and must be programmed to 00. clears CHGSET by writing a 1 to it. 0: No change to the setup buffer contents. 1: Setup buffer contents changed. automatically set to 1 and USB Module will send STALL handshake also in the Status stage. STALL handshake. DSTALL is automatically cleared when a Setup token arrives. 0: Do not send a STALL handshake for any IN or OUT token in the Data stage. 0: Software has control of the OUT 0 endpoint buffer memory. clear OUTBUSY by writing a 1 to it.

cally when software writes BC in the USBEP0INBC Register. 0: Software has control of the IN 0 endpoint buffer memory. 1: INBUSY is automatically cleared when a Setup token arrives. 0: Do not send a NAK handshake. 1: Send a NAK handshake for every packet in the Status stage. STALL is automatically cleared when a Setup token arrives. 0: Do not send a STALL handshake. Table 188. USB IN 0–3 Byte Count Subregisters (USBIxBC) This bit is reserved and must be programmed to 0. BUSY is set, the USB Module will transmit a BC length data packet.

status for USB IN endpoints 1–3. Table 189. USB Subaddress Subregister (USBIxCS) These bits are reserved and must be programmed to 000000. INBUSY generates a USB interrupt request for the IN endpoint. empty and ready for loading by software. when software writes BC in the USBIxBC Subregister. 0: Do not send a STALL handshake. 1: Send a STALL handshake for all requests to the endpoint.

Table 190. USB OUT 0–3 Byte Count Subregisters (USBOxBC) This bit is reserved and must be programmed to 0.

and status for USB OUT endpoints 1–3. Table 191. USB OUT 1–3 Control and Status Subregisters (USBOxCS) These bits are reserved and must be programmed to 000000. 0 transition of OUTBUSY generates a USB interrupt request for the OUT endpoint. memory is ready for reading by software. ready to receive the next data packet from the host. 0: Do not send a STALL handshake. 1: Send a STALL handshake for all requests to the endpoint.

Table 192. USB Control and Status Subregister (USBCS) Note: *R/W1 = Writing a 1 clears this bit. Up) section on page 353 for details. 0: No device-initiated resume. 1: The USB Module resumed due to device-initiated resume. This bit is reserved and must be programmed to 0. issued by the USB host is missed. 0: Internal SOF timer is disabled. 1: Internal SOF timer is enabled. This bit is reserved and must be programmed to 0. 0: The internal pull-up resistor is connected. 1: The internal pull-up resistor is disconnected. This bit is reserved and must be programmed to 0.

formed to raise the crossover voltage to avoid a false Single-Ended-Zero (SE0). 0: No Force Data J Bus State Signaling. the data state for resume on the USB bus. 0: No remote device resume signaling. 1: Signal remote device resume by driving the Data K bus state on the USB bus. Table 193. USB Toggle Control Subregister (USBTOGCTL) Note: *R0/W = Write but reads back as 0. Before reading DATA, software should configure IN/OUT and EP to the desired endpoint. 0: The data toggle is set to DATA0 for the endpoint selected by IN/OUT and EP. 1: The data toggle is set to DATA1 for the endpoint selected by IN/OUT and EP. 0: Data toggle value unchanged. 1: Set the data toggle value to DATA1 for the endpoint selected by IN/OUT and EP. 0: Data toggle value unchanged.

0: OUT endpoint is selected. These bits are reserved and must be programmed to 00. Table 194. USB Frame Count Low Subregister (USBFCL) 00–FF: Lower 8-bits of the USB Frame Count.

PS029413-0921 P R E L I M I N A R Y USB Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 383

Table 195. USB Frame Count High Subregister (USBFCH) These bits are reserved and must be programmed to 00000. 0–7: Upper 3-bits of the USB Frame Count. Table 196. USB Function Address Subregister (USBFNADDR) This bit is reserved and must be programmed to 0. function address matches the function address assigned to the USB Module.

Table 197. USB Endpoint Pairing Subregister (USBPAIR) These bits are reserved and must be programmed to 0000. 0: OUT 2 and OUT 3 are not paired. 1: OUT 2 and OUT 3 are paired. These bits are reserved and must be programmed to 00. 0: IN 2 and IN 3 are not paired. 1: IN 2 and IN 3 are paired.

Table 198. USB IN Endpoint Valid Subregister (USBINVAL) These bits are reserved and must be programmed to 0000.

Table 199. USB OUT Endpoint Valid Subregister (USBOUTVAL) These bits are reserved and must be programmed to 0000.

address for the uppermost IN endpoint. Table 200. USB IN Endpoints Stop Address Subregister (USBISPADDR) These bits are reserved and must be programmed to 00. Memory section on page 341 for details.

Setup stage data packet from the latest control transfer. Table 201. USB Setup Buffer Byte 0–7 Subregisters (USBSUx) 00–FF: Setup data byte from the latest control transfer.

PS029413-0921 P R E L I M I N A R Y Direct Memory Access Controller Z8 Encore! XP® F6482 Series Product Specification 390 Chapter 18. Direct Memory Access Controller The Z8 Encore! Direct Memory Access (DMA) Controller provides four independent Direct Memory Access channels that provide high-speed transfers, offloading the CPU. The features of the DMA Controller include:

• Four independent DMA channels
• Flexible address control: fixed, increment, decrement, fixed word
• Register File <=> Register File, Register File <=> peripheral, peripheral <=> Register File, peripheral <=> peripheral transfers
• Direct or linked list operation
• Chaining of channel pairs to form a multi-transfer operation
• Round robin and fixed request priorities
• DMA and CPU bandwidth sharing control
• Up to 4 KB transfers
• End-of-count and watermark interrupts
• Two System Clock cycles per DMA transfer 18.1. Architecture The DMA Controller is comprised of four independent channels. Each channel has its own source, destination, transfer count and control registers. Each channel can be programmed to select one of the available DMA request sources. The DMA architecture, shown in Figure 60, consists of DMA request multiplexers, DMA channels, and the arbiter and bus controller.

CPU. Register Bus bandwidth allocation between the CPU and DMA is configurable. typical application would be to send data to serial channels such as I2C, UART, and SPI. The data to be sent is placed in a buffer by software. Figure 60. Direct Memory Access Block Diagram

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 392 18.2.1. DMA Registers and Subregisters Nine registers provide access to DMA control: two registers for each of the four DMA channels, plus a single global DMA control register. Use a DMA 0–3 Subaddress/Status Register (DMAxSA) and a DMA 0–3 Subdata Register (DMAxSd) together to provide access to subregisters for DMA channel configuration and control. DMAxSD provides a portal to the ten subregisters of each DMA channel. See the DMA Control Register Defi- nitions section on page 399 to learn more. 18.2.2. Address Control The DMA source address subregisters (DMAxSRCH and DMAxSRCL), containing the source address {SRCH, SRCL}, point to the data to be transferred. Each time a transfer occurs, the source address will either increment, decrement, stay fixed, or toggle the LSB (fixed word), as selected by the SRCCTL bit in the DMAxCTL0 subregisters. The destination address subregisters (DMAxDSTH and DMAxDSTL), containing the des- tination address {DSTH, DSTL}, point to the destination for the data transfer. Each time a transfer occurs, the destination address will either increment, decrement, stay fixed, or toggle the LSB (fixed word), as selected by the DSTCTL bit in the DMAxCTL0 subregis- ters. Fixed address control is useful when accessing 8-bit peripherals. Increment or decrement address control is useful when transferring a block of data, depending on the order of data in the buffer (ascending or descending). Fixed word address control provides convenient access to 2-byte data words from 16-bit peripherals such as in the timers or the ADC. After each transfer, the least significant bit of the fixed word address is toggled, and the byte count is decremented. If the initial address ends with 0, the next address will end with 1, effectively counting up. If the initial address ends with 1, the next address will end with 0, effectively counting down. 18.2.3. DMA Request Selection The DMA requestor is selected with the REQSELbit in the DMAxCTL1 registers. If REQSEL = 0, software initiates a DMA transfer upon enabling the DMA Controller. This selection is useful for transferring data between sections of the Register File. If REQSEL = 1–31, the corresponding peripheral identified in the DMAxCTL1 registers ini- tiates the DMA transfer. To learn more about when a particular DMA requestor asserts and deasserts a DMA request, refer to the following sections of this product specification: 10.1.5. Timer Interrupts and DMA – see page 170 11.4. Multi-Channel Timer Interrupts and DMA – see page 192 14.1.14. UART-LDD and DMA Support – see page 254 15.3.7. ESPI and DMA – see page 294

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 393 16.2.7. DMA Control of I2C Transactions – see page 326 17.2.10. USB Module Interrupts and DMA – see page 355 20.2.1. AES Operation and DMA – see page 427 21.2.8. ADC Interrupts and DMA – see page 451 22.2.4. DAC Interrupt and DMA – see page 470 18.2.4. Transfer Types Three transfer types provide Register Bus bandwidth-sharing options, and are selected with the BURST bit in the DMA Control Register. If no DMA requests are asserted, the CPU has 100% of the Register Bus bandwidth. 18.2.4.1. Block (BURST = 00) The DMA Controller can be configured to transfer data blocks by selecting BURST = 00. It will transfer the entire transfer length as long as the DMA request is asserted. The CPU will not execute instructions while the DMA Controller is transferring the block. The DMA Controller will pause to allow CPU execution, but only if the DMA requestor does not continue to assert DMA requests during the block transfer. Care should be taken using block transfer if CPU response time is critical. 18.2.4.2. Burst4 (BURST = 01) The DMA Controller can be configured to limit data transfer length to bursts of 4 transfers by selecting BURST = 01. After 4 consecutive DMA transfers, the CPU is allowed to exe- cute an instruction; i.e., one CPU instruction is interleaved with a burst of 4 DMA trans- fers. If the requesting DMA does not require all four transfers and deasserts a DMA request, CPU instruction execution will occur after the last required transfer. 18.2.4.3. Single (BURST = 10) The DMA Controller can be configured to limit data transfer length to a single transfer by selecting BURST = 10. After a DMA transfer, the CPU will execute one instruction; i.e., one CPU instruction is interleaved with each DMA transfer). 18.2.5. Direct Operation 18.2.5.1. DMA Setup with Autoincrement The DMA Subregister selection and status registers have an autoincrement that allows the DMA Controller to be set up without modifying the DMASA subregister address in the DMAxSA Register. To enable autoincrementing, set the AUTOINC bit in the DMA Control Register. DMASA is autoincremented whenever DMAxSD is accessed (i.e., read or written) while DMAx is not active. This autoincrement allows for convenient channel setup, because software can sequentially write to the DMA channel subregisters without

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 394 causing intervening writes to DMAxSA. To take advantage of autoincrementing, software must write the DMAxSD values in order, typically from subregister address 0 (DMAxSRCH) to subregister address 7 (DMAxCTL1). When the autoincremented value of DMASA reaches 7, the next access to DMAxSD will reset DMASA back to 0. Autoincrementing is not required to start from zero; it will always start from the address value in DMASA. To write only the transfer count value and then reenable the DMA, con- figure DMASA to 4h, then write the DMAxSD Register four times to access the DMA count and control subregisters in the same order listed above. If DMASA is written with a value greater than 7, the autoincrement function will toggle DMASA[0] at each DMAxSD access for convenient cycling between subregister addresses 8 and 9 when configuring linked list operation. To return to the lower subregis- ters, write DMASA with a value less than 8h. Clear the AUTOINC bit before executing an instruction to manipulate bits in a DMA sub- register such as AND, BIT, and OR. These instructions perform read-modify-write opera- tions. If AUTOINC is set, these instructions will cause the subregister address to increment twice: first upon the read, and again upon the write. DMA active status can be polled by reading the ACT bit in the DMAxSA Register, or by reading the ENABLE bit in the DMAxCTL1 Subregister. 18.2.5.2. Chain Operation DMA channel pairs may be chained together to form a multi-transfer operation. If the CHAIN01 bit is set in the DMACTL Register, DMA0 is chained to DMA1. The same operation is true if the CHAIN23 bit is set in the DMACTL Register and DMA2 is chained to DMA3. When chain operation is enabled for a DMA channel pair, initially one DMA channel of the pair should be enabled. When the enabled DMA channel reaches an end-of-count, it will reset its ENABLE bit , set its partner’s ENABLE bit, then clear the CHAINxy bit. Software should service the corresponding buffer and, if further chaining is desired, again set CHAINxy. This setting enables the chained channel to perform DMA operation such that the DMA channels work in a ping-pong fashion. 18.2.6. Linked List Operation To implement seamless back-to-back DMA transactions, linked list operation is available. Linked list operation can be selected on a channel-by-channel basis. 18.2.6.1. Operation Linked list operation employs descriptors in the Register File to control DMA. These descriptors are usually set up as lists of descriptors. Each descriptor consists of 8 bytes and must be aligned on an 8-byte address boundary. The 8 bytes of the descriptor correspond directly to the first 8 subregisters of the DMA channel. In this description of linked list

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 395 operation, the descriptor bytes will be identified as a descriptor byte with a corresponding subregister name; e.g., a DMAxCTL0 descriptor byte. After creating one or multiple descriptors in the Register File, software writes the address of the first linked list descriptor to {LAH, LAL} in the Linked List Descriptor Address subregisters (DMAxLAH and DMAxLAL), thereby providing the DMA Controller with the descriptor location in the Register File. The write to DMAxLAL also triggers the DMA Controller to automatically start linked list operation. The DMA Controller then reads into the DMA subregisters the descriptor pointed to by {LAH, LAL}, and assuming the ENABLE bit is set in the DMAxCTL1 descriptor byte, the DMA Controller executes the descriptor. Linked list operation active status can be polled by reading LLACT in the DMAxSA Register. When the DMA Controller reaches an end-of-count, it can write completion status back to the descriptor by clearing the ENABLE bit in the DMAxCTL1 descriptor byte, and it can generate an interrupt, if enabled, signalling that execution of the descriptor has been com- pleted. The DMA Controller then increments the linked list descriptor address, {LAH, LAL}, by 8 to point to the next descriptor; it then transfers the new descriptor to the DMA Subregister. Linked list operation will be disabled upon reaching the end-of-count if the HALT bit is set in the DMAxCTL0 descriptor byte of the current descriptor. Upon reading a descriptor with the ENABLE bit cleared, the DMA Controller will become disabled. In addition, software can stop a linked list DMA operation by directly clearing the ENABLE bit in the DMAxCTL1 Subregister for that channel. In this case, the DMA Controller will complete any transaction in progress, then stop. During linked list operation, the ENABLE bit is set while executing descriptors and cleared while reading descriptors. The DMA Controller will be disabled only if the ENABLE bit is cleared while executing a descriptor. Software can clear the ENABLE bit twice in succession to guarantee that the ENABLE bit is cleared while executing a descriptor. Alternatively, global disable, the GDISABLE bit in the DMACTL Register, can be set to pause DMA activity, then the ENABLE bit can be read. If the ENABLE bit is set, software can clear the ENABLE bit to disable the DMA Controller and clear GDIS- ABLE. Any time a DMA is disabled while in linked list operation, the DMA Controller reverts back to direct operation. A write to the DMAxLAL Subregister is required to again start linked list operation. 18.2.6.2. Descriptor Setup A DMA descriptor consists of eight bytes located in the Register File, and contains the same information that is written to configure direct operation. These descriptor bytes are loaded by the DMA Controller to the first 8 DMA subregisters, DMAxSRCH through Note:

Descriptor Address subregisters, DMAxLAH and DMAxLAR. list or create a looping operation over a set of descriptors. Table 202. DMA Descriptors

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 397 ister File. Because the ENABLE bit in the DMAxCTL1 Subregister is cleared upon reach- ing the end-of-count, the ENABLE bit in the descriptor will also be cleared. The CPU can poll the linked list descriptor {LAH, LAL} + 7 address to determine if the ENABLE bit is cleared, indicating that the transaction has completed. When LLCTL = 10, status writes are disabled such that the DMA Controller will not over- write the linked list descriptor LAH, LAL} + 7 address. Because a status is not written back, the list can be used again. Repeat Descriptor. When LLCTL = 01, repeat descriptor operation is selected, and the DMA Controller loops on the current descriptor until disabled by software. When repeat descriptor operation is selected, the DMA Controller does not write a status back to the descriptor, nor does it increment the linked list descriptor address, {LAH, LAL}. Software can terminate repeat descriptor operation in a number of ways:

• Directly clearing the ENABLE bit in the DMAxCTL1 Subregister will disable the DMA Controller when the current transaction, if any, completes
• Directly setting the HALT bit or changing the LLCTL bit in the DMAxCTL0 Subreg- ister will result in the newly-specified operation commencing at the end-of-count
• Altering the ENABLE, HALT, or LLCTL bits in the descriptor bytes in the Register File. The descriptor changes will take effect when an end-of-count is reached prompt- ing the DMA Controller to again read the descriptor Halt. When the HALT bit is set, the DMA Controller will clear the ENABLE bit upon an end-of-count, thereby disabling the DMA Controller. When an end-of-count is reached with the HALT bit set, the DMA Controller will write a status if LLCTL = 00. The linked list descriptor address, {LAH, LAL}, will not increment, but will point to the descriptor upon completion. 18.2.7. Global Disable It is possible to quickly block DMA activity when the CPU requires 100% of the Register Bus bandwidth; for example, during high-priority interrupt service routines. When the GDISABLE bit in the DMACTL Register is set, DMA activity is blocked regardless of the state of the individual channel the ENABLE bit. Setting the GDISABLE bit does not affect the state of a DMA channel, and DMA activity resumes when the GDISABLE bit is cleared. 18.2.8. DMA Channel Priority Two priority schemes can be selected for servicing DMA requests, namely: fixed priority and round-robin priority. Linked list descriptor fetch has the highest priority. The priority scheme is selected by the PRIORITY bit in the DMACTL Register.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 398 18.2.8.1. Linked List Descriptor Request Priority Because a linked list descriptor fetch has the highest priority, other DMA requests are ignored while a descriptor is being transferred from the Register File to the DMA regis- ters. 18.2.8.2. Round Robin Priority Round-robin priority is the default at System Reset, and is selected by clearing the PRI- ORITY bit. With round-robin priority, each channel request is serviced for the length of its burst size or until it deasserts a DMA request, whichever occurs first. After a channel is serviced, it is assigned lowest priority and is taken out of the rotation until all other requesting channels are serviced. 18.2.8.3. Fixed Priority Fixed priority is selected by setting the PRIORITY bit. With fixed priority, channel requests are serviced with the following priority order from highest to lowest: DMA0, DMA1, DMA2, DMA3. Lower-priority DMA channels are not serviced until higher-pri- ority DMA channels deassert DMA request. 18.2.9. Interrupts Independent interrupt control is provided for end-of-count and watermark interrupts. An indication of whether the most recent interrupt was due to an end-of-count or watermark is provided by the IRQS bit in the DMA 0–3 Subregister Selection and Status registers. 18.2.10.End-of-Count Interrupt An interrupt is generated when the end-of-count is reached. If interrupted on an end-of- count, the EOCIRQE bit is set in the DMAxCTL0 Subregister. The EOCIRQE bit can be cleared if the application is not required to service the buffer, or will service the buffer in conjunction with a future buffer. 18.2.11.Watermark Interrupt The DMA Controller is able to generate an interrupt prior to an end-of-count being reached. If the value of the WMCNT bit in the DMAxCNTH Subregister matches the cur- rent count, {CNTH, CNTL}, in the DMAxCNTH and DMAxCNTL subregisters, a water- mark interrupt will be generated. To disable watermark interrupts, configure WMCNT = 0h. Only a single watermark interrupt will be generated for a given count value.

channels, plus a single global DMA control register. Table 203 lists these DMA registers. and control. DMAxSD provides a portal to the ten subregisters of each DMA channel. Table 203. DMA Registers and Subregisters Note: *DMASA in each DMAxSA Regi ster contains the subregister address.

Status and DMA 0–3 Subdata registers combine to provide access to all DMA controls. Table 204. DMA 0–3 Subaddress/Status Register (DMAxSA) Note: x references bits in the range [3:0]. 0: End-of-count interrupt was the most recent DMA interrupt. 1: Watermark interrupt was the most recent DMA interrupt. This bit is reserved and must be programmed to 0. DMA Controller has stopped servicing the linked list. 0: No Linked List operation is in progress. 1: A Linked List operation is in progress.

The DMA 0–3 Subdata registers, shown in Table 205, set the DMA channel operation. which DMAx subregister is read from or written to by a DMAx Subdata Register access. described in the DMA 0–3 Subaddress/Status Registers section on page 400. linked list operation; it is set while executing descriptors, and cleared while reading descriptors. Table 205. DMA 0–3 Subdata Register (DMAxSD) Note: x references bits in the range [3:0]. operation as selected by DMASA.

Table 206. DMA Global Control Register (DMACTL) 0: DMA requests are enabled for those DMA channels that have ENABLE=1. 1: DMA requests are blocked for all DMA channels. 0: DMA executes channel requests using round robin priority. 1: DMA executes channel requests using fixed priority. This bit is reserved and must be programmed to 0. 0: Autoincrement is disabled. 1: Autoincrement is enabled.

Subregister. In addition, DMAxSRCH contains transfer in list (TXLIST) control. 0: DMA3 and DMA2 are independent of each other. 0: DMA1 and DMA0 are independent of each other. Table 207. DMA Source Address High Subregister (DMAxSRCH) section on page 396 for details. These bits are reserved and must be programmed to 000. 0–F: Upper 4 bits of the DMA source address.

Table 208. DMA Source Address Low Subregister (DMAxSRCL) 00–FF: Lower 8-bits of the DMA source address. Table 209. DMA Destination Address High Subregister (DMAxDSTH) These bits are reserved and must be programmed to 0000. 0–F: Upper 4 bits of the DMA destination address.

Table 210. DMA Destination Address Low Subregister (DMAxDSTL) 00–FF: Lower 8 bits of the DMA destination address.

fer, the count is decremented. DMAxCNTH also contains the watermark selection. Table 211. DMA Count Subregister High (DMAxCNTH) 0000: Watermark interrupt disabled. 0001: Watermark interrupt when 1 byte remains. 0010: Watermark interrupt when 4 bytes remain. 0011: Watermark interrupt when 8 bytes remain. 0100: Watermark interrupt when 12 bytes remain. 0101: Watermark interrupt when 16 bytes remain. 0110: Watermark interrupt when 20 bytes remain. 0111: Watermark interrupt when 24 bytes remain. 1000: Watermark interrupt when 28 bytes remain. 1001: Watermark interrupt when 32 bytes remain. 1010: Watermark interrupt when 36 bytes remain. 1011: Watermark interrupt when 40 bytes remain. 1100: Watermark interrupt when 44 bytes remain. 1101: Watermark interrupt when 48 bytes remain. 1110: Watermark interrupt when 52 bytes remain. 1111: Watermark interrupt when 56 bytes remain. 0–F: Upper 4 bits of the DMA transfer count.

The DMA Control 0 subregisters, shown in Table 213, contains control of the DMA channel. Table 212. DMA Count Subregister Low (DMAxCNTL) 00–FF: Lower 8 bits of the DMA transfer count. Table 213. DMA 0–3 Control 0 Subregisters (DMAxCTL0) LLCTL has an effect only during linked list operation. 00: Normal linked list operation with status write and without repeat descriptor. list descriptor address {LAH, LAL}. 10: No status write. DMA will not o verwrite the DMA descriptor. 0: No interrupt is generated when end-of-count is reached. 1: An interrupt is generated when end-of-count is reached. HALT has an effect only in linked list operation. address {LAH, LAL} upon completion of this descriptor and the next descriptor is loaded. linked list descriptor address {LAH, LAL}.

requestor selection for the DMA channel. Table 214. DMA 0–3 Control 1 Subregisters (DMAxCTL1) This bit is cleared when DMA reaches end-of-count (EOC). These bits are reserved and must be programmed to 00.

PS029413-0921 P R E L I M I N A R Y DMA Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 409 [4:0] REQSEL DMA Requestor Selection 00000: Software. DMA service is requested upon enabling DMA. 00001: Reserved. 00010: SPI0 RX. 00011: SPI0 TX. 00100: SPI1 RX. 00101: SPI1 TX. 00110: USB DMA0. 00111: USB DMA1. 01000: AES RX. 01001: AES TX. 01010: UART0 RX. 01011: UART0 TX. 01100: UART1 RX. 01101: UART1 TX. 01110: I 2C RX. 01111: I2C TX. 10000: ADC. 10001: DAC. 10010: Timer 0. 10011: Timer 1. 10100: Timer 2. 10101: Multi-channel Timer channel A. 10110: Multi-channel Timer channel B. 10111: Multi-channel Timer channel C. 11000: Multi-channel Timer channel D. Others: Reserved. Bit Description (Continued)

LAL automatically starts the Linked List DMAx even if DMAxLAH is not written. Table 215. DMA 0–3 Linked List Descriptor Address High Subregister (DMAxLAH) These bits are reserved and must be programmed to 0000. LAH and LAL together form the 12-bit address that points to the current linked list descriptor. 0–F: The upper 4 bits of the linked list descriptor address. Table 216. DMA 0–3 Linked List Descriptor Address Low Subregister (DMAxLAL) LAH and LAL together form the a 12-bit address that points to the current linked list descriptor. list DMA operation. A write to DMAxLAH is not required to start linked list operation. 00–F8: The lower 8 bits of the linked list descriptor address.

PS029413-0921 P R E L I M I N A R Y Event System Z8 Encore! XP® F6482 Series Product Specification 411 Chapter 19. Event System The F6482 Series devices provide an eight-channel Event System that can route up to eight signals independent of any CPU or DMA activity. Any Event System source can be selected to drive a signal on an Event System channel. These Event System sources are:

• Software
• Timers
• Multi-Channel Timer
• Real Time Clock (RTC)
• Comparators
• GPIO Event System Destinations:
• Timers
• Multi-Channel Timer
• Real Time Clock (RTC)
• ADC
• DAC
• GPIO The Event System is active in all operating modes, including Stop Mode. 19.1. Architecture This chapter discusses the Event System, including Event System sources, channels, and destinations. A diagram of the Event System is shown in Figure 61.

allows critical timing signals to pass directly without incurring interrupt latencies. Event System channel can service one or more destinations. System channel is driven by a single, selectable signal source. Figure 61. Event System Block Diagram

additional configuration of the GPIO port alternate function selection registers is required. ing ESSSD in the ESSSD Register. Table 217 lists the available Event System signal sources. Table 217. Event System Signal Sources

dress Register (ESDSA) and the Event System Destination Subdata Register (ESDSD). by writing/reading the ESDSD bit in the ESDSD Register. Table 218 lists the Event System destinations. Table 218. The GPIO PxAF, PxAFS1, and PxAFS2 subregisters select the Event System Table 218. Event System Destinations

PS029413-0921 P R E L I M I N A R Y Timing Considerations Z8 Encore! XP® F6482 Series Product Specification 415 output, ESOUT[3:0], that is available for a particular port pin. See the General-Purpose Input/Output chapter on page 55 to learn more regarding alternate function selection. 19.4. Timing Considerations The Event System essentially performs a multiplexing function. Signals sourced to Event System channels do not go through a synchronization process within the Event System. As such, the signals on Event System channels must be sufficient in duration for detection by their corresponding destinations. Any source and destination pair that are using the same clock, one of SYSCLK, PCLK, or the WTO, can be connected to each other via the Event System without concern about source signal duration. When the Event System source and destination pair are using dissimilar clocks, the Event System source signal should be at least 1.5 times the duration of the clock period of the Event System destination to assure that the destination will detect the signal from the source. 19.5. Event System Usage Examples To illustrate the usage of the Event System, let’s examine the following two examples. Example 1: Triggering Periodic ADC Conversions Using a Timer. In this example, a timer serves as the signal source to Event System channel 0 and the this channel is selected to trigger ADC conversions.

• Select Timer 0 out as the signal source for Event System channel 0, as follows: – Write 00h to the ESSSA Register to select the ESCH0SRC Subregister. – Write 10h to the ESSSD Register. This accesses the ESCH0SRC Subregister to select Timer 0 out as the Event System channel 0 source.
• Configure the ADC conversion parameters. For instance, the ADC could be configured with a window function such that interrupts are generated only when the window is ex- ceeded.
• If a DMA is desired, configure the DMA Controller to transfer the ADC results to memory.
• Configure the ADC to respond to Event System channel 0, as follows: – Write 04h to the ESDSA Register to select the ESDST04CH Subregister. – Write 08h to the ESDSD Register. This accesses ESDST04CH Subregister to enable Event System connection to the ADC and to select channel 0 as input to the ADC.

PS029413-0921 P R E L I M I N A R Y Event System Usage Examples Z8 Encore! XP® F6482 Series Product Specification 416

• Set Timer 0 to Counter Mode with half the desired ADC conversion periodicity, then enable Timer 0. Each Timer 0 Out rising edge will be detected by the ADC, resulting in a new ADC conversion. Example 2: Observing a Event System Channel on a GPIO. This example builds on the previous example by additionally routing Event System channel 0 to GPIO Port C7.
• Select Timer 0 out as the signal source for channel 0, as follows: – Write 00h to the ESSSA Register to select the ESCH0SRC Subregister. – Write 10h to the ESSSD Register. This accesses ESCH0SRC Subregister to select Timer 0 out as the Event System channel 0 source.
• Configure the ADC conversion parameters. For instance, the ADC could be configured with a window function such that interrupts are generated only when the window is ex- ceeded.
• If DMA is desired, configure the DMA Controller to transfer the ADC results to mem- ory.
• Configure the ADC to respond to Event System channel 0, as follows: – Write 04h to the ESDSA Register to select the ESDST04CH Subregister. – Write 08h to the ESDSD Register. This accesses the ESDST04CH Subregister to enable Event System connection to the ADC and to select channel 0 as input to the ADC.
• Configure Port C7 to respond to Event System channel 0, as follows: – Write 02h to the GPIO PCADDR Register to select the PCAF Subregister. – Write 80h to the GPIO PCCTL Register to enable alternate function for Port C7. – Write 07h to the GPIO PCADDR Register to select the PCAFS1 Subregister. – Write 00h to the GPIO PCCTL Register as partial selection of ESOUT[1] for Port C7. – Write 08h to the GPIO PCADDR Register to select the PCAFS2 Subregister. – Write 80h to the GPIO PCCTL Register to complete selection of ESOUT[1] for Port C7. – Write 31h to the ESDSA Register to select the ESDST31CH Subregister. – Write 08h to the ESDSD Register. This accesses the ESDST31CH Subregister to enable Event System connection to the ESOUT[1] and to select channel 0 as input to ESOUT[1].
• Configure Timer 0 to Counter Mode with half the desired ADC conversion periodicity, then enable Timer 0. Each Timer 0 Out rising edge will be detected by the ADC, result- ing in a new ADC conversion; the Timer 0 Out signal will be available on Port C7.

System registers and subregisters. Table 219. Event System Registers and Subregisters

Source Subdata Register (ESSSD). Table 220. Event System Source Subaddress Register (ESSSA) These bits are reserved and must be programmed to 0000.

which ESCHxSRC subregister is accessed. Table 221. Event System Source Subdata Register (ESSSD) This bit is reserved and must be programmed to 0.

enable the channel and select the source that drives the channel. Table 222. Event System Channel 0–7 Source Subregisters (ESCHxSRC) This bit is reserved and must be programmed to 0. 00h: Channel Disabled (Low). 1Ch: Multi-Channel Timer Output A. 1Dh: Multi-Channel Timer Output B. 1Eh: Multi-Channel Timer Output C. 1Fh: Multi-Channel Timer Output D. 42h: Comparator 0/1 window detection (C01).

through the Event System Destination Subdata Register (ESDSD). Table 223. Event System Destination Subaddress Register (ESDSA) This bit is reserved and must be programmed to 0.

in the ESDSA Register determines which ESDSTxCH Subregister is accessed. 1Ch: Multi-Channel Timer Input A. 1Dh: Multi-Channel Timer Input B. 1Eh: Multi-Channel Timer Input C. 1Fh: Multi-Channel Timer Input D. 20h: Multi-Channel Timer Input. 30h: ESOUT[0]. Event System GPIO Out 0. 31h: ESOUT[1]. Event System GPIO Out 1. 32h: ESOUT[2]. Event System GPIO Out 2. 33h: ESOUT[3]. Event System GPIO Out 3. Table 224. Event System Destination Subdata Register (ESDSD) This bit is reserved and must be programmed to 0.

select the Event System channel to connect to the destination. Table 225. Event System Destination 0–3F Channel Subregisters (ESDSTxCH) This bit is reserved and must be programmed to 0. destination is connected to logic 0. 1: The selected Event System channel is connected to the addressed destination. 000: Channel 0 is connected to the destination if DSTCON = 1. 001: Channel 1 is connected to the destination if DSTCON = 1. 010: Channel 2 is connected to the destination if DSTCON = 1. 011: Channel 3 is connected to the destination if DSTCON = 1. 100: Channel 4 is connected to the destination if DSTCON = 1. 101: Channel 5 is connected to the destination if DSTCON = 1. 110: Channel 6 is connected to the destination if DSTCON = 1. 111: Channel 7 is connected to the destination if DSTCON = 1.

PS029413-0921 P R E L I M I N A R Y Advanced Encryption Standard (AES) Z8 Encore! XP® F6482 Series Product Specification 424 Chapter 20. Advanced Encryption Standard (AES) Accelerator F6482 Series MCUs are equipped with an AES accelerator that implements the Rijndael cipher encoding and decoding algorithm in compliance with the NIST Advanced Encryp- tion Standard. It processes 128-bit data blocks with a 128-bit key. In addition to an Elec- tronic Codebook mode, NIST Cipher Block Chaining and Output Feedback modes are also supported. An automatic start feature facilitates use with the DMA Controller, and applications can be configured to be interrupted upon completion or error. This AES accelerator includes the following features:

• Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
• Based on Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
• Processes 128-bit data blocks with an 8-bit data interface
• Contains a dedicated 128-bit key buffer
• Supports the NIST OFB and CBC confidentiality modes (a software assist is required for decryption)
• DMA support for all modes of operation 20.1. AES Architecture The AES accelerator implements Electronic Codebook (ECB) encryption or decryption on 128-bit data blocks. In addition to ECB encryption and decryption, the AES accelerator also provides a hardware assist feature for Output Feedback (OFB) and Cipher Block Chaining (CBC) modes; a software assist is required for decryption. AES encryption is performed as defined in the FIPS-197 Specification. The Cipher Block Chaining (CBC) and Output Feedback (OFB) modes are described in the SP 800–38A Specification. A block diagram of the AES accelerator is shown in Figure 62.

tion operation in conjunction with clearing START/BUSY in the AESCTL Register. The encryption/decryption operation can be initiated either manually or with auto-start. Figure 63. AES State Array Input and Output Table 226. Register Bit Settings for Auto-Start

0 X 1 1 YES

1 X XXX N O

decryption operation but ERROR in the AESSTAT Register is set. Two DMA requests are provided: RxIRQ for receive data, and TxIRQ for transmit data. configuration, as described in the Direct Memory Access Controller chapter on page 390. Table 227 summarizes DMA request conditions. The following subsections describe AES ECB Mode. Table 227. Register Bit Settings for DMA Support, AUTODIS = 0

00 X X 0 0

0 X1010

Note: *If AUTODIS = 1, START/BUSY must be set by software.

PS029413-0921 P R E L I M I N A R Y AES Operation Z8 Encore! XP® F6482 Series Product Specification 429 20.2.2.2. AES ECB Encryption Example The following example outlines a procedure for performing AES encryption in ECB Mode. 1. Write the AESCTRL Register as follows: AES_EN = 1, MODE = 00 (ECB), DECRYPT = 0, AUTODIS = 1. 2. Write the AESKEY Register with the encryption key. 3. Write plain text to the A ESDATA Register or use DMA. 4. Set START/BUSY in the AESSTAT Register or use auto-start, AUTODIS = 0 in step 5. Poll START/BUSY or use interrupt. 6. Read cipher text from the AESDATA Register or use DMA. 7. Repeat steps 3 through 6 for additional blocks. 20.2.2.3. AES ECB Decryption Example The following example outlines a procedure for performing AES decryption in ECB Mode. 1. Write the AESCTRL Register as follows: AES_EN = 1, MODE = 00 (ECB), DECRYPT = 1, AUTODIS = 1. 2. Write the AESKEY Register with the decryption (R[10]) key. 3. Write cipher text to the A ESDATA Register or use DMA. 4. Set START/BUSY in the AESSTAT Register or use auto-start, AUTODIS = 0 in step 1. 5. Poll START/BUSY bit or use interrupt. 6. Read the plain text from the AESDATA Register or use DMA. 7. Repeat steps 3 through 6 for additional blocks. 20.2.3. Initialization Vector When using CBC Mode or OFB Mode, the Initialization Vector must be loaded before encryption/decryption by setting IVEN = 1 and writing the Initialization Vector to the AESIV Register. The successful 16 byte load of the Initialization Vector is indicated by the IVLD = 1 in the AESSTAT Register. The Initialization Vector load must be completed before using the DMA Controller to perform AESDATA Register accesses. Loading the Initialization Vector is a one-time setup that must be completed before the CBC or OFB mode can be used. However, if the AES becomes disabled (AESEN = 0), KEYLD and IVLD will be cleared, and the AESKEY and AESIV registers must be reloaded to again set KEYLD and IVLD as required for auto-start (AUTODIS = 0).

The following steps are required to support OFB Mode encryption operation.

1. Write the AESCTRL Register as follows: AES_EN = 1, MODE = 01 (OFB),
2. Write the AESKEY Register with the encryption key.
3. Write the Initialization Vect or to the AESIV Register.
4. Clear the IVEN bit; DMA and IR Q will not occur while this bit is set.
5. Write the plain text data to th e AESDATA Register, or use DMA.
6. Set the START/BUSY bit in the A ESSTAT Register, or use auto-start by setting
7. Poll the START/BUSY bit, or use an interrupt.
8. Read the cipher text from the AESDATA Register, or use DMA. The Initialization

operation, as shown in Figure 66. Figure 67. OFB Mode Decryption Flow Diagram

1. Write the AESCTRL Register as follows: AES_EN = 1, MODE = 10 (CBC),
2. Write the AESKEY Register with the encryption key.
3. Write the Initialization Vect or to the AESIV Register.
4. Clear the IVEN bit; DMA reques t or IRQ will not occur while this bit is set.
5. Write the plain text to the AESDATA Register, or use DMA.
6. Set the START/BUSY bit in the A ESSTAT Register, or use auto-start by setting
7. Poll the START/BUSY bit, or use an interrupt.
8. Read the cipher text from the AESDATA Register, or use DMA. The Initialization

AES encryption operation, as shown in Figure 68. 6 through 9 for additional blocks. Figure 69. ECB Mode Decryption Flow Diagram for CBC Cipher Text

PS029413-0921 P R E L I M I N A R Y AES Register Definitions Z8 Encore! XP® F6482 Series Product Specification 434 20.2.6. Decrypt Key Derivation The Round 10 (R[10]) expanded encryption key can be used as the decryption key for decrypting data sent using the encryption key. This decryption key can be derived and made available for retrieval by performing a decrypt key derivation using MODE = 11. For this operation, real or dummy plain text data can be used. When the operation is com- pleted, the derived 16-byte R[10] decryption key can be read from the AESDATA Register and stored for use as a decryption key. The first key byte read is the most significant byte (associated with s(0,0) in Figure 63 – see page 426). Whenever MODE is written to 11, KEYLD is cleared. The decryption key will be derived only if the encryption key was loaded while MODE = 11 which sets KEYLD = 1. After a decrypt key derivation is completed, the decryption key is available to be read. When any other confidentiality mode is selected, the decryption key can no longer be read without again setting MODE = 11, loading the encryption key, and starting/completing the decrypt key derivation. The following example outlines a procedure for deriving and retrieving the decryption key. 1. Write the AESCTRL Register as follows: AES_EN = 1, MODE = 11 (KEYGEN), DECRYPT = 0, AUTODIS = 1. 2. Write the AESKEY Register with the encryption key. 3. Write real or dummy data to the AESDATA Register, or use DMA. 4. Set the START/BUSY bit in the A ESSTAT Register, or use auto-start by setting AUTODIS = 0 in Step 1. 5. Poll the START/BUSY bit, or use an interrupt. 6. Read the R[10] key from the AESDATA Register and store it. 7. Select another MODE. 20.3. AES Register Definitions The AES accelerator is accessed through the registers listed in Table 228. The remainder of this chapter describes each of these registers.

data to the AES accelerator. Table 228. AES Register Summary AES Data Register (AESDATA) FB8h Accessed when IVEN = 0. AES Key Register (AESKEY) FB9h AES Key Register. AES Control Register (AESCTL) FBAh AES Control Register. AES Status Register (AESSTAT) FBBh AES Status Register. Table 229. AES Data Register (AESDATA) while START/BUSY = 1 causes the ERROR bit to be set, and the access is ignored.

The AES Key Register is shown in Table 231. Table 230. AES Initialization Vector Register (AESIV) Table 231. AES Key Register (AESKEY) disabled, and must be loaded after enabling the AES by setting the AESEN bit.

The AES Control Register, shown in Table 232, configures the AES for operation. Table 232. AES Control Register (AESCTL) This bit is reserved and must be programmed to 0. 1: Enables interrupt on DONE (BUSY = 0) and ERROR. 00: Electronic Codebook (ECB) Mode. 01: Output Feedback (OFB) Mode. 10: Cipher Block (CBC) Mode. Vector must be loaded after AES enabled. 1: AES accelerator enabled for operation.

TheAES Status Register is shown in Table 233. Table 233. AES Status Register (AESSTAT) Note: *R/W1 = Writing a 1 clears this bit. : AES is idle or the requested encryption/decryption operation is complete. These bits are reserved and must be programmed to 000. 0: No error occurred during processing. 1: Error occurred during processing. 0: Initialization vector not fully loaded. 1: Initialization vector fully loaded.

PS029413-0921 P R E L I M I N A R Y Analog-to-Digital Converter Z8 Encore! XP® F6482 Series Product Specification 439 Chapter 21. Analog-to-Digital Converter The F6482 Series MCUs include a seventeen-channel Successive Approximation Register Analog-to-Digital Converter (SAR ADC). This ADC converts an analog input signal to a 12-bit or 14-bit binary number, and includes the following additional features:

• 12-bit or 2-pass 14-bit resolution
• Twelve analog input sources multiplexed with general-purpose I/O ports
• Five internal analog input sources including: Op Amp A output, Op Amp B output, temperature sensor, bandgap, and AVDD/2 fixed reference
• Four input modes: two single-ended modes, balanced differential mode, and unbal- anced differential mode
• Conversion initiated by software or Event System input
• Channel scanning function
• Optional conversion averaging of 2, 4, 8, 16 samples
• Continuous conversion function that can be used with or without channel sequencing
• DMA support
• Fast conversion time, as low as 3 µs
• Programmable timing controls including ADC clock prescaler
• Window check function
• Interrupt on conversion complete or outside window
• Internal voltage reference selections of AVDD or buffered VBIAS from the Reference System (2.5 V, 2.0 V, 1.5 V, 1.25 V)
• Buffered VBIAS internal reference voltage can be driven externally on VREF+
• Ability to utilize external reference voltage
• In-situ calibration for all operating modes
• Auto-disable
• Two power settings 21.1. Architecture The ADC can be operated with either single-ended inputs or differential inputs. The archi- tecture, shown in Figure 70, consists of input multiplexers, sample-and-hold, an internal

dow detection, and voltage reference options. The ADC can be serviced by the DMA. Figure 70. Analog-to-Digital Converter Block Diagram

• Single-ended input
• Single-ended input with translation buffering
• Balanced differential inputs
• Unbalanced differential inputs with translation buffering Single-ended input mode is selected by configuring INMODE = 00. In this mode, one of 17 positive inputs can be selected using both ANAINH and ANAINL, and are referenced to VREF–. In this mode, VREF+ can range up to AVDD. Single-ended input mode with translation buffering is selected by configuring INMODE = 11. In this mode, one of 17 positive inputs can be selected using both ANAINH and ANAINL, and are referenced to VREF– . The input signal is translated into a balanced differential signal using a translation buffer. This type of translation provides improved differential nonlinearity (DNL) at the expense of the current consumed by the translation buffer. In this mode, VREF+ can range up to AVDD – 0.5 V . Balanced differential input mode is selected by configuring INMODE = 01. In this mode, one of 6 positive input pairs can be selected using ANAINL, and the inputs are treated as balanced, in that the positive input can be higher or lower than the negative input. In this mode, VREF+ can range up to AVDD. Zilog recommends using balanced differential input mode 2-pass 14-bit conversion. Unbalanced differential input mode with input translation is selected by configuring INMODE = 10. In this mode, one of 6 positive input pairs can be selected using ANAINL, and the inputs are treated as unbalanced, in that the positive input must be higher than the negative input. The input signal is translated into a balanced differential signal using a translation buffer. This type of translation provides improved DNL at the expense of the current consumed by the translation buffer. In this mode, VREF+ can range up to AVDD – 0.5V . The characteristics of these four input modes are summarized in Table 234.

Table 234. Input Mode Summary

00 Single-Ended No No AV DD

01 Balanced Differential No Yes AV DD

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 442 21.2.2. ADC Data Format The ADC supports two data formats, unsigned and signed, selected by DFORMAT in the ADC Control 1 Register. When using signed data format, negative values are sign extended. Figures 71 through 73 show the relationship between data formats at 12-bit res- olution, and ADC output data for the selectable input modes. The equation for calculating the ADC output data value is a function of input mode, resolution, and data format. The following equations can be used to calculate an ADC output data value for common com- binations of input mode, resolution, and data format. Single-ended input modes (INMODE = 00, 11), unsigned (DFORMAT = 0 ) : ADC Output = FSR x ((ANAx – VREF–) ÷ (VREF+ – VREF– )) In the equation above, FSR (full-scale range) is 4095 for 12-bit conversions, and 16383 for 2-pass 14-bit conversions. Balanced differential input mode (INMODE = 01), signed (DFORMAT = 1 ) : ADC Output = FSR x ((ANAx – ANAx+1) ÷ (VREF+ – VREF– )) In the equation above, 12-bit conversion FSR (full scale range) is –2048 for negative inputs and +2047 for positive inputs; 2-pass 14-bit conversion FSR is –8192 for negative inputs and +8191 for positive inputs. Unbalanced differential input mode (INMODE = 10), unsigned (DFOR M AT = 0 ) : ADC Output = FSR x ((ANAx – ANAx+1) ÷ (VREF+ – VREF– )) In the equation above, FSR (full-scale range) is 4095 for 12-bit conversions and 16383 for 2-pass 14-bit conversions. Data is always right-justified with 14-bit width even when 12-bit resolution is selected. Conversion resolution can be configured to be 12-bit or 2-pass 14-bit, as defined by the RESOLUT bit in the ADC Control 1 Register. Note that bit 0 of the ACDCTL1 Register must be set for proper ADC operation.

mode. Each of these five options is described in the following subsections. can be moved by software or DMA. Figure 73. ADC Data (12-Bit) vs. Input Voltage for Unbalanced Differential Input Mode

0 VREF

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 445 formed only on the channels selected in ANAINL and ANAINH. Channels that are not selected are skipped. The ADC configuration is identical for each channel scanned as defined in the ADC con- trol registers. Timing parameters, ST and SST, should be configured for the requirements of the worst-case channel. If single-shot conversion is selected (CONTCONV = 0), the ADC performs the scan sequence once. If continuous conversion is enabled, the ADC repeats the scan sequence in a continuous fashion. An interrupt can be generated for each channel conversion result. The data for each chan- nel result can be moved by software or DMA. ADC scanning continues while the F6482 Series device is in Debug Mode, during which the CPU fetch unit stops. This activity can result in a loss of synchronization between user code and ADC scanned data. 21.2.3.3. Conversion Averaging The ADC is capable of processing data from multiple individual conversions to form an averaged result. When averaging is enabled by setting the A VE bit, A VESAMP deter- mines whether 2, 4, 8, or 16 samples are averaged to produce a result. An interrupt will be generated only when a final sample is obtained and processed into the average. If channel scanning is enabled, the averaged result is obtained sequentially for each channel being scanned. 21.2.3.4. Power Control The ADC is capable of performing conversions at two different power settings, as selected by the POWER bit. When POWER = 00, the ADC runs at higher current consumption, and can be clocked at up to 5 MHz. When POWER = 10, the ADC runs at lower current con- sumption and can be clocked at up to 1 MHz. The lower power consumption setting can reduce overall current consumption for longer sampling times because the current con- sumption during sampling is reduced. 21.2.3.5. Resolution When the RESOLUT bit is cleared, 12-bit conversions are performed. For applications that require even higher resolution, 2-pass 14-bit resolution conversions are performed when RESOLUT is set. These conversions involve somewhat longer timings than those described in the 2-Pass 14-Bit Resolution Timing section on page 448. When performing 2-pass 14-bit conversion, Zilog recommends using the following input mode selection: I N M O D E = 0 1 . 21.2.4. Starting and Stopping Conversions ADC activity is initiated by writing the START bits in the ADC Control 0 Register to per- form a conversion (START = 01), offset calibration (START = 10), or gain calibration Note:

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 446 (START = 11). When SCAN = 1, starting a conversion by writing START = 01 initiates channel scanning. Additionally, the Event System can trigger a new conversion and cause START to be set to 01. When a calibration is initiated, SCAN and CONTCONV are ignored. When a conversion or calibration completes, START is cleared to 00 automatically by hardware. To avoid disrupting a conversion already in progress, START can be read to indicate ADC operation status (busy or available). If the result from a previous ADC oper- ation is not read before the result from a subsequent ADC operation is complete, the previ- ous result is overwritten. The recommended procedure to stop continuous conversions is to first clear SCAN, if set, and then to clear CONTCONV together with A VE, if set. The currently-active conversion will continue to completion, at which time START is cleared to 00. 21.2.5. Voltage References The ADC positive voltage reference is selected with REFSEL. The ADC negative refer- ence should always be configured as VREF– using the GPIO Alternate Function Selection described in the General-Purpose Input/Output chapter on page 55. ADC positive voltage reference selection options are:

• AVDD (REFSEL = 00)
• External voltage reference on VREF+ (REFSEL = 01)
• Internal voltage reference buffer which buffers VBIAS from the Reference System (REFSEL = 10) via an internal connection
• Internal voltage reference buffer connected to VREF+ which buffers VBIAS from the Reference System (REFSEL = 11) VBIAS in the Reference System offers four possible level settings that are selected with AVDD is always at least 0.5 V greater than the selected VBIAS level. Wake-up of the inter- nal voltage reference buffer can be performed automatically or manually. Automatic Wake-Up. If the ADC bits are cleared to 00 in the PWRCTL1 Register, then when ADC activity is triggered, the ADC and ADC internal voltage reference buffer will wake up for the duration of the ADC wake-up period, TWAKE_ADC, prior to the ADC con- version being performed (see the Electrical Characteristics chapter on page 601). When the conversion is completed, the ADC auto-disable feature will automatically disable the ADC and the ADC internal voltage reference buffer when no further conversions are scheduled. If performing multiple sequential conversions due to averaging, scanning or continuous conversion, the wake-up time is incurred only prior to the first conversion. Manual Wake-Up. When the ADC bits are set to 11 in the PWRCTL1 Register, the ADC is continuously enabled and the ADC internal voltage reference buffer is continuously

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 447 enabled if it is selected as the ADC positive voltage reference. The ADC bits are typically set when the ADC internal voltage reference buffer is connected to the VREF+ pin (REFSEL = 11 in the ADCCTL2 Register). When using the internal voltage reference buffer connected to VREF+ (REFSEL = 11), an external bypass capacitor is required, as defined in the Electrical Characteristics chapter on page 601. If the DAC is also configured to drive VREF+, the DAC voltage reference buffer selection is used. 21.2.6. ADC Timing System Clock can be prescaled to form the ADC clock with the divisor defined by the PRESCALE bit. ADC timing is a function of resolution, as described in the following sec- tions. When the ADC exits the idle state to perform a conversion, a wake-up time, TWAKE_ADC, may be incurred, as defined in ADC Wake-up, Sampling, and Settling on page 449 and the Electrical Characteristics chapter on page 601. 21.2.6.1. 12-Bit Resolution Timing Each 12-bit resolution (RESOLUT = 0) ADC measurement consists of 3 phases: 1. Input sampling time, as defined by the ST bit, is a function of source impedance and the desired accuracy, as discussed later in this section. The minimum input sampling period is 200 ns, with the input translation buffer disabled (INMODE = 00, 01), and 800 ns with the input translation buffer enabled (INMODE = 10, 11). 2. Sample-and-hold amplifier set tling time, as defined by the SST bit, is a minimum of 200 ns, with the input translation buffer disabled (INMODE = 00, 01), and 800 ns with the input translation buffer enabled (INMODE = 10, 11). 3. Sample conversion time is 13 AD C clock cycles with a maximum frequency of 5.0 MHz. Figure 74 shows the timing of a 12-bit ADC conversion. Note:

2 KΩ (max) resistance and a shunt 5 pF (max) between the signal source and the ADC

the minimum sampling time specified. In this equation, ST > 0.74µs. registers to be the minimum conversion value (all 0s). tents will not result in a comparison against residual ADC output data. Figure 77. ADC Input Equivalent Circuit

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 451 21.2.8. ADC Interrupts and DMA The ADC can generate an interrupt request upon each new ADC result for any completed conversion or calibration (START= 01, 10, 11). The ADC can also generate an interrupt if the conversion result is outside the range defined by the window threshold registers (ADCUWINH, ADCUWINL, ADCLINH, ADCLWINL). Use the IRQ bit in the ADC Control 0 Register to select whether interrupts are generated due to only exceeding the window thresholds or due to both exceeding the window thresholds and end of convert. An interrupt request that is pending when the ADC is disabled or idle (ready) is not auto- matically cleared. The ADC will assert a DMA request upon each new ADC result, and will deassert a DMA request whenever the ADCD_L Register (DMACTL = 0) or ADCD_H Register (DMACTL = 1) is read by the DMA or software. When DMACTL = 0, the typical goal is to transfer both data bytes, and the DMA is configured to have fixed word address control for the DMA source address; the source address is configured to be the ADCD_H Register address. When DMACTL = 1, the typical goal is to transfer only the most significant data byte, and the DMA is configured to have fixed address control for the DMA source address; the source address is configured to be the ADCD_H Register address. If starting a new ADC conversion and DMA transfer sequence, reading the ADC_L Regis- ter (DMACTL = 0) or the ADC_H Register (DMACTL = 1) prior to enabling DMA and starting conversion ensures that any residual ADC DMA request from prior ADC activity is deasserted. A DMA request is not asserted upon the completion of an offset or gain cal- ibration. 21.2.9. Calibration and Compensation Both gain and offset calibration can be performed in situ to achieve even higher accuracy than specified in the Electrical Characteristics chapter on page 601. These calibration operations are performed using the current ADC configuration, as defined by the INMODE, PRESCALE, ST, and SST bits. After these parameters are reconfigured, initiat- ing calibration prior to performing conversions can optimize results. Only initiate calibra- tion when continuous conversion is not selected (i.e., CONTCONV = 0). Offset calibration is performed when the START bits are written to 10. Prior to initiating offset calibration, 14-bit resolution must be selected by setting RESOLUT = 1. The offset result can be used for both 12-bit and 14-bit resolution conversions. The calibration is complete when START is cleared to 00. The value in the OFFSET field is automatically applied to compensate subsequent conver- sions by hardware. Offset correction by hardware is effective for signed mode (DFORMAT = 1) only. For unsigned mode (DFORMAT = 0), software should store the value of OFFSET, clear OFFSET to 00h, and perform any desired offset compensation. As each ADC configuration can exhibit a unique offset calibration, the offset calibration value for each ADC configuration of interest can be stored. Stored offset values can be used to compensate both 12-bit and 14-bit resolution conversions as shown in Table 235.

ADC status information and contains conversion control options. Table 235. Compensating ADC results for ADC offset Table 236. ADC Control 0 Register (ADCCTL0)

PS029413-0921 P R E L I M I N A R Y ADC Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 453 Bit Description [7:6] START ADC Start/Busy 00: Reading 00 indicates the ADC is available to begin a conversion or calibration. 01: Writing 01 starts a conversio n. Reading 01 indicates that a conversion is currently in progress. 10: Writing 10 starts an offset calibration. Reading 10 indicate s that an offset calibration is currently in progress. Set RESOLUT = 1 prior to initiating an offset calibration. 11: Writing 11 starts a gain calib ration. Reading 11 indicates that a gain calibration is currently in progress. [5] DMACTL DMA Request Control 0: Reading the ADCD_L Register clears a DMA request. This setting is typically used when a DMA accesses both ADC data bytes with DMA fixed word addressing. 1: Reading the ADCD_H Register clears a DMA request. This setting is typically used when a DMA accesses only the most significant ADC data byte with DMA fixed addressing. [4] IRQ Interrupt Control 0: Outside window. 1: Both end of convert and outside window. [3] CONTCONV Continuous Conversion Enable 0: Single-shot conversion. 1: Continuous conversion. [2] AVE Averaging Enable 0: Averaging of ADC samples is disabled. 1: Averaging of ADC samples is enabled. The number of samples to convert to form each ADC result are determined by AVESAMP. [1:0] AVESAMP Averaging Samples If AVE = 1, ADC samples are averaged to form an ADC result. 00: 2 samples are converted to form each ADC result. 01: 4 samples are converted to form each ADC result. 10: 8 samples are converted to form each ADC result. 11: 16 samples are converted to form each ADC result.

reference selection and power consumption. Table 237. ADC Control 1 Register (ADCCTL1) 00: Higher maximum conversion speed, higher power consumption. 10: Lower maximum conversion speed, lower power consumption. The channels to be scanned are determined by ANAINH and ANAINL. 0: Channel scanning is disabled. 1: Channel scanning is enabled. 10: Unbalanced differential with translation buffer. 11: Single-ended with translation buffer. 0: Data is unsigned (binary). 1: Data is signed (two’s complement). Negative values are sign-extended. 1: 2-pass 14-bit resolution. This bit is reserved and must be programmed to 1 which changes the reset value.

scanned are defined both in ADCINSH and ADCINSL. Table 238. ADC Control 2 Register (ADCCTL2) 01: VREF+ pin driven by an external source. 10: Buffered VBIAS from the Reference System using an internal connection. 11: Buffered VBIAS from the Reference System drives the VREF+ pin. 0000: ADC Clock is System Clock divided by 1. 0001: ADC Clock is System Clock divided by 2. 0010: ADC Clock is System Clock divided by 3. 0011: ADC Clock is System Clock divided by 4. 0100: ADC Clock is System Clock divided by 5. 0101: ADC Clock is System Clock divided by 6. 0110: ADC Clock is System Clock divided by 7. 0111: ADC Clock is System Clock divided by 8. 1000: ADC Clock is System Clock divided by 9. 1001: ADC Clock is System Clock divided by 10. 1010: ADC Clock is System Clock divided by 11. 1011: ADC Clock is System Clock divided by 12. 1100: ADC Clock is System Clock divided by 13. 1101: ADC Clock is System Clock divided by 14. 1110: ADC Clock is System Clock divided by 15. 1111: ADC Clock is System Clock divided by 16.

inputs to be scanned, otherwise, only ADCINSL is used to select the ADC input(s). Table 239. ADC Input Select High Register (ADCINSH) This bit is reserved and must be programmed to 0. ADC Input Selection is a function of SCAN and INMODE. xxxxxx1: ANA8 input is selected for ADC scanning. Additional inputs may be selected. xxxxx1x: ANA9 input is selected for ADC scanning. Additional inputs may be selected. xxxx1xx: ANA10 input is selected for ADC scanning. Additional inputs may be selected. xxx1xxx: ANA11 input is selected for ADC scanning. Additional inputs may be selected. Table 240. ADC Input Select Low Register (ADCINSL)

PS029413-0921 P R E L I M I N A R Y ADC Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 457 Bit Description [7:0] ANAINL Analog Input Selection Low ADC Input Selection is a function of SCAN and INMODE. SCAN=0, INMODE=00, 11 00000000: ANA0 input is selected fo r analog-to-digital conversion. 00000001: ANA1 input is selected fo r analog-to-digital conversion. 00000010: ANA2 input is selected fo r analog-to-digital conversion. 00000011: ANA3 input is selected fo r analog-to-digital conversion. 00000100: ANA4 input is selected fo r analog-to-digital conversion. 00000101: ANA5 input is selected fo r analog-to-digital conversion. 00000110: ANA6 input is selected fo r analog-to-digital conversion. 00000111: ANA7 input is selected fo r analog-to-digital conversion. 00001000: ANA8 input is selected fo r analog-to-digital conversion. 00001001: ANA9 input is selected fo r analog-to-digital conversion.

PS029413-0921 P R E L I M I N A R Y ADC Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 458 [7:0] ANAINL (cont’d.) 00001010: ANA10 input is selected for analog-to-digital conversion. 00001011: ANA11 input is selected for analog-to-digital conversion. 00001100: Op Amp A output is select ed for analog-to-digital conversion. 00001101: Op Amp B output is select ed for analog-to-digital conversion. 00001110: Temperature Sensor is selected for analog-to-digital c onversion. 00001111: AVDD/2 Fixed Reference is selected for analog-to-digital conversion. 00010000: Bandgap reference is sel ected for analog-to-digital conversion. All other bits are reserved. SCAN=0, INMODE=01, 10 0000000x: ANA0 input is selected as the positive input for analog-to-digital conversion. ANA1 input is selected as the negative input for analog-to-digital conversion. 0000001x: ANA2 input is selected as the positive input for analog-to-digital conversion. ANA3 input is selected as the negative input for analog-to-digital conversion. 0000010x: ANA4 input is selected as the positive input for analog-to-digital conversion. ANA5 input is selected as the negative input for analog-to-digital conversion. 0000011x: ANA6 input is selected as the positive input for analog-to-digital conversion. ANA7 input is selected as the negative input for analog-to-digital conversion. 0000100x: ANA8 input is selected as the positive input for analog-to-digital conversion. ANA9 input is selected as the negative input for analog-to-digital conversion. 0000101x: ANA10 input is selected as the positive input for analog-to-digital conversion. ANA11 input is selected as the negative input for analog-to-digital conversion. All other bits are reserved. SCAN=1, INMODE=00, 11 xxxxxxx1: ANA0 input is selected for ADC scanning. Additional inputs may be selected. xxxxxx1x: ANA1 input is selected f or ADC scanning. Additional inputs may be selected. xxxxx1xx: ANA2 input is selected f or ADC scanning. Additional inputs may be selected. xxxx1xxx: ANA3 input is selected f or ADC scanning. Additional inputs may be selected. xxx1xxxx: ANA4 input is selected f or ADC scanning. Additional inputs may be selected. xx1xxxxx: ANA5 input is selected f or ADC scanning. Additional inputs may be selected. x1xxxxxx: ANA6 input is selected f or ADC scanning. Additional inputs may be selected. 1xxxxxxx: ANA7 input is selected f or ADC scanning. Additional inputs may be selected. SCAN=1, INMODE=01, 10 00xxxxx1: ANA0 and ANA1 are selec ted as a differential input pair for ADC scanning. ANA0 input is selected as the positive input for analog-to-digital conversion. ANA1 input is selected as the negative input for analog-to-digital conversion. 00xxxx1x: ANA2 and ANA3 are selec ted as a differential input pair for ADC scanning. ANA2 input is selected as the positive input for analog-to-digital conversion. ANA3 input is selected as the negative input for analog-to-digital conversion. 00xxx1xx: ANA4 and ANA5 are sele cted as a differential input pair for ADC scanning. ANA4 input is selected as the positive input for analog-to-digital conversion. ANA5 input is selected as the negative input for analog-to-digital conversion. 00xx1xxx: ANA6 and ANA7 are sele cted as a differential input pair for ADC scanning. ANA6 input is selected as the positive input for analog-to-digital conversion. ANA7 input is selected as the negative input for analog-to-digital conversion. Bit Description (Continued)

00x1xxxx: ANA8 and ANA9 are sele cted as a differential input pair for ADC scanning. ANA8 input is selected as the positive input for analog-to-digital conversion. ANA9 input is selected as the negative input for analog-to-digital conversion. 001xxxxx: ANA10 and ANA11 are sele cted as a differential input pair for ADC scanning. ANA10 input is selected as the positive input for analog-to-digital conversion. ANA11 input is selected as the negative input for analog-to-digital conversion. All other bits are reserved. Table 241. ADC Offset Calibration Register (ADCOFF) offset errors. The ADC places the result from offset calibration (START=10) in OFFSET. and perform any desired offset compensation. [7:2] 00–3F: 2’s complement offset value. [7:0] 00–FF: 2’s complement offset value.

The ADC Data High Register, shown in Table 242, contains the MSBs of the ADC result. latches data in the ADC Low Register. The ADC Data Low Register, shown in Table 243, contains the LSBs of the ADC result. latches data in the ADC Low Register. Table 242. ADC Data High Register (ADCD_H) [7:6] Reserved: these bits must be programmed to 00. until the next ADC conversion has completed. Table 243. ADC Data Low Register (ADCD_L) ADC Data Low is a function of RESOLUT. the ADC Data High Byte register is read.

racy requirements as described in the ADC Timing section on page 447. the ADC Data High Byte register is read. Table 244. Sample Time (ADCST)

with ADCUWINL to define the ADC window upper threshold. SST is dependent upon the value of INMODE. Table 245. ADC Window Upper Threshold High Register (ADCUWINH)

with ADCUWINH to define the ADC window upper threshold. [7:4] Reserved: these bits must be programmed to 0000. [7:6] Reserved: these bits must be programmed to 00. Table 246. ADC Window Upper Threshold Low Register (ADCUWINL) the value of UWINH and UWINL. [7:0] 00–FF: The 8 LSBs of the last conversion result are compared against this data register.

with ADCLWINL to set the ADC window lower threshold. Table 247. ADC Window Lower Threshold High Register (ADCLWINH) [7:4] Reserved: these bits must be programmed to 0000. [7:6] Reserved: these bits must be programmed to 00.

with ADCLWINH to set the ADC window lower threshold. Table 248. ADC Window Lower Threshold Low Register (ADCLWINL) [7:0] 00–FF: The 8 LSBs of the last conversion result are compared against this data register.

PS029413-0921 P R E L I M I N A R Y Digital-to-Analog Converter Z8 Encore! XP® F6482 Series Product Specification 466 Chapter 22. Digital-to-Analog Converter The F6482 Series MCUs include a high-performance Digital-to-Analog Converter (DAC). This DAC converts a 12-bit digital input code to an analog output signal. The DAC offers the following features:

• 12-bit resolution
• Output driven externally on GPIO; internal connections to comparators and ADC
• Conversion initiated by software or Event System input
• Data buffering option
• Data can be left- or right-justified with either unsigned (binary) or signed (two’s-com- plement) format
• DMA support
• Internal positive voltage reference selections of AVDD or the DAC VREF from the Ref- erence System (2.5 V, 2.0 V, 1.5 V, 1.25 V) which is driven on VREF+ for decoupling
• Ability to utilize external reference voltage
• Three power settings providing programmable power vs. settling time; see the Electri- cal Characteristics chapter on page 601 to learn more 22.1. Architecture The DAC architecture, shown in Figure 78, consists of a data register, an internal voltage reference buffer, and a 12-bit DAC.

In this equation, data represents the value of {DACDH, DACDL}. Figure 78. Digital-to-Analog Converter Block Diagram

(VREF+ – VREF–) ÷ 2, and FSR is –2048 for negative inputs and +2047 for positive inputs. is also selectable as an input to the comparators and the ADC.

• Software or DMA write to the DACD_H Register (DACTRIG = 0).
• Event System (DACTRIG = 1). If new data exists in the data registers, data conversion is triggered by the assertion of the Event System input.

Figure 79. Output Voltage vs. DAC Data

0 FFFh

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 469 When the DAC is enabled, data existing in the data registers is converted. The data regis- ters can be written while the DAC is disabled to provide the initial data word to be con- verted when the DAC is enabled. Data can be right-justified or left-justified, as selected by the JUSTIFY bit in the DAC- CTL Register. If data is left-justified, 8-bit resolution can be achieved by writing only the Data High Register, DACD_H. 22.2.2. Power Control The DAC is capable of performing conversions at three different power settings, as selected by the POWER bit. When POWER = 00, the DAC runs at its highest current con- sumption and with the fastest settling time. When POWER = 10, the DAC runs at its low- est current consumption and with the slowest settling time. The lower power consumption setting can reduce overall current consumption for applications with slower switching requirements. 22.2.3. Voltage References DAC positive voltage reference selection options are selected by REFSEL to be one of the following:

• AVDD (REFSEL = 000)
• Internal voltage reference buffer connected to VREF+ (REFSEL = 1xx) which buffers the DAC internal voltage reference from the Reference System
• External voltage reference on VREF+ (REFSEL = 011) The DAC negative reference should always be configured as VREF– using the GPIO Alternate Function Selection, which is described in the General-Purpose Input/Output chapter on page 55. Unless using AVDD (REFSEL = 000), the DAC positive voltage refer- ence should be configured as VREF+ using the GPIO Alternate Function selection. When using the internal voltage reference buffer connected to VREF+ (REFSEL = 1xx), an exter- nal bypass capacitor is required. Typically, an external bypass capacitor is also employed for an external voltage reference on VREF+ (REFSEL = 011). The Reference System offers four possible internal voltage reference level settings that are cised to ensure that AVDD is always at least 0.5 V greater than the selected internal voltage reference level. When the internal voltage reference buffer is selected, it is automatically enabled if both the DAC is enabled and the DAC output is selected using the GPIO alter- nate function registers. The ADC voltage reference buffer can also be configured to connect to VREF+. If both the ADC voltage reference buffer and the DAC voltage reference buffer are selected to con- nect to VREF+, hardware will connect only the DAC voltage reference buffer to VREF+.

interrupt request that is pending when the DAC is disabled is not automatically cleared. The DAC Control Register, shown in Table 248, contains control for the DAC. Table 248. DAC Control Register (DACCTL) 00: Higher conversion speed, higher power consumption. 01: Moderate conversion speed, moderate power consumption. 10: Lower conversion speed, lower power consumption.

PS029413-0921 P R E L I M I N A R Y DAC Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 471 [5:3] REFSEL DAC Positive Voltage Reference Select If REFSEL = 1xx and the ADC is also configured to drive VREF+, the DAC voltage reference buffer selection is used. 000: Internal connection to AV DD. 001: Reserved. 010: Reserved. 011: V REF+ pin driven by an external source. 100: 1.25V internal voltage reference from the Reference System is buffered and drives the VREF+ pin. 101: 1.5V internal voltage reference from the Reference System is buffered and drives the VREF+ pin. 110: 2.0V internal voltage reference from the Reference System is buffered and drives the VREF+ pin. 111: 2.5V internal voltage reference from the Reference System is buffered and drives the VREF+ pin. [2] DFORMAT Data Format 0: Data is unsigned (binary). 1: Data is signed (two’s complement). [1] DACTRIG DAC Triggering 0: DAC conversion is triggered by a software or DMA write to the DACD_H register. 1: DAC conversion is triggered by an Event System input. While converting the data, interrupt request and DMA request will be asserted allowing transfer of the next data word to be converted. [0] JUSTIFY Data Register Justification 0: Data is left-justified. 1: Data is right-justified. Bit Description (Continued)

Data High Register initiates a conversion if the DAC is enabled. input. The justification of the bits in this register is defined by JUSTIFY . Table 249. DAC Data High Register (DACD_H) The justification of data in this register is a function of JUSTIFY. [7:0] 00–FF: The 8 MSBs of the data to be converted are written to this data register. [7:4] 0–F: Reserved , and must be programmed to 0000. [3:0] 0–F: The 4 MSBs of the data to be converted are written to the 4 LSBs of this data register. Table 250. DAC Data Low Register (DACD_L) The justification of data in this register is a function of JUSTIFY. [7:4] 0–F: The 4 LSBs of the data to be converted are written to the 4 MSBs of this data register.

PS029413-0921 P R E L I M I N A R Y DAC Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 473 [3:0] 0–F: Reserved , and must be programmed to 0000. JUSTIFY = 1 (Right-Justified) [7:0] 00–FF: The 8 LSBs of the data to be converted are written to this data register. Bit Description (Continued)

PS029413-0921 P R E L I M I N A R Y Operational Amplifiers Z8 Encore! XP® F6482 Series Product Specification 474 Chapter 23. Operational Amplifiers Two low-power operational amplifiers (op amps) are available with Zilog’s F6482 Series MCUs: Op Amp A and Op Amp B. These amplifiers are identical to each other, but each has different selectable features. Op Amp A can be configured internally with various voltage gain settings, whereas Op Amp B can be configured internally as a current source/ sink. Both op amps can be internally configured to provide unity gain feedback. Each op amp input and output is accessible from the package pins. Features include:

• Two general-purpose op amps (Op Amp A and Op Amp B), individually enabled and configured
• Rail-to-rail inputs and outputs
• Two power vs. bandwidth settings featuring low active currents of 1 µA and 30 µA
• Flexible multiplexed op amp inputs and outputs
• Outputs can drive selectable internal destinations such as the ADC, comparators and op amp inputs without consuming a GPIO
• Internal input and output connections available to conserve pins
• Can be internally configured as a unity gain buffer
• Op Amp A can be configured as a programmable gain amplifier using an internal pro- grammable resistive feedback network that provides 16 gain steps
• Op Amp B can be configured internally as a regulated current source or sink – Internal current levels typically configured as 10 µA, 100 µA, or 1 mA – High-accuracy current sourcing/sinking with external resistor 23.1. Architecture Op Amp A and Op Amp B have identical amplifiers but have different selectable features. Figure 80 shows a simplified block diagram of Op Amp A, including input connections and feedback paths for unity gain and programmable gain.

to disable it results in higher Stop Mode current than necessary. digital conversion with the integrated ADC or comparators. Figure 81. Op Amp B Block Diagram

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 477 All inputs and outputs can be selected to connect to assigned GPIO pins to support user external feedback and coupling networks to meet analog front-end acquisition require- ments. To connect GPIOs to an op amp, configure the appropriate alternate function, as described in the General-Purpose Input/Output chapter on page 55, and configure the OUTCTL bit. In addition, to reduce the demand for external pins or components, op amps can be configured for the following internal connections:

• Unity gain buffer
• Programmable gain amplifier using an internal programmable gain network (Op Amp
• Current sink or source using an internal current drive network (Op Amp B)
• Inputs from the reference system, including the internal programmable references and the 1.0 V internal fixed reference (Op Amp B)
• Outputs to op amp inputs, Comparator 0, Comparator 1, and the ADC The internal connections can also improve performance by eliminating external board and connectivity from loading while going off- and on-chip. Op amp positive inputs are selected with the INPSEL bit, and op amp negative inputs are selected with the INNSEL bit. The op amp outputs, AMPAOUT and AMPBOUT, share package pin connections with ADC inputs. When making an ADC measurement that does not involve an op amp on such a shared pin, either disable the op amp or disconnect it from the GPIO with the appropriate OUTCTL setting. The unique features that mate to each op amp are described in the Op Amp A section that follows, and in the Op Amp B section on page 478. 23.2.1. Op Amp A Op Amp A can be configured internally for unity gain or as a noninverting programmable gain amplifier with 16 available gain selections, 1.5x to 64x, that are selected by writing to the GAIN bit. As shown in Figure 80 on page 475, three positive and three negative inputs are available. The positive Op Amp A inputs are selected with the INPSEL bit in the AMPACTL0 Register, and include:
• A GPIO pin used as the Op Amp A positive input, AMPAINP
• Op Amp B output. This selection provides an internal connection that does not involve the GPIO used as the Op Amp B output, AMPBOUT
• Internal Programmable Reference 0, with level selected by the PREFLVL bit, and source selected by the PREFSRC bit in the CMP0CTL1 Register; see Table 259 on page 496 to learn more

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 478 The negative Op Amp A inputs are selected with the INNSEL bit in the AMPACTL1 Reg- ister, and include:

• GPIO pin used as Op Amp A negative input, AMPAINN
• Op Amp A output through internal feedback network using an internal connection with gain, defined by the GAIN bit
• Op Amp A output, a unity gain configuration using an internal connection The Op Amp A output, AMPAOUT, can be selected as an internal input to OPAMP B, Comparator 0, Comparator 1, and the ADC. Additionally, it can be connected to the GPIO used as AMPAOUT by setting the OUTCTL bit in the AMPACTL0 Register, and config- uring the appropriate alternate function, as described in the General-Purpose Input/Output chapter on page 55. This GPIO can also be selected as an input to the ADC. 23.2.2. Op Amp B As shown in Figure 81 on page 476, four positive and three negative inputs are available. The positive Op Amp B inputs are selected with the INPSEL bit in the AMPBCTL0 Reg- ister, and include:
• 1.0 V from the Reference System; see the Comparators and Reference System chapter on page 486 to learn more
• A GPIO pin used as the Op Amp B positive input, AMPBINP
• Op Amp A output. This selection provides an internal connection that does not involve the GPIO used as the Op Amp A output, AMPAOUT
• Internal Programmable Reference 1, with level selected by the PREFLVL bit and source selected by the PREFSRC bit in the CMP1CTL1 Register; see Table 261 on page 498 to learn more The negative Op Amp B inputs are selected with the INNSEL and MODE bits in the AMPBCTL1 Register, and include:
• A GPIO pin used as the Op Amp B negative input, AMPBINN
• An internal connection from the current drive network
• Op Amp B output, a unity gain configuration using an internal connection The Op Amp B output, AMPBOUT, can be selected as an internal input to Op Amp A and the ADC. Additionally, it can be connected to the GPIO used as AMPBOUT by selecting OUTCTL = 11 in the AMPBCTL0 Register and configuring the appropriate alternate func- tion, as described in the General-Purpose Input/Output chapter on page 55. This GPIO can also be selected as an input to Comparator 0, Comparator 1, and the ADC.

Table 251. Op Amp Register Summary

Table 252. Op Amp A Control 0 Register (AMPACTL0) Output chapter on page 55. This GPIO can also be selected as an input to the ADC. These bits are reserved and must be programmed to 00000. 00: Reserved; no connection. 01: GPIO pin used as Op Amp A positive input, AMPAINP. the GPIO used as Op Amp B output, AMPBOUT. Register (CMP0CTL1) on page 496 to learn more.

programmable gain and Op Amp A. Table 253. Op Amp A Control 1 Register (AMPACTL1) GAIN is effective only when INNSEL = 01. 0: Low power, 1 µA current, 40 kHz unity gain bandwidth (nominal values). 1: Normal power, 30 µA current, 620 kHz unity gain bandwidth (nominal values). set, both op amps will operate with normal power. This bit is reserved and must be programmed to 0. 00: GPIO pin used as Op Amp A negative input, AMPAINN. 10: Op Amp A output, unity gain configuration using internal connection.

Table 254. Op Amp B Control 0 Register (AMPBCTL0) OUTCTL is dependent upon the value of MODE. Input/Output chapter on page 55. 00, 11: Op Amp B output is disconnected from the GPIO used as AMPBOUT. Input/Output chapter on page 55.

current sourcing/sinking and for Op Amp B. These bits are reserved and must be programmed to 0. 00: 1.0 V (nominal) reference from the Reference System. 01: GPIO pin used as Op Amp B input, AMPBINP. the GPIO used as the Op Amp A output, AMPAOUT. 1 Control 1 Register (CMP1CTL1) on page 498 to learn more. 1 Control 1 Register (CMP1CTL1) on page 498 to learn more. Table 255. Op Amp B Control 1 Register (AMPBCTL1)

PS029413-0921 P R E L I M I N A R Y Op Amp Register Definitions Z8 Encore! XP® F6482 Series Product Specification 485 Bit Description [7:6] Reserved These bits are reserved and must be programmed to 00. [5:4] IRESSEL Current Source Resistor Select RESSEL is meaningful only when MODE = 1 00: External resistor, connected to the GPIO used as Op Amp B negative input, AMPBINN, forms current drive set point. 01: Internal 31.25 KΩ (nominal) resistor forms current drive set point and provides 10 µA*. 10: Internal 3.125 KΩ (nominal) resistor forms current drive set point and provides 100 µA*. 11: Internal 312.5 Ω (nominal) re sistor forms current drive set point and provides 1.0 mA*. The Op Amp B IRESSEL = 11 setting is not recommended for AVDD < 3V [3] OPOWER Op Amp Power/Speed Select 0: Low power, 1 µA current, 40 kHz unity gain bandwidth (nominal values). 1: Normal power, 30 µA current, 620 kHz unity gain bandwidth (nominal values). Note: This bit is OR’ed with the Op Amp A OPOWER bit such that if either OPOWER bit is set, both op amps will operate with normal power. [2] Reserved This bit is reserved and must be programmed to 0. [1] INNSEL Negative Input Signal Select INNSEL is dependent upon the value of MODE MODE = 0 0: GPIO pin used as Op Amp B negative input, AMPBINN. 1: Op Amp B output, unity gain configuration. MODE = 1 x: Connection to current drive set point resistor selected by IRESSEL. [0] MODE Mode 0 = Normal mode, INNSEL bit selects the Op Amp B negative input. 1 = Current drive mode, INNSEL has no effect. Note: *Assumes the Programmable Re ference 1 level is 0.3125 V.

PS029413-0921 P R E L I M I N A R Y Comp arators and Reference System Z8 Encore! XP® F6482 Series Product Specification 486 Chapter 24. Comparators and Reference System The F6482 Series devices feature a reference system and two identical general-purpose, rail-to-rail comparators, each of which compares two analog input signals with four speed- vs.-power settings and three hysteresis options. A 4-to-1 input multiplexer exists on each comparator positive input and each comparator negative input. Multiplexing can be con- figured such that a GPIO (C0INP/C1INP) pin provides a positive comparator input and/or a GPIO (C0INN/C1INN) provides a negative input. The output of each comparator is available as an interrupt source and can be routed to an external pin using the GPIO multi- plex, as well as to the Event System. Features for each comparator include:

• Positive input selections offering a GPIO, a temperature sensor and op amp outputs AMPAOUT and AMPBOUT
• Negative input selections offering a GPIO, fixed internal reference levels, a program- mable internal reference, and the DAC
• Output can be an interrupt source
• Output can drive an external pin and/or be an Event System source
• Operation in Stop Mode
• Power-vs.-speed control with four available settings
• Hysteresis control with three available settings
• Window detection: signal above window, signal inside window, signal below window
• Additional output in the form of a logical OR of each comparator output, is an Event System source, is useful for window detection signaling Features of the Reference System are as follows:
• Reference Generator: – Fixed reference voltages including: the bandgap voltage, AVDD/2, 0.75 V , 1.0 V , and 1.25 V , that are available to certain internal functions – VBIAS with four selectable levels (2.5 V , 2.0 V , 1.5 V , 1.25 V) that is available as an internal positive voltage reference for the ADC and as a GPIO alternate func- tion to provide a low-power external reference – DAC internal positive voltage reference with four selectable levels (2.5 V , 2.0 V , 1.5 V , 1.25 V)
• Two programmable references provide 32 taps (steps), with the highest tap selectable as either VBIAS or AVDD

PS029413-0921 P R E L I M I N A R Y Comparator Operation Z8 Encore! XP® F6482 Series Product Specification 489 24.2. Comparator Operation Two identical general-purpose CMOS analog comparators each provide rail-to-rail opera- tion with four speed-vs.-power settings and three hysteresis options. These comparators are enabled by setting the COMP0 and COMP1 bits in the PWRCTL0 Register, which is described in the Low-Power Modes chapter on page 50. The power setting is determined by the CPOWER bit, which selects current consumption ranging from 27 µA, with a prop- agation delay of 150 ns, to 0.2 µA, with a propagation delay of 10 µs. The low power set- tings can allow for continuous comparator usage in low-power systems. Hysteresis is selected by the HYST bit; selections range from no hysteresis to 40 mV . A 4-to-1 input multiplexer exists on each comparator positive input and each comparator negative input. The positive input is selected using the INPSEL bit to be either the temper- ature sensor, GPIO or one of the op amp outputs, AMPAOUT or AMPBOUT. The nega- tive input is selected using the INNSEL and PREFEN bits to be either a GPIO, a fixed reference (0.75V/1.25 V), the bandgap voltage, a programmable internal reference or the DAC output. Multiplexing can be configured such that a GPIO (C0INP/C1INP) pin pro- vides the positive comparator input and/or a GPIO (C0INN/C1INN) provides the negative input. When connecting to GPIO, use the appropriate GPIO alternate function selection, as described in the General-Purpose Input/Output chapter on page 55. The comparator output polarity is determined by the POLSEL bit. When POLSEL = 0, the comparator output is noninverted such that the comparator output is High when the posi- tive comparator input voltage is greater than the negative comparator input voltage. When POLSEL = 1, the comparator output is inverted such that the comparator output is Low when the positive comparator input voltage is greater than the negative comparator input voltage. The output of each comparator can be routed to a GPIO pin, C0OUT or C1OUT, as well as to the Event System. When connecting to GPIO, use the appropriate GPIO alternate func- tion selection, as described in the General-Purpose Input/Output chapter on page 55. Additionally, the comparator output state can be read directly from the CSTATUS bit in the COMPCTL Register. An additional output, C01, is the logical OR of each comparator output, and is an Event System source; it is useful for window detection signaling. A window compare feature provides coordinated detection reporting for the two compara- tors. WINEN = 1 selects Window Mode. The impact of WINEN and POLSEL on the com- parator outputs is summarized in Table 256 on page 490.

• Select Op Amp A as the positive input for both comparators.
• Select the GPIO used for AMPBOUT as the positive input for both comparators. Op Amp B can be enabled to drive the inputs or disabled to allow for external drive of the inputs.
• Select C0INP as the positive input for COMP0 and C1INP as the positive input for COMP1; connect C0INP and C1INP externally. The comparator outputs are used to provide interrupts, as described in the Interrupt Con- troller chapter on page 127.

Table 256. Effect of WINEN and POLSEL on Comparator Outputs Note: *Window state naming is fr om the perspective of noninverted polarity (POLSEL = 0) for both comparators.

PS029413-0921 P R E L I M I N A R Y Reference System Operation Z8 Encore! XP® F6482 Series Product Specification 491 The comparator can be powered down to save supply current or can continue to operate in Stop Mode. For details, see the Power Control Register 0 on page 52. In Stop Mode, the comparator interrupt, if enabled, automatically initiates a Stop-Mode Recovery and gener- ates an interrupt request. In the Reset Status Register (RSTSTAT) (see page 48), the stop bit is set to 1. Additionally, the Comparator request bit in the Interrupt Request 2 Register (see page 135) is set. Following completion of the Stop-Mode Recovery, and if interrupts are enabled, the CPU responds to the interrupt request by fetching the comparator inter- rupt vector. Because of the propagation delay of the comparator, spurious interrupts can result after enabling the comparator. Zilog recommends not enabling the comparator without first disabling interrupts, then waiting for the comparator output to settle. The following code example shows how to safely enable the comparator: di ldx CMP0CTL0,r0 ; set-up comparator ldx CMP0CTL1,r1 ; set-up comparator ldx PWRCTL0,r2 ; enable comparators nop nop ; wait for output to settle ldx IRQ2,#0 ; clear any spurious interrupts pending ei 24.3. Reference System Operation The Reference System provides predetermined fixed voltage levels and two programma- ble references that provide user-selectable voltage levels. Features of the Reference Sys- tem include:

• Reference Generator: – Fixed reference voltages including: the bandgap voltage, AVDD/2, 0.75 V , 1.0 V , and 1.25 V , that are available to certain internal functions – VBIAS with four selectable levels (2.5 V , 2.0 V , 1.5 V , 1.25 V) that is available as an internal positive voltage reference for the ADC and as a GPIO alternate func- tion to provide a low-power external reference – DAC internal positive voltage reference with four selectable levels (2.5 V , 2.0 V , 1.5 V , 1.25 V)
• Two programmable references provide 32 taps (steps), with the highest tap selectable as either VBIAS or AVDD Caution:

PS029413-0921 P R E L I M I N A R Y Reference System Operation Z8 Encore! XP® F6482 Series Product Specification 492 The Reference Generator behavior during Normal Mode and Halt Mode is as follows:

• Fixed reference voltages are always available
• VBIAS is available if any of the following conditions are true: – VBIASEN is set in the CMPCTL Register – A programmable reference is enabled – An internal reference voltage is selected for the ADC – An internal reference voltage is selected for the DAC and the DAC is enabled To output VBIAS on the VBIAS pin, select the corresponding GPIO alternate function and set the VBIASEN bit in the CMPCTL Register.
• The DAC VREF is available if an internal reference voltage is selected for the DAC and the DAC is enabled The Reference Generator behavior during Stop Mode is as follows:
• Fixed reference voltages are available if FRECOV=1
• VBIAS is available if FRECOV=1 and any of the following conditions are true: – VBIASEN is set in the CMPCTL Register – A programmable reference is enabled by setting PREFEN and clearing the PREF- SRC in the CMPxCTL1 Register – An internal reference voltage is selected for the ADC. To output VBIAS on the VBIAS pin, select the corresponding GPIO alternate function and set the VBIASEN bit in the CMPCTL Register. When enabled, the Reference Generator provides low current consumption. In addition, any particular fixed reference is automatically enabled upon selection in the function that uses the fixed reference. Each internal programmable reference features an independent enable, PREFEN, that eliminates current consumption if a particular programmable reference is not required. Each programmable reference can drive its assigned comparator and/or its assigned op amp. Programmable Reference 0 can be selected as an input to Comparator 0 and/or Op Amp A. Programmable Reference 1 can be selected as an input to Comparator 1 and/or Op Amp B. Each programmable reference provides 32 levels, selectable with PREFLVL. The upper- most level can be selected as VBIAS from the Reference Generator (PREFSRC = 0) or selected as AVDD (PREFSRC = 1). The level of the VBIAS is determined by REFLVL in the ADCCTL2 Register; see the Analog-to-Digital Converter chapter on page 439 for details. VBIAS also serves as a voltage reference for the ADC and VBIAS pin.

PS029413-0921 P R E L I M I N A R Y Comparator and Reference System Regist er Z8 Encore! XP® F6482 Series Product Specification 493 24.4. Comparator and Reference System Register Defini - tions This section defines the features of the following Comparator and Reference System regis- ters: Comparator Control Register (CMPCTL) at address F8Fh Comparator 0 Control 0 Register (CMP0CTL0) at address F90h Comparator 0 Control 1 Register (CMP0CTL1) at address F91h Comparator 1 Control 0 Register (CMP1CTL0) at address F92h Comparator 1 Control 1 Register (CMP1CTL1) at address F93h

Table 257. Comparator Control Register (CMPCTL) GPIO alternate function, VBIASEN must be set. registers if the VBIAS pin is to be driven by VBIAS. These bits are reserved and must be programmed to 000. This bit is reserved and must be programmed to 0. based on independent comparators. based on a window logic function of both comparators. Note: *C0OUT and C1OUT inc lude the effect of POLSEL.

The Comparator 0 Control 0 Register is shown in Table 258. Status is dependent upon the state of WINEN. 0x: Comparator 0 Out put (C0OUT) is Low*. 1x: Comparator 0 Out put (C0OUT) is High*. x0: Comparator 1 Out put (C1OUT) is Low*. x1: Comparator 1 Out put (C1OUT) is High*. 01: Below Window (C0OUT = C1OUT = 0)*. 10: Above Window (C0OUT = C1OUT = 1)*. Table 258. Comparator 0 Control 0 Register (CMP0CTL0) 00: Ultra-low power, current = 200 nA, Tpd = 10 µs (nominal values). 01: Low power, current = 1 µA, Tpd = 1.5 µs (nominal values). 10: Normal, current = 4 µA, Tpd = 700 ns (nominal values). 11: High Speed/Power, current = 27 µA, Tpd = 150 ns (nominal values). Note: *C0OUT and C1OUT inc lude the effect of POLSEL.

parator 0 and Programmable Reference 0. 00: GPIO pin used as Comparator 0 negative input, C0INN. 10: 1.25 V (nominal) reference from the Reference Generator. 11: GPIO pin used as DAC output, DAC. 10: GPIO pin used as Op Amp B output, AMPBOUT. the GPIO used as Op Amp A output, AMPAOUT. Table 259. Comparator 0 Control 1 Register (CMP0CTL1) comparator input voltage is greater than the negative comparator input voltage. input voltage is greater than the negative comparator input voltage.

The Comparator 1 Control 0 Register is shown in Table 260. 0: VBIAS is the highest tap of the Programmable Reference. DD is the highest tap of the Programmable Reference. Table 260. Comparator 1 Control 0 Register (CMP1CTL0) 00: Ultra-low power, current = 200 nA, Tpd = 10 µs (nominal values). 01: Low power, current = 1 µA, Tpd = 1.5 µs (nominal values). 10: Normal, current = 4 µA, Tpd = 700 ns (nominal values). 11: High Speed/Power, current = 27 µA, Tpd = 150 ns (nominal values).

parator 1 and Programmable Reference 1. 00: GPIO pin used as Comparator 1 negative input, C1INN. 10: 0.75 V (nominal) reference from the Reference Generator. 11: GPIO pin used as DAC output, DAC. 00: GPIO pin used as Comparator 1 positive input, C1INP. 10: GPIO pin used as Op Amp B output, AMPBOUT. AMPAOUT, which is the GPIO used as the Op Amp A output. Table 261. Comparator 1 Control 1 Register (CMP1CTL1) comparator input voltage is greater than the negative comparator input voltage. input voltage is greater than the negative comparator input voltage.

PS029413-0921 P R E L I M I N A R Y Comparator and Reference System Regist er Z8 Encore! XP® F6482 Series Product Specification 499 [5] PREFSRC Programmable Reference Source Selection 0: VBIAS is the highest tap of the Programmable Reference. 1: AV DD is the highest tap of the Programmable Reference. [4:0] PREFLVL Programmable Reference Level Selection 00000 to 11111:Programmable reference level = (PREFSRC selection) * (PREFLVL + 1) ÷ 32. Bit Description (Continued)

PS029413-0921 P R E L I M I N A R Y Temperature Sensor Z8 Encore! XP® F6482 Series Product Specification 500 Chapter 25. Temperature Sensor The on-chip Temperature Sensor allows temperature measurement on the die to an accu- racy of ±4° C over a range of –40° C to +85° C. Over a reduced range, the accuracy is ±1.5° C. This block is a moderately accurate temperature sensor for low-power applica- tions in which high accuracy is not required. The Temperature Sensor offers the following features:

• On-chip temperature sensor
• ±4° C full-range accuracy for calibrated version
• ±1.5° C accuracy over the range of 20° C to 30° C
• Temperature sensor output available to the ADC and comparators 25.1. Operation The on-chip Temperature Sensor is a Proportional To Absolute Temperature (PTAT) topol- ogy. The temperature sensor can be disabled by a bit in the Power Control Register 0 (see page 52) to reduce power consumption. The Temperature Sensor can be directly read by the ADC to determine the absolute value of its output. The temperature sensor output is also available as an input to the comparator for threshold-type measurement determination. The accuracy of the sensor when used with the comparator is less than when measured by the ADC. To learn more about select- ing the Temperature Sensor as an ADC input, see the Analog-to-Digital Converter chapter on page 439. For details about selecting the Temperature Sensor as a Comparator input, see the Comparators and Reference System chapter on page 486. During normal operation, the die undergoes heating that will cause a mismatch between the ambient temperature and that measured by the sensor. For best results, the F6482 Series device should be placed into Stop Mode for sufficient period such that the die and ambient temperatures converge (this period will be dependent on the thermal design of the system). The Temperature Sensor should be measured immediately after recovery from Stop Mode. The Temperature Sensor can remain active during Stop Mode to minimize the latency between Stop-Mode Recovery and performing a temperature measurement. The following equation defines the relationship between the Temperature Sensor voltage and the die temperature. VTS = (T + 273) * 0.003272 V/°C – 0.025 V In this equation, VTS is the Temperature Sensor output in volts and T is the temperature in °C.

and VREF is the ADC voltage reference value in volts. ence are shown in Table 262. Table 262. Temperature vs. ADC Output, ADC VREF = 1.25 V

Table 262. Temperature vs. ADC Output, ADC V

PS029413-0921 P R E L I M I N A R Y Liquid Crystal Display Controller Z8 Encore! XP® F6482 Series Product Specification 503 Chapter 26. Liquid Crystal Display Controller The Z8 Encore! Liquid Crystal Display (LCD) Controller contains dual data memory banks and provides low-power bias generation, waveform generation, and drives the liq- uid crystal display. The LCD Controller offers the following features:

• Directly drives 3 V LCDs
• Up to 4 common lines and 24 segment lines
• Compatible with static, 1/2, 1/3, 1/4 duty shows operating at full, 1/2, 1/3 bias
• Selectable Type A or Type B LCD waveform generation
• Dual memory banks and blinking modes
• Frame rate interrupt (every two frames for Type B) or blink rate interrupt – The frame rate (or blink rate) dividers can be used as a timer even if LCD wave- forms are not being generated
• Can be selected to remain active in Stop Mode
• VLCD is selectable as either the internal regulated charge pump (2.5 V to 3.5 V), VDD, or external supply
• Two contrast control methods are provided: – Programmable charge pump voltage – Dead time insertion for both internal VDD and external VLCD 26.1. Architecture The LCD Controller is comprised of two display memory banks, clock dividers, a charge pump, a bias generator, and a waveform generator. The clock dividers include a prescaler, a frame rate divider, and a blink rate divider. The architecture of the LCD Controller is shown in Figure 85.

caler and the frame rate divider. Display blinking is supported using the blink rate divider. be supplied by an internal charge pump, VDD, or an external voltage reference. Figure 85. Liquid Crystal Display Controller Block Diagram

8 Waveform

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 505 26.2.1. LCD Registers and Subregisters Five registers configure the LCD Controller, and two registers provide access to the LCD Display Memory Bank A and Bank B subregisters. The LCD Subaddress Register (LCDSA) and an LCD Subdata Register (LCDSD) together provide access to the 12 sub- registers of each bank of LCD display memory – namely, the LCDMEMAx and LCD- MEMBx subregisters. LCDSD provides a portal to these subregisters. For convenient access, the address in the LCDSA Register autoincrements modulo 12 with each LCDSD read or write to provide convenient access to LCD data memory subregisters without intervening writes to the LCDSA Register. To use autoincrementing when loading LCD display memory, software typically configures the starting address in the LCDSA Register to be 00h (Bank A) or 10h (Bank B), and must write the LCDSD values in order. When the autoincremented value of LCDSA reaches 0Bh (Bank A), the next access to the LCDSD Register will reset LCDSA to 00h. When the autoincremented value of LCDSA reaches 1Bh (Bank B), the next access to the LCDSD Register will reset LCDSA to 10h. To maintain an average zero DC bias for the LCD segments, changes in the control regis- ters take effect at the end of the waveform generator frame pattern. 26.2.2. LCD Display Memory The following sections describe the LCD display memory. 26.2.2.1. LCD Display Memory Banks A and B Two banks of LCD display memory, Bank A and Bank B, are provided; each bank consists of 12 bytes of display data. As described in the LCD Registers and Subregisters section on page 505, the LCD Subaddress Register (LCDSA) and a LCD Subdata Register (LCDSD) together provide access to subregisters in the LCD Display Memory Bank A and Bank B; i.e., the LCDMEMAx and LCDMEMBx subregisters. At any given time, only one LCD display memory bank is selected as the data source for the LCD; this bank can be selected with the DMMODE bit in the LCDCTL2 Register. Two additional DMMODE selections are available: alternating between banks and blank- ing the display. The bank currently selected as the source for the LCD Controller output is indicated by the MSTAT bit in the LCDCTL2 Register. Alternating between display mem- ory banks can be used to perform blinking with timing set by the blink rate control, as described in the LCD Blinking and Blanking section on page 508. 26.2.2.2. Writing the Display Memory When using Type A LCD waveforms, a display memory bank that is currently selected as the source for the waveform generator can be written any time without causing a DC volt- age on LCD segments. When using Type B LCD waveforms, a display memory bank that is currently selected as the source for the waveform generator should be written just prior to the frame boundary of the alternate frame to avoid an average nonzero DC voltage on the LCD display segments. If the IRQS bit is cleared in the LCDCTL2 Register, LCD

described in the LCD Control 2 Register section on page 526. waveform generator, while the other LCD display memory bank is updated. Table 263 shows how the LCD display memory is organized. Table 263. LCD Display Memory Organization Note: *LCDSA in the LCDSA Regist er contains the subregister address.

divide ratio is selected using the FDIV bit, and results in the frame clock. In this equation, DEAD CYCLES is selected by the value of CONTRAST. In this equation, DEAD CYCLES is selected by the value of CONTRAST. Type B waveforms, the common signals repeat after every two LCD frames. Table 263. LCD Display Memory Organization (Continued) Note: *LCDSA in the LCDSA Regist er contains the subregister address.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 508 As an example, the configuration that follows results in a frame rate that corresponds to the following equation:

• CLKSEL = 0 (PCLK @ 32.768 kHz)
• PRESCALE = 010 (divide by 4)
• FDIV = 1001 (divide by 20)
• LCDMODE= 1001, 1010, 1011, or 1100 (1/4 duty)
• CPEN = 0 (internal charge pump off)
• CONTRAST = 010 (2 dead cycles if CPEN = 0) 26.2.4. LCD Blinking and Blanking Blinking can be performed using a single LCD display memory bank or using both LCD display memory banks. In either case, the blinking rate is controlled by BDIV in the LCD Control 0 Register (LCDCTL0). The blink rate is determined as follows: Blink rate = (frame rate) ÷ (4 * BDIV) When using a single display memory bank, the blinking mode is configured using BMODE. When BMODE = 00, no blinking occurs; otherwise, blinking will occur on the display segment accessed by SEG0 and COM0 (BMODE = 01), the 4 display segments accessed by SEG0 and COM[3:0] (BMODE = 10), or on all segments ( B M O D E = 1 1 ) . Alternating between display memory banks A and B can be employed to perform blink- ing. To enable the ability to alternate between display memory banks, configure DMMODE = 10 in the LCD Control 2 Register. When DMMODE = 10, BMODE has no effect upon operation. To blank the display, configure DMMODE = 11 in the LCD Control 2 Register (LCDCTL2). Blanking the display in this way does not alter LCD display memory. When DMMODE = 11, BMODE has no effect upon operation. 26.2.5. Using the LCD as a Timer The prescaler, frame rate divider, and blinking divider can be used as a timer even if LCD waveforms are not being generated. To use the LCD as a timer without LCD waveform generation, configure the prescaler and dividers, as described in the LCD Frame Timing section on page 507 and the LCD Blinking and Blanking section on page 508; clear the WGENEN bit in the LCDCTL3 Register, and set the LCD bit in the PWRCTL0 Register. Interrupts are generated, as described in the Interrupts section on page 519.

diagram is shown in Figure 86. The internal charge pump is enabled by setting the CPEN bit in the LCDCTL1 Register. viding contrast control, as described in the Contrast Control section on page 518. Figure 86. LCD Voltage and Bias Generation Block Diagram

(BIASGSEL = 1), the internal charge pump output current capacity is also increased. erator current consumption and the bias drive. rized in Table 265, are selected with the LCDMODE bit in the LCTCTL2 Register. Table 264. VLCD and Bias Generator Source Selection Note: *Typically not s elected, because the bias generator resistive network will discharge VLCD.

waveforms for Static Mode are shown in Figure 87. Table 265. LCD Mode Selection and Corresponding Waveform Characteristics

with 1/2 bias are shown in Figure 88 (Type A) and Figure 89 (Type B). Figure 87. Static Mode Example Waveforms

Figure 88. 1/2 Duty Mode with 1/2 Bias Type A Example Waveforms

Mode with 1/3 bias are shown in Figure 90 (Type A) and Figure 91 (Type B). Figure 89. 1/2 Duty Mode with 1/2 Bias Type B Example Waveforms

0 V–½ VLCD

Figure 90. 1/3 Duty Mode with 1/3 Bias Type A Example Waveforms

Figure 91. 1/3 Duty Mode with 1/3 Bias Type B Example Waveforms

Duty Mode with 1/3 bias are shown in Figure 92 (Type A) and Figure 93 (Type B). Figure 92. 1/4 Duty Mode with 1/3 Bias Type A Example Waveforms

trast control using this CONTRAST bit. Figure 93. 1/4 Duty Mode with 1/3 Bias Type B Example Waveforms

the current frame is completed. registers provide access to the LCD Display Memory Bank A and B subregisters. the end of the waveform generator frame pattern. vides a portal to the these LCD display memory bank subregisters. Table 266. LCD Controller Registers and Subregisters Note: * LCDSA in the LCDSA Regist er contains the subregister address.

combine to provide access to all LCD display memory. ing, software must write the LCDSD values in order, typically starting from address 00h. the next access to the LCDSD Register will reset LCDSA to 10h. Table 267. LCD Subaddress Register (LCDSA) These bits are reserved and must be programmed to 000. access. LCDSA increments modulo 12 whenever LCDSD is read or written. access. LCDSA increments modulo 12 whenever LCDSD is read or written.

Table 268. LCD Subdata Register (LCDSD)

clock selection, clock prescale division and frame clock division. Table 269. LCD Clock Register (LCDCLK)

ing mode. Writes to this register take effect at the end of the current waveform. Table 270. LCD Control 0 Register (LCDCTL0)

generators. Writes to this register take effect at the end of the current waveform. BMODE has no effect if DMMODE = 1x. 01: One display segment blinks, th e LCD display segment accessed by SEG0, COM0. This bit is reserved and must be programmed to 0. Table 271. LCD Control 1 Register (LCDCTL1) higher-bias drive for the waveform transition. 000: Continuous low bias drive. 001: Higher bias drive for 1 prescaler output clock period, low bias drive otherwise. 010: Higher bias drive for 2 prescaler output clock periods, low bias drive otherwise. 011: Higher bias drive for 3 prescaler output clock periods, low bias drive otherwise. 100: Higher bias drive for 4 prescaler output clock periods, low bias drive otherwise. 101: Higher bias drive for 5 prescaler output clock periods, low bias drive otherwise. 110: Higher bias drive for 6 prescaler output clock periods, low bias drive otherwise. 0: The internal LCD Controller charge pump is disabled.

PS029413-0921 P R E L I M I N A R Y LCD Co ntrol Register Definitions Z8 Encore! XP® F6482 Series Product Specification 525 [3] BIASGSEL Bias Generator Selection 0: The normal transition bias drive is selected, nominally 360 kΩ for 1/3 LCD waveform biasing and 240 kΩ for 1/2 LCD waveform biasing. Normal internal charge pump output current is also selected. 1: The high transition bias drive is selected, nominally90 kΩ for 1/3 LCD waveform biasing and 60 kΩ for 1/2 LCD waveform biasing. High internal charge pump output current is also selected. [2:0] CONTRAST Contrast Control CONTRAST is a function of CPEN and waveform type (LCDMODE[2]). CPEN = 0, LCDMODE[2] = 0 (type B waveform): CONTRAST sets the number of frame clock cycles that all LCD Controller outputs are driven to VSS. 000: 0 dead cycles. 001: 1 dead cycles. 010: 2 dead cycles. 011: 3 dead cycles. 100: 4 dead cycles. 101: 6 dead cycles. 110: 8 for 1/2 and 1/4 duty. Reserved (not supported) for 1/3 duty. 111: Reserved. CPEN = 0, LCDMODE[2] = 1 (type A waveform): CONTRAST sets the number of frame clock cycles that all LCD Controller outputs are driven to V SS. 000: 0 dead cycles. 001: 1 dead cycles. 010: 2 dead cycles. 011: 3 dead cycles. 100: 4 dead cycles. 101: 5 dead cycles. 110: 6 dead cycles. 111: 8 for 1/2 and 1/4 duty. Reserved (not supported) for 1/3 duty. CPEN = 1: CONTRAST sets t7he V LCD level generated by the internal charge pump. 000: VLCD = 2.50V (nominal). 001: VLCD = 2.64V (nominal). 010: VLCD = 2.78V (nominal). 011: VLCD = 2.92V (nominal). 100: VLCD = 3.06V (nominal). 101: VLCD = 3.20V (nominal). 110: VLCD = 3.35V (nominal). 111: VLCD = 3.50V (nominal). Bit Description (Continued)

effect at the end of the current waveform. Table 272. LCD Control 2 Register (LCDCTL2) 0: LCD Display Memory Bank A is currently the source for the LCD Controller outputs. 1: LCD Display Memory Bank B is currently the source for the LCD Controller outputs. (LCDMODE[2]=1) and 7/4 frame for type B waveforms (LCDMODE[2]=0). and 5/3 frame for type B waveforms (LCDMODE[2]=0). Memory Bank A to LCD Memory Bank B. 0000: 1 common (COM0), 1/1 duty , static bias, static waveform. 0001: 2 commons (COM[1:0]), 1/2 d uty, 1/2 bias, type A waveform. 0010: 2 commons (COM[1:0]), 1/2 d uty, 1/2 bias, type B waveform. 0011: 2 commons (COM[1:0]), 1/2 d uty, 1/3 bias, type A waveform. 0100: 2 commons (COM[1:0]), 1/2 d uty, 1/3 bias, type B waveform. 0101: 3 commons (COM[2:0]), 1/3 d uty, 1/2 bias, type A waveform. 0110: 3 commons (COM[2:0]), 1/3 d uty, 1/2 bias, type B waveform. 0111: 3 commons (COM[2:0]), 1/3 d uty, 1/3 bias, type A waveform. 1000: 3 commons (COM[2:0]), 1/3 d uty, 1/3 bias, type B waveform. 1001: 4 commons (COM[3:0]), 1/4 d uty, 1/2 bias, type A waveform. 1010: 4 commons (COM[3:0]), 1/4 d uty, 1/2 bias, type B waveform. 1011: 4 commons (COM[3:0]), 1/4 d uty, 1/3 bias, type A waveform. 1100: 4 commons (COM[3:0]), 1/4 d uty, 1/3 bias, type B waveform.

controlled by BMODE in the LCDCTL0 Register. controlled by BMODE in the LCDCTL0 Register. rate divider output. BMODE in the LCDCTL0 Register has no effect upon operation. Upon enable, Bank A will be selected first. 11: Blank all segments. BMODE in the LCDCTL0 Register has no effect upon operation. Table 273. LCD Control 3 Register (LCDCTL3) This bit is reserved and must be programmed to 0. 0: Input from external VLCD. 1: Output from internal charge pump or internal VDD as selected by CPEN. 1: Enabled for normal operation. These bits are reserved and must be programmed to 0000.

Table 274. LCD Display Memory Bank A Subregisters (LCDMEMAx) 00–FF: LCD display memory bank data. Table 275. LCD Display Memory Bank B Subregisters (LCDMEMBx) 00–FF: LCD display memory bank data.

(32768), or 16KB (16384) of nonvolatile Flash memory with read/write/erase capability. through the On-Chip Debugger. protected block is configured to be at the desired page boundary. mation about their operation, see the Flash Option Bit Address Space section on page 546. Figure 94 shows the Flash memory arrangement. Table 276. F6482 Series Flash Memory Configurations

Figure 94. Flash Memory Arrangement

16 KB Flash

32 KB Flash

60 KB Flash

64 KB Flash

PS029413-0921 P R E L I M I N A R Y Flash Information Area Z8 Encore! XP® F6482 Series Product Specification 531 27.1. Flash Information Area The Flash Information Area is separate from Program Memory and is mapped to the two pages in the address range FC00h to FFFFh. This area is used primarily for factory trim- ming purposes. Not all of these addresses are user-accessible. The trim bits’ working val- ues can be accessed using the Trim Bit Address and Trim Bit Data registers, as described in the Flash Option Bits chapter on page 542. To map the Flash Information Area to Program Memory address range FC00h to FFFFh, set the INFO_EN bit in the Flash Page Select Register (FPS). 27.2. Operation The Flash Controller programs and erases Flash memory, and provides the proper Flash controls and timing for byte programming, Page Erase, and Mass Erase operations in Flash memory. The Flash Controller also contains several protection mechanisms to pre- vent accidental programming or erasure; these mechanisms operate on the page, block, and full-memory levels. The flow chart in Figure 95 shows basic Flash Controller operation. The following sec- tions provide details about the Lock, Unlock, Byte Programming, Page Protect, Page Unprotect, Page Select Page Erase, and Mass Erase operations listed in Figure 95.

Figure 95. Flash Controller Operation Flowchart

Locked Loop (FLL) to a minimum frequency of 1 MHz. Space section on page 546 and the On-Chip Debugger section on page 560. block level protection control of the Flash Controller. Table 277. To learn more, see the Flash Option Bit Address Space section on page 546.

1. Write the Page Select Register with the target page.
2. Write the first unlock command,

73h, to the Flash Control Register.

1. Write the second unlock command, 8Ch, to the Flash Control Register.
2. Rewrite the Page Select Registe r with the target page previously stored in this register

Table 277. Flash Code Protection Using the Flash Option Bit available through the On-Chip Debugger. 1 Programming and Page E rase are enabled for all of Flash Program Memory. Mass Erase is available through the On-Chip Debugger.

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 534 If the two Page Select writes do not match, the controller reverts to a locked state. If the two writes match, the selected page becomes active. For details, see Figure 95 on page 532. The Programming, Page Erase and Mass Erase operations will not be allowed if the FWP bit is cleared or if the page resides in a protected block. After unlocking a specific page, Byte Programing or Page Erase may be performed. At the conclusion of a Page Erase, the Flash Controller is automatically locked. To lock the Flash Controller after byte programming, write the Flash Control Register with any value other than the Page Erase or Mass Erase commands. 27.2.3.3. Flash Block Protection The final protection mechanism is implemented on a block basis. Any number of contigu- ous pages in Flash memory, starting from page 0, can be protected. When set, the FBP_EN bit in the Flash Block Protection Register enables Flash block protection. When Flash block protection is enabled, the FBPS field in the Flash Block Protection Register identi- fies the page number of the first page that is not protected. All pages below this page are protected. The Flash Block Protect Register is shared with the Page Select Register, and is selected for access by writing the 5Eh command byte to the Flash Control Register while the Flash Controller is locked. When selected, any subsequent read or write to the Page Select Reg- ister targets the Flash Block Protect Register. To deselect the Flash Block Protect Register, write any value to the Flash Control Register. The Flash Block Protect Register is initialized to 0 on Reset, putting each page into an unprotected state. When the FBP_EN bit in the Flash Block Protect Register is written to 1, the block of Flash pages up to – but not including – the page number in the FBPS field can no longer be written or erased. After the FBP_EN bit of the Flash Block Protect Reg- ister has been set, it cannot be cleared except by a System Reset. 27.2.4. Programming Flash memory is enabled for byte programming on the active page after unlocking the Flash Controller. Erase the address(es) to be programmed using either the Page Erase or Mass Erase command prior to programming. An erased Flash byte contains all ones (FFh). The programming operation can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits) from 0 to 1 requires execution of either the Page Erase or Mass Erase command. Programming can be performed using the On-Chip Debugger’s Write Memory command or an eZ8 CPU execution of the LDC or LDCI instructions. For a description of these LDC and LDCI instructions, refer to the eZ8 CPU Core User Manual (UM0128), which is Note:

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 535 available free for download from the Zilog website. While the Flash Controller programs Flash memory, the eZ8 CPU remains idle, but the system clock and on-chip peripherals continue to operate. After an address is written, the page remains unlocked, allowing for subsequent writes to other addresses on the same page. To exit programming mode and lock Flash memory, write any value to the Flash Control Register except for the Mass Erase or Page Erase commands. 27.2.5. Byte Programming Mode If the PMODE field is set to Byte Programming Mode, byte writes to program memory from user code program a byte into Flash. 27.2.6. Word Programming Mode If the PMODE field is set to Word Programming Mode, Flash memory must be pro- grammed one word (16 bits) at a time. Two byte writes to program memory from user code are required in the following sequence: 1. Byte write to the even addre ss. This byte is registered until either Word Programming is completed or the register is overwritten by a new byte write to an even address. 2. Byte write to the odd address . Writing an odd address triggers Word Programming of the stored even address byte and the current byte to the current word address (LSB ignored). If only the odd address is written, Byte Programming of the odd address byte is performed and the even address byte in program memory is unchanged. Each Flash memory row of 128 bytes is subject to a maximum cumulative program time and, as specified in the Electrical Characteristics chapter on page 601, rows start at address multiples of 0080h. Therefore, the first three rows start at addresses 0000h, 0080h, and 0100h, respectively. The byte at each address of Flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. 27.2.7. Page Erase Flash memory can be erased one page (512 bytes) at a time. Page erasing Flash memory sets all bytes in the active page to the value FFh. The Flash Page Select Register identifies the page to be erased. Only a page residing outside the protected block can be erased. With the Flash Controller unlocked, writing the value 95h to the Flash Control Register initiates the Page Erase operation on the active page. While the Flash Controller executes the Page Caution:

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 536 Erase operation, the eZ8 CPU remains idle, but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation com- pletes. If the Page Erase operation is performed using the OCD, poll the Flash Status Reg- ister to determine when the Page Erase operation is complete. When the Page Erase is complete, the Flash Controller returns to its locked state. 27.2.8. Mass Erase Flash memory can also be mass erased using the Flash Controller, but only by using the On-Chip Debugger. Mass erasing Flash memory sets all bytes to the value FFh. With the Flash Controller unlocked, writing the value 63h to the Flash Control Register initiates the Mass Erase operation. While the Flash Controller executes the Mass Erase operation, the eZ8 CPU remains idle, but the system clock and on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Status Register to determine when the Mass Erase operation is complete. When the Mass Erase is complete, the Flash Controller returns to its locked state. Mass Erase does not affect the user page in the Flash Information Area. Use Page Erase to erase the user page in the Flash Information Area. 27.2.9. Flash Controller Bypass The Flash Controller can be bypassed so that the control signals for Flash memory can be brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Program- ming algorithms by controlling the Flash programming signals directly. Zilog recommends row programming for gang programming applications and large-vol- ume customers who do not require the in-circuit initial programming of Flash memory. Mass Erase and Page Erase operations are also supported when the Flash Controller is bypassed. For more information about bypassing the Flash Controller, please contact Zilog Technical Support. 27.2.10.Flash Controller Behavior in Debug Mode The following changes in the behavior of the Flash Controller occur when the Flash Con- troller is accessed using the On-Chip Debugger:

• The Flash Write Protect option bit is ignored
• The Flash Block Protect Register is ignored for programming operations
• Programming operations are not limited to the page selected in the Page Select Register
• Bits in the Flash Block Protect Register can be written to 1 or 0
• The second write of the Page Select Register to unlock the Flash Controller is not necessary

PS029413-0921 P R E L I M I N A R Y Flash Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 537

• The Page Select Register can be written when the Flash Controller is unlocked.
• The Mass Erase command is enabled through the Flash Control Register For security reasons, the Flash controller allows only a single page to be opened for write/erase. When writing multiple Flash pages, the Flash controller must go through the unlock sequence again to select another page. 27.3. Flash Control Register Definitions This section defines the features of the following Flash Control registers. Flash Control Register Flash Status Register : see page 538 Flash Page Select Register: see page 539 Flash Block Protect Register: see page 540 Flash Programming Configuration: see page 541 27.3.1. Flash Control Register The Flash Controller must remain unlocked when using the Flash Control Register (shown in Table 278) before programming or erasing Flash memory. The Flash Controller is unlocked by writing the Flash Page Select Register, then 73h 8Ch, sequentially, to the Flash Control Register. A final write must then be made to the Flash Page Select Register with the same value as the previous write. When the Flash Controller is unlocked, Mass Erase or Page Erase can be initiated by writing the appropriate command to the FCTL. Page Erase applies only to the active page selected in the Flash Page Select Register. Mass Erase is enabled only through the On-Chip Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state. The write-only Flash Con- trol Register shares its Register File address with the read-only Flash Status Register. Caution:

shares its Register File address with the write-only Flash Control Register. Table 278. Flash Control Register (FCTL) 95h: Page Erase command (must be third command in sequence to initiate Page Erase). 63h: Mass Erase command (must be third command in sequence to initiate Mass Erase). 5Eh: Enable Flash Block Protect Register Access. Table 279. Flash Status Register (FSTAT) These bits are reserved and must be programmed to 00000. 000: Flash Controller locked. 001: First unlock command received (73h written). 010: Second unlock command received (8Ch written). 011: Flash Controller unlocked. 100: Block Protect Register selected. 101: Program operation in progress. 110: Page erase operation in progress. 111: Mass erase operation in progress.

address target the Flash Page Select Register. This register is used to select one of the Flash memory pages to be programmed or erased. chosen for program/erase operation. Table 280. Flash Page Select Register (FPS) 0: Information Area is not selected. address space in the FC00h–FFFFh address range. This 7-bit field identifies the Flash memory page for Page Erase and page unlocking. always be 0. For Z8F1681 devices, the upper two bits must always be 0.

lect this register, write any value to the Flash Control Register. register bits can only be cleared) by a System Reset. Table 281. Flash Block Protect Register (FBP) 0: Block Protection is not enabled. 1: Block Protection is enabled. FBP_EN bit is set, all pages below the page number in this field are protected.

bit that configures the number of bytes that are programmed simultaneously. Table 282. Flash Programming Configuration Register (FPCONFIG) These bits are reserved and must be programmed to 0000000.

PS029413-0921 P R E L I M I N A R Y Flash Option Bits Z8 Encore! XP® F6482 Series Product Specification 542 Chapter 28. Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of F6482 Series MCU operation. The configuration data are stored in Flash Program Memory and are read during Reset. The features available for control through the Flash option bits include:

• Watchdog Timer time-out response selection – interrupt or System Reset
• Watchdog Timer enabled at Reset
• The ability to prevent unwanted read access to user code in Program Memory
• The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory
• The VBO can be configured as always enabled, enabled only during Normal and Halt modes to reduce Stop Mode power consumption, or disabled
• LVD voltage threshold selection
• Factory trimming information for multiple analog functions 28.1. Operation The following sections describe Flash option bit operation. 28.1.1. Option Bit Configuration by Reset Each time Flash option bits are programmed or erased, the device must be Reset for changes to take effect. During any Reset operation (System Reset or Stop-Mode Recov- ery), these Flash option bits are automatically read from Flash Program Memory and writ- ten to the Option Configuration registers. These Option Configuration registers control operation of the devices within the F6482 Series MCU. Option bit control is established before the device exits System Reset and before the eZ8 CPU begins code execution. The Option Configuration registers are not part of the Register File and are not accessible for read or write access. 28.1.2. Option Bit Types The following sections describe the option bit types. 28.1.2.1. User Option Bits The user option bits are contained in the first two bytes of Program Memory. Zilog pro- vides user access to these bits because these locations contain application-specific device

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 543 configurations. The information contained here is lost when page 0 of the Program mem- ory is erased. 28.1.2.2. Trim Option Bits The trim option bits are contained in the information area of Flash memory. These bits are factory-programmed values required to optimize the operation of onboard analog circuitry and cannot be permanently altered by the user. Program memory can be erased without endangering these values. It is possible to alter working values of these bits by accessing the Trim Bit Address and Data registers, but these working values are lost after a power loss. There are 32 bytes of trim data. To modify one of these values, the user code must first write a value between 00h and 1Fh into the Trim Bit Address Register. The next write to the Trim Bit Data Register changes the working value of the target trim data byte. Reading trim data requires the user code to write a value between 00h and 1Fh into the Trim Bit Address Register. The next read from the Trim Bit Data Register returns the working value of the target trim data byte. The trim address ranges from information address 20–3F only. The remainder of the infor- mation area is not accessible via the trim bit address and data registers. 28.1.2.3. Zilog Option Bits The Zilog option bits are also contained in the information area of Flash memory. These bits are factory-programmed values that configure device peripherals and cannot be altered by the user. Program memory can be erased without endangering these values. Prior to locking the Flash Information Area, it is possible to alter working values of these bits using the OCD Write Option Bits command, but these working values are lost after a power loss. The working value of these bits can be read by using the OCD Read Option Bits command. The programmed value of these bits can be read after selecting the lower information page using the Flash Page Select Register by reading program memory addresses FC00h–FC1Fh. 28.1.2.4. Zilog Device Data Zilog device data are also contained in the lower information page of Flash memory. These bits are factory-programmed values that contain a part number and other manufac- turing information; these values cannot be altered by the user. Program memory can be erased without endangering these values. The value of these bits can be read after select- ing the lower information page using the Flash Page Select Register by reading program memory addresses FC40h–FC57h. Note:

PS029413-0921 P R E L I M I N A R Y Flash Op tion Bit Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 544 28.2. Flash Option Bit Control Register Definitions This section defines the features of the following Flash option bit registers. Trim Bit Address Register (TRMADR): see page 545 Trim Bit Data Register (TRMDR): see page 546 Flash Option Bits at Program Memory Address 0000h: see page 546 Flash Option Bits at Program Memory Address 0001h: see page 547 Trim Bit Address Description: see page 548 Trim Option Bits at Address 0000h (TBA0): see page 548 Trim Option Bits at Address 0001h (TTEMP0): see page 549 Trim Option Bits at Address 0002h (TTEMP1): see page 549 Trim Option Bits at Address 0003h (TIPO): see page 550 Trim Option Bits at Address 0004h (TLVD_VBO): see page 550 Trim Option Bits at Address 0005h (TVREF): see page 552 Trim Option Bits at Address 0006h (TVBGVREG): see page 552 Trim Option Bits at Address 0007h (TWDT): see page 553 Trim Option Bits at Address 0008h (TLCD0): see page 553 Trim Option Bits at Address 0009h (TLCD1): see page 554 Trim Option Bits at Address 000Ah: see page 554 Trim Option Bits at Address 000Bh: see page 555 Trim Option Bits at Address 000Ch (TVBIAS): see page 555

Area address range 20h–3Fh, as indicated in Table 284. Table 283. Trim Bit Address Register (TRMADR) Table 284. Trim Bit Address Map

reserved for the user-programmable Flash Option bits. See Table 286. Table 285. Trim Bit Data Register (TRMDR) Table 286. Flash Option Bits at Program Memory Address 0000h Note: *RESET = POR reset only; X = undefined; R/W = read/write. enabled for the eZ8 CPU to acknowledge the interrupt request. unprogrammed (erased) Flash.

setting is the default for unprogrammed (erased) Flash. 00: Reserved (defaults to disabled). 01: Voltage Brown-Out Protection is disabled. unprogrammed (erased) Flash. setting is default for unprogrammed (erased) Flash. available using the On-Chip Debugger. Table 287. Flash Option Bits at Program Memory Address 0001h Note: X = undefined; R/W = read/write.

details about each, see Tables 290 through 301. The Trim Option Bits Register at address 0000h, shown in Table 289, is reserved. Table 288. Trim Bit Address Description Table 289. Trim Option Bits at Address 0000h (TBA0) Note: X = und efined; R/W = read/write; R = read-only.

291, govern control of the temperature sensor trim bits. Table 290. Trim Option Bits at Address 0001h (TTEMP0) Note: X = und efined; R/W = read/write; R = read-only. Contains gain trimming bits for the Temperature Sensor. Table 291. Trim Option Bits at Address 0002h (TTEMP1) Note: X = und efined; R/W = read/write; R = read-only. Contains offset trimming bits for the Temperature Sensor.

the Internal Precision Oscillator trim bits. the V oltage Brown-Out and Low V oltage Detect trim bits. Table 292. Trim Option Bits at Address 0003h (TIPO) Note: X = und efined; R/W = read/write; R = read-only. Contains trimming bits for Internal Precision Oscillator. Table 293. Trim Option Bits at Address 0004h (TLVD_VBO) Note: *RESET = POR reset only; X = undefined; R/W = read/write; R = read-only. Typical LVD_TRIM values are listed in Table 294.

Table 294. LVD_Trim Values 11111 1.65 Minimum LVD thre shold; default on Reset.

of the DAC and ADC/DAC V oltage Reference (VREF). the bandgap and voltage regulator trim bits. Table 295. Trim Option Bits at Address 0005h (TVREF) Note: X = und efined; R/W = read/write; R = read-only. Table 296. Trim Option Bits at Address 0006h (TVBGVREG) Note: *RESET = POR reset only; X = undefined; R/W = read/write.

The Trim Option Bits Register at address 0007h (see Table 297), governs control of the WDT. 299, govern control of the LCD trim bits. Table 297. Trim Option Bits at Address 0007h (TWDT) Note: X = und efined; R/W = read/write; R = read-only. This bit is reserved and is factory-programmed to 0. This bit is reserved and is factory-programmed to 1. Table 298. Trim Option Bits at Address 0008h (TLCD0) Note: X = und efined; R/W = read/write; R = read-only.

Tables 300 and 301, are reserved for future use. Table 299. Trim Option Bits at Address 0009h (TLCD1) Note: X = und efined; R/W = read/write; R = read-only. Table 300. Trim Option Bits at Address 000Ah Note: X = und efined; R/W = read/write; R = read-only.

of the 1.25V VBIAS V oltage Reference (VBIAS). Table 301. Trim Option Bits at Address 000Bh Note: X = und efined; R/W = read/write; R = read-only. Table 302. Trim Option Bits at Address 000Ch (TVBIAS) Note: X = und efined; R/W = read/write; R = read-only.

PS029413-0921 P R E L I M I N A R Y Non-Volatile Data Storage Z8 Encore! XP® F6482 Series Product Specification 556 Chapter 29. Non-Volatile Data Storage Many of the F6482 Series devices contain a 128-byte Non-V olatile Data Storage (NVDS) element. This data memory can perform over 100,000 write cycles. 29.1. Operation The NVDS is implemented by special-purpose Zilog software stored in areas of program memory not accessible to users. These special-purpose routines use Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maximize the write/ erase endurance of Flash memory. Not all members of the F6482 Series feature NVDS. To learn more, see Table 1 on page 3. 29.2. NVDS Code Interface Two routines are required to access the NVDS: a write routine and a read routine. Both of these routines are accessed with a CALL instruction to a predefined address outside the program memory space accessible to users. Both the NVDS address and data are single- byte values. To prevent the user code from being disturbed, these routines save the work- ing register set before using it; therefore, 16 bytes of stack space is required to preserve the site. After finishing the call to these routines, the working register set of the user code is recovered. During both read and write accesses to the NVDS, interrupt service is not disabled. Any interrupts that occur during the NVDS execution must not disturb the working register and existing stack contents; otherwise, the array becomes corrupted. Zilog recommends dis- abling interrupts before executing NVDS operations. Use of the NVDS requires 16 bytes of available stack space. The contents of the working register set are saved before calling NVDS read or write routines. For correct NVDS operation, Flash operation timing requirements must be met. To learn more, see the Flash Operation Timing section on page 533. 29.2.1. Byte Write To write a byte to the NVDS array, the user code must first push the address, then the data byte, onto the stack. The user code issues a CALL instruction to the address of the Byte Write routine (0xF3FD). At the return from the subroutine, the write status byte resides in Note:

ally, the user code should pop the address and data bytes off the stack. data pushed by the user code. Sufficient memory must be available for this stack usage. effect. Illegal write operations have a 7 µs execution time. NVDS, the FLL must be running at a minimum of 1 MHz. Word write is not available. To read a byte from the NVDS array, user code must first push the address onto the stack. User code issues a CALL instruction to the address of the byte-read routine (i.e., 0xF000). in Table 304. In addition, the user code should pop the address byte off the stack. Table 303. Write Status Byte All bits are reserved and must be programmed to 0000. 0: The write attempted was to a legal address (one that is within the NVDS array size). 1: The write attempted was to an illegal address (one that exceeds the NVDS array size). 0: No NVDS write error occurred. 1–7: An NVDS write error occurred. The memory location accessed may be corrupt.

speeds result in proportionally higher execution times. Table 304. Read Status Byte All bits are reserved and must be programmed to 0000. 0: The write attempted was to a legal address (one that is within the NVDS array size). 1: The write attempted was to an illegal address (one that exceeds the NVDS array size). 0: No NVDS read e rror occurred. All bits are reserved and must be programmed to 00.

ever, actual speed benefits are not always realized. Table 305. NVDS Access Latency

Isolated USB, USB, or Ethernet Smart Cables when using in conjunction with ZDS II.

• The eZ8 CPU fetch unit stops, thereby idling the eZ8 CPU, unless directed by the OCD to execute specific instructions
• The system clock operates unless in Stop Mode
• All enabled on-chip peripherals operate unless in Stop Mode or otherwise defined by the on-chip peripheral to disable in Debug Mode
• Automatically exits Halt Mode
• Constantly refreshes the Watchdog Timer, if enabled 30.2.3.1. Entering Debug Mode The device enters Debug Mode following any of these operations:

Figure 100. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #2 of 2

• Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface
• eZ8 CPU execution of a breakpoint (BRK) instruction (when enabled)
• Match of PC to OCDCNTR Register (when enabled)
• OCDCNTR Register decrements to 0000h (when enabled)
• The DBG pin is Low when the device exits Reset 30.2.3.2. Exiting Debug Mode The device exits Debug Mode following any of these operations:
• Clearing the DBGMODE bit in the OCD Control Register to 0
• Power-on reset
• Voltage Brown-Out reset
• Asserting the RESET pin Low to initiate a Reset
• Driving the DBG pin Low when the device is in Stop Mode initiates a System Reset 30.2.4. OCD Data Format The On-Chip Debugger (OCD) interface uses the asynchronous data format defined for RS-232. Each character is transmitted as 1 start bit, 8 data bits (least-significant bit first), and 1 stop bit; see Figure 101. 30.2.5. OCD Auto-Baud Detector/Generator To run over a range of baud rates (bits per second) with differing system clock frequen- cies, the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is idle until it receives data. The OCD requires that the first character sent from the host is the character 80h, which contains eight continuous bits Low (1 start bit plus 7 data bits). The Auto-Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly.

Figure 101. OCD Data Format

character, the Auto-Baud Detector will remain reset. automatically run at the desired baud rate. a high-speed synchronous interface is shown in Figure 102. Table 306. OCD Baud-Rate Limits

• Serial Break (a minimum of ten continuous bits Low)
• Framing Error (the received stop bit is Low)
• Transmit Collision (OCD and host simultaneous transmission detected by the OCD) When the OCD detects one of these errors, it aborts any command currently in progress, transmits a Serial Break 4096 system clock cycles long back to the host, and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision can be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the inter- face, returning a Serial Break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host transmits a Serial Break on the DBG pin when first connecting to the F6482 Series device or when recovering from an error. A Serial Break from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Control Register. A Serial Break leaves the device in Debug Mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character.

Figure 102. Synchronous Operation

invalid. A new Auto-Baud value must be configured with the new clock frequency. the Auto-Baud is set, the device will automatically send a Serial Break for 4096 clocks.

• The values of SCKDIV or SCKSEL in the CLKCTL0 Register have been changed
• A write to CLKCTL3 when DCOEN = 1 and FLLEN = 1 in the CLKCTL5 Register and SCKSEL = 000 (DCO is the System Clock)
• A write to CLKCTL6 when DCOEN = 1 and FLLEN = 0 in the CLKCTL5 Register and SCKSEL = 000 (DCO is the System Clock) 30.2.9. Transmit Flow Control Transmit flow control is implemented by the use of a remote start bit. When transmit flow control is enabled, the transmitter will wait for the remote host to send the start bit. Trans- mit flow control is useful in applications in which receive overruns can occur. The remote host can transmit a remote start bit by sending the character FFh. The trans- mitter will append its data after the start bit. Due to the wire and nature of the open-drain bus, the start bit sent by the remote host and the data bits sent by the F6482 Series device appear as one character, as shown in Figure 103.

Figure 103. Start Bit Flow Control

PS029413-0921 P R E L I M I N A R Y Operation Z8 Encore! XP® F6482 Series Product Specification 568 30.2.10.Breakpoints Execution breakpoints are generated using the BRK instruction (op code 00h). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If breakpoints are enabled, the OCD idles the eZ8 CPU and enters Debug Mode. If breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as a NOP instruction. If breakpoints are enabled, the OCD can be configured to automatically enter Debug Mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK instruction, then the CPU remains able to service interrupt requests. The loop on BRK instruction can service interrupts in the background. For interrupts to be serviced in the background, there cannot be any breakpoints in the interrupt service rou- tine. Otherwise, the CPU stops on the breakpoint in the interrupt routine. For interrupts to be serviced in the background, interrupts must also be enabled. Interrupts are typically dis- abled during critical sections of code in which interrupts do not occur (such as adjusting the stack pointer or modifying shared data). Through the OCD, host debugger software can poll the IDLE bit of the OCDSTAT Regis- ter to determine if the OCD is looping on a BRK instruction. When the host wants to stop the CPU on the BRK instruction on which it is looping, the host must not set the DBG- MODE bit of the OCDCTL Register. The CPU may have vectored to an interrupt service routine. Instead, the host clears the BRKLOOP bit to allow the CPU to finish the interrupt service routine it may be in, then return to the BRK instruction. When the CPU returns to the BRK instruction on which it was previously looping, it automatically sets the DBG- MODE bit and enters Debug Mode. The majority of the OCD commands remain disabled when the eZ8 CPU is looping on a BRK instruction. The eZ8 CPU must be in Debug Mode before these commands can be issued. 30.2.10.1.Breakpoints in Flash Memory The BRK instruction is op code 00h, which corresponds to the fully programmed state of a byte in Flash memory. To implement a breakpoint, write 00h to the desired address, overwriting the current instruction. To remove a breakpoint, erase the corresponding page of Flash memory and reprogram with the original data. 30.2.11.OCD Counter Register The On-Chip Debugger contains a multipurpose 16-bit counter register that can be used for the following tasks:

• Count system clock cycles between breakpoints
• Generate a BRK when it counts down to 0
• Generate a BRK when its value matches the Program Counter

PS029413-0921 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F6482 Series Product Specification 569 When configured as a counter, the OCDCNTR Register starts counting when the On-Chip Debugger exits Debug Mode, and stops counting when it reenters Debug Mode or when it reaches the maximum count of FFFFh. The OCDCNTR Register automatically resets itself to 0000h when the OCD exits Debug Mode if it is configured to count clock cycles between breakpoints. If the OCDCNTR Register is configured to generate a BRK when it counts down to zero, it will not be reset when the CPU starts running. The counter will start counting down toward zero when the On-Chip Debugger exits Debug Mode. If the On-Chip Debugger enters Debug Mode before the OCDCNTR Register counts down to zero, the OCDCNTR will stop counting. If the OCDCNTR Register is configured to generate a BRK when the program counter matches the OCDCNTR Register, the OCDCNTR Register will not be reset when the CPU resumes executing and it will not be decremented when the CPU is running. A BRK will be generated when the program counter matches the value in the OCDCNTR Register before executing the instruction at the location of the program counter. The OCDCNTR Register is used by many of the OCD commands. It counts the number of bytes for the register and memory read/write commands. It retains the residual value when generating the CRC. If the OCDCNTR is used to generate a BRK, its value must be written as a final step before exiting Debug Mode. Because this register is overwritten by multiple OCD commands, it must only be used to generate temporary breakpoints, such as stepping over CALL instructions or running to a specific instruction and stopping. When the OCDCNTR Register is read, it returns the inverse of the data in this register. The OCDCNTR Register is only decremented when counting. The mode in which it counts the number of clock cycles in between execution is achieved by counting down from its maximum count. When the OCDCNTR Register is read, the counter appears to have counted up because its value is inverted. The value in this register is always inverted when it is read. If this register is used as a hardware breakpoint, the value read from this register will be the inverse of the data actually in the register. 30.3. On-Chip Debugger Commands The host communicates to the On-Chip Debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are avail- able. In Debug Mode, all OCD commands become available unless the user code is pro- tected by programming the Flash Read Protect option bit (FRP). This FRP option bit prevents the code in memory from being read out of the F6482 Series device. When this option is enabled, several of the OCD commands are disabled. Caution:

those commands that are disabled by programming the Flash Read Protect option bit. Table 307. On-Chip Debugger Commands the on-chip RAM are disabled. the on-chip RAM are disabled. Note: Unlisted command by te values are reserved.

PS029413-0921 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F6482 Series Product Specification 571 In the following OCD Commands, data and commands sent from the host to the On-Chip Debugger are identified by DBG ← Command/Data. Data sent from the On-Chip Debug- ger back to the host is identified by DBG → Data. Read Revision (00h). The Read OCD Revision command determines the version of the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision number changes. DBG ← 00h DBG → REVID[15:8] (Major revision number) DBG → REVID[7:0] (Minor revision number) Write OCD Counter Register (01h). The Write OCD Counter Register command writes the data that follows to the OCDCNTR Register. If the device is not in Debug Mode, the data is discarded. DBG ← 01h DBG ← OCDCNTR[15:8] DBG ← OCDCNTR[7:0] Read OCD Status Register (02h). The Read OCD Status Register command reads the OCDSTAT Register. DBG ← 02h DBG → OCDSTAT[7:0] Read OCD Counter Register (03h). The OCD Counter Register can be used to count system clock cycles in between breakpoints, generate a BRK when it counts down to 0, or generate a BRK when its value matches the Program Counter. Because this register is really a downcounter, the returned value is inverted when this register is read; therefore, the returned result appears to be an upcounter. If the device is not in Debug Mode, this command returns FFFFh. DBG ← 03h DBG → ~OCDCNTR[15:8] DBG → ~OCDCNTR[7:0] Write OCD Control Register (04h). The Write OCD Control Register command writes the data that follows to the OCDCTL Register. DBG ← 04h DBG ← OCDCTL[7:0] Read OCD Control Register (05h). The Read OCD Control Register command reads the value of the OCDCTL Register. DBG ← 05h DBG → OCDCTL[7:0]

PS029413-0921 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F6482 Series Product Specification 572 Write Program Counter (06h). The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in Debug Mode or if the Read Protect Option bit is enabled, the Program Counter (PC) values are discarded. DBG ← 06h DBG ← ProgramCounter[15:8] DBG ← ProgramCounter[7:0] Read Program Counter (07h). The Read Program Counter command reads the value in the eZ8 CPU’s Program Counter (PC). If the device is not in Debug Mode or if the Read Protect option bit is enabled, this command returns FFFFh. DBG ← 07h DBG → ProgramCounter[15:8] DBG → ProgramCounter[7:0] Write Register (08h). The Write Register command writes data to the Register File. Data can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If the device is not in Debug Mode, the address and data values are discarded. If the Read Pro- tect option bit is enabled, then only writes to the on-chip peripheral registers are allowed and all other register write data values are discarded. DBG ← 08h DBG ← {0h,Register Address[11:8]} DBG ← Register Address[7:0] DBG ← Size[7:0] DBG ← 1–256 data bytes Read Register (09h). The Read Register command reads data from the Register File. Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to zero). If the device is not in Debug Mode, or if the Read Protect option bit is enabled and on-chip RAM is being read from, this command returns FFh for all of the data values. DBG ← 09h DBG ← {0h,Register Address[11:8] DBG ← Register Address[7:0] DBG ← Size[7:0] DBG → 1–256 data bytes Write Program Memory (0Ah). The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). The on-chip Flash Controller must be written and unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in Debug Mode, or if the Read Protect option bit is enabled, the data is discarded. DBG ← 0Ah DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0]

PS029413-0921 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F6482 Series Product Specification 573 DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1–65536 data bytes Read Program Memory (0Bh). The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in Debug Mode or if the Read Protect option bit is enabled, this command returns FFh for the data. DBG ← 0Bh DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1–65536 data bytes Write Data Memory (0Ch). The Write Data Memory command writes data to Data Mem- ory. This command is equivalent to the LDE and LDEI instructions. Data is written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not in Debug Mode, or if the Read Protect option bit is enabled, the data is discarded. DBG ← 0Ch DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1–65536 data bytes Read Data Memory (0Dh). The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in Debug Mode, this command returns FFh for the data. DBG ← 0Dh DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1–65536 data bytes Read Program Memory CRC (0Eh). The Read Program Memory CRC command com- putes and returns the cyclic redundancy check (CRC) of Program Memory using the 16-bit CRC-CCITT polynomial (x16 + x12 + x5 + 1). The CRC is preset to all ones. The least-sig- nificant bit of the data is shifted through the polynomial first. The CRC is inverted when it is transmitted. If the device is not in Debug Mode, this command returns FFFFh for the CRC value. Unlike most other OCD Read commands, there is a delay from the issuance of the command until the OCD returns the data. The OCD reads the Program Memory, calcu-

PS029413-0921 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F6482 Series Product Specification 574 lates the CRC value, and returns the result. The delay is a function of the Program Mem- ory size and is approximately equal to the system clock period multiplied by the number of bytes in Program Memory. DBG ← 0Eh DBG → CRC[15:8] DBG → CRC[7:0] Step Instruction (10h). The Step Instruction command steps one assembly instruction at the current Program Counter (PC) location. If the device is not in Debug Mode, or if the Read Protect Option bit is enabled, the OCD ignores this command. DBG ← 10h Stuff Instruction (11h). The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0–4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions wherein the first byte of the instruction has been overwritten by a breakpoint. If the device is not in Debug Mode, or if the Read Protect option bit is enabled, the OCD ignores this command. DBG ← 11h DBG ← op code[7:0] Execute Instruction (12h). The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over breakpoints. The number of bytes to send for the instruction depends on the op code. If the device is not in Debug Mode, or if the Read Protect option bit is enabled, the OCD ignores this com- mand. DBG ← 12h DBG ← 1–5 byte op code Write Line Control Register (18h). The Write Line Control Register command writes the data that follows to the Line Control Register. DBG ← 18h DBG ← LCR[7:0] Read Line Control Register (19h). The Read Line Control Register command returns the current value in the Line Control Register. DBG ← 19h DBG → LCR[7:0] Read Baud Reload Register (1Bh). The Read Baud Reload Register command returns the current value in the Baud Reload Register. DBG ← 1Bh DBG → BAUD[15:8] DBG → BAUD[7:0]

This section defines the features of the following On-Chip Debugger control registers. can also reset the F6482 Series device. function is implemented by writing 40h to this register. Table 308. OCD Control Register (OCDCTL) 0: The device is running (operating in Normal Mode). 1: The device is in Debug Mode. instruction is decoded, the OCD takes action depending upon the BRKLOOP bit. 0: BRK instruction is disabled. 1: BRK instruction is enabled.

PS029413-0921 P R E L I M I N A R Y On-Chip Debugger Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 576 [5] DBGACK Debug Acknowledge This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends a Debug Acknowledge character (FFh) to the host when a breakpoint occurs. This bit automatically clears itself when an acknowledge character is sent. 0: Debug Acknowledge is disabled. 1: Debug Acknowledge is enabled. [4] BRKLOOP Breakpoint Loop This bit determines what action the OCD takes when a BRK instruction is decoded and breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically set to 1 and the OCD enters Debug Mode. If BRKLOOP is set to 1, the eZ8 CPU loops on the BRK instruction. 0: BRK instruction sets DBGMODE to 1. 1: eZ8 CPU loops on BRK instruction. [3] BRKPC Break when PC == OCDCNTR If this bit is set to 1, then the OCDCNTR Register is used as a hardware breakpoint. When the program counter matches the value in the OCDCNTR Register, DBGMODE is automatically set to 1. If this bit is set, the OCDCNTR Register does not count when the CPU is running. 0: OCDCNTR is setup as counter. 1: OCDCNTR generates hardware break when PC == OCDCNTR. [2] BRKZRO Break when OCDCNTR == 0000h If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCDCNTR Register counts down to 0000h. If this bit is set, the OCDCNTR Register is not reset when the part exits Debug Mode. 0: OCD does not generate BRK when OCDCNTR decrements to 0000h. 1: OCD sets DBGMODE to 1 when OCDCNTR decrements to 0000h. [1] Reserved This bit is reserved and must be programmed to 0. [0] RST Reset Setting this bit to 1 resets the device. The controller goes through a normal POR sequence with the exception that the On-Chip Debugger is not reset. This bit is automatically cleared to 0 when the reset finishes. 0: No effect. 1: Reset the device. Bit Description (Continued)

state of the debugger and the system. Table 309. OCD Status Register (OCDSTAT) is running or if it is idle. 1: The eZ8 CPU is either stopped or looping on a BRK instruction. 0: The device is not in Halt Mode. 1: The device is in Halt Mode. 0: The Read Protect option bit is disabled (Flash option bit is 1). These bits are reserved and must be programmed to 00000. Table 310. OCD Line Control Register (OCDLCR)

The Baud Reload Register contains the measured auto-baud value. This control bit sets the polarity of the ninth bit when nine bit mode is enabled. a remote start bit is enabled to detect valid characters. 0: Transmit Flow Control disabled. 1: Transmit Flow Control using Remote Start bit. 0: Pin is not driven High during 0 to 1 transitions. 1: Pin is driven High during 0 to 1 transitions. 0: Pin is only driven Low during transmission (Open-Drain). 1: Pin is always driven during transmission. 0: Pin output driver is low drive strength. 1: Pin output driver is high drive strength. Table 311. Baud Reload Register

PS029413-0921 P R E L I M I N A R Y On-Chip Debugger Control Register Definitions Z8 Encore! XP® F6482 Series Product Specification 579 Bit Description [15:12] Reserved These bits are reserved and must be set to 0000. [11:0] RELOAD Baud Reload Value This value is the measured Auto-Baud value. Its value can be calculated using the following formula: RELOAD = SYSCLK BAUDRATE x 8

ments. Each statement contains labels, operations, operands and comments. fies that step in the program as an entry point for use by other instructions. segment of an assembly language program is presented in Table 312. Table 312. Assembly Language Source Program Example JP START ; Everything after th e semicolon is a comment. ; program where the START label occurs.

mat if you prefer manual program coding or intend to implement your own assembler. 43h; the assembly syntax and resulting object code is as listed in Table 313. object code is as listed in Table 314. The register file size varies depending on the device type. LD 234h, #%01 ; Another Load (LD) instruction with two operands. Table 313. Assembly Language Syntax Example 1 Table 314. Assembly Language Syntax Example 2 Table 312. Assembly Language Source Program Example (Continued)

Table 315. Notational Shorthand

Summary section on page 588.

• Arithmetic
• Bit Manipulation
• Block Transfer
• CPU Control
• Load
• Logical
• Program Control
• Rotate and Shift

Table 316. Additional Symbols

because these instructions should be considered as a subset of more than one category. and the condition code is cc. Table 317. Arithmetic Instructions

Table 318. Bit Manipulation Instructions Table 319. Block Transfer Instructions Table 320. CPU Control Instructions

Table 321. Load Instructions Table 322. Logical Instructions Table 320. CPU Control Instructions (Continued)

Table 323. Program Control Instructions Table 324. Rotate and Shift Instructions

required for the instruction execution. Table 325. eZ8 CPU Instruction Summary

• = Value is a function of the result of the operation.

Table 325. eZ8 CPU Instruction Summary (Continued)

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

Table 326. Op Code Map Abbreviations

Figures 104 and 105 provide information about each of the eZ8 CPUinstructions. Figure 104. First Op Code Map

Figure 105. Second Op Code Map after 1Fh

trical characteristics can be found in the individual chapters of this document. Stresses greater than those listed in Table 327 can cause permanent damage to the device. improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS). Table 327. Absolute Maximum Ratings* Note: *Operating temperature is s pecified in the DC Characteristics section.

enced to VSS, which is the primary system ground. Table 328. DC Characteristics

1. These values are provided for design guidance only and are not tested in production.
2. This condition excludes all pins that have on-chip pull-ups, when driven Low.

**Table 327. Absolute Maximum Ratings* (Continued)** Note: *Operating temperature is s pecified in the DC Characteristics section.

all active peripheral currents plus the appropriate current characteristics shown below. Table 329. Supply Current Characteristics

20 MHz3,4,5

1. These values are provided for design guidance only and are not tested in production.
2. Typical conditions are defined as 3.0 V at 25° C, unless otherwise noted.
3. All internal pull ups are disabled and all push-pull outputs are unloaded.
4. All open-drain outputs are pulled up to VDD/AVDD and are at a High state.
5. System clock source is an external square wave clock signal driven through the CLKIN pin.
6. All inputs are at VDD/AVDD or VSS/AVSS as appropriate.

Table 328. DC Characteristics (Continued)

1. These values are provided for design guidance only and are not tested in production.
2. This condition excludes all pins that have on-chip pull-ups, when driven Low.

timing information assumes a standard load of 50 pF on all outputs. Table 330. AC Characteristics Table 329. Supply Current Characteristics (Continued)

1. These values are provided for design guidance only and are not tested in production.
2. Typical conditions are defined as 3.0 V at 25° C, unless otherwise noted.
3. All internal pull ups are disabled and all push-pull outputs are unloaded.
4. All open-drain outputs are pulled up to VDD/AVDD and are at a High state.
5. System clock source is an external square wave clock signal driven through the CLKIN pin.
6. All inputs are at VDD/AVDD or VSS/AVSS as appropriate.

Figure 106. Maximum System Clock Frequency vs. VDD Table 331. Power-On Reset Electrical Characteristics and Timing guidance only and are not tested in production.

Table 332. Voltage Brown-Out Electrical Characteristics and Timing guidance only and are not tested in production. Table 333. Stop-Mode Recovery (SMR) Timing

6 SYSCLKs

6 SYSCLKs FRECOV = 1

guidance only and are not tested in production.

Table 334. Flash Memory Electrical Characteristics and Timing Table 335. Watchdog Timer Electrical Characteristics and Timing guidance only and are not tested in production.

Table 336. Non-Volatile Data Storage Electrical Characteristics and Timing Table 337. Analog-to-Digital Converter Electrical Characteristics and Timing

14 Bit RESOLUT = 1 (2-pass 14-

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design

guidance only and are not tested in production.

1. TS is applied twice if INMODE = 10 and RESOLUT = 1.
2. TSS is applied twice if RESOLUT = 1.

Table 337. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design

guidance only and are not tested in production.

1. TS is applied twice if INMODE = 10 and RESOLUT = 1.
2. TSS is applied twice if RESOLUT = 1.

1.25 AV DD V REFSEL = 01,

1.25 AV DD–0

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design

guidance only and are not tested in production.

1. TS is applied twice if INMODE = 10 and RESOLUT = 1.
2. TSS is applied twice if RESOLUT = 1.

5 MHz 12-bit (RESOLUT = 0);

2 MHz 14-bit (RESOLUT = 1);

1 MHz 12-bit (RESOLUT = 0);

0.8 MHz 14-bit (RESOLUT = 1);

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design

guidance only and are not tested in production.

1. TS is applied twice if INMODE = 10 and RESOLUT = 1.
2. TSS is applied twice if RESOLUT = 1.

Table 338. Digital-to-Analog Converter Electrical Characteristics and Timing guidance only and are not tested in production.

0.35 V/µs POWER = 10

Table 338. Digital-to-Analog Converter Electrical Characteristics and Timing (Continued) guidance only and are not tested in production.

Table 339 presents electrical and timing data for the F6482 Series’ Comparator function. Table 339. Comparator Electrical Characteristics

2 Input Hysteresis 0 mV HYST = 0x

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production.

1. Hysteresis is defined as overdrive of one input relative to the other to cause output transition, thus is half of the

Table 340 presents electrical and timing data for the F6482 Series’ Reference System. Table 340. Reference System Electrical Characteristics

2 Larger

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production.

1. VPREF is a user-set programmable reference voltage. See Tables 259 and 261 in the Comparators and Refer-

ence System chapter on page 486.

Table 341. Temperature Sensor Electrical Characteristics guidance only and are not tested in production. Table 340. Reference System Electrical Characteristics (Continued)

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production.

1. VPREF is a user-set programmable reference voltage. See Tables 259 and 261 in the Comparators and Refer-

ence System chapter on page 486.

Table 342. Operational Amplifier Electrical Characteristics guidance only and are not tested in production.

Table 342. Operational Amplifier Electrical Characteristics (Continued) guidance only and are not tested in production.

Table 343. Low Voltage Detect Electrical Characteristics

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production.

1. VTP is a user-set threshold voltage to be detected. See Table 294 on page 551 in the Flash Option Bits chapter

Table 344. LCD Electrical Characteristics

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production.

1. Based on PCLK= 32.768 kHz (CKSEL = 0), 32 Hz frame rate (PRESCALE = 011, FDIV = 0111), and LCD mode of 1/

(VLCDDIR = 0, CPEN = 0). No LCD panel load.

2.5 V V

Table 344. LCD Electrical Characteristics (Continued)

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production.

1. Based on PCLK= 32.768 kHz (CKSEL = 0), 32 Hz frame rate (PRESCALE = 011, FDIV = 0111), and LCD mode of 1/

(VLCDDIR = 0, CPEN = 0). No LCD panel load.

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production.

1. Based on PCLK= 32.768 kHz (CKSEL = 0), 32 Hz frame rate (PRESCALE = 011, FDIV = 0111), and LCD mode of 1/

(VLCDDIR = 0, CPEN = 0). No LCD panel load.

Table 345. USB Electrical Characteristics RPUUSB Internal Pull-up Resistor 900 1575 Ω Idle bus state. guidance only, and are not tested in production. Table 346. IPO Electrical Characteristics guidance only and are not tested in production.

Table 347. High Frequency Crystal Oscillator (HFXO) Characteristics

1. Data in the Typical column is from characterization at 3.0 V and 25° C. These values are provided for design guid-

ance only and are not tested in production. Table 346. IPO Electrical Characteristics (Continued) guidance only and are not tested in production.

Table 348. Low Frequency Oscillator (LFXO) Characteristics guidance only and are not tested in production. Table 349. PLL Electrical Characteristics guidance only and are not tested in production.

Oscillator (DCO) and Frequency-Locked Loop functions. Table 350. DCO and FLL Electrical Characteristics guidance only and are not tested in production.

Figure 107. Port Input Sample Timing Table 351. GPIO Port Input Timing

0 Latched

PS029413-0921 P R E L I M I N A R Y Packaging Z8 Encore! XP® F6482 Series Product Specification 632 Chapter 34. Packaging Zilog’s F6482 Series of MCUs includes the Z8Fxx82 and Z8Fxx81 devices. The Z8F6482, Z8F6082, Z8F3282 and Z8F1682 devices are available in the following packages:

• 64-pin Low-Profile Quad Flat Package, 10 mm x10 mm (LQFP)
• 80-pin Low-Profile Quad Flat Package (LQFP) The Z8F6481, Z8F6081, Z8F3281 and Z8F1681 are available in the following packages:
• 32-pin Quad Flat No Lead (QFN)
• 44-pin Quad Flat No Lead (QFN)
• 44-pin Low-Profile Quad Flat Package (LQFP)
• 64-pin Low-Profile Quad Flat Package, 10 mm x10 mm (LQFP) Current diagrams for each of these packages are published in Zilog’s Packaging Product Specification (PS0072), which is available free for download from the Zilog website.

Z8 Encore! XP® F6482 Series Product Specification 633 Chapter 35. Ordering Information 35.1. Part Number Listing Order your F6482 Series devices from Zilog using the part numbers listed in Table 356. For more information about ordering, please consult your local Zilog sales office. The Zilog website lists all regional offices and provides additional Z8 Encore! XP product information. Table 356. F6482 Series Ordering Information

Description

Z8 Encore! XP F6482 Series with 6 4KB Flash, 12-Bit Analog-to-Digital Converter Extended Temperature: –40 °C to 85 °C Z 8 F 6 4 8 2 A T 0 2 4 X K 6 4 K B3 . 7 5 K B 10121 6 7 4 1 3 1 2 22211 L Q F P 8 0 - p i n package Z 8 F 6 4 8 2 A R 0 2 4 X K 6 4 K B3 . 7 5 K B 10120 5 1 3 0 3811110 L Q F P 6 4 - p i n package Z 8 F 6 4 8 1 A R 0 2 4 X K 6 4 K B3 . 7 5 K B 00121 5 2 4 0 3 1 2 22211 L Q F P 6 4 - p i n package Z 8 F 6 4 8 1 Q N 0 2 4 X K 6 4 K B3 . 7 5 K B 00111 3 6 3 9 3 1 0 22211 Q F N 4 4 - p i n package Z 8 F 6 4 8 1 A N 0 2 4 X K 6 4 K B3 . 7 5 K B 00111 3 6 3 9 3 1 0 22211 L Q F P 4 4 - p i n package Z 8 F 6 4 8 1 Q K 0 2 4 X K 6 4 K B3 . 7 5 K B 00111 2 6 3 1 3911110 Q F N 3 2 - p i n package

PS029413-0921 P R E L I M I N A R Y Part Number Listing Z8 Encore! XP® F6482 Series Product Specification 634 Z8 Encore! XP F6082 Series with 60 KB Flash, 12-Bit Analog-to-Digital Converter Extended Temperature: –40 °C to 85 °C Z 8 F 6 0 8 2 A T 0 2 4 X K 6 0 K B3 . 7 5 K B 11121 6 7 4 1 3 1 2 22211 L Q F P 8 0 - p i n package Z 8 F 6 0 8 2 A R 0 2 4 X K 6 0 K B3 . 7 5 K B 11120 5 1 3 0 3811110 L Q F P 6 4 - p i n package Z 8 F 6 0 8 1 A R 0 2 4 X K 6 0 K B3 . 7 5 K B 01121 5 2 4 0 3 1 2 22211 L Q F P 6 4 - p i n package Z 8 F 6 0 8 1 Q N 0 2 4 X K 6 0 K B3 . 7 5 K B 01111 3 6 3 9 3 1 0 22211 Q F N 4 4 - p i n package Z 8 F 6 0 8 1 A N 0 2 4 X K 6 0 K B3 . 7 5 K B 01111 3 6 3 9 3 1 0 22211 L Q F P 4 4 - p i n package Z 8 F 6 0 8 1 Q K 0 2 4 X K 6 0 K B3 . 7 5 K B 01111 2 6 3 1 3911110 Q F N 3 2 - p i n package Z8 Encore! XP F3282 Series with 32KB Flash, 12-Bit Analog-to-Digital Converter Extended Temperature: –40 °C to 85 °C Z 8 F 3 2 8 2 A T 0 2 4 X K 3 2 K B3 . 7 5 K B 11121 6 7 4 1 3 1 2 22211 L Q F P 8 0 - p i n package Z 8 F 3 2 8 2 A R 0 2 4 X K 3 2 K B3 . 7 5 K B 11120 5 1 3 0 3811110 L Q F P 6 4 - p i n package Z 8 F 3 2 8 1 A R 0 2 4 X K 3 2 K B3 . 7 5 K B 01121 5 2 4 0 3 1 2 22211 L Q F P 6 4 - p i n package Z 8 F 3 2 8 1 Q N 0 2 4 X K 3 2 K B3 . 7 5 K B 01111 3 6 3 9 3 1 0 22211 Q F N 4 4 - p i n package Z 8 F 3 2 8 1 A N 0 2 4 X K 3 2 K B3 . 7 5 K B 01111 3 6 3 9 3 1 0 22211 L Q F P 4 4 - p i n package Z 8 F 3 2 8 1 Q K 0 2 4 X K 3 2 K B3 . 7 5 K B 01111 2 6 3 1 3911110 Q F N 3 2 - p i n package

PS029413-0921 P R E L I M I N A R Y Part Number Listing Z8 Encore! XP® F6482 Series Product Specification 635 Z8 Encore! XP F1682 Series with 16 KB Flash, 12-Bit Analog-to-Digital Converter Extended Temperature: –40 °C to 85 °C Z 8 F 1 6 8 2 A T 0 2 4 X K 1 6 K B 2 K B 11121 6 7 4 1 3 1 2 22211 L Q F P 8 0 - p i n package Z 8 F 1 6 8 2 A R 0 2 4 X K 1 6 K B 2 K B 11120 5 1 3 0 3811110 L Q F P 6 4 - p i n package Z 8 F 1 6 8 1 A R 0 2 4 X K 1 6 K B 2 K B 01121 5 2 4 0 3 1 2 22211 L Q F P 6 4 - p i n package Z 8 F 1 6 8 1 Q N 0 2 4 X K 1 6 K B 2 K B 01111 3 6 3 9 3 1 0 22211 Q F N 4 4 - p i n package Z 8 F 1 6 8 1 A N 0 2 4 X K 1 6 K B 2 K B 01111 3 6 3 9 3 1 0 22211 L Q F P 4 4 - p i n package Z 8 F 1 6 8 1 Q K 0 2 4 X K 1 6 K B 2 K B 01111 2 6 3 1 3911110 Q F N 3 2 - p i n package Z8 Encore! XP F6482 Series Development Kit Z8F64820100ZCOG Z8 Encore! XP F6482 Series Development Kit ZUSBSC00100ZACG USB Smart Cable Accessory Kit ZUSBOPTSC01ZACG USB Opto-Isolat ed Smart Cable Accessory Kit ZENETSC0100ZACG Ethernet Smart Cable Accessory Kit

operate correctly. This version is identified by the 2247 suffix on the device part number. Please refer to UM0275 for more information about the Z8F6482 ZMOTION Library. Table 357. ZMOTION Library Series Ordering Information

PS029413-0921 P R E L I M I N A R Y Part Number Suffix Designations Z8 Encore! XP® F6482 Series Product Specification 637 35.2. Part Number Suffix Designations Zilog part numbers consist of a number of components, as indicated in the following example. Example. Part number Z8F6482AT024XK is an 8-bit, 24 MHz Flash microcontroller with

64 KB of Flash memory and containing an LCD peripheral in an 80-pin LQFP package,

operating within a –40°C to +85°C temperature range and built using lead-free solder. Z8 F 64 82 A T 024 X K Environmental Flow K = Green plastic packaging compound Temperature Range X = –40°C to +85°C Speed 024 = 24 MHz Pin Count* K = 32 N = 44 R = 64 T = 80 Package* A = LQFP Q = QFN Device Type 82 = Contains the LCD peripheral 81 = Does not contain the LCD peripheral Memory Size 64 = 64 KB Flash, 3.75 KB RAM, 0 B NVDS 60 = 60 KB Flash, 3.75 KB RAM, 128 B NVDS 32 = 32 KB Flash, 3.75 KB RAM, 128 B NVDS 16 = 16 KB Flash, 2 KB RAM, 128 B NVDS Memory Type F = Flash Device Family Z8 = Zilog 8-bit microcontroller Note: * See Table 358 for the co mbination of package and pin count.

delivery might be uncertain at times, because of start-up yield issues. Table 358. Package and Pin Count Description

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 639 Index Symbols @ 583 # 583 % 583 Numerics 10-bit ADC 5 A absolute maximum ratings 601 AC characteristics 604 acronyms and expansions 9 active state 243 ADC 584 12-bit resolution timing 447 2-pass 14-bit resolution timing 448 architecture 439 block diagram 440 calibration and compensation 451 channel scanning 444 continuous conversion 444 control 0 register 452 control 1 register 454 control 2 register 454 control register definitions 452 conversion averaging 445 conversion options 444 data format 442 data high register 460 data low register 460 electrical characteristics 608 electrical characteristics and timing 608 input modes 441 input select high register 455 input select low register 456 interrupts and DMA 451 offset calibration register 459 operation 440 power control 445 references 446 resolution 445 sample time register 461 single-shot 444 starting and stopping conversions 445 start-up, sampling, and settling 449 timing 447 window detection 450 window lower threshold high register 464 window lower threshold low register 465 window upper threshold high register 462 window upper threshold low register 463 ADC Channel Register 1 (ADCCTL) 520, 521, 522 ADC Data High Byte Register (ADCDH) 523, 524, 526 ADC Data Low Bit Register (ADCDL) 464, 465, 472, 527, 528 ADCX 584 ADD 584 add - extended addressing 584 add with carry 584 add with carry - extended addressing 584 additional symbols 583 Address Space 24 ADDX 584 Advanced Encryption Standard Accelerator – see AES 424 AES architecture 424 CBC mode description 430, 432 CBC mode encryption example 433 cipher block chaining (CBC) mode 432 cipher text 425 control register 437 data register 435 decrypt key derivation 434 ECB decryption example 429 ECB encryption example 429

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 640 electronic codebook (ECB) mode 427 hardware assist 424 initialization vector 429 initialization vector register 436 key register 436 OFB mode encryption example 431 operation 425 output feedback (OFB) mode 430 plain text 425 register definitions 434 Rijndael cipher encoding and decoding algo- rithm 424 software assist 424 status register 438 AES accelerator block diagram 425 AES ECB mode description 428 AES operation and DMA 427 alarm condition 211, 212, 229 alarm status 211 alternating between banks, LCD 505 amplifier 51, 476 programmable gain 474, 477 settling time 447, 448 analog signals 20 Analog-to-Digital Converter – see ADC 439 AND 586 ANDX 586 architecture ADC 439 AES 424 clock system 97 comparators and reference system 487 DAC 466 DMA controller 390 ESPI 281 event system 411 GPIO 56 I2C 306 interrupt controller 130 LCD controller 503 multi-channel timers 187 noise filter 255 OCD 560 op amps 474 timers 150 UART-LDD 231 USB 340 arithmetic instructions 584 autobaud state 242 B B 583 b 582 baud rate generator ESPI 294 interrupts, UART 253 UART 254 BCD 211, 213, 214, 217, 218, 219, 220, 221, 222, 223, 224, 225, 229 counting 228 BCD_EN 213, 214, 215, 216, 218, 219, 220, 221, 222, 223, 224, 225, 228 BCLR 585 binary number suffix 583 binary operation 211, 215, 216, 217, 219, 220, 221, 222, 223, 224, 225 binary-coded decimal operation – see BCD 211 BIT 585 bit 582 clear 585 manipulation instructions 585 set 585 set or clear 585 swap 585 test and jump 587 test and jump if non-zero 587 test and jump if zero 587 bit jump and test if non-zero 587 bit swap 587 blanking the LCD display 505 block diagram ADC 440 AES accelerator 425 comparators 487 DAC 467 DMA 391 ESPI 282

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 641 event system 412 F6482 series architecture 4 I2C 307 input path 172 interrupt controller 130 LCD controller 504 LCD voltage and bias generation 509 noise filter system 172, 255 OCD 560 Op Amp A 475 Op Amp B 476 PLL 112 real-time clock 210 reference system 488 timer 150 UART-LDD 231 USB 340 block transfer instructions 585 BRK 587 BSET 585 BSWAP 585, 587 BTJ 587 BTJNZ 587 BTJZ 587 byte read, NVDS 557 byte write, NVDS 556 C calendar mode operation mode = 0 226 mode = 1 227 calibration and compensation, ADC 451 temperature sensor 502 CALL procedure 587 capture mode 181, 182 capture/compare mode 181 CBC mode description, AES 430, 432 CBC mode encryption example, AES 433 cc 582 CCF 585 channel scanning ADC 444 cipher block chaining (CBC) mode, AES 432 clear 586 clear to send, UART 236 clock control 5 120 clock phase, SPI 285 clock selection 98 Clock System 96 clock system architecture 97 clock control 0 register 114 clock control 1 register 116 clock control 2 register 117 clock control 3 register 118 clock control 4 register 119 clock control 5 register 120 clock control 6 register 121 clock control 7 register 122 clock control 8 register 122 clock control 9 register 123 clock control A register 123 clock control B register 125 clock control C register 126 digitally controlled oscillator 108 failure detection and recovery 103 frequency locked loop 109 high-frequency crystal oscillator 104 IPO 107 low-frequency crystal oscillator 106 phase locked loop 112 register definitions 114 selection 98 watchdog timer oscillator 108 CLR 586 code interface, NVDS 556 COM 586 comparator 0 control 0 register 495 0 control 1 register 496 1 control 0 register 497 1 control 1 register 498 control register 494 electrical characteristics and timing 614 electrical characteristics, converter 614 comparators

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 642 operation 489 Comparators and Reference System 486 comparators and reference system architecture 487 control register definitions 493 comparators block diagram 487 compare - extended addressing 584 compare with carry 584 compare with carry - extended addressing 584 complement 586 complement carry flag 585 condition code 582 continuous conversion, ADC 444 control register AES 437 control register definitions, ESPI 295 control register definitions, UART 258 control register, I2C 331 control transfers, USB 345 conversion options, ADC 444 counter mode operation 214, 215, 216, 217, 221, 222, 223, 224 CP 584 CPC 584 CPCX 584 CPU and peripheral overview 5 CPU control instructions 585 CPX 584 current measurement operation 504 current sinking 474, 484 current sourcing 474, 484 Customer Feedback Form 659 D DA 582, 584 DAC 466 architecture 466 block diagram 467 control register 470 control register definitions register definitions DAC control 470 data high register 472 data low register 472 electrical characteristics 612 electrical characteristics and timing 612 interrupts and DMA 470 operation 467 power control 469 starting a conversion 468 voltage references 469 DALI clock requirements, UART 244 mode initialization, UART 245 mode operation, UART 245 protocol mode, UART 243 DALI clock requirements UART 244 DALI mode initialization UART 245 DALI mode operation UART 245 DALI protocol mode UART 243 DALI receive during Stop Mode, UART 247 DALI receive operation, UART 246 DALI transmit operation, UART 245 data program 26 data format, ADC 442 data memory 26 data register, ESPI 295 data register, I2C 329 data-handling procedure, UART-LDD 252 DC characteristics 602 DCO 108 electrical characteristics 626 DEC 584 decimal adjust 584 decrement 584 decrement and jump non-zero 587 decrement word 584 decrypt key derivation, AES 434 DECW 584 destination operand 583 destination selection

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 643 event system 414 device, port availability 55 DI 585 digitally controlled oscillator 108 DCO operation 108 operating modes 108 Digital-to-Analog Converter 466 direct address 582 Direct Memory Access Controller 390 disable interrupts 585 DJNZ 587 DMA 0–3 subaddress/status registers 400 0–3 subdata registers 401 ADC interrupts 451 AES operation and 427 and DAC interrupts 470 and ESPI 294 block diagram 391 control register definitions 213, 399 control, I2C transactions 326 controller architecture 390 controller operation 391 destination address subregisters 404 global control register 402 multi-channel timer 192 source address subregisters 403 support, UART-LDD 254 transfer in list option 396 DMX clock requirements, UART 248 master mode operation, UART 249 mode initialization, UART 249 mode operation, UART 249 protocol mode, UART 247 slave during Stop Mode, UART 250 slave operation, UART 249 dst 583 E EI 585 electrical characteristics 601 absolute maximum ratings 601 AC 604 ADC 608 analog-to-digital converter 608 comparator 614 comparator converter 614 DAC 612 DC 602 digitally controlled oscillator and frequency- locked loop 626 digital-to-analog converter 612 Flash memory 607 GPIO input data sample timing 627 high frequency crystal oscillator 624 internal precision oscillator 623 liquid crystal display 620 low voltage detect 619 low-frequency crystal oscillator 625 non-volatile data atorage 608 NVDS 608 on-chip peripheral AC and DC 605 op amps 617 phase-locked loop oscillator 625 power-on reset 605 reference system 615 temperature sensor 616 universal serial bus 623 watchdog timer 607 electrical noise 440 electronic codebook (ECB) mode, AES 427 enable interrupt 585 endpoint buffer memory, USB 341 Enhanced Serial Peripheral Interface – see ESPI 281 ER 582 error-handling procedure, UART-LDD 252 ESPI and DMA 294 architecture 281 baud rate generator 294 baud rate high and low byte register 303 block diagram 282 clock phase 285 control register definitions 295 data register 295

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 644 error detection 292 interrupts 293 master operation 290 mode fault error 293 mode register 299 multi-master operation 291 operation 284 protocol configuration 289 receive overrun error 293 serial clock 283 signals 283 slave mode abort error 293 slave operation 291 slave select 283 slave select modes of operation 287 slave select, I2S mode 289 slave select, SPI Mode slave SPI mode select, ESPI 287 status register 301 throughput 285 transfer format 285, 286 transmit data command register 296 transmit underrun error 292 event system 411 architecture 411 block diagram 412 channel 0–7 source subregisters 420 destination 0–3F channel subregisters 423 destination selection 414 destination subaddress register 421 destination subdata register 422 register definitions 417 source selection 412 source subaddress register 418 source subdata register 419 timing considerations 415 usage examples 415 example AES decryption, ECB mode 429 AES encryption, CBC mode 433 AES encryption, ECB mode 429 AES encryption, OFB mode 431 event system usage 415 multi-channel timer application 193 extended addressing register 582 external driver enable, UART 236 external pin reset 43 eZ8 CPU assembly language programming 580 assembly language syntax 581 features 5 instruction classes 583 instruction notation 582 instruction set 580 instruction summary 588 F F6482 Series available packages 12 block diagram 4 features 1 overview 1 part selection guide 2 pin characteristics 22 pin configurations 12 signal descriptions 18 failure detection and recovery clock system 103 FBP register 540 features, F6482 Series 1 FiltSatB 172, 255, 256 first op code map 599 flags register 583 Flash controller 5 option bit address space 546 option bit configuration by reset 542 option bit control register definitions 544 option bit types 542 option bits, zilog device data 543 register definitions Flash option bit control 544 trim bit address space 548 trim option bits 543 user option bits 542

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 645 zilog option bits 543 Flash information area 26, 531 Flash memory 529 arrangement 530 block protection 534 byte programming 534 byte programming mode 535 code protection against accidental program and erasure 533 code protection against external access 533 code protection using the Flash controller 533 control register 537 control register definitions 537 controller behavior in debug mode 536 controller bypass 536 Flash block protect register 540 Flash programming configuration register 541 Flash status register 538 information area 531 mass erase 536 operation 531 page erase 535 page select register 539 programming 534 timing operation 533 word programming mode 535 Flash option bits 542 address space 546 configuration by reset 542 operation 542 trim 543 trim bit address 0003h 550 trim bit address 0004h 550 trim bit address 0005h 552 trim bit address 0006h 552 trim bit address 0007h 553 trim bit address 000Ah 554 trim bit address 000Bh 555 trim bit address 000Ch 555 trim bit address register 0000h 548 trim bit address space 548 trim bit addresses 0001h and 0002h 549 trim bit addresses 0008h and 0009h 553 trim bit data register 546 types 542 user 542 zilog 543 zilog device data 543 FLL 109 electrical characteristics 626 FPCONFIG register 541 FPS register 539 frequency locked loop 109 FLL operation 110 operating modes 109 FSTAT register 538 G gated mode 181 General-Purpose Input/Output 55 GPIO 5 alternate functions 56 architecture 56 external clock setup 57 high frequency crystal oscillator override 57 input data sample timing 627 interrupts 85 low-frequency crystal oscillator override 57 port A–C pull-up enable subregisters 91, 92 port A–H address registers 86 port A–H alternate function subregisters 88 port A–H control registers 87 port A–H data direction subregisters 87 port A–H high drive enable subregisters 89 port A–H input data registers 94 port A–H output control subregisters 88 port A–H output data registers 95 port A–H stop mode recovery subregisters 90 port availability by device 55 port input timing 627 port output timing 628 shared reset pin 57 H H 583 HALT 585

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 646 Halt Mode low-power modes 51 halt mode 585 hexadecimal number prefix/suffix 583 HFXO 57, 104 high frequency crystal oscillator electrical characteristics 624 high-frequency crystal oscillator 104 operating modes 105 operation 105 I I2C 5 10-bit address transaction 314 architecture 306 baud high and low byte registers 332, 334, 339 block diagram 307 control register 331 control register definitions 329 controller signals 18 data register 329 general call 320 interrupts 309 master address-only transactions 312 master arbitration 311 master read transaction, 10-bit address 317 master read transaction, 7-bit address 316 master read transaction, data DMA 327 master transaction diagrams 312 master transactions 311 master write transaction, 10-bit address 314 master write transaction, 7-bit address 313 master write transaction, data DMA 326 Master/Slave Controller 306 master/slave controller registers 307 multimaster/multislave system 311 operation 308 receive interrupts 309 SDA and SCL signals 308 single master/one or more slaves 311 slave address match interrupts 309 slave read transaction, data DMA 328 slave receive transaction, 10-bit address 322 slave receive transaction, 7-bit address 321 slave transaction diagrams 320 slave transactions 319 slave transmit transaction with 7-bit address 323 slave write transaction, data DMA 328 software address recognition 320 software control, transactions 311 start byte address recognition 320 stop and start conditions 311 transactions, DMA control of 326 transmit interrupts 309 IM 582 immediate data 582 immediate operand prefix 583 INC 584 increment 584 increment word 584 INCW 584 indexed 582 indirect address prefix 583 indirect register 582 indirect register pair 582 indirect working register 582 indirect working register pair 582 initialization vector register, AES 436 initialization vector, AES 429 input modes, ADC 441 input path block diagram 172 instruction classes, eZ8 CPU 583 instruction set eZ8 CPU 580 object code 580 pseudo-operations 580 source, destination 581 instructions ADC 584 ADCX 584 ADD 584 ADDX 584 AND 586 ANDX 586 arithmetic 584 BCLR 585

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 647 BIT 585 bit manipulation 585 block transfer 585 BRK 587 BSET 585 BSWAP 585, 587 BTJ 587 BTJNZ 587 BTJZ 587 CALL 587 CCF 585 CLR 586 COM 586 CP 584 CPC 584 CPCX 584 CPU control 585 CPX 584 DA 584 DEC 584 DECW 584 DI 585 DJNZ 587 EI 585 HALT 585 INC 584 INCW 584 IRET 587 JP 587 LD 586 LDC 586 LDCI 585, 586 LDE 586 LDEI 585 LDX 586 LEA 586 load 586 logical 586 MULT 584 NOP 585 OR 586 ORX 586 POP 586 POPX 586 program control 587 PUSH 586 PUSHX 586 RCF 585 RET 587 RL 587 RLC 587 rotate and shift 587 RR 587 RRC 587 SBC 584 SCF 585 SRA 587 SRL 587 SRP 585 stop 586 SUB 584 SUBX 584 SWAP 587 TCM 585 TCMX 585 TM 585 TMX 585 TRAP 587 watchdog timer refresh 586 XOR 586 XORX 586 internal precision oscillator – see IPO 107 interrupt control register 148 interrupt controller 127, 132 architecture 130 block diagram 130 interrupt assertion types 131 interrupt vectors and priority 131 operation 130 register definitions 132 software interrupt assertion 132 interrupt edge select register 145 interrupt request 0 register 132 interrupt request 1 register 134 interrupt request 2 register 135 interrupt request 3 register 136 interrupt return 587 interrupt vector listing 127

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 648 interrupts ADC and DMA 451 and DMA, DAC 470 ESPI 293 I2C 309 LCD controller 519 multi-channel timer 192 UART 250 IPO clock system 107 electrical characteristics 623 operation 107 IR 582 Ir 582 IRET 587 IRQ0 enable high and low bit registers 137 IRQ1 enable high and low bit registers 139, 140 IRQ2 enable high and low bit registers 142 IRR 582 Irr 582 J JP 587 jump, conditional, relative, and relative conditional 587 K key register, AES 436 L LCD alternating between banks 505 blanking the display 505 electrical characteristics 620 voltage doubler 509 voltage tripler 509 LCD controller 1/2 duty mode 512 1/3 duty mode 514 1/4 duty mode 517 architecture 503 bias generator selection 509 blinking and blanking 508 block diagram 504 clock register 522 contrast control 518 control 0 register 523 control 1 register 524 control 2 register 526 control 3 register 527 display memory 505 display memory bank A subregisters 528 display memory bank B subregisters 528 display memory banks A and B 505 display memory organization 506 frame timing 507 internal charge pump 509 interrupts 519 operation 504 outputs 510 register definitions 519 registers and siubregisters 505 static mode 511 Stop Mode operation 519 subaddress register 520 subdata register 521 using the LCD as a timer 508 VLCD and bias generator source selection 510 voltage and bias generation 509 waveform generation 510 writing the display memory 505 LCD voltage and bias generation block diagram 509 LD 586 LDC 586 LDCI 585, 586 LDE 586 LDEI 585, 586 LDX 586 LEA 586 LFXO 57, 106 LIN master mode operation, UART 241 LIN mode initialization, UART 240 LIN mode operation, UART 240 LIN protocol mode, UART 239

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 649 LIN slave operation 242 UART 242 LIN sleep mode, UART 241 LIN sleep state 242 LIN system clock requirements, UART 240 Liquid Crystal Display Controller 503 load 586 load constant 585 to/from program memory 586 with auto-increment addresses 586 load effective address 586 load external data 586 to/from data memory and auto-increment ad- dresses 585, 586 load instructions 586 load using extended addressing 586 logical AND 586 extended addressing 586 logical exclusive OR 586 extended addressing 586 logical instructions 586 logical OR 586 extended addressing 586 low voltage detect electrical characteristics 619 low-frequency crystal oscillator 106 electrical characteristics 625 operation 106 low-power modes 50 Halt Mode 51 peripheral-level power control 52 power control register definitions 52 Stop Mode 50 M master interrupt enable 130 master operation, ESPI 290 master-in, slave-out 283 master-out, slave-in 283 memory endpoint buffer, USB 341 program 24 message frames 239 MISO 283 mode capture 181, 182 capture/compare 181 gated 181 PWM 181, 182 module setup, USB 344 MOSI 283 MULT 584 multi-channel timer 187 address map 195 application examples 193 block diagram 188 capture operation 192 capture/compare channel operation 191 channel status 0–1 registers 202 channel-y control registers 203 channel-y high and low byte registers 205 clock prescaler 189 clock source 189 continuous compare operation 191 control 0 and 1 registers 199 control register definitions 195 count modulo mode 190 count up/down mode 190 counter 188 DMA 192 high and low byte registers 196 I/O 188 interrupt 192 interrupts and DMA 192 low-power modes 193 mode control 189 multiple timer intervals generation 194 one-shot compare operation 191 operation 188 operation in Halt Mode 193 operation in Stop Mode 193 power reduction during operation 193 PWM output operation 191 PWM programmable deadband generation 193 reload high and low byte registers 197 start 189 subaddress register 198

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 650 subregisters 0–2 199 multi-channel timers architecture 187 multichannel timers signals 20 multi-master operation, ESPI 291 multimaster/multislave I2C system 311 multiply 584 multiprocessor mode receive inputs, UART 238 UART 237 N network address 238, 275 noise filter architecture 255 system block diagram 172, 255 UART 255 noise, electrical 440 Non-Volatile Data Storage – see NVDS 556 NOP (no operation) 585 notation b 582 cc 582 DA 582 ER 582 IM 582 IR 582 Ir 582 IRR 582 Irr 582 p 582 R 582 r 582 RA 582 RR 582 rr 582 vector 582 X 582 NVDS byte read 557 byte write 556 code interface 556 electrical characteristics 608 and timing 608 operation 556 optimizing memory usage for execution speed 559 power failure protection 558 O object code, instruction set 580 OCD architecture 560 auto-baud detector/generator 564 automatic reset 567 baud reload register 578 block diagram 560 breakpoints 568 commands 569 control register 575 control register definitions 575 counter register 568 data format 564 DBG pin to RS-232 Interface 562 debug mode 563 debugger break 587 high-speed synchronous communication 565 interface 561, 562 line control register 577 operation 561 reset and go 575 reset and stop 575 serial errors 566 signals 21 status register 577 timing 629 transmit flow control 567 wire and 567 OCD commands execute instruction (12h) 574 read baud reload register (1Bh) 574 read data memory (0Dh) 573 read line control register (19h) 574 read OCD control register (05h) 571 read OCD counter register (03h) 571

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 651 read OCD status register (02h) 571 read program counter (07h) 572 read program memory (0Bh) 573 read program memory CRC (0Eh) 573 read register (09h) 572 read revision (00h) 571 step instruction (10h) 574 stuff instruction (11h) 574 write data memory (0Ch) 573 write line control register (18h) 574 write OCD control register (04h) 571 write OCD counter register (01h) 571 write program counter (06h) 572 write program memory (0Ah) 572 write register (08h) 572 OFB mode encryption example, AES 431 On-Chip Debugger – see OCD 560 Op Amp A 477 block diagram 475 Op Amp B 478 block diagram 476 op amps A Control 0 Register 480 A Control 1 Register 482 architecture 474 B Control 0 Register 483 B Control 1 Register 484 control register definitions 480 electrical characteristics 617 operation 476 op code maps 597 abbreviations 598 first 599 second after 1Fh 600 operation ADC 440 AES 425 comparators 489 current measurement 504 DAC 467 DMA controller 391 ESPI 284 Flash memory 531 Flash option bits 542 I2C 308 LCD controller 504 NVDS 556 OCD 561 op amps 476 reference system 491 temperature sensor 500 UART 256 USB 341 Operational Amplifiers – see op amps 474 OR 586 Ordering Information 633 ORX 586 oscillator signals 20 output feedback (OFB) mode, AES 430 overrun errors, UART-LDD 252 overview, USB registers and subregisters 341 P p 582 Packaging 632 part numbers suffix designations 636 part selection guide 2 PC 583 Phase Locked Loop – see PLL 112 pin characteristics 22 pin configurations 12 Pin Descriptions 12 PLL block diagram 112 electrical characteristics, oscillator 625 operation 112 polarity 582 POP 586 using extended addressing 586 POPX 586 port availability, device 55 port input timing (GPIO) 627 port output timing, GPIO 628 power control, DAC 469 power supply

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 652 signals 21 power-on reset (POR) 40 precharacterization 638 program control instructions 587 program counter 583 program memory 24 programmable gain 6, 474, 477, 480, 482 programming Flash memory 534 protocol configuration, ESPI 289 pseudo-operations, instruction set 580 PUSH 586 using extended addressing 586 PUSHX 586 PWM Mode 181, 182 R R 582 r 582 RA register address 582 RCF 585 real-time clock 210, 226 alarm 211 alarm control register 226 alarm day-of-the-week register 224, 226 alarm hours register 223 alarm minutes register 222 alarm seconds register 221 block diagram 210 calendar mode operation 211 control register 228 count register writing 212 counter mode operation 211 counts, synchronous reading of 212 day-of-the-month register 219 day-of-the-week register 216 enable 212 hours register 215 minutes register 214 month register 219 power-on reset 213, 214, 215, 216, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227 recommended operation 212 seconds register 213 source selection 211 timing register 227 year register 220 receive data register, UART-LDD 258 receiver interrupts, UART 251 receiving UART data-interrupt-driven method 235 receiving UART data-polled method 234 reference system block diagram 488 electrical characteristics and timing 615 operation 491 references, ADC 446 register 120, 582 ADC control 0 452 ADC control 1 454 ADC control 2 454 ADC data high 460 ADC data low 460 ADC input select high 455 ADC input select low 456 ADC offset calibration 459 ADC sample time 461 ADC window lower threshold high 464 ADC window lower threshold low 465 ADC window upper threshold high 462 ADC window upper threshold low 463 AES data 435 baud low and high byte, I2C 332, 334, 339 baud rate high and low byte, ESPI 303 clock control 0 114 clock control 1 116 clock control 2 117 clock control 3 118 clock control 4 119 clock control 6 121 clock control 7 122 clock control 8 122 clock control 9 123 clock control A 123 clock control B 125 clock control C 126 comparator 0 control 0 495

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 653 0 control 1 496 1 control 0 497 1 control 1 498 comparator control 494 comparators and reference system definitions 493 control, I2C 331 DAC control 470 DAC data high 472 DAC data low 472 data, ESPI 295 DMA 0–3 subaddress/status 400 DMA 0–3 subdata 401 DMA global control 402 event system, destination subaddress 421 event system, destination subdata 422 event system, source subaddress 418 event system, source subdata 419 Flash block protect 540 Flash control 537 Flash page select 539 Flash programming configuration 541 Flash status 538 I2C control definitions 329 I2C master/slave controller 307 interrupt request 0 132 interrupt request 1 134 interrupt request 2 135 interrupt request 3 136 LCD clock 522 LCD control 0 523 LCD control 1 524 LCD control 2 526 LCD control 3 527 LCD subaddress 520 LCD subdata 521 mode, ESPI 299 OCD baud reload 578 OCD control 575 OCD line control 577 OCD status 577 Op Amp A Control 0 480 Op Amp A Control 1 482 Op Amp B Control 0 483 Op Amp B Control 1 484 real-time clock timing 227 SPI data (SPIDATA) 481, 494, 495 status, ESPI 301 timer 0–2 noise filter control (TxNFC) 186 transmit data command, ESPI 296 trim bit data 546 USB 341 USB control 360 USB DMA 0–1 control 361 USB DMA data 362 USB interrupt control 363 USB subdata 359 watchdog timer reload high byte (WDTH) 209 watchdog timer reload low byte (WDTL) 209 register definitions 132 ADC control 452 AES 434 clock system 114 comparators and reference system 493 DMA control 213, 399 ESPI control 295 event system 417 Flash memory control 537 I2C control 329 LCD controller 519 multi-channel timer 195 OCD control 575 op amps 480 power control 52 reset 48 timer control 174 UART-LDD control 258 USB control 356 register file 24 register pair 582 register pointer 583 register, USB subaddress 357 registers ADC channel 1 520, 521, 522 ADC data high byte 523, 524, 526 ADC data low bit 464, 465, 472, 527, 528 reset carry flag 585

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 654 low-voltage detection 47 power-on reset 40 register definitions 48 stop-mode recovery 44 system 39 system reset 39 types 38 watchdog timer 43 reset and go, OCD 575 reset and stop, OCD 575 Reset, Stop-Mode Recovery and Low-Voltage De- tection 38 response 239, 243 RET 587 return 587 RL 587 RLC 587 rotate and shift instructions 587 rotate left 587 rotate left through carry 587 rotate right 587 rotate right through carry 587 RP 583 RR 582, 587 rr 582 RRC 587 RSTSTAT register voltage brown-out reset 42 S saturated state output 172, 255 saturated state, UART-LDD operation 256 SBC 584 SCF 585 SCK 283 SDA and SCL signals, I2C 308 second op code map after 1Fh 600 serial clock, ESPI 283 serial peripheral interface, enhanced – see ESPI 281 set carry flag 585 set register pointer 585 shift right arithmetic 587 shift right logical 587 signal descriptions 18 signals, ESPI 283 single master/one or more slave I2C system 311 single-shot, ADC 444 slave I2S mode select, ESPI 289 slave operation, ESPI 291 slave select 425 modes of operation, ESPI 287 slave select, ESPI 283 slave transactions, I2C 319 Sleep state 242 sleep state 241 software control, I2C transactions 311 software trap 587 source operand 583 source selection event system 412 source, destination – instruction set 581 SP 583 special modes, UART 237 SPI signals 283 SPI controller signals 19 SPIDATA register 481, 494, 495 SRA 587 src 583 SRL 587 SRP 585 SS 283 stack pointer 583 starting a conversion, DAC 468 status per event reset 49 status register AES 438 stop 586 Stop Mode 586 low-power modes 50 operation, LCD controller 519 stop-mode recovery 46, 47 stop-mode recovery characteristics and latency reset 39 SUB 584

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 655 subregister DMA destination address 404 DMA source address 403 event system, channel 0–7 source 420 event system, destination 0–3F channel 423 LCD display memory bank A 528 LCD display memory bank B 528 USB setup buffer byte 0–7 389 USB clock gate 367 USB control and status 380 USB endpoint 0 control and status 375 USB endpoint pairing 385 USB frame count 382 USB function address 384 USB IN 0–3 byte count 376 USB IN 1–3 control and status 377 USB IN endpoint 1–3 start address 366 USB IN endpoint valid 386 USB IN endpoints start address 365 USB IN endpoints stop address 388 USB IN interrupt enable 372 USB IN interrupt request 369 USB interrupt identification 368 USB OUT 0–3 byte count 378 USB OUT 1–3 control and status 379 USB OUT endpoint 1–3 start address 364 USB OUT endpoint valid 387 USB OUT interrupt enable 373 USB OUT interrupt request 370 USB protocol interrupt enable 374 USB protocol interrupt request 371 USB toggle control 381 subtract 584 extended addressing 584 with carry 584 SUBX 584 SWAP 587 swap nibbles 587 symbols, additional 583 system reset 39 reset 39 T TCM 585 TCMX 585 Temperature Sensor 500 temperature sensor calibration 502 electrical characteristics 616 operation 500 test complement under mask 585 test complement under mask - extended addressing 585 test under mask 585 test under mask - extended addressing 585 timer block diagram 150 timer input path and noise filter architecture 172 block diagram 172 operation 172 timers 149 architecture 150 capture mode 162, 181, 182 capture/compare mode 166, 181 compare mode 164 continuous mode 156 counter mode 157 gated mode 165, 181 operating modes 152 PWM Mode 159, 160, 181, 182 reading the timer count values 170 reload high and low byte registers 176 signals 19 timer control register definitions 174 timer input path and noise filter 171 timer interrupts and DMA 170 timer output signal operation 171 timers 0–2 control registers 179, 180, 184, 185 high and low byte registers 175, 177, 178 timing ADC 447 timing considerations event system 415 TM 585

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 656 TMX 585 transactions, I2C master 311 transfer in list DMA option 396 transmit data command register, ESPI 296 transmit data register, UART-LDD 258 transmitting UART data-interrupt-driven method 233 transmitting UART data-polled method 232 TRAP 587 TRMDR register 546 TxNFC register 186 U UART 5, 242 baud rate generator 254 baud rate generator interrupts 253 clear to send operation 236 control register definitions 258 DALI clock requirements 244 DALI mode initialization 245 DALI mode operation 245 DALI protocol mode 243 DALI receive during Stop Mode 247 DALI receive operation 246 DALI transmit operation 245 data format 232 DMX clock requirements 248 DMX master mode operation 249 DMX mode initialization 249 DMX mode operation 249 DMX protocol mode 247 DMX slave during Stop Mode 250 DMX slave operation 249 external driver enable operation 236 interrupts 250 LIN master mode operation 241 LIN mode initialization 240 LIN mode operation 240 LIN protocol mode 239 LIN sleep mode 241 LIN sleep state 242 LIN system clock requirements 240 multiprocessor mode 237 receive inputs 238 noise filter 255 operation 256 receiver interrupts 251 receiving data using interrupt-driven method 235 receiving data using the polled method 234 special modes 237 transmitting data using the interrupt-driven method 233 transmitting data using the polled method 232 UART controller signals 18 UART timing 630 UART-LDD 230 address compare register 275 architecture 231 baud rate high and low byte registers 276 control 0 register 267 control 1 registers 269 DALI control register 273 data-handling procedure 252 DMA support 254 DMX control register 274 error-handling procedure 252 LIN control register 272 mode select and status register 264 multiprocessor control register 269 noise filter control register 271 receive data register 258 status 0 registers 259 transmit data register 258 UART-LDD block diagram 231 UART-LDD overrun errors 252 unity gain 474, 475, 478 bandwidth 476, 482, 485 buffer 477 Universal Serial Bus 340 usage examples event system 415 USB architecture 340 bulk IN transfers 348 bulk OUT transfers 349

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 657 clock gate subregister 367 control and status subregister 380 control read 346 control register 360 control register definitions 356 control transfers using endpoint 0 345 control write 345 device-initiated resume 353 DMA 0–1 control registers 361 DMA data register 362 electrical characteristics 623 endpoint 0 control and status subregister 375 endpoint buffer memory 341 endpoint pairing 350 endpoint pairing subregister 385 frame count subregisters 382 frame number 352 function address 350 function address subregister 384 host-initiated resume 354 IN 0–3 byte count subregisters 376 IN 1–3 control and status subregister 377 IN endpoint 1–3 start address subregisters 366 IN endpoint valid subregister 386 IN endpoints start address subregister 365 IN endpoints stop address subregister 388 IN interrupt enable subregister 372 IN interrupt request subregister 369 interrupt control register 363 interrupt identification subregister 368 module setup 344 operation 341 OUT 0–3 byte count subregisters 378 OUT 1–3 control and status subregisters 379 OUT endpoint 1–3 start address subregisters 364 OUT endpoint valid subregister 387 OUT interrupt enable subregister 373 OUT interrupt request subregister 370 protocol interrupt enable subregister 374 protocol interrupt request subregister 371 registers and subregisters, overview 341 remote wake-up 353 reset bus state 352 setting valid endpoints 344 setup buffer 347 setup buffer byte 0–7 subregisters 389 SOF frame number 352 subaddress register 357 subdata register 359 suspend 353 suspend/resume 352 toggle control 351 toggle control subregister 381 transfer control 351 transfers using endpoints 1–3 348 USB – see Universal Serial Bus 340 USB block diagram 340 using a GPIO port pin transition reset 47 using a watchdog timer time-out reset 46 using an external RESET pin reset 47 using the comparator 46 using the LVD interrupt reset 46 using the RTC 46 using the timer 46 V vector 582 voltage brown-out reset 42 voltage doubler 509 voltage doubler, LCD 509 voltage references, DAC 469 voltage tripler, LCD 509 W watchdog timer 206 approximate time-out delay 206

electrical characteristics

interrupt, normal operation 207 interrupt, Stop Mode 207

Z8 Encore! XP® F6482 Series Product Specification PS029413-0921 P R E L I M I N A R Y Index 658 operation 206 refresh 586 reload unlock sequence 208 reload upper, high and low registers 208 reset 43 reset in normal operation 207 reset in Stop Mode 208 retrigger 207 time-out response 207 timer register definitions 208 watchdog timer oscillator 108 WDTH register 209 WDTL register 209 window detection, ADC 450 working register 582 working register pair 582 WTO 108 X X 582 XOR 586 XORX 586

PS029413-0921 P R E L I M I N A R Y Customer Support Z8 Encore! XP® F6482 Series Product Specification 659 Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other fac- ets about Zilog product offerings, please visit the Zilog Knowledge Base at http:// zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com.