Z8F1621PM020EC

Z8F6421PM020SC ZILOG | Alldatasheet

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High Performance 8-Bit Microcontrollers Z8 Encore!® 64K Series ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 PS019915-1005

This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters

532 Race Street

San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

Z8 Encore!® 64K Series Product Specification iii

Revision History

Each instance in Table 1 reflects a change to this document from its previous revi- sion. To see more detail, click the appropriate link in the table. Table 1. Revision History of this Document

Description

Page # January 2005 Added Die Form Sales information to Table 1. March 2005 Provided timing equation when the Baud Rate Generator for a peripheral is used as a simple timer. Closes CR#5618. 109, 115, 131, 137, 155 August 2005 Updated “Manual Objectives” on page xviii, “Introduction” on page 1, “Available Packages” on page 6, “Program Memory” on page 18, “Flash Memory” on page 178, “Option Bits” on page 190, “On-Chip Debugger Commands” on page 198, “Absolute Maximum Ratings” on page 209, “DC Characteristics” on page 211, Figure 48 on page 218, “On-Chip Peripheral AC and DC Electrical Characteristics” on page 219, “AC Characteristics” on page 224, “Ordering Information” on page 262, and “Part Number Suffix Designations” on page 267. Removed “Preliminary” from all pages. Deleted first sentence of “Electrical Characteristics” chapter. Deleted “Precharacterization Product” section in the “Packaging” chapter. Added automotive/industrial parts; removed all ROM references. October 2005 The paragraph tag for “Ordering Information” has been changed from H1 Heading to Chapter Title. 262

Z8 Encore!® 64K Series Product Specification iv Table of Contents

Z8 Encore!® 64K Series Product Specification v

Z8 Encore!® 64K Series Product Specification vi

Z8 Encore!® 64K Series Product Specification vii

Z8 Encore!® 64K Series Product Specification viii

Z8 Encore!® 64K Series Product Specification ix

Z8 Encore!® 64K Series Product Specification x

Z8 Encore!® 64K Series Product Specification xiv List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33.

Z8 Encore!® 64K Series Product Specification xv Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . . 128 Table 64. Table 65. Table 66. Table 67. Table 68. Table 69.

Table 105. Recommended Crystal Oscillator Specifications (20MHz Operation) . . . 206

Table 108. Power-On Reset and Voltage Brown-Out Electrical

Z8 Encore!® 64K Series Product Specification PS019915-1005 Manual Objectives xviii Manual Objectives This Product Specification provides detailed operating information for the Flash devices within the Z8 Encore!® 64K Series Microcontroller (MCU) products. Within this docu- ment, the Z8F642x, Z8F482x, Z8F322x, Z8F242x, and Z8F162x devices are referred to collectively as the Z8 Encore!® 64K Series unless specifically stated otherwise. About This Manual ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that there are different styles of learning. Therefore, we have designed this Product Specification to be used either as a how to procedural manual or a reference guide to important data. Intended Audience This document is written for ZiLOG customers who are experienced at working with microcontrollers, integrated circuits, or printed circuit assemblies. Manual Conventions The following assumptions and conventions are adopted to provide clarity and ease of use: Courier Typeface Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the Courier typeface. Where the use of the font is not indicated, as in the Index, the name of the entity is pre- sented in upper case. Example: FLAGS[1] is smrf. Hexadecimal Values Hexadecimal values are designated by uppercase H suffix and appear in the Courier typeface. Example: R1 is set to F8H. Brackets The square brackets, [ ], indicate a register or bus.

Z8 Encore!® 64K Series Product Specification xix Example: for the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant bit, and R1[0] is the least significant bit. Braces The curly braces, { }, indicate a single register or bus created by concatenating some com- bination of smaller registers, buses, or individual bits. Example: the 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer (RP) and Working Register R1. 0H is the most significant nibble (4-bit value) of the 12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register. Parentheses The parentheses, ( ), indicate an indirect register address lookup. Example: (R1) is the memory location referenced by the address contained in the Working Register R1. Parentheses/Bracket Combinations The parentheses, ( ), indicate an indirect register address lookup and the square brackets, [ ], indicate a register or bus. Example: assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the contents of the memory location at address 1234h. Use of the Words Set, Reset and Clear The word set implies that a register bit or a condition contains a logical 1. The words reset or clear imply that a register bit or a condition contains a logical 0. When either of these terms is followed by a number, the word logical may not be included; however, it is implied. Notation for Bits and Similar Registers A field of bits within a register is designated as: Register[n:n]. Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address. Use of the Terms LSB, MSB, lsb, and msb In this document, the terms LSB and MSB, when appearing in upper case, mean least sig- nificant byte and most significant byte, respectively. The lowercase forms, lsb and msb, mean least significant bit and most significant bit, respectively. Use of Initial Uppercase Letters Initial uppercase letters designate settings and conditions in general text. Example 1: The receiver forces the SCL line to Low.

Z8 Encore!® 64K Series Product Specification xx Example 2: The Master can generate a Stop condition to abort the transfer. Use of All Uppercase Letters The use of all uppercase letters designates the names of states, modes, and commands. Example 1: The bus is considered BUSY after the Start condition. Example 2: A START command triggers the processing of the initialization sequence. Example 3: STOP mode Bit Numbering Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example, the 8 bits of a register are numbered from 0 to 7. Safeguards It is important that all users understand the following safety terms, which are defined here. Indicates a procedure or file may become corrupted if the user does not fol- low directions. Trademarks ZiLOG®, eZ8, Z8 Encore!®, and Z8® are trademarks of ZiLOG, Inc. in the U.S.A. and other countries. All other trademarks are the property of their respective corporations. Caution:

Z8 Encore!® 64K Series Product Specification PS019915-1005 Introduction Introduction The Z8 Encore!® MCU family of products are a line of ZiLOG microcontroller products based upon the 8-bit eZ8 CPU. The Z8 Encore!® 64K Series, hereafter referred to collec- tively as the Z8 Encore!® or the 64K Series adds Flash memory to ZiLOG’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward compat- ible with existing Z8® instructions. The rich peripheral set of the Z8 Encore!® makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors.

Features

20 MHz eZ8 CPU

Up to 64 KB Flash with in-circuit programming capability Up to 4 KB register RAM 12-channel, 10-bit analog-to-digital converter (ADC) Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control I2C Serial Peripheral Interface Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders Up to four 16-bit timers with capture, compare, and PWM capability Watch-Dog Timer (WDT) with internal RC oscillator 3-channel DMA Up to 60 I/O pins 24 interrupts with configurable priority On-Chip Debugger Voltage Brown-out Protection (VBO) Power-On Reset (POR)

Table 1. Z8 Encore!® 64K Series Part Selection Guide

Z8 Encore!® 64K Series Product Specification Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8® code Expanded internal Register File allows access of up to 4KB New instructions improve execution efficiency for code developed using higher-level programming languages, including C Pipelined instruction fetch and execution New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL New instructions support 12-bit linear addressing of the Register File Up to 10 MIPS operation C-Compiler friendly 2-9 clock cycles per instruction For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail- able for download at www.zilog.com. General Purpose I/O The 64K Series features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for gen- eral purpose I/O (GPIO). Each pin is individually programmable. All ports (except B and H) support 5V-tolerant inputs. Flash Controller The Flash Controller programs and erases the Flash memory. 10-Bit Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from up to 12 different analog input sources. UARTs Each UART is full-duplex and capable of handling asynchronous data transfers. The UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.

Z8 Encore!® 64K Series Product Specification I2C The inter-integrated circuit (I2C®) controller makes the Z8 Encore!® compatible with the I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL) line. Serial Peripheral Interface The serial peripheral interface (SPI) allows the Z8 Encore!® to exchange data between other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface. Timers Up to four 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and oper- ate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages. Interrupt Controller The 64K Series products support up to 24 interrupts. These interrupts consist of 12 inter- nal and 12 general-purpose I/O pins. The interrupts have 3 levels of programmable inter- rupt priority. Reset Controller The Z8 Encore!® can be reset using the RESET pin, power-on reset, Watch-Dog Timer (WDT), STOP mode exit, or Voltage Brown-Out (VBO) warning signal. On-Chip Debugger The Z8 Encore!® features an integrated On-Chip Debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing registers, programming the Flash, setting breakpoints and executing code. A single-pin interface provides communi- cation to the OCD. DMA Controller The 64K Series features three channels of DMA. Two of the channels are for register RAM to and from I/O operations. The third channel automatically controls the transfer of data from the ADC to the memory.

please refer to Packaging on page 257. Encore!® 64K Series product line. Table 2. Z8 Encore!® 64K Series Package Options

Figure 2. 64K Series in 40-Pin Dual Inline Package (PDIP) Note: Timer 3 is not supported.

Figure 3. 64K Series in 44-Pin Plastic Leaded Chip Carrier (PLCC)

Figure 4. 64K Series in 44-Pin Low-Profile Quad Flat Package (LQFP)

Figure 5. 64K Series in 64-Pin Low-Profile Quad Flat Package (LQFP)

Figure 6. 64K Series in 68-Pin Plastic Leaded Chip Carrier (PLCC)

Figure 7. 64K Series in 80-Pin Quad Flat Package (QFP)

Signal and Pin Descriptions Z8 Encore!® 64K Series Product Specification Signal Descriptions Table 3 describes the Z8 Encore! signals. Refer to the section Pin Configurations on page 7 to determine the signals available for the specific package styles. Table 3. Signal Descriptions General-Purpose I/O Ports A-H PA[7:0] I/O Port A[7:0]. These pins are used for general-purpose I/O and support 5V-tolerant inputs. PB[7:0] I/O Port B[7:0]. These pins are used for general-purpose I/O. PC[7:0] I/O Port C[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs PD[7:0] I/O Port D[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs PE[7:0] I/O Port E[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs. PF[7:0] I/O Port F[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs. PG[7:0] I/O Port G[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs. PH[3:0] I/O Port H[3:0]. These pins are used for general-purpose I/O. I2C Controller SCL O Serial Clock. This is the output clock for the I2C. This pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is configured for alternate function to enable the SCL function, this pin is open-drain. SDA I/O Serial Data. This open-drain pin transfers data between the I2C and a slave. This pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is configured for alternate function to enable the SDA function, this pin is open-drain. SPI Controller SS I/O Slave Select. This signal can be an output or an input. If the Z8 Encore!® 64K Series is the SPI master, this pin may be configured as the Slave Select output. If the Z8 Encore!® 64K Series is the SPI slave, this pin is the input slave select. It is multiplexed with a general-purpose I/O pin. SCK I/O SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! 64K® Series is the SPI master, this pin is an output. If the Z8 Encore!® 64K Series is the SPI slave, this pin is an input. It is multiplexed with a general-purpose I/O pin.

Signal and Pin Descriptions Z8 Encore!® 64K Series Product Specification MOSI I/O Master Out Slave In. This signal is the data output from the SPI master device and the data input to the SPI slave device. It is multiplexed with a general-purpose I/O pin. MISO I/O Master In Slave Out. This pin is the data input to the SPI master device and the data output from the SPI slave device. It is multiplexed with a general-purpose I/O pin. UART Controllers TXD0 / TXD1 O Transmit Data. These signals are the transmit outputs from the UARTs. The TXD signals are multiplexed with general-purpose I/O pins. RXD0 / RXD1 I Receive Data. These signals are the receiver inputs for the UARTs and IrDAs. The RXD signals are multiplexed with general-purpose I/O pins. CTS0 / CTS1 I Clear To Send. These signals are control inputs for the UARTs. The CTS signals are multiplexed with general-purpose I/O pins. DE0 / DE1 O Driver Enable. This signal allows automatic control of external RS-485 drivers. This signal is approximately the inverse of the TXE (Transmit Empty) bit in the UART Status 0 register. The DE signal may be used to ensure an external RS-485 driver is enabled when data is transmitted by the UART. Timers T0OUT / T1OUT/ T2OUT / T3OUT O Timer Output 0-3. These signals are output pins from the timers. The Timer Output signals are multiplexed with general-purpose I/O pins. T3OUT is not available in 44- pin package devices. T0IN / T1IN/ T2IN / T3IN I Timer Input 0-3. These signals are used as the capture, gating and counter inputs. The Timer Input signals are multiplexed with general-purpose I/O pins. T3IN is not available in 44-pin package devices. Analog ANA[11:0] I Analog Input. These signals are inputs to the analog-to-digital converter (ADC). The ADC analog inputs are multiplexed with general-purpose I/O pins. VREF I Analog-to-digital converter reference voltage input. The VREF pin must be left unconnected (or capacitively coupled to analog ground) if the internal voltage reference is selected as the ADC reference voltage. Oscillators XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. This signal is usable with external RC networks and an external clock driver. Table 3. Signal Descriptions (Continued)

Signal and Pin Descriptions Z8 Encore!® 64K Series Product Specification XOUT O External Crystal Output. This pin is the output of the crystal oscillator. A crystal can be connected between it and the XIN pin to form the oscillator. When the system clock is referred to in this manual, it refers to the frequency of the signal at this pin. This pin must be left unconnected when not using a crystal. RCOUT O RC Oscillator Output. This signal is the output of the RC oscillator. It is multiplexed with a general-purpose I/O pin. This signal must be left unconnected when not using a crystal. On-Chip Debugger DBG I/O Debug. This pin is the control and data input and output to and from the On-Chip Debugger. This pin is open-drain. For operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be supplied with power and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-drain and must have an external pull-up resistor to ensure proper operation. Reset RESET I RESET. Generates a Reset when asserted (driven Low). Power Supply VDD I Power Supply. AVDD I Analog Power Supply. VSS I Ground. AVSS I Analog Ground. Caution:

Table 4. Pin Characteristics of the 64K Series

Z8 Encore!® 64K Series Product Specification PS019915-1005 Address Space Address Space Overview The eZ8 CPU can access three distinct address spaces: The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral, and general-purpose I/O port control registers. The Program Memory contains addresses for all memory locations having executable code and/or data. The Data Memory contains addresses for all memory locations that hold data only. These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU User Manual available for download at www.zilog.com. Register File The Register File address space in the 64K Series is 4KB (4096 bytes). The Register File is composed of two sections—control registers and general-purpose registers. When instructions are executed, registers are read from when defined as sources and written to when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256-byte control register section are reserved (unavailable). Reading from an reserved Register File addresses returns an undefined value. Writing to reserved Register File addresses is not recom- mended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. The 64K Series provide 2KB to 4KB of on-chip RAM depending upon the device. Reading from Register File addresses outside the available RAM addresses (and not within the con- trol register address space) returns an undefined value. Writing to these Register File addresses produces no effect. Refer to the Part Selection Guide on page 2 to determine the amount of RAM available for the specific 64K Series device.

Table 5. Z8 Encore® 64K Series Program Memory Maps

• See Table 23 on page 63 for a list of the interrupt vectors.

Table 5. Z8 Encore® 64K Series Program Memory Maps (Continued)

• See Table 23 on page 63 for a list of the interrupt vectors.

Table 6. Z8 Encore!® 64K Series Information Area Map

devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports. Consider registers for unimplemented peripherals as Reserved. Table 7. 64K Series Register File Address Map

Table 7. 64K Series Register File Address Map (Continued)

Z8 Encore!® 64K Series Z8 Encore! Control Register Summary Timer 0 High Byte T0H (F00H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [15:8] Timer 0 Low Byte T0L (F01H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [7:0] Timer 0 Reload High Byte T0RH (F02H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [15:8] Timer 0 Reload Low Byte T0RL (HF03 - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [7:0] Timer 0 PWM High Byte T0PWMH (F04H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 PWM value [15:8] Timer 0 Control 0 T0CTL0 (F06H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 0 Input signal is GPIO pin 1 = Timer 0 Input signal is Timer 3 out Reserved Timer 0 Control 1 T0CTL1 (F07H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled Timer 1 High Byte T1H (F08H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [15:8] Timer 1 Low Byte T1L (F09H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [7:0] Timer 1 Reload High Byte T1RH (F0AH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [15:8] Timer 1 Reload Low Byte T1RL (F0BH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [7:0]

Z8 Encore!® 64K Series Z8 Encore! Timer 1 PWM High Byte T1PWMH (F0CH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [15:8] Timer 1 PWM Low Byte T1PWML (F0DH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [7:0] Timer 1 Control 0 T1CTL0 (F0EH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 1 Input signal is GPIO pin 1 = Timer 1 Input signal is Timer 0 out Reserved Timer 1 Control 1 T1CTL1 (F0FH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled Timer 2 High Byte T2H (F10H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 current count value [15:8] Timer 2 Low Byte T2L (F11H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 current count value [7:0] Timer 2 Reload High Byte T2RH (F12H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 reload value [15:8] Timer 2 Reload Low Byte T2RL (F13H- Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 reload value [7:0] Timer 2 PWM High Byte T2PWMH (F14H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 PWM value [15:8] Timer 2 PWM Low Byte T2PWML (F15H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 PWM value [7:0] Timer 2 Control 0 T2CTL0 (F16H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 2 Input signal is GPIO pin 1 = Timer 2 Input signal is Timer 1 out Reserved

Z8 Encore!® 64K Series Z8 Encore! Timer 2 Control 1 T2CTL1 (F17H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = CAPTURE/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled Timer 3 High Byte T3H (F18H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 current count value [15:8] Timer 3 Low Byte T3L (F19H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 current count value [7:0] Timer 3 Reload High Byte T3RH (F1AH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 reload value [15:8] Timer 3 Reload Low Byte T3RL (F1BH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 reload value [7:0] Timer 3 PWM High Byte T3PWMH (F1CH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 PWM value [15:8] Timer 3 PWM Low Byte T3PWML (F1DH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 PWM value [7:0] Timer 3 Control 0 T3CTL0 (F1EH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 3 Input signal is GPIO pin 1 = Timer 3 Input signal is Timer 2 out Reserved Timer 3 Control 1 T3CTL1 (F1FH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled

Z8 Encore!® 64K Series Z8 Encore! UART0 Transmit Data U0TXD (F40H - Write Only) D7 D6 D5 D4 D3 D2 D1 D0 UART0 transmitter data byte [7:0] UART0 Receive Data U0RXD (F40H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 UART0 receiver data byte [7:0] UART0 Status 0 U0STAT0 (F41H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data Register Empty 0 = Transmit Data Register is full 1 = Transmit Data register is empty Break Detect 0 = No break occurred 1 = A break occurred Framing Error 0 = No framing error occurred 1 = A framing occurred Overrun Error 0 = No overrun error occurred 1 = An overrun error occurred Parity Error 0 = No parity error occurred 1 = A parity error occurred Receive Data Available 0 = Receive Data Register is empty 1 = A byte is available in the Receive Data Register UART0 Control 0 U0CTL0 (F42H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Loop Back Enable 0 = Normal operation 1 = Transmit data is looped back to the receiver Stop Bit Select 0 = Transmitter sends 1 Stop bit 1 = Transmitter sends 2 Stop bits Send Break 0 = No break is sent 1 = Output of the transmitter is zero Parity Select 0 = Even parity 1 = Odd parity Parity Enable 0 = Parity is disabled 1 = Parity is enabled CTS Enable 0 = CTS signal has no effect on the transmitter 1 = UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 = Receiver disabled 1 = Receiver enabled Transmit Enable 0 = Transmitter disabled 1 = Transmitter enabled

Z8 Encore!® 64K Series Z8 Encore! UART0 Control 1 U0CTL1 (F43H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors generate interrupt requests 1 = Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 = DE signal is active High 1 = DE signal is active Low Multiprocessor Bit Transmit 0 = Send a 0 as the multiprocessor bit 1 = Send a 1 as the multiprocessor bit Multiprocessor Mode [0] See Multiprocessor Mode [1] below Multiprocessor (9-bit) Enable 0 = Multiprocessor mode is disabled 1 = Multiprocessor mode is enabled Multiprocessor Mode [1] with Multiprocess Mode bit 0: 00 = Interrupt on all received bytes 01 = Interrupt only on address bytes 10 = Interrupt on address match and following data 11 = Interrupt on data following an address match UART0 Status 1 U0STAT1 (F44H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Mulitprocessor Receive Returns value of last multiprocessor bit New Frame 0 = Current byte is not start of frame 1 = Current byte is start of new frame Reserved UART0 Address Compare U0ADDR (F45H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART0 Address Compare [7:0] UART0 Baud Rate Generator High Byte U0BRH (F46H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [15:8] UART0 Baud Rate Generator Low Byte U0BRL (F47H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [7:0] UART1 Transmit Data U1TXD (F48H - Write Only) D7 D6 D5 D4 D3 D2 D1 D0 UART1 transmitter data byte[7:0] UART1 Receive Data U1RXD (F48H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 UART receiver data byte [7:0]

Z8 Encore!® 64K Series Z8 Encore! UART1 Status 0 U1STAT0 (F49H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data Register Empty 0 = Transmit Data Register is full 1 = Transmit Data register is empty Break Detect 0 = No break occurred 1 = A break occurred Framing Error 0 = No framing error occurred 1 = A framing occurred Overrun Error 0 = No overrun error occurred 1 = An overrun error occurred Parity Error 0 = No parity error occurred 1 = A parity error occurred Receive Data Available 0 = Receive Data Register is empty 1 = A byte is available in the Receive Data Register UART1 Control 0 U1CTL0 (F4AH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Loop Back Enable 0 = Normal operation 1 = Transmit data is looped back to the receiver Stop Bit Select 0 = Transmitter sends 1 Stop bit 1 = Transmitter sends 2 Stop bits Send Break 0 = No break is sent 1 = Output of the transmitter is zero Parity Select 0 = Even parity 1 = Odd parity Parity Enable 0 = Parity is disabled 1 = Parity is enabled CTS Enable 0 = CTS signal has no effect on the transmitter 1 = UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 = Receiver disabled 1 = Receiver enabled Transmit Enable 0 = Transmitter disabled 1 = Transmitter enabled

Z8 Encore!® 64K Series Z8 Encore! UART1 Control 1 U0CTL1 (F4BH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors generate interrupt requests 1 = Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 = DE signal is active High 1 = DE signal is active Low Multiprocessor Bit Transmit 0 = Send a 0 as the multiprocessor bit 1 = Send a 1 as the multiprocessor bit Multiprocessor Mode [0] See Multiprocessor Mode [1] below Multiprocessor (9-bit) Enable 0 = Multiprocessor mode is disabled 1 = Multiprocessor mode is enabled Multiprocessor Mode [1] with Multiprocess Mode bit 0: 00 = Interrupt on all received bytes 01 = Interrupt only on address bytes 10 = Interrupt on address match and following data 11 = Interrupt on data following an address match UART1 Status 1 U0STAT1 (F4CH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Mulitprocessor Receive Returns value of last multiprocessor bit New Frame 0 = Current byte is not start of frame 1 = Current byte is start of new frame Reserved UART1 Address Compare U0ADDR (F4DH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART1 Address Compare [7:0] UART1 Baud Rate Generator High Byte U0BRH (F4EH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART1 Baud Rate divisor [15:8] UART1 Baud Rate Generator Low Byte U1BRL (F4FH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 UART1 Baud Rate divisor [7:0] I2C Data I2CDATA (F50H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C data [7:0] I2C Status I2CSTAT (F51H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 NACK Interrupt 0 = No action required to service NAK 1 = START/STOP not set after NAK Data Shift State 0 = Data is not being transferred 1 = Data is being transferred Transmit Address State 0 = Address is not being transferred 1 = Address is being transferred Read 0 = Write operation 1 = Read operation 10-Bit Address 0 = 7-bit address being transmitted 1 = 10-bit address being transmitted Acknowledge 0 = Acknowledge not transmitted/received 1 = For last byte, Acknowledge was transmitted/received Receive Data Register Full 0 = I2C has not received data 1 = Data register contains received data Transmit Data Register Empty 0 = Data register is full 1 = Data register is empty

Z8 Encore!® 64K Series Z8 Encore! I2C Control I2CCTL (F52H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C Signal Filter Enable 0 = Digital filtering disabled 1 = Low-pass digital filters enabled on SDA and SCL input signals Flush Data 0 = No effect 1 = Clears I2C Data register Send NAK 0 = Do not send NAK 1 = Send NAK after next byte received from slave Enable TDRE Interrupts 0 = Do not generate an interrupt when the I2C Data register is empty 1 = Generate an interrupt when the I2C Transmit Data register is empty Baud Rate Generator Interrupt Request 0 = Interrupts behave as set by I2C control 1 = BRG generates an interrupt when it counts down to zero Send Stop Condition 0 = Do not issue Stop condition after data transmission is complete 1 = Issue Stop condition after data transmission is complete Send Start Condition 0 = Do not send Start Condition 1 = Send Start Condition I2C Enable 0 = I2C is disabled 1 = I2C is enabled I2C Baud Rate Generator High Byte I2CBRH (F53H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [15:8] I2C Baud Rate Generator Low Byte I2CBRL (F54H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [7:0] SPI Data SPIDATA (F60H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Data [7:0] SPI Control SPICTL (F61H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Enable 0 = SPI disabled 1 = SPI enabled Master Mode Enabled 0 = SPI configured in Slave mode 1 = SPI configured in Master mode Wire-OR (open-drain) Mode Enabled 0 = SPI signals not configured for open-drain 1 = SPI signals (SCK, SS, MISO, and MOSI) configured for open-drain Clock Polarity 0 = SCK idles Low 1 = SPI idles High Phase Select Sets the phase relationship of the data to the clock. BRG Timer Interrupt Request 0 = BRG timer function is disabled 1 = BRG time-out interrupt is enabled Start an SPI Interrupt Request 0 = No effect 1 = Generate an SPI interrupt request Interrupt Request Enable 0 = SPI interrupt requests are disabled 1 = SPI interrupt requests are enabled

Z8 Encore!® 64K Series Z8 Encore! SPI Status SPISTAT (F62H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Slave Select 0 = If Slave, SS pin is asserted 1 = If Slave, SS pin is not asserted Transmit Status 0 = No data transmission in progress 1 = Data transmission now in progress Reserved Slave Mode Transaction Abort 0 = No slave mode transaction abort detected 1 = Slave mode transaction abort was detected Collision 0 = No multi-master collision detected 1 = Multi-master collision was detected Overrun 0 = No overrun error detected 1 = Overrun error was detected Interrupt Request 0 = No SPI interrupt request pending 1 = SPI interrupt request is pending SPI Mode SPIMODE (F63H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Slave Select Value If Master and SPIMODE[1] = 1: 0 = SS pin driven Low 1 = SS pin driven High Slave Select I/O 0 = SS pin configured as an input 1 = SS pin configured as an output (Master mode only) Number of Data Bits Per Character 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bit 110 = 6 bits 111 = 7 bits Diagnostic Mode Control 0 = Reading from SPIBRH, SPIBRL returns reload values 1 = Reading from SPIBRH, SPIBRL returns current BRG count value Reserved SPI Diagnostic State SPIDST (F64H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 SPI State Transmit Clock Enable 0 = Internal transmit clock enable signal is deasserted 1 = Internal transmit clock enable signal is asserted Shift Clock Enable 0 = Internal shift clock enable signal is deasserted 1 = Internal shift clock enable signal is asserted SPI Baud Rate Generator High Byte SPIBRH (F66H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [15:8] SPI Baud Rate Generator Low Byte SPIBRL (F67H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [7:0] ADC Control ADCCTL (F70H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Analog Input Select 0000 = ANA0 0001 = ANA1 0010 = ANA2 0011 = ANA3 0100 = ANA4 0101 = ANA5 0110 = ANA6 0111 = ANA7 1000 = ANA8 1001 = ANA9 1010 = ANA10 1011 = ANA11 11xx = Reserved Continuous Mode Select 0 = Single-shot conversion 1 = Continuous conversion External VREF select 0 = Internal voltage reference selected 1 = External voltage reference selected Reserved Conversion Enable 0 = Conversion is complete 1 = Begin conversion

Z8 Encore!® 64K Series Z8 Encore! ADC Data High Byte ADCD_H (F72H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 ADC Data [9:2] ADC Data Low Bits ADCD_L (F73H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Reserved ADC Data [1:0] DMA0 Control DMA0CTL (FB0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Received Data register contains valid data 101 = UART1 Received Data register contains valid data 110 = I2C receiver contains valid data 111 = Reserved Word Select 0 = DMA transfers 1 byte per request 1 = DMA transfers 2 bytes per request DMA0 Interrupt Enable 0 = DMA0 does not generate interrupts 1 = DMA0 generates an interrupt when End Address data is transferred DMA0 Data Transfer Direction 0 = Register File to peripheral registers 1 = Peripheral registers to Register File DMA0 Loop Enable 0 = DMA disables after End Address 1 = DMA reloads Start Address after End Address and continues to run DMA0 Enable 0 = DMA0 is disabled 1 = DMA0 is enabled DMA0 I/O Address DMA0IO (FB1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Peripheral Register Address Low byte of on-chip peripheral control registers on Register File page FH DMA0 Address High Nibble DMA0H (FB2H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Start Address [11:8] DMA0 End Address [11:8] DMA0 Start/Current Address Low Byte DMA0START (FB3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Start Address [7:0] DMA0 End Address Low Byte DMA0END (FB4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 End Address [7:0] DMA1 Control DMA1CTL (FB8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Transmit Data register is empty 101 = UART1 Transmit Data register is empty 110 = I2C Transmit Data register is empty 111 = Reserved Word Select 0 = DMA transfers 1 byte per request 1 = DMA transfers 2 bytes per request DMA1 Interrupt Enable 0 = DMA1 does not generate interrupts 1 = DMA1 generates an interrupt when End Address data is transferred DMA1 Data Transfer Direction 0 = Register File to peripheral registers 1 = Peripheral registers to Register File DMA1 Loop Enable 0 = DMA disables after End Address 1 = DMA reloads Start Address after End Address and continues to run DMA1 Enable 0 = DMA1 is disabled 1 = DMA1 is enabled

Z8 Encore!® 64K Series Z8 Encore! DMA1 I/O Address DMA1IO (FB9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Peripheral Register Address Low byte of on-chip peripheral control registers on Register File page FH DMA1 Address High Nibble DMA1H (FBAH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Start Address [11:8] DMA1 End Address [11:8] DMA1 Start/Current Address Low Byte DMA1START (FBBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Start Address [7:0] DMA1 End Address Low Byte DMA1END (FBCH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 DMA1 End Address [7:0] DMA_ADC Address DMAA_ADDR (FBDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved DMA_ADC Address DMA_ADC Control DMAACTL (FBEH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC Analog Input Number 0000 = Analog input 0 updated 0001 = Analog input 0-1 updated 0010 = Analog input 0-2 updated 0011 = Analog input 0-3 updated 0100 = Analog input 0-4 updated 0101 = Analog input 0-5 updated 0100 = Analog input 0-6 updated 0101 = Analog input 0-7 updated 1000 = Analog input 0-8 updated 1001 = Analog input 0-9 updated 1010 = Analog input 0-10 updated 1011 = Analog inputs 0-11 updated 11xx = Reserved Reserved Interrupt request enable 0 = DMA_ADC does not generate interrupt requests 1 = DMA_ADC generates interrupt requests after last analog input DMA_ADC Enable 0 = DMA_ADC is disabled 1 = DMA_ADC is enabled DMA Status DMAA_STAT (FBFH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Interrupt Request Indicator 0 = DMA0 is not the source of the IRQ 1 = DMA0 is the source of the IRQ DMA1 Interrupt Request Indicator 0 = DMA1 is not the source of the IRQ 1 = DMA1 is the source of the IRQ DMA_ADC Interrupt Request Indicator 0 = DMA_ADC is not the source of the IRQ 1 = DMA_ADC is the source of the IRQ Reserved Current ADC analog input Identifies the analog input the ADC is currently converting

Z8 Encore!® 64K Series Z8 Encore! Interrupt Request 0 IRQ0 (FC0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC Interrupt Request SPI Interrupt Request I2C Interrupt Request UART 0 Transmitter Interrupt Request UART 0 Receiver Interrupt Request Timer 0 Interrupt Request Timer 1 Interrupt Request Timer 2 Interrupt Request For all of the above peripherals: 0 = Peripheral IRQ is not pending 1 = Peripheral IRQ is awaiting service IRQ0 Enable High Bit IRQ0ENH (FC1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable High Bit I2C IRQ Enable High Bit UART 0 Transmitter IRQ Enable High UART 0 Receiver IRQ Enable High Bit Timer 0 IRQ Enable High Bit Timer 1 IRQ Enable High Bit Timer 2 IRQ Enable High Bit IRQ0 Enable Low Bit IRQ0ENL (FC2H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable Low Bit I2C IRQ Enable Low Bit UART 0 Transmitter IRQ Enable Low UART 0 Receiver IRQ Enable Low Bit Timer 0 IRQ Enable Low Bit Timer 1 IRQ Enable Low Bit Timer 2 IRQ Enable Low Bit Interrupt Request 1 IRQ1 (FC3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin Interrupt Request 0 = IRQ from corresponding pin [7:0] is not pending 1 = IRQ from corresponding pin [7:0] is awaiting service IRQ1 Enable High Bit IRQ1ENH (FC4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin IRQ Enable High Bit IRQ1 Enable Low Bit IRQ1ENL (FC5H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin IRQ Enable Low Bit

Z8 Encore!® 64K Series Z8 Encore! Interrupt Request 2 IRQ2 (FC6H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin Interrupt Request 0 = IRQ from corresponding pin [3:0] is not pending 1 = IRQ from corresponding pin [3:0] is awaiting service DMA Interrupt Request UART 1 Transmitter Interrupt Request UART 1 Receiver Interrupt Request Timer 3 Interrupt Request For all of the above peripherals: 0 = Peripheral IRQ is not pending 1 = Peripheral IRQ is awaiting service IRQ2 Enable High Bit IRQ2ENH (FC7H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable High Bit DMA IRQ Enable High Bit UART 1 Transmitter IRQ Enable High UART 1 Receiver IRQ Enable High Bit Timer 3 IRQ Enable High Bit IRQ2 Enable Low Bit IRQ2ENL (FC8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable Low Bit DMA IRQ Enable Low Bit UART 1 Transmitter IRQ Enable Low UART 1 Receiver IRQ Enable Low Bit Timer 3 IRQ Enable Low Bit Interrupt Edge Select IRQES (FCDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Interrupt Edge Select [7:0] 0 = Falling edge 1 = Rising edge Interrupt Port Select IRQPS (FCEH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Port Pin Select [7:0] 0 = Port A pin is the interrupt source 1 = Port D pin is the interrupt source Interrupt Control IRQCTL (FCFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reserved Interrupt Request Enable 0 = Interrupts are disabled 1 = Interrupts are enabled Port A Address PAADDR (FD0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port A Control PACTL (FD1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A Control[7:0] Provides Access to Port Sub-Registers Port A Input Data PAIN (FD2H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port A Input Data [7:0] Port A Output Data PAOUT (FD3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port A Output Data [7:0]

Z8 Encore!® 64K Series Z8 Encore! Port B Address PBADDR (FD4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port B Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port B Control PBCTL (FD5H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port B Control[7:0] Provides Access to Port Sub-Registers Port B Input Data PBIN (FD6H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port B Input Data [7:0] Port B Output Data PBOUT (FD7H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port B Output Data [7:0] Port C Address PCADDR (FD8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port C Control PCCTL (FD9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Control[7:0] Provides Access to Port Sub-Registers Port C Input Data PCIN (FDAH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port C Input Data [7:0] Port C Output Data PCOUT (FDBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port C Output Data [7:0] Port D Address PDADDR (FDCH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port D Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port D Control PDCTL (FDDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port D Control[7:0] Provides Access to Port Sub-Registers Port D Input Data PDIN (FDE H- Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port D Input Data [7:0] Port D Output Data PDOUT (FDFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port D Output Data [7:0]

Z8 Encore!® 64K Series Z8 Encore! Port E Address PEADDR (FE0H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port E Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port E Control PECTL (FE1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port E Control[7:0] Provides Access to Port Sub-Registers Port E Input Data PEIN (FE2H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port E Input Data [7:0] Port E Output Data PEOUT (FE3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port E Output Data [7:0] Port F Address PFADDR (FE4H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port F Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port F Control PFCTL (FE5H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port F Control[7:0] Provides Access to Port Sub-Registers Port F Input Data PFIN (FE6H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port F Input Data [7:0] Port F Output Data PFOUT (FE7H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port F Output Data [7:0] Port G Address PGADDR (FE8H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port G Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port G Control PGCTL (FE9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port G Control[7:0] Provides Access to Port Sub-Registers Port G Input Data PGIN (FEAH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port G Input Data [7:0] Port G Output Data PGOUT (FEBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port G Output Data [7:0]

Z8 Encore!® 64K Series Z8 Encore! Port H Address PHADDR (FECH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port H Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function Port H Control PHCTL (FEDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port H Control [3:0] Provides Access to Port Sub-Registers Reserved Port H Input Data PHIN (FEEH - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Port H Input Data [3:0] Reserved Port H Output Data PHOUT (FEFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Port H Output Data [3:0] Reserved Watch-Dog Timer Control WDTCTL (FF0H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 SM Configuration Indicator Reserved EXT 0 = Reset not generated by RESET pin 1 = Reset generated by RESET pin WDT 0 = WDT timeout has not occurred 1 = WDT timeout occurred STOP 0 = SMR has not occurred 1 = SMR has occurred POR 0 = POR has not occurred 1 = POR has occurred Watch-Dog Timer Reload Upper Byte WDTU (FF1H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [23:16] Watch-Dog Timer Reload Middle Byte WDTH (FF2 H- Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [15:8] Watch-Dog Timer Reload Low Byte WDTL (FF3H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [7:0] Flash Control FCTL (FF8H - Write Only) D7 D6 D5 D4 D3 D2 D1 D0 Flash Command 73H = First unlock command 8CH = Second unlock command 95H = Page erase command 63H = Mass erase command 5EH = Flash Sector Protect reg select

Z8 Encore!® 64K Series Z8 Encore! Flash Status FSTAT (FF8H - Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Flash Controller Status 00_0000 = Flash controller locked 00_0001 = First unlock received 00_0010 = Second unlock received 00_0011 = Flash controller unlocked 00_0100 = Flash Sector Protect register selected 00_1xxx = Programming in progress 01_0xxx = Page erase in progress 10_0xxx = Mass erase in progress Reserved Page Select FPS (FF9H - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Page Select [6:0] Identifies the Flash memory page for Page Erase operation. Information Area Enable 0 = Information Area access is disabled 1 = Information Area access is enabled Flash Sector Protect FPROT (FF9H - Read/Write to 1’s) D7 D6 D5 D4 D3 D2 D1 D0 Flash Sector Protect [7:0] 0 = Sector can be programmed or erased from user code 1 = Sector is protected and cannot be programmed or erased from user code Flash Frequency High Byte FFREQH (FFAH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [15:8] Flash Frequency Low Byte FFREQL (FFBH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [7:0] Flags FLAGS (FFC - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 F1 - User Flag 1 F2 - User Flag 2 H - Half Carry D - Decimal Adjust V - Overflow Flag S - Sign Flag Z - Zero Flag C - Carry Flag Register Pointer RP (FFDH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Working Register Page Address [11:8] Working Register Group Address [7:4] Stack Pointer High Byte SPH (FFEH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [15:8] Stack Pointer Low Byte SPL (FFFH - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [7:0]

Table 8. Reset and STOP Mode Recovery Characteristics and Latency

66 WDT Oscillator cycles + 16 System Clock cycles

of Reset, all GPIO pins are configured as inputs. peripherals remain idle through the 16 cycles of the system clock. Table 9. Reset Sources and Resulting Reset Type

The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode. chapter for information on configuring VBO_AO. Figure 9. Voltage Brown-Out Reset Operation trol register is set to signify that the reset was initiated by the Watch-Dog Timer.

reset. Following the system reset the POR bit in the WDT Control register is set. control registers, and general-purpose RAM. Table 10. STOP Mode Recovery Sources and Resulting Action

Reset and STOP Mode Recovery Z8 Encore!® 64K Series Product Specification STOP Mode Recovery Using Watch-Dog Timer Time-Out If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP Mode Recovery sequence. In the Watch-Dog Timer Control register, the WDT and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon time- out and the 64K Series devices are configured to respond to interrupts, the eZ8 CPU ser- vices the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery sequence. STOP Mode Recovery Using a GPIO Port Pin Transition HALT Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source. On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin value (from High to Low or from Low to High) initiates STOP Mode Recovery. The GPIO STOP Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in dura- tion. In the Watch-Dog Timer Control register, the STOP bit is set to 1. In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input Data registers record the Port transition only if the signal stays on the Port pin through the end of the STOP Mode Recovery delay. Thus, short pulses on the Port pin can initiate STOP Mode Recovery with- out being written to the Port Input Data register or without initiating an in- terrupt (if enabled for that pin). Caution:

Z8 Encore!® 64K Series Product Specification PS019915-1005 Low-Power Modes Low-Power Modes Overview The 64K Series products contain power-saving features. The highest level of power reduc- tion is provided by STOP mode. The next level of power reduction is provided by the HALT mode. STOP Mode Execution of the eZ8 CPU’s STOP instruction places the device into STOP mode. In STOP mode, the operating characteristics are: Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is driven Low. System clock is stopped eZ8 CPU is stopped Program counter (PC) stops incrementing The Watch-Dog Timer and its internal RC oscillator continue to operate, if enabled for operation during STOP mode. The Voltage Brown-Out protection circuit continues to operate, if enabled for operation in STOP mode using the associated Option Bit. All other on-chip peripherals are idle. To minimize current in STOP mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (VCC or GND), the Voltage Brown-Out protection must be disabled, and the Watch-Dog Timer must be disabled. The devices can be brought out of STOP mode using STOP Mode Recovery. For more information on STOP Mode Recovery refer to the Reset and STOP Mode Recovery chapter beginning on page 43. STOP Mode must not be used when driving the 64K Series devices with an external clock driver source. Caution:

Z8 Encore!® 64K Series Product Specification HALT Mode Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are: Primary crystal oscillator is enabled and continues to operate System clock is enabled and continues to operate eZ8 CPU is stopped Program counter (PC) stops incrementing Watch-Dog Timer’s internal RC oscillator continues to operate The Watch-Dog Timer continues to operate, if enabled All other on-chip peripherals continue to operate The eZ8 CPU can be brought out of HALT mode by any of the following operations: Interrupt Watch-Dog Timer time-out (interrupt or reset) Power-on reset Voltage-brown out reset External RESET pin assertion To minimize current in HALT mode, all GPIO pins which are configured as inputs must be driven to one of the supply rails (VCC or GND).

programmable. All ports (except B and H) support 5V-tolerant inputs. Table 11 lists the port pins available with each device and package type. Table 11. Port Availability by Device and Package Type

associated with each port pin. Table 12. Port Alternate Function Mapping

interrupts using the GPIO pins. Four registers for each Port provide access to GPIO control, input data, and output data. together to provide access to sub-registers for Port configuration and control. Table 12. Port Alternate Function Mapping (Continued)

vide access to all GPIO Port control (Table 14). Table 13. GPIO Port Registers and Sub-Registers Table 14. Port A-H GPIO Address Registers (PxADDR)

Port A–H Control register (Table 15). No function. Provides some protection against accidental Port reconfiguration. STOP Mode Recovery Source Enable. Table 15. Port A–H Control Registers (PxCTL)

ter by writing 01H to the Port A–H Address register (Table 16). tion overrides the Data Direction register setting. 0 = Output. Data in the Port A–H Output Data register is driven onto the port pin. ister. The output driver is tri-stated. Table 16. Port A-H Data Direction Sub-Registers Table 17. Port A-H Alternate Function Sub-Registers

register determines the direction of the pin. 0 = The drains are enabled for any output mode. 1 = The drain of the associated pin is disabled (open-drain mode). Table 18. Port A-H Output Control Sub-Registers

pins directly and, as a result, alternate functions are also affected. 0 = The Port pin is configured for standard output current drive. 1 = The Port pin is configured for high output current drive. through the Port A–H Control register by writing 05H to the Port A–H Address register. Table 19. Port A–H High Drive Enable Sub-Registers

pin during STOP mode do not initiate STOP Mode Recovery. this pin during STOP mode initiates STOP Mode Recovery. from the corresponding port pins. The Port A–H Input Data registers are Read-only. Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High). Table 20. Port A-H STOP Mode Recovery Source Enable Sub-Registers Table 21. Port A–H Input Data Registers (PxIN)

The Port A–H Output Data register (Table 22) writes output data to the pins. 0 = Drive a logical 0 (Low). ting the corresponding Port Output Control register bit to 1. Table 22. Port A-H Output Data Register (PxOUT)

Z8 Encore!® 64K Series Product Specification PS019915-1005 Interrupt Controller Interrupt Controller Overview The interrupt controller on the 64K Series products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt controller include the following: 24 unique interrupt vectors:

12 GPIO port pin interrupt sources

12 on-chip peripheral interrupt sources Flexible GPIO interrupts 8 selectable rising and falling edge GPIO interrupts 4 dual-edge interrupts 3 levels of individually programmable interrupt priority Watch-Dog Timer can be configured to generate an interrupt Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the CPU and the interrupting peripheral. When the service routine is com- pleted, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt control has no effect on operation. Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man- ual is available for download at www.zilog.com. Interrupt Vector Listing Table 23 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even Program Memory address and the least significant byte (LSB) at the following odd Program Memory address.

Table 23. Interrupt Vectors in Order of Priority

Table 23. Level 3 interrupts always have higher priority than Level 2 interrupts which, in execution of the first LDX command and the last LDX command are lost.

and the last LDX command are lost. enable individual interrupts, set interrupt priorities, and indicate interrupt requests. Table 24. Interrupt Request 0 Register (IRQ0)

Z8 Encore!® 64K Series Product Specification T2I—Timer 2 Interrupt Request 0 = No interrupt request is pending for Timer 2. 1 = An interrupt request from Timer 2 is awaiting service. T1I—Timer 1 Interrupt Request 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. T0I—Timer 0 Interrupt Request 0 = No interrupt request is pending for Timer 0. 1 = An interrupt request from Timer 0 is awaiting service. U0RXI—UART 0 Receiver Interrupt Request 0 = No interrupt request is pending for the UART 0 receiver. 1 = An interrupt request from the UART 0 receiver is awaiting service. U0TXI—UART 0 Transmitter Interrupt Request 0 = No interrupt request is pending for the UART 0 transmitter. 1 = An interrupt request from the UART 0 transmitter is awaiting service. I2CI— I2C Interrupt Request 0 = No interrupt request is pending for the I2C. 1 = An interrupt request from the I2C is awaiting service. SPII—SPI Interrupt Request 0 = No interrupt request is pending for the SPI. 1 = An interrupt request from the SPI is awaiting service. ADCI—ADC Interrupt Request 0 = No interrupt request is pending for the Analog-to-Digital Converter. 1 = An interrupt request from the Analog-to-Digital Converter is awaiting service. Interrupt Request 1 Register The Interrupt Request 1 (IRQ1) register (Table 25) stores interrupt requests for both vec- tored and polled interrupts. When a request is presented to the interrupt controller, the cor- responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending.

0 = No interrupt request is pending for GPIO Port A or Port D pin x. 1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service. D) is determined by the values in the Interrupt Port Select Register. register to determine if any interrupt requests are pending. 0 = No interrupt request is pending for Timer 3. 1 = An interrupt request from Timer 3 is awaiting service. Table 25. Interrupt Request 1 Register (IRQ1) Table 26. Interrupt Request 2 Register (IRQ2)

Z8 Encore!® 64K Series Product Specification U1RXI—UART 1 Receive Interrupt Request 0 = No interrupt request is pending for the UART1 receiver. 1 = An interrupt request from UART1 receiver is awaiting service. U1TXI—UART 1 Transmit Interrupt Request 0 = No interrupt request is pending for the UART 1 transmitter. 1 = An interrupt request from the UART 1 transmitter is awaiting service. DMAI—DMA Interrupt Request 0 = No interrupt request is pending for the DMA. 1 = An interrupt request from the DMA is awaiting service. PCxI—Port C Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. where x indicates the specific GPIO Port C pin number (0 through 3). IRQ0 Enable High and Low Bit Registers The IRQ0 Enable High and Low Bit registers (Tables 28 and 29) form a priority encoded enabling for interrupts in the Interrupt Request 0 register. Priority is generated by setting bits in each register. Table 27 describes the priority control for IRQ0. Table 27. IRQ0 Enable and Priority Encoding where x indicates the register bits from 0 through 7. Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)

Z8 Encore!® 64K Series Product Specification T2ENH—Timer 2 Interrupt Request Enable High Bit T1ENH—Timer 1 Interrupt Request Enable High Bit T0ENH—Timer 0 Interrupt Request Enable High Bit U0RENH—UART 0 Receive Interrupt Request Enable High Bit U0TENH—UART 0 Transmit Interrupt Request Enable High Bit I2CENH—I2C Interrupt Request Enable High Bit SPIENH—SPI Interrupt Request Enable High Bit ADCENH—ADC Interrupt Request Enable High Bit T2ENL—Timer 2 Interrupt Request Enable Low Bit T1ENL—Timer 1 Interrupt Request Enable Low Bit T0ENL—Timer 0 Interrupt Request Enable Low Bit U0RENL—UART 0 Receive Interrupt Request Enable Low Bit U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit I2CENL—I2C Interrupt Request Enable Low Bit SPIENL—SPI Interrupt Request Enable Low Bit ADCENL—ADC Interrupt Request Enable Low Bit IRQ1 Enable High and Low Bit Registers The IRQ1 Enable High and Low Bit registers (Tables 31 and 32) form a priority encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by setting bits in each register. Table 30 describes the priority control for IRQ1. Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL) Table 30. IRQ1 Enable and Priority Encoding where x indicates the register bits from 0 through 7.

Z8 Encore!® 64K Series Product Specification PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source. PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source. IRQ2 Enable High and Low Bit Registers The IRQ2 Enable High and Low Bit registers (Tables 34 and 35) form a priority encoded enabling for interrupts in the Interrupt Request 2 register. Priority is generated by setting bits in each register. Table 33 describes the priority control for IRQ2. Table 31. IRQ1 Enable High Bit Register (IRQ1ENH) Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL) Table 33. IRQ2 Enable and Priority Encoding where x indicates the register bits from 0 through 7.

Table 34. IRQ2 Enable High Bit Register (IRQ2ENH) Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)

the edge triggered interrupt. Shorter pulses may be captured but not guaranteed. 0 = An interrupt request is generated on the falling edge of the PAx/PDx input. 1 = An interrupt request is generated on the rising edge of the PAx/PDx input. rupts. The Interrupt Edge Select register controls the active interrupt edge. 0 = PAx is used for the interrupt for PAx/PDx interrupt request. 1 = PDx is used for the interrupt for PAx/PDx interrupt request. Table 36. Interrupt Edge Select Register (IRQES) Table 37. Interrupt Port Select Register (IRQPS)

instruction, eZ8 CPU acknowledgement of an interrupt request, or Reset. Table 38. Interrupt Control Register (IRQCTL)

Z8 Encore!® 64K Series Product Specification PS019915-1005 Timers Timers Overview The 64K Series products contain up to four 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) signals. The tim- ers’ features include: 16-bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input, clock gating, or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. Timer output pin Timer interrupt In addition to the timers described in this chapter, the Baud Rate Generators for any unused UART, SPI, or I2C peripherals may also be used to provide basic timing function- ality. Refer to the respective serial communication peripheral chapters for information on using the Baud Rate Generators as timers. Timer 3 is unavailable in the 44-pin package devices. Architecture Figure 12 illustrates the architecture of the timers.

Figure 12. Timer Block Diagram FFFFH, the timer rolls over to 0000H and continues counting.

Z8 Encore!® 64K Series Product Specification out, first set the TPOL bit in the Timer Control 1 Register to the start value before begin- ning ONE-SHOT mode. Then, after starting the timer, set TPOL to the opposite bit value. The steps for configuring a timer for ONE-SHOT mode and initiating the count are as fol- lows: Write to the Timer Control 1 register to: Disable the timer Configure the timer for ONE-SHOT mode Set the prescale value If using the Timer Output alternate function, set the initial output level (High or Low) Write to the Timer High and Low Byte registers to set the starting count value Write to the Timer Reload High and Low Byte registers to set the Reload value If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function Write to the Timer Control 1 register to enable the timer and initiate counting In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon timer Reload. The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows: Write to the Timer Control 1 register to: Disable the timer Configure the timer for CONTINUOUS mode Set the prescale value One-Shot Mode Time-Out Period (s) Reload Value Start Value Prescale System Clock Frequency (Hz)

Z8 Encore!® 64K Series Product Specification If using the Timer Output alternate function, set the initial output level (High or Low) Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H), affecting only the first pass in CONTINUOUS mode. After the first timer Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H. Write to the Timer Reload High and Low Byte registers to set the Reload value. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control 1 register to enable the timer and initiate counting. In CONTINUOUS mode, the system clock always provides the timer input. The timer period is given by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT mode equation must be used to determine the first time-out period. COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer Control 1 Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled. The input frequency of the Timer Input signal must not exceed one-fourth the system clock frequency. Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COUNTER mode and initiating the count are as fol- lows: Write to the Timer Control 1 register to: Disable the timer Configure the timer for COUNTER mode Continuous Mode Time-Out Period (s) Reload Value Prescale System Clock Frequency (Hz) Caution:

Z8 Encore!® 64K Series Product Specification Select either the rising edge or falling edge of the Timer Input signal for the count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function does not have to be enabled Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in COUNTER mode. After the first timer Reload in COUNTER mode, counting always begins at the reset value of 0001H. Generally, in COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. Write to the Timer Reload High and Low Byte registers to set the Reload value. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Input alternate function. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control 1 register to enable the timer. In COUNTER mode, the number of Timer Input transitions since the timer start is given by the following equation: PWM Mode In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16- bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control 1 register is set to 1, the Timer Output signal begins as a High (1) and then transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control 1 register is set to 0, the Timer Output signal begins as a Low (0) and then transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H. The steps for configuring a timer for PWM mode and initiating the PWM operation are as follows: Counter Mode Timer Input Transitions Current Count Value Start Value

Z8 Encore!® 64K Series Product Specification Write to the Timer Control 1 register to: Disable the timer Configure the timer for PWM mode Set the prescale value Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. Write to the PWM High and Low Byte registers to set the PWM value. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control 1 register to enable the timer and initiate counting. The PWM period is given by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the One-Shot mode equation must be used to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by: If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by: Capture Mode In CAPTURE mode, the current timer count value is recorded when the desired external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control 1 register determines if the Capture occurs on a rising edge or a falling edge of the PWM Period (s) Reload Value Prescale System Clock Frequency (Hz) PWM Output High Time Ratio (%) Reload Value PWM Value Reload Value 100 PWM Output High Time Ratio (%) PWM Value Reload Value 100

Z8 Encore!® 64K Series Product Specification Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt and continues counting. The steps for configuring a timer for CAPTURE mode and initiating the count are as fol- lows: Write to the Timer Control 1 register to: Disable the timer Configure the timer for CAPTURE mode. Set the prescale value. Set the Capture edge (rising or falling) for the Timer Input. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). Write to the Timer Reload High and Low Byte registers to set the Reload value. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, then the interrupt was generated by a Reload. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Input alternate function. Write to the Timer Control 1 register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: Compare Mode In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon Com- pare. Capture Elapsed Time (s) Capture Value Start Value Prescale System Clock Frequency (Hz)

Z8 Encore!® 64K Series Product Specification If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. The steps for configuring a timer for COMPARE mode and initiating the count are as fol- lows: Write to the Timer Control 1 register to: Disable the timer Configure the timer for COMPARE mode Set the prescale value Set the initial logic level (High or Low) for the Timer Output alternate function, if desired Write to the Timer High and Low Byte registers to set the starting count value. Write to the Timer Reload High and Low Byte registers to set the Compare value. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control 1 register to enable the timer and initiate counting. In COMPARE mode, the system clock always provides the timer input. The Compare time is given by the following equation: GATED Mode In GATED mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control 1 register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset. Compare Mode Time (s) Compare Value Start Value Prescale System Clock Frequency (Hz)

Z8 Encore!® 64K Series Product Specification The steps for configuring a timer for GATED mode and initiating the count are as follows: Write to the Timer Control 1 register to: Disable the timer Configure the timer for GATED mode Set the prescale value Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the reset value of 0001H. Write to the Timer Reload High and Low Byte registers to set the Reload value. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Input alternate function. Write to the Timer Control 1 register to enable the timer. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer Input transition. The desired transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control 1 Register. The timer input is the system clock. Every subsequent desired transition (after the first) of the Timer Input signal captures the current count value. The Capture value is written to the Timer PWM High and Low Byte Registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the count are as follows: Write to the Timer Control 1 register to: Disable the timer Configure the timer for CAPTURE/COMPARE mode Set the prescale value Set the Capture edge (rising or falling) for the Timer Input Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H).

Z8 Encore!® 64K Series Product Specification Write to the Timer Reload High and Low Byte registers to set the Compare value. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Input alternate function. Write to the Timer Control 1 register to enable the timer. Counting begins on the first appropriate transition of the Timer Input signal. No interrupt is generated by this first edge. In m/COMPARE mode, the elapsed time from timer start to Capture event can be calcu- lated using the following equation: Reading the Timer Count Values The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte reg- ister is read, the contents of the Timer Low Byte register are placed in a holding register. A subsequent read from the Timer Low Byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte register returns the actual value in the counter. Timer Output Signal Operation Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled every time the counter is reloaded. Timer Control Register Definitions Timers 0-2 are available in all packages. Timer 3 is only available in the 64-, 68-, and 80- pin packages. Timer 0-3 High and Low Byte Registers The Timer 0-3 High and Low Byte (TxH and TxL) registers (Tables 38 and 39) contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TMRL always returns this temporary register when the timers are enabled. When the timer is disabled, reads from the TMRL reads the register directly. Writing to the Timer High and Low Byte registers while the timer is enabled is not recom- mended. There are no temporary holding registers available for write operations, so simul- Capture Elapsed Time (s) Capture Value Start Value Prescale System Clock Frequency (Hz)

Byte) at the next clock edge. The counter continues counting from the new value. Timer 3 is unavailable in the 40- and 44-pin packages. These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value. Table 38. Timer 0-3 High Byte Register (TxH)

two byte form the 16-bit Compare value. Table 40. Timer 0-3 Reload High Byte Register (TxRH) Table 41. Timer 0-3 Reload Low Byte Register (TxRL)

the Capture values for the Capture and Capture/COMPARE modes. operating in Capture or Capture/COMPARE modes. Table 42. Timer 0-3 PWM High Byte Register (TxPWMH) Table 43. Timer 0-3 PWM Low Byte Register (TxPWML)

0 = Timer Input signal comes from the pin. 1 = For Timer 0, Input signal is connected to Timer 3 output. For Timer 1, Input signal is connected to Timer 0 output. For Timer 2, Input signal is connected to Timer 1 output. For Timer 3, Input signal is connected to Timer 2 output. value, and determine the timer operating mode. Operation of this bit is a function of the current operating mode of the timer. Table 44. Timer 0-3 Control 0 Register (TxCTL0) Table 45. Timer 0-3 Control 1 Register (TxCTL1)

Z8 Encore!® 64K Series Product Specification ONE-SHOT mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. PWM mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. CAPTURE mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. GATED mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal.

Z8 Encore!® 64K Series Product Specification When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, TxOUT will change to whatever state the TPOL bit is in. The tim- er does not need to be enabled for that to happen. Also, the Port data direc- tion sub register is not needed to be set to output on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT. PRES—Prescale value. The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the Timer is disabled. This insures proper clock division each time the Timer is restarted. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 TMODE—TIMER mode 000 = ONE-SHOT mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = CAPTURE/COMPARe mode Caution:

Z8 Encore!® 64K Series Product Specification PS019915-1005 Watch-Dog Timer Watch-Dog Timer Overview The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore!® into unsuitable operating states. The Watch-Dog Timer includes the following features: On-chip RC oscillator A selectable time-out response: WDT Time-out response: Reset or interrupt 24-bit programmable time-out value Operation The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the 64K Series devices when the WDT reaches its terminal count. The Watch-Dog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer has only two modes of operation—ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. An enable can be performed by executing the WDT instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the Watch-Dog Timer to operate all the time, even if a WDT instruction has not been executed. The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is given by the following equation: where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator frequency is 10kHz. The Watch-Dog Timer cannot be refreshed once it reaches 000002H. The WDT Reload Value must not be set to values below 000004H. Table 46 provides information on approximate time-out delays for the minimum and maximum WDT reload values. WDT Time-out Period (ms) WDT Reload Value

Z8 Encore!® 64K Series Product Specification Watch-Dog Timer Refresh When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog Timer Reload registers. The Watch-Dog Timer then counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload registers. Counting resumes following the reload operation. When the 64K Series devices are operating in Debug Mode (through the On-Chip Debug- ger), the Watch-Dog Timer is continuously refreshed to prevent spurious Watch-Dog Timer time-outs. Watch-Dog Timer Time-Out Response The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the Watch-Dog Timer generates either an interrupt or a Reset. The WDT_RES Option Bit determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits chap- ter for information regarding programming of the WDT_RES Option Bit. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Watch-Dog Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watch-Dog Timer counter rolls over to its maximum value of FFFFFH and continues counting. The Watch-Dog Timer counter is not automatically returned to its Reload Value. WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the 64K Series devices are in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP bit in the Watch- Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to Table 46. Watch-Dog Timer Approximate Time-Out Delays 400μs Minimum time-out delay FFFFFF 16,777,215 1677.5s Maximum time-out delay

Z8 Encore!® 64K Series Product Specification the Reset and STOP Mode Recovery chapter for more information on STOP Mode Recovery. If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. WDT Reset in Normal Operation If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the device into the Reset state. The WDT status bit in the Watch-Dog Timer Control register is set to 1. Refer to the Reset and STOP Mode Recovery chapter for more information on Reset. WDT Reset in STOP Mode If enabled in STOP mode and configured to generate a Reset when a time-out occurs and the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the STOP bit in the Watch-Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to the Reset and STOP Mode Recovery chapter for more information. Default operation is for the WDT and its RC oscillator to be enabled during STOP mode. WDT RC Disable in STOP Mode To minimize power consumption in STOP Mode, the WDT and its RC oscillator can be disabled in STOP mode. The following sequence configures the WDT to be disabled when the 64K Series devices enter STOP Mode following execution of a STOP instruction: Write 55H to the Watch-Dog Timer Control register (WDTCTL). Write AAH to the Watch-Dog Timer Control register (WDTCTL). Write 81H to the Watch-Dog Timer Control register (WDTCTL) to configure the WDT and its oscillator to be disabled during STOP Mode. Alternatively, write 00H to the Watch-Dog Timer Control register (WDTCTL) as the third step in this sequence to reconfigure the WDT and its oscillator to be enabled during STOP Mode. This sequence only affects WDT operation in STOP mode. Watch-Dog Timer Reload Unlock Sequence Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers. The follow sequence is required to unlock the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access.

Write 55H to the Watch-Dog Timer Control register (WDTCTL). Write AAH to the Watch-Dog Timer Control register (WDTCTL). Write the Watch-Dog Timer Reload Upper Byte register (WDTU). Write the Watch-Dog Timer Reload High Byte register (WDTH). Write the Watch-Dog Timer Reload Low Byte register (WDTL). locking mechanism prevents spurious writes to the Reload registers. Table 47. Watch-Dog Timer Control Register (WDTCTL)

Z8 Encore!® 64K Series Product Specification POR—Power-On Reset Indicator If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time- out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read. STOP—STOP Mode Recovery Indicator If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP mode. Reading this register also resets this bit. WDT—Watch-Dog Timer Time-Out Indicator If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. EXT—External Reset Indicator If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this register resets this bit. Reserved These bits are reserved and must be 0. SM—STOP Mode Configuration Indicator 0 = Watch-Dog Timer and its internal RC oscillator will continue to operate in STOP Mode. 1 = Watch-Dog Timer and its internal RC oscillator will be disabled in STOP Mode. Watch-Dog Timer Reload Upper, High and Low Byte Registers The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg- isters (Tables 48 through 50) form the 24-bit reload value that is loaded into the Watch- Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the desired Reload Value. Read- ing from these registers returns the current Watch-Dog Timer count value. Reset or STOP Mode Recovery Event POR STOP WDT EXT Power-On Reset Reset using RESET pin assertion Reset using Watch-Dog Timer time-out Reset using the On-Chip Debugger (OCDCTL[1] set to 1) Reset from STOP Mode using DBG Pin driven Low STOP Mode Recovery using GPIO pin transition STOP Mode Recovery using Watch-Dog Timer time-out

Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value. Middle byte, Bits[15:8], of the 24-bit WDT reload value. Table 48. Watch-Dog Timer Reload Upper Byte Register (WDTU) R/W* - Read returns the current WDT count value. Write sets the desired Reload Value. Table 49. Watch-Dog Timer Reload High Byte Register (WDTH) R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.

Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value. Table 50. Watch-Dog Timer Reload Low Byte Register (WDTL) R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.

Z8 Encore!® 64K Series Product Specification UART Overview The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communica- tion channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include: 8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking Option of one or two Stop bits Separate transmit and receive interrupts Framing, parity, overrun and break detection Separate transmit and receive enables 16-bit Baud Rate Generator (BRG) Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes Baud Rate Generator timer mode Driver Enable output for external bus transceivers Architecture The UART consists of three primary functional blocks: transmitter, receiver, and baud rate generator. The UART’s transmitter and receiver function independently, but employ the same baud rate and data format. Figure 13 illustrates the UART architecture.

begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits. out parity and with parity, respectively. Figure 13. UART Block Diagram

Z8 Encore!® 64K Series Product Specification 101 Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data. Write the UART Control 1 register to select the outgoing address bit. Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. If desired and MULTIPROCESSOR mode is enabled, make any changes to the MULTIPROCESSOR Bit Transmitter (MPBT) value. 10. To transmit additional bytes, return to Step 5. Transmitting Data using the Interrupt-Driven Method The UART transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow these steps to configure the UART for interrupt- driven data transmission: Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. Execute a DI instruction to disable interrupts. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the desired priority. If MULTIPROCESSOR mode is desired, write to the UART Control 1 register to enable MULTIPROCESSOR (9-bit) mode functions. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR mode Write to the UART Control 0 register to: Set the transmit enable bit (TEN) to enable the UART for data transmission Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity Set or clear the CTSE bit to enable or disable control from the remote receiver via the CTS pin

Z8 Encore!® 64K Series Product Specification 102 Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: Write the UART Control 1 register to select the outgoing address bit: Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data register to again become empty. Receiving Data using the Polled Method Follow these steps to configure the UART for polled data reception: Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. Write to the UART Control 1 register to enable Multiprocessor mode functions, if desired. Write to the UART Control 0 register to: Set the receive enable bit (REN) to enable the UART for data reception Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 6. If the Receive Data register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data. Read data from the UART Receive Data register. If operating in Multiprocessor (9-bit) mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0]. Return to Step 5 to receive additional data.

Z8 Encore!® 64K Series Product Specification 103 Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error con- ditions). Follow these steps to configure the UART receiver for interrupt-driven operation: Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. Execute a DI instruction to disable interrupts. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the desired priority. Clear the UART Receiver interrupt in the applicable Interrupt Request register. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode functions, if desired. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable Multiprocessor mode Set the MULTIPROCESSOR Mode Bits, MPMD[1:0], to select the desired address matching scheme Configure the UART to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a DMA block) Write the device address to the Address Compare Register (automatic multiprocessor modes only). Write to the UART Control 0 register to: Set the receive enable bit (REN) to enable the UART for data reception Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: Check the UART Status 0 register to determine the source of the interrupt - error, break, or received data. If the interrupt was caused by data available, read the data from the UART Receive Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0]. Clear the UART Receiver interrupt in the applicable Interrupt Request register.

the middle of a character transmission, the current character is sent completely. Figure 16. UART Asynchronous MULTIPROCESSOR Mode Data Format

Z8 Encore!® 64K Series Product Specification 105 on the multi-node network. The following three MULTIPROCESSOR modes are avail- able in hardware: Interrupt on all address bytes Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all MULTIPROCESSOR modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software clears MPMD[0]. At this point, each new incoming byte interrupts the CPU. The software is then responsible for determining the end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame is different from the UART’s address, then set MPMD[0] to 1 causing the UART interrupts to go inactive until the next address byte. If the new frame’s address matches the UART’s, the data in the new frame is processed as well. The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART’s address into the UART Address Compare Register. This mode introduces more hardware control, interrupting only on frames that match the UART’s address. When an incoming address byte does not match the UART’s address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an interrupt is issued and further interrupts now occur on each succesive data byte. The first data byte in the frame contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts continue sand the NEWFRM bit is set for the first byte of the new frame. If there is no match, then the UART ignores all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s address into the UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame is still accompanied by a NEWFRM assertion. External Driver Enable The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi-transceiver bus, such as RS-485. Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 17. The Driver Enable signal asserts when a byte is written to the UART Transmit Data register. The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the

polarity of the Driver Enable signal. Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) tion as a basic timer with interrupt capability. Transmit Data register clears the TDRE bit to 0.

Z8 Encore!® 64K Series Product Specification 107 Receiver Interrupts The receiver generates an interrupt when any of the following occurs: A data byte has been received and is available in the UART Receive Data register. This interrupt can be disabled independent of the other receiver interrupt sources. The received data interrupt occurs once the receive character has been received and placed in the Receive Data register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error. Note that in multiprocessor mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte. A break is received An overrun is detected A data framing error is detected UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and should be ignored. The BRKD bit indi- cates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received. UART Data and Error Handling Procedure Figure 18 illustrates the recommended procedure for use in UART receiver interrupt ser- vice routines.

Figure 18. UART Receiver Interrupt Service Routine Flow Generator to function as an additional counter if the UART functionality is not employed.

BRGCTL bit in the UART Control 1 register to 1. Decoder chapter on page 120. with the Read-only UART Receive Data register. Table 51. UART Transmit Data Register (UxTXD)

UART transmitter data byte to be shifted out through the TXDx pin. with the Write-only UART Transmit Data register. operating configuration and status. UART Receive Data register clears this bit. 0 = The UART Receive Data register is empty. 1 = There is a byte in the UART Receive Data register. Table 52. UART Receive Data Register (UxRXD) Table 53. UART Status 0 Register (UxSTAT0)

Z8 Encore!® 64K Series Product Specification 111 PE—Parity Error This bit indicates that a parity error has occurred. Reading the UART Receive Data regis- ter clears this bit. 0 = No parity error occurred. 1 = A parity error occurred. OE—Overrun Error This bit indicates that an overrun error has occurred. An overrun occurs when new data is received and the UART Receive Data register has not been read. If the RDA bit is reset to 0, then reading the UART Receive Data register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. FE—Framing Error This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data register clears this bit. 0 = No framing error occurred. 1 = A framing error occurred. BRKD—Break Detect This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data register clears this bit. 0 = No break occurred. 1 = A break occurred. TDRE—Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data. Writing to the UART Transmit Data register resets this bit. 0 = Do not write to the UART Transmit Data register. 1 = The UART Transmit Data register is ready to receive an additional byte to be transmit- ted. TXE—Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is fin- ished. 0 = Data is currently transmitting. 1 = Transmission is complete. CTS—CTS signal When this bit is read it returns the level of the CTS signal.

Data register resets this bit to 0. 0 = The current byte is not the first data byte of a new frame. 1 = The current byte is the first data byte of a new frame. Data register resets this bit to 0. been written while the UART is enabled. This register contains multiprocessor control and status bits. Table 54. UART Status 1 Register (UxSTAT1) Table 55. UART Control 0 Register (UxCTL0)

This bit enables or disables the receiver. 0 = The CTS signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. progress, so ensure that the transmitter has finished sending data before setting this bit. 1 = The output of the transmitter is zero. 0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits. 1 = All transmitted data is looped back to the receiver. Table 56. UART Control 1 Register (UxCTL1)

Z8 Encore!® 64K Series Product Specification 114 MPMD[1:0]—MULTIPROCESSOR Mode If MULTIPROCESSOR (9-bit) mode is enabled, 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. 10 = The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an address mismatch occurs. 11 = The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register. MPEN—MULTIPROCESSOR (9-bit) Enable This bit is used to enable MULTIPROCESSOR (9-bit) mode. 0 = Disable MULTIPROCESSOR (9-bit) mode. 1 = Enable MULTIPROCESSOR (9-bit) mode. MPBT—MULTIPROCESSOR Bit Transmit This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. 0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit). 1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit). DEPOL—Driver Enable Polarity 0 = DE signal is Active High. 1 = DE signal is Active Low. BRGCTL—Baud Rate Control This bit causes different UART behavior depending on whether the UART receiver is enabled (REN = 1 in the UART Control 0 Register). When the UART receiver is not enabled, this bit determines whether the Baud Rate Gener- ator issues interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low Byte is read. RDAIRQ—Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Con- troller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request.

0 = Infrared Encoder/Decoder is disabled. UART operates normally operation. the Infrared Encoder/Decoder. interrupts and RDA assertions only occur in the event of a match. This 8-bit value is compared to the incoming address bytes. BRGCTL bit in the UART Control 1 register to 1. Table 57. UART Address Compare Register (UxADDR)

For reliable communication, the UART baud rate error must never exceed 5 percent. used crystal oscillator frequencies. Table 58. UART Baud Rate High Byte Register (UxBRH) Table 59. UART Baud Rate Low Byte Register (UxBRL)

Table 60. UART Baud Rates

20.0 MHz System Clock

18.432 MHz System Clock

16.667 MHz System Clock

11.0592 MHz System Clock

10.0 MHz System Clock

5.5296 MHz System Clock

3.579545 MHz System Clock

1.8432 MHz System Clock

Table 60. UART Baud Rates (Continued)

Z8 Encore!® 64K Series Product Specification 121 Operation When the Infrared Endec is enabled, the transmit data from the associated on-chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infra- red transceiver via the TXD pin. Likewise, data received from the infrared transceiver is passed to the Infrared Endec via the RXD pin, decoded by the Infrared Endec, and then passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared Endec data rate is calculated using the following equation: Transmitting IrDA Data The data to be transmitted using the infrared transceiver is first sent to the UART. The UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is output to complete the full 16-clock data period. Figure 20 illustrates IrDA data transmis- sion. When the Infrared Endec is enabled, the UART’s TXD signal is internal to the 64K Series products while the IR_TXD signal is output through the TXD pin. Infrared Data Rate (bits/s) System Clock Frequency (Hz) UART Baud Rate Divisor Value

Figure 20. Infrared Data Transmission Series products while the IR_RXD signal is received through the RXD pin.

Figure 21. Infrared Data Reception ception of the 1.6μs minimum width pulses allowed by the IrDA standard. reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the Endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchronized to the incoming data stream when a Start bit is received.

Z8 Encore!® 64K Series Product Specification 124 Infrared Encoder/Decoder Control Register Definitions All Infrared Endec configuration and status information is set by the UART control regis- ters as defined beginning on page 109. To prevent spurious signals during IrDA data transmission, set the IREN bit in the UARTx Control 1 register to 1 to enable the Infrared Encoder/ Decoder before enabling the GPIO Port alternate function for the corre- sponding pin. Caution:

Slave as illustrated in Figures 22 through 24. Figure 22. SPI Configured as a Master in a Single Master, Single Slave System

Serial Peripheral Interface Z8 Encore!® 64K Series Product Specification 127 During an SPI transfer, data is sent and received simultaneously by both the Master and the Slave SPI devices. Separate signals are required for data and the serial clock. When an SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register in the Master and another 8-bit shift register in the Slave are connected as a circular buffer. The SPI shift register is single-buffered in the transmit and receive directions. New data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read. SPI Signals The four basic SPI signals are: MISO (Master-In, Slave-Out) MOSI (Master-Out, Slave-In) SCK (SPI Serial Clock) SS (Slave Select) The following paragraphs discuss these SPI signals. Each signal is described in both Mas- ter and Slave modes. Master-In, Slave-Out The Master-In, Slave-Out (MISO) pin is configured as an input in a Master device and as an output in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance state if the Slave is not selected. When the SPI is not enabled, this signal is in a high- impedance state. Master-Out, Slave-In The Master-Out, Slave-In (MOSI) pin is configured as an output in a Master device and as an input in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance state. Serial Clock The Serial Clock (SCK) synchronizes data movement both in and out of the device through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator cre- ates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave’s SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock sig- nal from the Master synchronizes the data transfer between the Master and Slave devices. Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times the system (XIN) clock period.

sequence of NUMBITS clock cycles (refer to NUMBITS field in the SPIMODE register). of multiple characters or may deassert between each character. employed to select external SPI Slave devices. Table 61. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation

Figure 26. SPI Timing When PHASE is 1

Serial Peripheral Interface Z8 Encore!® 64K Series Product Specification 131 ister. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUMBITS field in the SPIMODE register must be set to be consistent with the other SPI devices. The STR bit in the SPICTL register may be used if desired to force a “startup” interrupt. The BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register are not used in slave mode. The SPI baud rate generator is not used in slave mode so the SPIBRH and SPIBRL registers need not be initialized. If the slave has data to send to the master, the data must be written to the SPIDAT register before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT regis- ter is not written prior to the slave transaction, the MISO pin outputs whatever value is currently in the SPIDAT register. Due to the delay resulting from synchronization of the SPI input signals to the internal sys- tem clock, the maximum SPICLK baud rate that can be supported in slave mode is the sys- tem clock frequency (XIN) divided by 8. This rate is controlled by the SPI master. Error Detection The SPI contains error detection logic to support SPI communication protocols and recog- nize when communication errors have occurred. The SPI Status register indicates when a data transmission error has been detected. Overrun (Write Collision) An overrun error (write collision) indicates a write to the SPI Data register was attempted while a data transfer is in progress (in either master or slave modes). An overrun sets the OVR bit in the SPI Status register to 1. Writing a 1 to OVR clears this error flag. The data register is not altered when a write occurs while data transfer is in progress. Mode Fault (Multi-Master Collision) A mode fault indicates when more than one Master is trying to communicate at the same time (a multi-master collision). The mode fault is detected when the enabled Master’s SS pin is asserted. A mode fault sets the COL bit in the SPI Status register to 1. Writing a 1 to COL clears this error flag. Slave Mode Abort In slave mode of operation if the SS pin deasserts before all bits in a character have been transferred, the transaction is aborted. When this condition occurs the ABT bit is set in the SPISTAT register as well as the IRQ bit (indicating the transaction is complete). The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous trans- action left off. Writing a 1 to ABT clears this error flag. SPI Interrupts When SPI interrupts are enabled, the SPI generates an interrupt after character transmis- sion/reception completes in both master and slave modes. A character can be defined to be

Serial Peripheral Interface Z8 Encore!® 64K Series Product Specification 132 1 through 8 bits by the NUMBITS field in the SPI Mode register. In slave mode it is not necessary for SS to deassert between characters to generate the interrupt. The SPI in Slave mode can also generate an interrupt if the SS signal deasserts prior to transfer of all the bits in a character (see description of slave abort error above). Writing a 1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts. To start the transfer pro- cess, an SPI interrupt may be forced by software writing a 1 to the STR bit in the SPICTL register. If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator time- out. This timer function must be enabled by setting the BIRQ bit in the SPICTL register. This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT register, just the SPI interrupt bit in the interrupt controller. SPI Baud Rate Generator In SPI Master mode, the Baud Rate Generator creates a lower frequency serial clock (SCK) for data transmission synchronization between the Master and the external Slave. The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud rate is calculated using the following equation: Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value of (2 X 65536 = 131072). When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte registers. Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the SPI Control register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation: Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ] SPI Baud Rate (bits/s) System Clock Frequency (Hz) BRG[15:0]

are ignored and the Overrun error flag, OVR, is set in the SPI Status register. ten to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0]. Transmit and/or receive data. The SPI Control register (Table 63) configures the SPI for transmit and receive operations. Table 62. SPI Data Register (SPIDATA)

0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller. 1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller. IRQ bit in the SPI Status register clears this bit to 0. 0 = The Baud Rate Generator timer function is disabled. 1 = The Baud Rate Generator timer function and time-out interrupt are enabled. Polarity Control section for more information on operation of the PHASE bit. 0 = SPI signal pins not configured for open-drain. 1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function. This setting is typically used for multi-master and/or multi-slave configurations. 0 = SPI configured in Slave mode. 1 = SPI configured in Master mode. Table 63. SPI Control Register (SPICTL)

their reset state if the SPIEN bit in the SPICTL register = 0. Rate Generator is used as a timer to generate the SPI interrupt. 0 = No SPI interrupt request pending. 1 = SPI interrupt request is pending. 0 = An overrun error has not occurred. 1 = An overrun error has been detected. 0 = A multi-master collision (mode fault) has not occurred. 1 = A multi-master collision (mode fault) has been detected. 0 = A slave mode transaction abort has not occurred. 1 = A slave mode transaction abort has been detected. 0 = No data transmission currently in progress. 1 = Data transmission currently in progress. Table 64. SPI Status Register (SPISTAT) R/W* = Read access. Write a 1 to clear the bit to 0.

1 = SS input is not asserted (High). If SPI enabled as a Master, this bit is not applicable. read using the SPIBRH and SPIBRL register locations. Low byte values are not buffered. Exercise caution if reading the values while the BRG is counting. Table 65. SPI Mode Register (SPIMODE)

0 = SS pin configured as an input. 1 = SS pin configured as an output (Master mode only). This bit has no effect if SSIO = 0 or SPI configured as a Slave. is a read only register used for SPI diagnostics. 0 = The internal Transmit Clock Enable signal is deasserted. data out is updated on the next system clock (MOSI or MISO). Defines the current state of the internal SPI State Machine. Table 66. SPI Diagnostic State Register (SPIDST)

bit reload value, BRG[15:0], for the SPI Baud Rate Generator. SPI BRG Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ]. Most significant byte, BRG[15:8], of the SPI Baud Rate Generator’s reload value. Least significant byte, BRG[7:0], of the SPI Baud Rate Generator’s reload value. Table 67. SPI Baud Rate High Byte Register (SPIBRH) Table 68. SPI Baud Rate Low Byte Register (SPIBRL)

Z8 Encore!® 64K Series Product Specification PS019915-1005 I2C Controller 139 I2C Controller Overview The I2C Controller makes the 64K Series products bus-compatible with the I2CTM proto- col. The I2C Controller consists of two bidirectional bus lines—a serial data signal (SDA) and a serial clock signal (SCL). Features of the I2C Controller include: Transmit and Receive Operation in MASTER mode Maximum data rate of 400kbit/sec 7- and 10-bit addressing modes for Slaves Unrestricted number of data bytes transmitted per transfer The I2C Controller in the 64K Series products does not operate in Slave mode.

Z8 Encore!® 64K Series Product Specification 141 Master receives from a 7-bit slave Master receives from a 10-bit slave SDA and SCL Signals I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin alternate functions are selected for their respective GPIO ports, the pins are automatically configured for open-drain operation. The master (I2C) is responsible for driving the SCL clock signal, although the clock signal can become skewed by a slow slave device. During the low period of the clock, the slave pulls the SCL signal Low to suspend the transaction. The master releases the clock at the end of the low period and notices that the clock remains low instead of returning to a high level. When the slave releases the clock, the I2C Controller continues the transaction. All data is transferred in bytes and there is no limit to the amount of data transferred in one operation. When transmitting data or acknowledging read data from the slave, the SDA signal changes in the middle of the low period of SCL and is sampled in the middle of the high period of SCL. I2C Interrupts The I2C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowl- edge and baud rate generator. These four interrupt sources are combined into a single interrupt request signal to the Interrupt Controller. The Transmit interrupt is enabled by the IEN and TXI bits of the Control register. The Receive and Not Acknowledge interrupts are enabled by the IEN bit of the Control register. The baud rate generator interrupt is enabled by the BIRQ and IEN bits of the Control register. Not Acknowledge interrupts occur when a Not Acknowledge condition is received from the slave or sent by the I2C Controller and neither the START or STOP bit is set. The Not Acknowledge event sets the NCKI bit of the I2C Status register and can only be cleared by setting the START or STOP bit in the I2C Control register. When this interrupt occurs, the I2C Controller waits until either the STOP or START bit is set before performing any action. In an interrupt service routine, the NCKI bit should always be checked prior to ser- vicing transmit or receive interrupt conditions because it indicates the transaction is being terminated. Receive interrupts occur when a byte of data has been received by the I2C Controller (master reading data from slave). This procedure sets the RDRF bit of the I2C Status regis- ter. The RDRF bit is cleared by reading the I2C Data register. The RDRF bit is set during the acknowledge phase. The I2C Controller pauses after the acknowledge phase until the receive interrupt is cleared before performing any other action.

Z8 Encore!® 64K Series Product Specification 142 Transmit interrupts occur when the TDRE bit of the I2C Status register sets and the TXI bit in the I2C Control register is set. Transmit interrupts occur under the following condi- tions when the transmit data register is empty: The I2C Controller is enabled The first bit of the byte of an address is shifting out and the RD bit of the I2C Status register is deasserted. The first bit of a 10-bit address shifts out. The first bit of write data shifts out. Writing to the I2C Data register always clears the TRDE bit to 0. When TDRE is asserted, the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently shifting out until the Data register is written with the next value to send or the STOP or START bits are set indicating the current byte is the last one to send. The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled (IEN bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an inter- rupt is generated when the baud rate generator counts down to 1. This allows the I2C baud rate generator to be used by software as a general purpose timer when IEN = 0. Software Control of I2C Transactions Software can control I2C transactions by using the I2C Controller interrupt, by polling the I2C Status register or by DMA. Note that not all products include a DMA Controller. To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller. The TXI bit in the I2C Control register must be set to enable transmit interrupts. To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I2C Status register should be polled. The TDRE bit asserts regardless of the state of the TXI bit. Either or both transmit and receive data movement can be controlled by the DMA Control- ler. The DMA Controller channel(s) must be initialized to select the I2C transmit and receive requests. Transmit DMA requests require that the TXI bit in the I2C Control regis- ter be set. A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge before the last byte has been sent. After receiving the Not Acknowledge, the I2C Controller sets the NCKI bit in the Status register and pauses until either the STOP or START bits in the Control register are set. Note: Caution:

Z8 Encore!® 64K Series Product Specification 143 In order for a receive (read) DMA transaction to send a Not Acknowledge on the last byte, the receive DMA must be set up to receive n-1 bytes, then software must set the NAK bit and receive the last (nth) byte directly. Start and Stop Conditions The master (I2C) drives all Start and Stop signals and initiates all transactions. To start a transaction, the I2C Controller generates a START condition by pulling the SDA signal Low while SCL is High. To complete a transaction, the I2C Controller generates a Stop condition by creating a low-to-high transition of the SDA signal while the SCL signal is high. The START and STOP bits in the I2C Control register control the sending of the Start and Stop conditions. A master is also allowed to end one transaction and begin a new one by issuing a Restart. This is accomplished by setting the START bit at the end of a transaction, rather than the STOP bit. Note that the Start condition not sent until the START bit is set and data has been written to the I2C Data register. Master Write and Read Transactions The following sections provide a recommended procedure for performing I2C write and read transactions from the I2C Controller (master) to slave I2C devices. In general soft- ware should rely on the TDRE, RDRF and NCKI bits of the status register (these bits gen- erate interrupts) to initiate software actions. When using interrupts or DMA, the TXI bit is set to start each transaction and cleared at the end of each transaction to eliminate a “trail- ing” Transmit interrupt. Caution should be used in using the ACK status bit within a transaction because it is diffi- cult for software to tell when it is updated by hardware. When writing data to a slave, the I2C pauses at the beginning of the Acknowledge cycle if the data register has not been written with the next value to be sent (TDRE bit in the I2C Status register = 1). In this scenario where software is not keeping up with the I2C bus (TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is delayed until the Data register is written with byte n + 1, and appears to be grouped with the data clock cycles for byte n+1. If either the START or STOP bit is set, the I2C does not pause prior to the Acknowledge cycle because no additional data is sent. When a Not Acknowledge condition is received during a write (either during the address or data phases), the I2C Controller generates the Not Acknowledge interrupt (NCKI = 1) and pause until either the STOP or START bit is set. Unless the Not Acknowledge was received on the last byte, the Data register will already have been written with the next address or data byte to send. In this case the FLUSH bit of the Control register should be set at the same time the STOP or START bit is set to remove the stale transmit data and enable subsequent Transmit interrupts. When reading data from the slave, the I2C pauses after the data Acknowledge cycle until the receive interrupt is serviced and the RDRF bit of the status register is cleared by read-

Acknowledge, the transaction can be repeated until the slave does Acknowledge. Figure 28. 7-Bit Address Only Transaction Format Software asserts the IEN bit in the I2C Control register. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. The I2C Controller sends the START condition to the I2C slave. bit when the address only transaction is completed. interrupt does not occur in the not acknowledge case because the STOP bit was set.

1. The I2C Controller shifts the data out of using the SDA signal. After the first bit is

sent, the Transmit interrupt is asserted.

1. If more bytes remain to be sent, return to step 9.
2. Software responds by setting the STOP bit of the I2C Control register (or START bit

Control register at the same time.

1. The I2C Controller completes transmission of the data on the SDA signal.
2. The slave may either Acknowledge or Not Acknowledge the last byte. Because either

the STOP or START bit is already set, the NCKI interrupt does not occur.

1. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus. The

STOP or START bit is cleared. Figure 30. 10-Bit Address Only Transaction Format Software asserts the IEN bit in the I2C Control register. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. least-significant bit must be 0 for the write operation. Software asserts the START bit of the I2C Control register. The I2C Controller sends the START condition to the I2C slave.

Z8 Encore!® 64K Series Product Specification 148 The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the read/write control bit (=0). The transmit operation is carried out in the same manner as 7- bit addressing. The procedure for a transmit operation on a 10-bit addressed slave is as follows: Software asserts the IEN bit in the I2C Control register. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. The I2C interrupt asserts because the I2C Data register is empty. Software responds to the TDRE interrupt by writing the first slave address byte to the I2C Data register. The least-significant bit must be 0 for the write operation. Software asserts the START bit of the I2C Control register. The I2C Controller sends the START condition to the I2C slave. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is asserted. Software responds by writing the second byte of address into the contents of the I2C Data register. 10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA signal. 11. If the I2C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 12. If the slave does not acknowledge the first address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 13. The I2C Controller shifts the second address byte out the SDA signal. After the first bit has been sent, the Transmit interrupt is asserted. 14. Software responds by writing a data byte to the I2C Data register. 15. The I2C Controller completes shifting the contents of the shift register on the SDA signal.

Z8 Encore!® 64K Series Product Specification 151 Software writes 11110B followed by the two address bits and a 0 (write) to the I2C Data register. Software asserts the START and TXI bits of the I2C Control register. The I2C Controller sends the Start condition. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. After the first bit has been shifted out, a Transmit interrupt is asserted. Software responds by writing the lower eight bits of address to the I2C Data register. The I2C Controller completes shifting of the two address bits and a 0 (write). If the I2C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 9. If the slave does not acknowledge the first address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore following steps). The I2C Controller loads the I2C Shift register with the contents of the I2C Data register (second address byte). 10. The I2C Controller shifts out the second address byte. After the first bit is shifted, the I2C Controller generates a Transmit interrupt. 11. Software responds by setting the START bit of the I2C Control register to generate a repeated START and by clearing the TXI bit. 12. Software responds by writing 11110B followed by the 2-bit slave address and a 1 (read) to the I2C Data register. 13. If only one byte is to be read, software sets the NAK bit of the I2C Control register. 14. After the I2C Controller shifts out the 2nd address byte, the I2C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 15. If the slave does not acknowledge the second address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 15. The I2C Controller sends the repeated START condition.

Z8 Encore!® 64K Series Product Specification 152 16. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register (third address transfer). 17. The I2C Controller sends 11110B followed by the two most significant bits of the slave read address and a 1 (read). 18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL If the slave were to Not Acknowledge at this point (this should not happen because the slave did acknowledge the first two address bytes), software would respond by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 19. The I2C Controller shifts in a byte of data from the I2C slave on the SDA signal. The I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last byte), else it sends an Acknowledge. 20. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register). 21. Software responds by reading the I2C Data register which clears the RDRF bit. If there is only one more byte to receive, set the NAK bit of the I2C Control register. 22. If there are one or more bytes to transfer, return to step 19. 23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C Controller. 24. Software responds by setting the STOP bit of the I2C Control register. 25. A STOP condition is sent to the I2C slave and the STOP and NCKI bits are cleared. I2C Control Register Definitions I2C Data Register The I2C Data register (Table 69) holds the data that is to be loaded into the I2C Shift regis- ter during a write to a slave. This register also holds data that is loaded from the I2C Shift

File address space, but is used only to buffer incoming and outgoing data. The Read-only I2C Status register (Table 70) indicates the status of the I2C Controller. When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty. the RD bit is set. This bit is cleared by writing to the I2CDATA register. byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt. cution of the On-Chip Debugger’s Read Register command). This bit indicates the status of the Acknowledge for the last byte transmitted or received. Table 69. I2C Data Register (I2CDATA) Table 70. I2C Status Register (I2CSTAT)

Z8 Encore!® 64K Series Product Specification 154 last byte transmitted or received. It is not reset at the beginning of each transaction and is not reset when this register is read. Software must be cautious in making decisions based on this bit within a transaction because software cannot tell when the bit is updated by hard- ware. In the case of write transactions, the I2C pauses at the beginning of the Acknowledge cycle if the next transmit data or address byte has not been written (TDRE = 1) and STOP and START = 0. In this case the ACK bit is not updated until the transmit interrupt is serviced and the Acknowl- edge cycle for the previous byte completes. Refer to Address Only Trans- action with a 7-bit Address on page 144 and Address Only Transaction with a 10-bit Address on page 146 for examples of how the ACK bit can be used. 10B—10-Bit Address This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit is set, if the five most-significant bits of the address are 11110B, this bit is set. When set, it is reset once the first byte of the address has been sent. RD—Read This bit indicates the direction of transfer of the data. It is active high during a read. The status of this bit is determined by the least-significant bit of the I2C Shift register after the START bit is set. TAS—Transmit Address State This bit is active high while the address is being shifted out of the I2C Shift register. DSS—Data Shift State This bit is active high while data is being shifted to or from the I2C Shift register. NCKI—NACK Interrupt This bit is set high when a Not Acknowledge condition is received or sent and neither the START nor the STOP bit is active. When set, this bit generates an interrupt that can only be cleared by setting the START or STOP bit, allowing the user to specify whether he wants to perform a STOP or a repeated START. Caution:

The I2C Control register (Table 71) enables the I2C operation. 1 = The I2C transmitter and receiver are enabled. 0 = The I2C transmitter and receiver are disabled. dition is sent before the sending the START condition. ler is disabled. This bit is ignored when the I2C Controller is enabled. 1 = An interrupt occurs every time the baud rate generator counts down to one. 0 = No baud rate generator interrupt occurs. This bit enables the transmit interrupt when the I2C Data register is empty (TDRE = 1). 1 = Transmit interrupt (and DMA transmit request) is enabled. 0 = Transmit interrupt (and DMA transmit request) is disabled. Table 71. I2C Control Register (I2CCTL)

Z8 Encore!® 64K Series Product Specification 156 NAK—Send NAK This bit sends a Not Acknowledge condition after the next byte of data has been read from the I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register. FLUSH—Flush Data Setting this bit to 1 clears the I2C Data register and sets the TDRE bit to 1. This bit allows flushing of the I2C Data register when a Not Acknowledge interrupt is received after the data has been sent to the I2C Data register. Reading this bit always returns 0. FILTEN—I2C Signal Filter Enable This bit enables low-pass digital filters on the SDA and SCL input signals. These filters reject any input pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock cycle latency on the inputs. 1 = low-pass filters are enabled. 0 = low-pass filters are disabled. I2C Baud Rate High and Low Byte Registers The I2C Baud Rate High and Low Byte registers (Tables 72 and 73) combine to form a 16- bit reload value, BRG[15:0], for the I2C Baud Rate Generator. When the I2C is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: Disable the I2C by clearing the IEN bit in the I2C Control register to 0. Load the desired 16-bit count value into the I2C Baud Rate High and Low Byte registers. Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the I2C Control register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation: Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ]

Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value. register returns the current value of the I2C Baud Rate Counter[15:8]. Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value. register returns the current value of the I2C Baud Rate Counter[7:0]. Table 72. I2C Baud Rate High Byte Register (I2CBRH) Table 73. I2C Baud Rate Low Byte Register (I2CBRL)

is a read only register used for I2C diagnostics and manufacturing test. Table 74. I2C Diagnostic State Register (I2CDST)

Z8 Encore!® 64K Series Product Specification 159 0_1111 10-bit address: Bit 0 (Least significant bit) of 2nd address byte 7-bit address: Bit 0 (Least significant bit) (R/W) of address byte 1_0000 10-bit addressing: Bit 7 (Most significant bit) of 1st address byte 1_0001 10-bit addressing: Bit 6 of 1st address byte 1_0010 10-bit addressing: Bit 5 of 1st address byte 1_0011 10-bit addressing: Bit 4 of 1st address byte 1_0100 10-bit addressing: Bit 3 of 1st address byte 1_0101 10-bit addressing: Bit 2 of 1st address byte 1_0110 10-bit addressing: Bit 1 of 1st address byte 1_0111 10-bit addressing: Bit 0 (R/W) of 1st address byte 1_1000 10-bit addressing: Acknowledge state for 1st address byte 1_1001 10-bit addressing: Bit 7 of 2nd address byte 7-bit addressing: Bit 7 of address byte 1_1010 10-bit addressing: Bit 6 of 2nd address byte 7-bit addressing: Bit 6 of address byte 1_1011 10-bit addressing: Bit 5 of 2nd address byte 7-bit addressing: Bit 5 of address byte 1_1100 10-bit addressing: Bit 4 of 2nd address byte 7-bit addressing: Bit 4 of address byte 1_1101 10-bit addressing: Bit 3 of 2nd address byte 7-bit addressing: Bit 3 of address byte 1_1110 10-bit addressing: Bit 2 of 2nd address byte 7-bit addressing: Bit 2 of address byte 1_1111 10-bit addressing: Bit 1 of 2nd address byte 7-bit addressing: Bit 1 of address byte TXRXSTATE State Description

ter is a read/write register used for I2C diagnostics. Table 75. I2C Diagnostic Control Register (I2CDIAG)

Z8 Encore!® 64K Series Product Specification PS019915-1005 Direct Memory Access Controller 161 Direct Memory Access Controller Overview The 64K Series Direct Memory Access (DMA) Controller provides three independent Direct Memory Access channels. Two of the channels (DMA0 and DMA1) transfer data between the on-chip peripherals and the Register File. The third channel (DMA_ADC) controls the Analog-to-Digital Converter (ADC) operation and transfers SINGLE-SHOT mode ADC output data to the Register File. Operation DMA0 and DMA1 Operation DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip peripheral control registers to the Register File, or from the Register File to the on-chip peripheral control registers. The sequence of operations in a DMAx data transfer is: DMAx trigger source requests a DMA data transfer. DMAx requests control of the system bus (address and data) from the eZ8 CPU. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte or a two-byte word (depending upon configuration) and then returns system bus control back to the eZ8 CPU. If Current Address equals End Address: DMAx reloads the original Start Address If configured to generate an interrupt, DMAx sends an interrupt request to the Interrupt Controller If configured for single-pass operation, DMAx resets the DEN bit in the DMAx Control register to 0 and the DMA is disabled. If Current Address does not equal End Address, the Current Address increments by 1 (single-byte transfer) or 2 (two-byte word transfer).

Direct Memory Access Controller Z8 Encore!® 64K Series Product Specification 162 Configuring DMA0 and DMA1 for Data Transfer Follow these steps to configure and enable DMA0 or DMA1: Write to the DMAx I/O Address register to set the Register File address identifying the on-chip peripheral control register. The upper nibble of the 12-bit address for on-chip peripheral control registers is always FH. The full address is {FH, DMAx_IO[7:0]} Determine the 12-bit Start and End Register File addresses. The 12-bit Start Address is given by {DMAx_H[3:0], DMA_START[7:0]}. The 12-bit End Address is given by {DMAx_H[7:4], DMA_END[7:0]}. Write the Start and End Register File address high nibbles to the DMAx End/Start Address High Nibble register. Write the lower byte of the Start Address to the DMAx Start/Current Address register. Write the lower byte of the End Address to the DMAx End Address register. Write to the DMAx Control register to complete the following: Select loop or single-pass mode operation Select the data transfer direction (either from the Register File RAM to the on- chip peripheral control register; or from the on-chip peripheral control register to the Register File RAM) Enable the DMAx interrupt request, if desired Select Word or Byte mode Select the DMAx request trigger Enable the DMAx channel DMA_ADC Operation DMA_ADC transfers data from the ADC to the Register File. The sequence of operations in a DMA_ADC data transfer is: ADC completes conversion on the current ADC input channel and signals the DMA controller that two-bytes of ADC data are ready for transfer. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte ADC output value to the Register File and then returns system bus control back to the eZ8 CPU. If the current ADC Analog Input is the highest numbered input to be converted: DMA_ADC resets the ADC Analog Input number to 0 and initiates data conversion on ADC Analog Input 0. If configured to generate an interrupt, DMA_ADC sends an interrupt request to the Interrupt Controller

Direct Memory Access Controller Z8 Encore!® 64K Series Product Specification 163 If the current ADC Analog Input is not the highest numbered input to be converted, DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input. Configuring DMA_ADC for Data Transfer Follow these steps to configure and enable DMA_ADC: Write the DMA_ADC Address register with the 7 most-significant bits of the Register File address for data transfers. Write to the DMA_ADC Control register to complete the following: Enable the DMA_ADC interrupt request, if desired Select the number of ADC Analog Inputs to convert Enable the DMA_ADC channel When using the DMA_ADC to perform conversions on multiple ADC in- puts, the Analog-to-Digital Converter must be configured for SINGLE- SHOT mode. If the ADC_IN field in the DMA_ADC Control Register is greater than 000b, the ADC must be in SINGLE-SHOT mode. CONTINUOUS mode operation of the ADC can only be used in conjunc- tion with DMA_ADC if the ADC_IN field in the DMA_ADC Control Register is reset to 000b to enable conversion on ADC Analog Input 0 only. DMA Control Register Definitions DMAx Control Register The DMAx Control register (Table 76) enables and selects the mode of operation for DMAx. Caution:

0 = DMAx is disabled and data transfer requests are disregarded. 0 = Register File → on-chip peripheral control register. 1 = on-chip peripheral control register → Register File. 0 = DMAx does not generate any interrupts. 1 = DMAx generates an interrupt when the End Address data is transferred. 0 = DMAx transfers a single byte per request. control register must be an even address. enabled within the Request Trigger Source block. Control register: UART0 Transmit Data register empty. Table 76. DMAx Control Register (DMAxCTL)

Control register: UART1 Transmit Data register empty. mitter Interrupt register empty. O Address register must contain an even numbered address. File Page FH (addresses F00H to FFFH). the Start/Current and End Addresses of DMAx. Table 77. DMAx I/O Address Register (DMAxIO) Table 78. DMAx Address High Nibble Register (DMAxH)

These bits, used with the DMAx End Address Low register, form a 12-bit End Address. The full 12-bit address is given by {DMA_END_H[3:0], DMA_END[7:0]}. address. The full 12-bit address is given by {DMA_START_H[3:0], DMA_START[7:0]}. register (Table 80), forms a 12-bit End Address. Table 79. DMAx Start/Current Address Low Byte Register (DMAxSTART)

most significant byte of the ADC data stored at the even numbered Register File address. register contains the value 72H. Table 80. DMAx End Address Low Byte Register (DMAxEND) Table 81. DMA_ADC Register File Address Example

{DMAA_ADDR[7:1], 4-bit ADC Analog Input Number, 0}. This bit is reserved and must be 0. interrupt enable) for ADC operation. Table 82. DMA_ADC Address Register (DMAA_ADDR)

0 = DMA_ADC is disabled and the ADC Analog Input Number (ADC_IN) is reset to 0. 0 = DMA_ADC does not generate any interrupts. Input specified by the ADC_IN field. These bits are reserved and must be 0. 0000 = ADC Analog Input 0 updated. 0001 = ADC Analog Inputs 0-1 updated. 0010 = ADC Analog Inputs 0-2 updated. 0011 = ADC Analog Inputs 0-3 updated. 0100 = ADC Analog Inputs 0-4 updated. 0101 = ADC Analog Inputs 0-5 updated. 0110 = ADC Analog Inputs 0-6 updated. 0111 = ADC Analog Inputs 0-7 updated. 1000 = ADC Analog Inputs 0-8 updated. 1001 = ADC Analog Inputs 0-9 updated. 1010 = ADC Analog Inputs 0-10 updated. 1011 = ADC Analog Inputs 0-11 updated. Table 83. DMA_ADC Control Register (DMAACTL)

This field identifies the Analog Input that the ADC is currently converting. This bit is reserved and must be 0. This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA_ADC is not the source of the interrupt from the DMA Controller. This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA1 is not the source of the interrupt from the DMA Controller. 1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt. This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA0 is not the source of the interrupt from the DMA Controller. 1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt. Table 84. DMA_ADC Status Register (DMAA_STAT)

Z8 Encore!® 64K Series Product Specification PS019915-1005 Analog-to-Digital Converter 171 Analog-to-Digital Converter Overview The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The features of the sigma-delta ADC include: 12 analog input sources are multiplexed with general-purpose I/O ports Interrupt upon conversion complete Internal voltage reference generator Direct Memory Access (DMA) controller can automatically initiate data conversion and transfer of the data from 1 to 12 of the analog inputs Architecture Figure 34 illustrates the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the ADC. The ADC converts an analog input signal to its digital representation. The 12-input analog multiplexer selects one of the 12 analog input sources. The ADC requires an input reference voltage for the conversion. The voltage ref- erence for the conversion may be input through the external VREF pin or generated inter- nally by the voltage reference generator.

Figure 34. Analog-to-Digital Converter Block Diagram ing codes) is guaranteed by design. sion is requested using the ADC Control register.

Analog-to-Digital Converter Z8 Encore!® 64K Series Product Specification 173 Single-Shot Conversion When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion are as follows: Enable the desired analog inputs by configuring the general-purpose I/O pins for alternate function. This configuration disables the digital input and output drivers. Write to the ADC Control register to configure the ADC and begin the conversion. The bit fields in the ADC Control register can be written simultaneously: Write to the ANAIN[3:0] field to select one of the 12 analog input sources. Clear CONT to 0 to select a single-shot conversion. Write to the VREF bit to enable or disable the internal voltage reference generator. Set CEN to 1 to start the conversion. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered-down state, the ADC uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. When the conversion is complete, the ADC control logic performs the following operations: 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}. CEN resets to 0 to indicate the conversion is complete. An interrupt request is sent to the Interrupt Controller. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered-down. Continuous Conversion When configured for continuous conversion, the ADC continuously performs an analog- to-digital conversion on the selected analog input. Each new data value over-writes the previous value stored in the ADC Data registers. An interrupt is generated after each con- version. In CONTINUOUS mode, users must be aware that ADC updates are lim- ited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not seen at the next output from the ADC. The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency. The steps for setting up the ADC and initiating continuous conversion are as follows: Caution:

Analog-to-Digital Converter Z8 Encore!® 64K Series Product Specification 174 Enable the desired analog input by configuring the general-purpose I/O pins for alternate function. This disables the digital input and output driver. Write to the ADC Control register to configure the ADC for continuous conversion. The bit fields in the ADC Control register may be written simultaneously: Write to the ANAIN[3:0] field to select one of the 12 analog input sources. Set CONT to 1 to select continuous conversion. Write to the VREF bit to enable or disable the internal voltage reference generator. Set CEN to 1 to start the conversions. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation. An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0], ADCD_L[7:6]} every 256 system clock cycles. An interrupt request is sent to the Interrupt Controller when each conversion is complete. To disable continuous conversion, clear the CONT bit in the ADC Control register to 0. DMA Control of the ADC The Direct Memory Access (DMA) Controller can control operation of the ADC includ- ing analog input selection and conversion enable. For more information on the DMA and configuring for ADC operations refer to the chapter Direct Memory Access Controller on page 161.

this bit to 0 when a conversion has been completed. in progress, the conversion restarts. This bit remains 1 until the conversion is complete. selected as the ADC reference voltage. provided through the VREF pin. 1 = Continuous conversion. ADC data updated every 256 system clock cycles. package style. Do not enable unavailable analog inputs. Table 85. ADC Control Register (ADCCTL)

put is held in this register. These bits are undefined after a Reset. Table 86. ADC Data High Byte Register (ADCD_H)

These bits are reserved and are always undefined. Table 87. ADC Data Low Bits Register (ADCD_L)

grammed and erased in-circuit by either user code or through the On-Chip Debugger. which can be protected from programming and erase operations on a per sector basis. Table 88 describes the Flash memory configuration for each device in the 64K Series. Table 88. Flash Memory Configurations

Figure 35. Flash Memory Arrangement Table 89. Flash Memory Sector Addresses

128 Pages

512 Bytes per Page

Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase). Table 90. 64K Series Information Area Map

Z8 Encore!® 64K Series Product Specification 181 Timing Using the Flash Frequency Registers Before performing a program or erase operation on the Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis- ters allow programming and erasure of the Flash with system clock frequencies ranging from 20kHz through 20MHz (the valid range is limited to the device operating frequen- cies). The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Fre- quency value must contain the system clock frequency in KHz. This value is calculated using the following equation:. Flash programming and erasure are not supported for system clock fre- quencies below 20KHz, above 20MHz, or outside of the device operating frequency range. The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper Flash programming and erase operations. Flash Read Protection The user code contained within the Flash memory can be protected from external access. Programming the Flash Read Protect Option Bit prevents reading of user code by the On- Chip Debugger or by using the Flash Controller Bypass mode. Refer to the Option Bits chapter and the On-Chip Debugger chapter for more information. Flash Write/Erase Protection The 64K Series provides several levels of protection against accidental program and era- sure of the Flash memory contents. This protection is provided by the Flash Controller unlock mechanism, the Flash Sector Protect register, and the Flash Write Protect option bit. Flash Controller Unlock Mechanism At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash memory. To program or erase the Flash memory, the Flash controller must be unlocked. After unlocking the Flash Controller, the Flash can be programmed or erased. Any value written by user code to the Flash Control register or Page Select Register out of sequence will lock the Flash Controller. The proper steps to unlock the Flash Controller from user code are: Write 00H to the Flash Control register to reset the Flash Controller. FFREQ[15:0] System Clock Frequency (Hz) 1000 Caution:

Z8 Encore!® 64K Series Product Specification 182 Write the page to be programmed or erased to the Page Select register. Write the first unlock command 73H to the Flash Control register. Write the second unlock command 8CH to the Flash Control register. Re-write the page written in step 2 to the Page Select register. Flash Sector Protection The Flash Sector Protect register can be configured to prevent sectors from being pro- grammed or erased. Once a sector is protected, it cannot be unprotected by user code. The Flash Sector Protect register is cleared after reset and any previously written protection values is lost. User code must write this register in their initialization routine if they want to enable sector protection. The Flash Sector Protect register shares its Register File address with the Page Select reg- ister. The Flash Sector Protect register is accessed by writing the Flash Control register with 5EH. Once the Flash Sector Protect register is selected, it can be accessed at the Page Select Register address. When user code writes the Flash Sector Protect register, bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than 5EH to the Flash Control register de-selects the Flash Sector Protect register and re-enables access to the Page Select register. The steps to setup the Flash Sector Protect register from user code are: Write 00H to the Flash Control register to reset the Flash Controller. Write 5EH to the Flash Control register to select the Flash Sector Protect register. Read and/or write the Flash Sector Protect register which is now at Register File address FF9H. Write 00H to the Flash Control register to return the Flash Controller to its reset state. Flash Write Protection Option Bit The Flash Write Protect option bit can be enabled to block all program and erase opera- tions from user code. Refer to the Option Bits chapter for more information. Byte Programming When the Flash Controller is unlocked, writes to Flash Memory from user code will pro- gram a byte into the Flash if the address is located in the unlocked page. An erased Flash byte contains all ones (FFH). The programming operation can only be used to change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page Erase or Mass Erase operation. Byte Programming can be accomplished using the eZ8 CPU’s LDC or LDCI instructions. Refer to the eZ8 CPU User Manual for a description of the LDC and LDCI instructions.

Z8 Encore!® 64K Series Product Specification 183 While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Interrupts that occur when a Program- ming operation is in progress are serviced once the Programming operation is complete. To exit Programming mode and lock the Flash Controller, write 00H to the Flash Control register. User code cannot program Flash Memory on a page that lies in a protected sector. When user code writes memory locations, only addresses located in the unlocked page are pro- grammed. Memory writes outside of the unlocked page are ignored. Each memory location must not be programmed more than twice before an erase occurs. The proper steps to program the Flash from user code are: Write 00H to the Flash Control register to reset the Flash Controller. Write the page of memory to be programmed to the Page Select register. Write the first unlock command 73H to the Flash Control register. Write the second unlock command 8CH to the Flash Control register. Re-write the page written in step 2 to the Page Select register. Write Flash Memory using LDC or LDCI instructions to program the Flash. Repeat step 6 to program additional memory locations on the same page. Write 00H to the Flash Control register to lock the Flash Controller. Page Erase The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Page Select register identifies the page to be erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. Interrupts that occur when the Page Erase operation is in progress are serviced once the Page Erase operation is com- plete. When the Page Erase operation is complete, the Flash Controller returns to its locked state. Only pages located in unprotected sectors can be erased. The proper steps to perform a Page Erase operation are: Write 00H to the Flash Control register to reset the Flash Controller. Write the page to be erased to the Page Select register. Write the first unlock command 73H to the Flash Control register. Write the second unlock command 8CH to the Flash Control register. Caution:

Z8 Encore!® 64K Series Product Specification 184 Re-write the page written in step 2 to the Page Select register. Write the Page Erase command 95H to the Flash Control register. Mass Erase The Flash memory cannot be Mass Erased by user code. Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Programming algorithms by controlling the Flash programming signals directly. Flash Controller Bypass is recommended for gang programming applications and large volume customers who do not require in-circuit programming of the Flash memory. Refer to the document entitled Third-Party Flash Programming Support for Z8 Encore!® for more information on bypassing the Flash Controller. This document is available for download at www.zilog.com. Flash Controller Behavior in Debug Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger: The Flash Write Protect option bit is ignored. The Flash Sector Protect register is ignored for programming and erase operations. Programming operations are not limited to the page selected in the Page Select register. Bits in the Flash Sector Protect register can be written to one or zero. The second write of the Page Select register to unlock the Flash Controller is not necessary. The Page Select register can be written when the Flash Controller is unlocked. The Mass Erase command is enabled through the Flash Control register. For security reasons, flash controller allows only a single page to be opened for write/erase. When writing multiple flash pages, the flash con- troller must go through the unlock sequence again to select another page. Caution:

erase operations, or to select the Flash Sector Protect register. 8CH = Second unlock command. 5EH = Flash Sector Protect register select.

• All other commands, or any command out of sequence, lock the Flash Controller.

Table 91. Flash Control Register (FCTL)

File address with the Write-only Flash Control Register. These bits are reserved and must be 0. Table 92. Flash Status Register (FSTAT)

pages to be erased or programmed. Each Flash Page contains 512 bytes of Flash memory. of the address given by the PAGE field are erased to FFH. 0 = Information Area is not selected. address space at addresses FE00H through FFFFH. tions. Flash Memory Address[15:9] = PAGE[6:0]. Table 93. Page Select Register (FPS)

accessed only after writing the Flash Control register with 5EH. User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code). 0 = Sector n can be programmed or erased from user code. 1 = Sector n is protected and cannot be programmed or erased from user code.

• User code can only write bits from 0 to 1.

Table 94. Flash Sector Protect Register (FPROT) R/W1 = Register is accessible for Read operations. Register can be written to 1 only (via user code).

These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value. Table 95. Flash Frequency High Byte Register (FFREQH) Table 96. Flash Frequency Low Byte Register (FFREQL)

Z8 Encore!® 64K Series Product Specification PS019915-1005 Option Bits 190 Option Bits Overview Option Bits allow user configuration of certain aspects of the 64K Series operation. The feature configuration data is stored in the Flash Memory and read during Reset. The fea- tures available for control via the Option Bits are: Watch-Dog Timer time-out response selection–interrupt or Reset. Watch-Dog Timer enabled at Reset. The ability to prevent unwanted read access to user code in Flash Memory. The ability to prevent accidental programming and erasure of the user code in Flash Memory. Voltage Brown-Out configuration-always enabled or disabled during STOP mode to reduce STOP mode power consumption. Oscillator mode selection-for high, medium, and low power crystal oscillators, or external RC oscillator. Operation Option Bit Configuration By Reset Each time the Option Bits are programmed or erased, the device must be Reset for the change to take place. During any reset operation (System Reset, Reset, or STOP Mode Recovery), the Option Bits are automatically read from the Flash Memory and written to Option Configuration registers. The Option Configuration registers control operation of the devices within the 64K Series. Option Bit control is established before the device exits Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not part of the Register File and are not accessible for read or write access. Option Bit Address Space The first two bytes of Flash Memory at addresses 0000H (Table 97) and 0001H (Table 98) are reserved for the user Option Bits. The byte at Flash Memory address 0000H configures user options. The byte at Flash Memory address 0001H is reserved for future use and must remain unprogrammed.

enabled for the eZ8 CPU to acknowledge the interrupt request. ting is the default for unprogrammed (erased) Flash. 00 = On-chip oscillator configured for use with external RC networks (<4MHz). 01 = Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). setting is the default for unprogrammed (erased) Flash. setting is the default for unprogrammed (erased) Flash. Table 97. Flash Option Bits At Flash Memory Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write.

Z8 Encore!® 64K Series Product Specification 192 1 = User program code is accessible. All On-Chip Debugger commands are enabled. This setting is the default for unprogrammed (erased) Flash. Reserved These Option Bits are reserved for future use and must always be 1.This setting is the default for unprogrammed (erased) Flash. FWP—Flash Write Protect (Flash version only) Flash Memory Address 0001H Reserved These Option Bits are reserved for future use and must always be 1. This setting is the default for unprogrammed (erased) Flash. FWP Programming, Page Erase, and Mass Erase through User Code is disabled. Mass Erase is available through the On-Chip Debugger. Programming, and Page Erase are enabled for all of Flash Program Memory. Table 98. Options Bits at Flash Memory Address 0001H Note: U = Unchanged by Reset. R = Read-Only. R/W = Read/Write.

Figure 36. On-Chip Debugger Block Diagram

one-pin interface is a bi-directional open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. pin to an RS-232 interface are depicted in Figures 37 and 38. an external pull-up resistor to ensure proper operation. Figure 37. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1)

Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) execute specific instructions. The system clock operates unless in STOP mode. All enabled on-chip peripherals operate unless in STOP mode. Automatically exits HALT mode. Constantly refreshes the Watch-Dog Timer, if enabled. Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface. eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled). automatically puts the device into DEBUG mode. Clearing the DBGMODE bit in the OCD Control Register to 0.

Asserting the RESET pin Low to initiate a Reset. Driving the DBG pin Low while the device is in STOP mode initiates a System Reset. Figure 39. OCD Data Format mended maximum baud rates for sample crystal frequencies. Table 99. OCD Baud-Rate Limits

Z8 Encore!® 64K Series Product Specification 197 OCD Serial Errors The On-Chip Debugger can detect any of the following error conditions on the DBG pin: Serial Break (a minimum of nine continuous bits Low) Framing Error (received Stop bit is Low) Transmit Collision (OCD and host simultaneous transmission detected by the OCD) When the OCD detects one of these errors, it aborts any command currently in progress, transmits a Serial Break 4096 system clock cycles long back to the host, and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the inter- face, returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host transmits a Serial Break on the DBG pin when first connecting to the 64K Series devices or when recovering from an error. A Serial Break from the host resets the Auto- Baud Generator/Detector but does not reset the OCD Control register. A Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the open- drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character. Breakpoints Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If Breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP. If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK instruction, then the CPU is still enabled to service DMA and interrupt requests. The loop on BRK instruction can be used to service interrupts in the background. For interrupts to be serviced in the background, there cannot be any breakpoints in the inter- rupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine. For interrupts to be serviced in the background, interrupts must also be enabled. Debug- ging software should not automatically enable interrupts when using this feature, since interrupts are typically disabled during critical sections of code where interrupts should not occur (such as adjusting the stack pointer or modifying shared data). Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is loop- ing on a BRK instruction. When software wants to stop the CPU on the BRK instruction it is looping on, software should not set the DBGMODE bit of the OCDCTL register. The CPU may have vectored to and be in the middle of an interrupt service routine when this bit gets set. Instead, software must clear the BRKLP bit. This action allows the CPU to

DBGMODE bit and enter DEBUG mode. in DEBUG mode before these commands can be issued. memory must be erased and reprogrammed with the original data. Series products. When this option is enabled, several of the OCD commands are disabled. Table 100. On-Chip Debugger Commands

changed, this revision number changes. mode is to reset the device. written to the Flash Control register. Table 100. On-Chip Debugger Commands (Continued)

Z8 Encore!® 64K Series Product Specification 200 DBG ← 04H DBG ← OCDCTL[7:0] Read OCD Control Register (05H)—The Read OCD Control Register command reads the value of the OCDCTL register. DBG ← 05H DBG → OCDCTL[7:0] Write Program Counter (06H)—The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the Program Counter (PC) values are discarded. DBG ← 06H DBG ← ProgramCounter[15:8] DBG ← ProgramCounter[7:0] Read Program Counter (07H)—The Read Program Counter command reads the value in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFFFH. DBG ← 07H DBG → ProgramCounter[15:8] DBG → ProgramCounter[7:0] Write Register (08H)—The Write Register command writes data to the Register File. Data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If the device is not in DEBUG mode, the address and data values are discarded. If the Read Protect Option Bit is enabled, then only writes to the Flash Control Registers are allowed and all other register write data values are discarded. DBG ← 08H DBG ← {4’h0,Register Address[11:8]} DBG ← Register Address[7:0] DBG ← Size[7:0] DBG ← 1-256 data bytes Read Register (09H)—The Read Register command reads data from the Register File. Data can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for all the data values. DBG ← 09H DBG ← {4’h0,Register Address[11:8] DBG ← Register Address[7:0] DBG ← Size[7:0] DBG → 1-256 data bytes Write Program Memory (0AH)—The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). The on-chip Flash Controller must be written to and unlocked for the

Z8 Encore!® 64K Series Product Specification 201 programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded. DBG ← 0AH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes Read Program Memory (0BH)—The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for the data. DBG ← 0BH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes Write Data Memory (0CH)—The Write Data Memory command writes data to Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded. DBG ← 0CH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes Read Data Memory (0DH)—The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in DEBUG mode, this command returns FFH for the data. DBG ← 0DH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes Read Program Memory CRC (0EH)—The Read Program Memory CRC command computes and returns the CRC (cyclic redundancy check) of Program Memory using

Z8 Encore!® 64K Series Product Specification 202 the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory. DBG ← 0EH DBG → CRC[15:8] DBG → CRC[7:0] Step Instruction (10H)—The Step Instruction command steps one assembly instruction at the current Program Counter (PC) location. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command. DBG ← 10H Stuff Instruction (11H)—The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command. DBG ← 11H DBG ← opcode[7:0] Execute Instruction (12H)—The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over Breakpoints. The number of bytes to send for the instruction depends on the opcode. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command DBG ← 12H DBG ← 1-5 byte opcode On-Chip Debugger Control Register Definitions OCD Control Register The OCD Control register (Table 101) controls the state of the On-Chip Debugger. This register enters or exits DEBUG mode and enables the BRK instruction. It can also reset the Z8F642x familyZ8R642x family device.

mode, a “run” function can be implemented by writing 40H to this register. by resetting the device, it cannot be written to 0. 0 = The 64K Series device is operating in Normal mode. 1 = The 64K Series device is in DEBUG mode. BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit. 0 = BRK instruction is disabled. 1 = BRK instruction is enabled. an Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. CPU loops on the BRK instruction. 0 = BRK instruction sets DBGMODE to 1. 1 = eZ8 CPU loops on BRK instruction. These bits are reserved and must be 0. Table 101. OCD Control Register (OCDCTL)

automatically cleared to 0 when the reset finishes. the debugger and the system. CPU is running or if it is idling. 1 = The eZ8 CPU is either stopped or looping on a BRK instruction. 0 = The device is not in HALT mode. 1 = The device is in HALT mode. 0 = The Read Protect Option Bit is disabled (1). 1 = The Read Protect Option Bit is enabled (0), disabling many OCD commands. Table 102. OCD Status Register (OCDSTAT)

Z8 Encore!® 64K Series Product Specification PS019915-1005 On-Chip Oscillator 205 On-Chip Oscillator Overview The products in the 64K Series feature an on-chip oscillator for use with external crystals with frequencies from 32KHz to 20MHz. In addition, the oscillator can support external RC networks with oscillation frequencies up to 4MHz or ceramic resonators with oscilla- tion frequencies up to 20MHz. This oscillator generates the primary system clock for the internal eZ8 CPU and the majority of the on-chip peripherals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32KHz–20MHz). If an external clock generator is used, the XOUT pin must be left unconnected. When configured for use with crystal oscillators or external clock drivers, the frequency of the signal on the XIN input pin determines the frequency of the system clock (that is, no internal clock divider). In RC operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle. Operating Modes The 64K Series products support 4 different oscillator modes: On-chip oscillator configured for use with external RC networks (<4MHz). Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 10.0MHz). Maximum power for use with high frequency crystals or ceramic resonators (8.0MHz to 20.0MHz). The oscillator mode is selected through user-programmable Option Bits. Refer to the Option Bits chapter for information. Crystal Oscillator Operation Figure 40 illustrates a recommended configuration for connection with an external funda- mental-mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz crys- tal specifications are provided in Table 103. Resistor R1 is optional and limits total power dissipation by the crystal. The printed circuit board layout must add no more than 4pF of

values of capacitors C1 and C2 to decrease loading. Figure 40. Recommended 20MHz Crystal Oscillator Configuration Table 103. Recommended Crystal Oscillator Specifications (20MHz Operation)

Figure 42. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kΩ Resistor lation as soon as the supply voltage exceeds 2.7V.

Z8 Encore!® 64K Series Product Specification PS019915-1005

Electrical Characteristics

Stresses greater than those listed in Table 104 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or VSS). Table 104. Absolute Maximum Ratings

1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),

RESET, and where noted otherwise.

Z8 Encore!® 64K Series Product Specification 210 Total power dissipation 500 mW Maximum current into VDD or out of VSS 140 mA 64-Pin LQFP Maximum Ratings at –40°C to 70°C Total power dissipation 1000 mW Maximum current into VDD or out of VSS 275 mA 64-Pin LQFP Maximum Ratings at 700C to 1250C Total power dissipation 540 mW Maximum current into VDD or out of VSS 150 mA 44-Pin PLCC Maximum Ratings at –40°C to 70°C Total power dissipation 750 mW Maximum current into VDD or out of VSS 200 mA 44-Pin PLCC Maximum Ratings at 700C to 1250C Total power dissipation 295 mW Maximum current into VDD or out of VSS mA 44-pin LQFP Maximum Ratings at –40°C to 70°C Total power dissipation 750 mW Maximum current into VDD or out of VSS 200 mA 44-pin LQFP Maximum Ratings at 700C to 1250C Total power dissipation 360 mW Maximum current into VDD or out of VSS 100 mA 40-pin PDIP Maximum Ratings at –40°C to 70°C Total power dissipation 1000 mW Maximum current into VDD or out of VSS 275 mA 40-pin PDIP Maximum Ratings at 700C to 1250C Total power dissipation 540 mW Maximum current into VDD or out of VSS 150 mA Table 104. Absolute Maximum Ratings (Continued)

1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),

RESET, and where noted otherwise.

Z8 Encore!® 64K Series Product Specification 211 DC Characteristics Table 105 lists the DC characteristics of the 64K Series products. All voltages are refer- enced to VSS, the primary system ground. Table 105. DC Characteristics Port A, C, D, E, F, and G pins.

Z8 Encore!® 64K Series Product Specification 212 CXOUT XOUT Pad Capacitance 9.52 pF IPU Weak Pull-up Current 100 350 μA VDD = 3.0 - 3.6 V IDDA Active Mode Supply Current (See Figures 43 and 44) GPIO pins configured as outputs mA VDD = 3.6 V, Fsysclk = 20 MHz VDD = 3.3 V mA VDD = 3.6 V, Fsysclk = 10 MHz VDD = 3.3 V IDDH Halt Mode Supply Current (See Figures 45 and 46) GPIO pins configured as outputs mA VDD = 3.6 V, Fsysclk = 20 MHz VDD = 3.3 V mA VDD = 3.6 V, Fsysclk = 10 MHz VDD = 3.3 V IDDS Stop Mode Supply Current (See Figures 47 and 48) GPIO pins configured as outputs 520 700 650 μA VDD = 3.6 V, VBO and WDT Enabled VDD = 3.3 V μA VDD = 3.6 V, TA = 0 to 700 VBO Disabled WDT Enabled VDD = 3.3 V μA VDD = 3.6 V, TA = –40 to +1050 VBO Disabled WDT Enabled VDD = 3.3 V 250 150 μA VDD = 3.6 V, TA = –40 to +1250 VBO Disabled WDT Enabled VDD = 3.3 V 1 This condition excludes all pins that have on-chip pull-ups, when driven Low. 2 These values are provided for design guidance only and are not tested in production. Table 105. DC Characteristics (Continued)

Z8 Encore!® 64K Series Product Specification 219 On-Chip Peripheral AC and DC Electrical Characteristics Table 106. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing

66 WDT Oscillator cycles

only and are not tested in production.

Z8 Encore!® 64K Series Product Specification 220 Table 107. External RC Oscillator Electrical Characteristics and Timing soon as the supply voltage exceeds 2.7V. Table 108. Reset and STOP Mode Recovery Pin Timing

Z8 Encore!® 64K Series Product Specification 221 Table 109 list the Flash Memory electrical characteristics and timing. Table 110 lists the Watch-Dog Timer electrical characteristics and timing. Table 109. Flash Memory Electrical Characteristics and Timing Table 110. Watch-Dog Timer Electrical Characteristics and Timing

Z8 Encore!® 64K Series Product Specification 222 Table 111 provides electrical characteristics and timing information for the Analog-to-Digital Converter. Figure 49 illustrates the input frequency response of the ADC. Table 111. Analog-to-Digital Converter Electrical Characteristics and Timing

Z8 Encore!® 64K Series Product Specification 223 Figure 49. Analog-to-Digital Converter Frequency Response

Z8 Encore!® 64K Series Product Specification 224 AC Characteristics The section provides information on the AC characteristics and timing. All AC timing information assumes a standard load of 50pF on all outputs. Table 112 lists the 64K Series AC characteristics and timing. Table 112. AC Characteristics Read-only from Flash memory. require an external clock driver.

Z8 Encore!® 64K Series Product Specification 225 General Purpose I/O Port Input Data Sample Timing Figure 50 illustrates timing of the GPIO Port input sampling. Table 113 lists the GPIO port input timing. Figure 50. Port Input Sample Timing Table 113. GPIO Port Input Timing

0 Latched

Z8 Encore!® 64K Series Product Specification 231 UART Timing Figure 56 and Table 119 provide timing information for UART pins for the case where the Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that the Driver Enable polarity has been configured to be Active Low and is represented here by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data register has been loaded with data prior to CTS assertion. Figure 56. UART Timing with CTS Table 119. UART Timing with CTS

1 Bit period +

Z8 Encore!® 64K Series Product Specification 232 Figure 57 and Table 120 provide timing information for UART pins for the case where the Clear To Send input signal (CTS) is not used for flow control. In this example, it is assumed that the Driver Enable polarity has been configured to be Active Low and is rep- resented here by DE. DE asserts after the UART Transmit Data Register has been written. DE remains asserted for multiple characters as long as the Transmit Data register is writ- ten with the next character before the current character has completed. Figure 57. UART Timing without CTS Table 120. UART Timing without CTS

1 Bit period

Z8 Encore!® 64K Series Product Specification PS019915-1005 eZ8 CPU Instruction Set 233 eZ8 CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without having to be concerned with actual memory addresses or machine instruction for- mats. A program written in assembly language is called a source program. Assembly lan- guage allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called state- ments. Each statement can contain labels, operations, operands and comments. Labels can be assigned to a particular instruction step in a source program. The label iden- tifies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example. Assembly Language Source Program Example JP START ; Everything after the semicolon is a comment. START: ; A label called “START”. The first instruction (JP START) in this ; example causes program execution to jump to the point within the ; program where the START label occurs. LD R4, R7 ; A Load (LD) instruction with two operands. The first operand, ; Working Register R4, is the destination. The second operand, ; Working Register R7, is the source. The contents of R7 is ; written into R4. LD 234H, #%01 ; Another Load (LD) instruction with two operands. ; The first operand, Extended Mode Register Address 234H, ; identifies the destination. The second operand, Immediate Data

Z8 Encore!® 64K Series Product Specification 234 ; value 01H, is the source. The value 01H is written into the ; Register at address 234H. Assembly Language Syntax For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually has the operands in the order ’source, destination’, but ordering is opcode-dependent. The fol- lowing instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. Example 1: If the contents of Registers 43H and 08H are added and the result is stored in 43H, the assembly syntax and resulting object code is: Example 2: In general, when an instruction format requires an 8-bit register address, that address can specify any register location in the range 0 - 255 or, using Escaped Mode Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H, the assembly syntax and resulting object code is: See the device-specific Product Specification to determine the exact register file range available. The register file size varies, depending on the device type. eZ8 CPU Instruction Notation In the eZ8 CPU Instruction Summary and Description sections, the operands, condition codes, status flags, and address modes are represented by a notational shorthand that is described in Table 121. Assembly Language Syntax Example 1 Assembly Language Code ADD 43H, 08H (ADD dst, src) Object Code (OPC src, dst) Assembly Language Syntax Example 2 Assembly Language Code ADD 43H, (ADD dst, src) Object Code (OPC src, dst)

Z8 Encore!® 64K Series Product Specification 235 Table 122 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections. Table 121. Notational Shorthand b Bit b b represents a value from 0 to 7 (000B to 111B). cc Condition Code See Condition Codes overview in the eZ8 CPU User Manual. DA Direct Address Addrs Addrs. represents a number in the range of 0000H to FFFFH ER Extended Addressing Register Reg Reg. represents a number in the range of 000H to FFFH IM Immediate Data #Data Data is a number between 00H to FFH Ir Indirect Working Register @Rn n = 0 –15 IR Indirect Register @Reg Reg. represents a number in the range of 00H to FFH Irr Indirect Working Register Pair @RRp p = 0, 2, 4, 6, 8, 10, 12, or 14 IRR Indirect Register Pair @Reg Reg. represents an even number in the range 00H to FEH p Polarity p Polarity is a single bit binary value of either 0B or 1B. r Working Register Rn n = 0 – 15 R Register Reg Reg. represents a number in the range of 00H to FFH RA Relative Address X X represents an index in the range of +127 to –128 which is an offset relative to the address of the next instruction rr Working Register Pair RRp p = 0, 2, 4, 6, 8, 10, 12, or 14 RR Register Pair Reg Reg. represents an even number in the range of 00H to FEH Vector Vector Address Vector Vector represents a number in the range of 00H to FFH X Indexed #Index The register or register pair to be indexed is offset by the signed Index value (#Index) in a +127 to -128 range.

Table 122. Additional Symbols

ation decides if the conditional jump is executed. Table 123. Condition Codes

Table 124. Arithmetic Instructions

Table 125. Bit Manipulation Instructions Table 126. Block Transfer Instructions Table 124. Arithmetic Instructions (Continued)

Table 127. CPU Control Instructions Table 128. Load Instructions

Table 129. Logical Instructions Table 130. Program Control Instructions

required for the instruction execution. Table 131. Rotate and Shift Instructions Table 132. eZ8 CPU Instruction Summary

• = Value is a function of the result of the operation.

Table 132. eZ8 CPU Instruction Summary (Continued)

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

not be tested and are used for Binary-Coded Decimal (BCD) arithmetic. positions in the Flags Register. tion restores the value saved on the stack into the Flags Register. Figure 58. Flags Register

Table 132. Figures 60 and 61 provide information on each of the eZ8 CPU instructions. Figure 59. Opcode Map Cell Description

Z8 Encore!® 64K Series Product Specification 254 Table 132. Opcode Map Abbreviations b Bit position IRR Indirect Register Pair cc Condition code p Polarity (0 or 1) X 8-bit signed index or displacement r 4-bit Working Register DA Destination address R 8-bit register ER Extended Addressing register r1, R1, Ir1, Irr1, IR1, rr1, RR1, IRR1, ER1 Destination address IM Immediate data value r2, R2, Ir2, Irr2, IR2, rr2, RR2, IRR2, ER2 Source address Ir Indirect Working Register RA Relative IR Indirect register rr Working Register Pair Irr Indirect Working Register Pair RR Register Pair

Figure 60. First Opcode Map

Figure 61. Second Opcode Map after 1FH

Figure 64. 44-Lead Plastic Lead Chip Carrier Package (PLCC) Figure 65. 64-Lead Low-Profile Quad Flat Package (LQFP)

1. LEADS ARE COPLANAR WITHIN 0.004".
2. CONTROLLING DIMENSION : INCH

1.27 BSC

0.050 BSC

Figure 67. 80-Lead Quad-Flat Package (QFP)

0.80 BSC

Ordering Information

Z8 Encore!® 64K Series Product Specification 262 Z8F642x with 64KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F6421PM020SC 64KB 4KB PDIP 40-pin package Z8F6421AN020SC 64KB 4KB LQFP 44-pin package Z8F6421VN020SC 64KB 4KB PLCC 44-pin package Z8F6422AR020SC 64KB 4KB LQFP 64-pin package Z8F6422VS020SC 64KB 4KB PLCC 68-pin package Z8F6423FT020SC 64KB 4KB QFP 80-pin package Extended Temperature: –40° to +105°C Z8F6421PM020EC 64KB 4KB PDIP 40-pin package Z8F6421AN020EC 64KB 4KB LQFP 44-pin package Z8F6421VN020EC 64KB 4KB PLCC 44-pin package Z8F6422AR020EC 64KB 4KB LQFP 64-pin package Z8F6422VS020EC 64KB 4KB PLCC 68-pin package Z8F6423FT020EC 64KB 4KB QFP 80-pin package Automotive/Industrial Temperature: –40° to +125°C Z8F6421PM020AC 64KB 4KB PDIP 40-pin package Z8F6421AN020AC 64KB 4KB LQFP 44-pin package Z8F6421VN020AC 64KB 4KB PLCC 44-pin package Z8F6422AR020AC 64KB 4KB LQFP 64-pin package Z8F6422VS020AC 64KB 4KB PLCC 68-pin package Z8F6423FT020AC 64KB 4KB QFP 80-pin package Note: Replace C with G for lead-free packaging.

Z8 Encore!® 64K Series Product Specification 263 Z8F482x with 48KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F4821PM020SC 48KB 4KB PDIP 40-pin package Z8F4821AN020SC 48KB 4KB LQFP 44-pin package Z8F4821VN020SC 48KB 4KB PLCC 44-pin package Z8F4822AR020SC 48KB 4KB LQFP 64-pin package Z8F4822VS020SC 48KB 4KB PLCC 68-pin package Z8F4823FT020SC 48KB 4KB QFP 80-pin package Extended Temperature: –40° to +105°C Z8F4821PM020EC 48KB 4KB PDIP 40-pin package Z8F4821AN020EC 48KB 4KB LQFP 44-pin package Z8F4821VN020EC 48KB 4KB PLCC 44-pin package Z8F4822AR020EC 48KB 4KB LQFP 64-pin package Z8F4822VS020EC 48KB 4KB PLCC 68-pin package Z8F4823FT020EC 48KB 4KB QFP 80-pin package Automotive/Industrial Temperature: –40° to +125°C Z8F4821PM020AC 48KB 4KB PDIP 40-pin package Z8F4821AN020AC 48KB 4KB LQFP 44-pin package Z8F4821VN020AC 48KB 4KB PLCC 44-pin package Z8F4822AR020AC 48KB 4KB LQFP 64-pin package Z8F4822VS020AC 48KB 4KB PLCC 68-pin package Z8F4823FT020AC 48KB 4KB QFP 80-pin package Part Number Flash RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA Note: Replace C with G for lead-free packaging.

Z8 Encore!® 64K Series Product Specification 264 Z8F322x with 32KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F3221PM020SC 32KB 2KB PDIP 40-pin package Z8F3221AN020SC 32KB 2KB LQFP 44-pin package Z8F3221VN020SC 32KB 2KB PLCC 44-pin package Z8F3222AR020SC 32KB 2KB LQFP 64-pin package Z8F3222VS020SC 32KB 2KB PLCC 68-pin package Extended Temperature: –40° to 105°C Z8F3221PM020EC 32KB 2KB PDIP 40-pin package Z8F3221AN020EC 32KB 2KB LQFP 44-pin package Z8F3221VN020EC 32KB 2KB PLCC 44-pin package Z8F3222AR020EC 32KB 2KB LQFP 64-pin package Z8F3222VS020EC 32KB 2KB PLCC 68-pin package Automotive/Industrial Temperature: –40° to 125°C Z8F3221PM020AC 32KB 2KB PDIP 40-pin package Z8F3221AN020AC 32KB 2KB LQFP 44-pin package Z8F3221VN020AC 32KB 2KB PLCC 44-pin package Z8F3222AR020AC 32KB 2KB LQFP 64-pin package Z8F3222VS020AC 32KB 2KB PLCC 68-pin package Part Number Flash RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA Note: Replace C with G for lead-free packaging.

Z8 Encore!® 64K Series Product Specification 265 Z8F242x with 24KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F2421PM020SC 24KB 2KB PDIP 40-pin package Z8F2421AN020SC 24KB 2KB LQFP 44-pin package Z8F2421VN020SC 24KB 2KB PLCC 44-pin package Z8F2422AR020SC 24KB 2KB LQFP 64-pin package Z8F2422VS020SC 24KB 2KB PLCC 68-pin package Extended Temperature: –40° to 105°C Z8F2421PM020EC 24KB 2KB PDIP 40-pin package Z8F2421AN020EC 24KB 2KB LQFP 44-pin package Z8F2421VN020EC 24KB 2KB PLCC 44-pin package Z8F2422AR020EC 24KB 2KB LQFP 64-pin package Z8F2422VS020EC 24KB 2KB PLCC 68-pin package Automotive/Industrial Temperature: –40° to 125°C Z8F2421PM020AC 24KB 2KB PDIP 40-pin package Z8F2421AN020AC 24KB 2KB LQFP 44-pin package Z8F2421VN020AC 24KB 2KB PLCC 44-pin package Z8F2422AR020AC 24KB 2KB LQFP 64-pin package Z8F2422VS020AC 24KB 2KB PLCC 68-pin package Part Number Flash RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA Note: Replace C with G for lead-free packaging.

Z8 Encore!® 64K Series Product Specification 266 For technical and customer support, hardware and software development tools, visit the ZiLOG web site at www.zilog.com. The latest released version of ZDS can be down- loaded from this site. Z8F162x with 16KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F1621PM020SC 16KB 2KB PDIP 40-pin package Z8F1621AN020SC 16KB 2KB LQFP 44-pin package Z8F1621VN020SC 16KB 2KB PLCC 44-pin package Z8F1622AR020SC 16KB 2KB LQFP 64-pin package Z8F1622VS020SC 16KB 2KB PLCC 68-pin package Extended Temperature: –40° to +105°C Z8F1621PM020EC 16KB 2KB PDIP 40-pin package Z8F1621AN020EC 16KB 2KB LQFP 44-pin package Z8F1621VN020EC 16KB 2KB PLCC 44-pin package Z8F1622AR020EC 16KB 2KB LQFP 64-pin package Z8F1622VS020EC 16KB 2KB PLCC 68-pin package Automotive/Industrial Temperature: –40° to +125°C Z8F1621PM020AC 16KB 2KB PDIP 40-pin package Z8F1621AN020AC 16KB 2KB LQFP 44-pin package Z8F1621VN020AC 16KB 2KB PLCC 44-pin package Z8F1622AR020AC 16KB 2KB LQFP 64-pin package Z8F1622VS020AC 16KB 2KB PLCC 68-pin package Z8F64200100KIT Development Kit Part Number Flash RAM I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels I2C SPI UARTs with IrDA Note: Replace C with G for lead-free packaging.

Z8 Encore!® 64K Series Product Specification 267 Part Number Suffix Designations Example: Part number Z8F6421AN020SC is an 8-bit microcontroller product in an LQFP package, using 44 pins, operating with a maximum 20MHz external clock frequency over a 0ºC to +70ºC temperature range and built using the Plastic-Standard environmental flow. F 64 21 A N 020 S C Environmental Flow: C = Plastic Standard G = Lead Free Package Temperature Range (°C): S = Standard, 0 to 70 E = Extended, –40 to +105 A = Automotive/Industrial, –40 to +125 Speed: 020 = 20MHz Pin Count: M = 40 pins N = 44 pins R = 64 pins S = 68 pins T = 80 pins Package: A = LQFP F = QFP P = PDIP V = PLCC Device Type Memory Size:

64 KB Flash, 4 KB RAM

48 KB Flash, 4 KB RAM

32 KB Flash, 2 KB RAM

24 KB Flash, 2 KB RAM

16 KB Flash, 2 KB RAM

Memory Type: F = Flash Device Family

Z8 Encore!® 64K Series Product Specification 268 Document Information Document Number Description The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table: PS Product Specification 0199 Unique Document Number Revision Number 0204 Month and Year Published

Z8 Encore!® 64K Series Product Specification 269 Customer Feedback Form The Z8 Encore!® 64K Series Product Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Customer Information Product Information Return Information ZiLOG, Inc. San Jose, CA 95126 Fax: (408) 558-8536 Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. Name Country Company Phone Address Fax City/State/Zip E-Mail Part #, Serial #, Board Fab #, or Rev. # Software Version Document Number Host Computer Description/Type

Z8 Encore!® 64K Series Product Specification 270 Index Symbols # 236 % 236 @ 236 Numerics 10-bit ADC 4 40-lead plastic dual-inline package 257 44-lead low-profile quad flat package 258 44-lead plastic lead chip carrier package 259 64-lead low-profile quad flat package 259 68-lead plastic lead chip carrier package 260 80-lead quad flat package 261 A absolute maximum ratings 209 AC characteristics 224 ADC 238 architecture 171 automatic power-down 172 block diagram 172 continuous conversion 173 control register 175 control register definitions 175 data high byte register 176 data low bits register 176 DMA control 174 electrical characteristics and timing 222 operation 172 single-shot conversion 173 ADCCTL register 175 ADCDH register 176 ADCDL register 176 ADCX 238 ADD 238 add - extended addressing 238 add with carry 238 add with carry - extended addressing 238 additional symbols 236 address space 17 ADDX 238 analog signals 14 analog-to-digital converter (ADC) 171 AND 241 ANDX 241 arithmetic instructions 238 assembly language programming 233 assembly language syntax 234 B B 236 b 235 baud rate generator, UART 108 BCLR 239 binary number suffix 236 BIT 239 bit 235 clear 239 manipulation instructions 239 set 239 set or clear 239 swap 239 test and jump 241 test and jump if non-zero 241 test and jump if zero 241 bit jump and test if non-zero 241 bit swap 242 block diagram 3 block transfer instructions 239 BRK 241 BSET 239 BSWAP 239, 242 BTJ 241 BTJNZ 241 BTJZ 241 C CALL procedure 241 capture mode 89 capture/compare mode 89

Z8 Encore!® 64K Series Product Specification 271 cc 235 CCF 240 characteristics, electrical 209 clear 240 clock phase (SPI) 128 CLR 240 COM 241 compare 89 compare - extended addressing 238 compare mode 89 compare with carry 238 compare with carry - extended addressing 238 complement 241 complement carry flag 239, 240 condition code 235 continuous conversion (ADC) 173 continuous mode 89 control register definition, UART 109 control register, I2C 155 counter modes 89 CP 238 CPC 238 CPCX 238 CPU and peripheral overview 3 CPU control instructions 240 CPX 238 customer feedback form 269 customer information 269 D DA 235, 238 data register, I2C 152 DC characteristics 211 debugger, on-chip 193 DEC 238 decimal adjust 238 decrement 238 decrement and jump non-zero 241 decrement word 238 DECW 238 destination operand 236 device, port availability 51 DI 240 direct address 235 direct memory access controller 161 disable interrupts 240 DJNZ 241 DMA address high nibble register 165 configuring for DMA_ADC data transfer 163 confiigurting DMA0-1 data transfer 162 control of ADC 174 control register 163 control register definitions 163 controller 5 DMA_ADC address register 167 DMA_ADC control register 168 DMA_ADC operation 162 end address low byte register 166 I/O address register 165 operation 161 start/current address low byte register 166 status register 169 DMAA_STAT register 169 DMAACTL register 168 DMAxCTL register 164 DMAxEND register 167 DMAxH register 165 DMAxI/O address (DMAxIO) 165 DMAxIO register 165 DMAxSTART register 166 document number description 268 dst 236 E EI 240 electrical characteristics 209 ADC 222 flash memory and timing 221 GPIO input data sample timing 225 watch-dog timer 221 enable interrupt 240 ER 235 extended addressing register 235 external pin reset 46 external RC oscillator 220

Z8 Encore!® 64K Series Product Specification 272 eZ8 CPU features 3 eZ8 CPU instruction classes 238 eZ8 CPU instruction notation 234 eZ8 CPU instruction set 233 eZ8 CPU instruction summary 242 F FCTL register 185 features, Z8 Encore! 1 first opcode map 255 FLAGS 236 flags register 236 flash controller 4 option bit address space 190 option bit configuration - reset 190 program memory address 0001H 192 flash memory arrangement 179 byte programming 182 code protection 181 configurations 178 control register definitions 185 controller bypass 184 electrical characteristics and timing 221 flash control register 185 flash status register 186 frequency high and low byte registers 189 mass erase 184 operation 180 operation timing 181 page erase 183 page select register 187 FPS register 187 FSTAT register 186 G gated mode 89 general-purpose I/O 51 GPIO 4, 51 alternate functions 52 architecture 52 control register definitions 54 input data sample timing 225 interrupts 54 port A-H address registers 55 port A-H alternate function sub-registers 57 port A-H control registers 56 port A-H data direction sub-registers 57 port A-H high drive enable sub-registers 59 port A-H input data registers 60 port A-H output control sub-registers 58 port A-H output data registers 61 port A-H STOP mode recovery sub-registers 59 port availability by device 51 port input timing 225 port output timing 226 H H 236 HALT 240 halt mode 50, 240 hexadecimal number prefix/suffix 236 I I2C 4 10-bit address read transaction 150 10-bit address transaction 147 10-bit addressed slave data transfer format 147 10-bit receive data format 150 7-bit address transaction 145 7-bit address, reading a transaction 149 7-bit addressed slave data transfer format 144, 145, 146 7-bit receive data transfer format 149 baud high and low byte registers 156, 158, 160 C status register 153 control register definitions 152 controller 139 controller signals 13 interrupts 141 operation 140 SDA and SCL signals 141 stop and start conditions 143

Z8 Encore!® 64K Series Product Specification 273 I2CBRH register 157, 158, 160 I2CBRL register 157 I2CCTL register 155 I2CDATA register 153 I2CSTAT register 153 IM 235 immediate data 235 immediate operand prefix 236 INC 238 increment 238 increment word 238 INCW 238 indexed 235 indirect address prefix 236 indirect register 235 indirect register pair 235 indirect working register 235 indirect working register pair 235 infrared encoder/decoder (IrDA) 120 instruction set, ez8 CPU 233 instructions ADC 238 ADCX 238 ADD 238 ADDX 238 AND 241 ANDX 241 arithmetic 238 BCLR 239 BIT 239 bit manipulation 239 block transfer 239 BRK 241 BSET 239 BSWAP 239, 242 BTJ 241 BTJNZ 241 BTJZ 241 CALL 241 CCF 239, 240 CLR 240 COM 241 CP 238 CPC 238 CPCX 238 CPU control 240 CPX 238 DA 238 DEC 238 DECW 238 DI 240 DJNZ 241 EI 240 HALT 240 INC 238 INCW 238 IRET 241 JP 241 LD 240 LDC 240 LDCI 239, 240 LDE 240 LDEI 239 LDX 240 LEA 240 load 240 logical 241 MULT 238 NOP 240 OR 241 ORX 241 POP 240 POPX 240 program control 241 PUSH 240 PUSHX 240 RCF 239, 240 RET 241 RL 242 RLC 242 rotate and shift 242 RR 242 RRC 242 SBC 239 SCF 239, 240 SRA 242 SRL 242 SRP 240

Z8 Encore!® 64K Series Product Specification 274 STOP 240 SUB 239 SUBX 239 SWAP 242 TCM 239 TCMX 239 TM 239 TMX 239 TRAP 241 watch-dog timer refresh 240 XOR 241 XORX 241 instructions, eZ8 classes of 238 interrupt control register 74 interrupt controller 5, 62 architecture 62 interrupt assertion types 65 interrupt vectors and priority 65 operation 64 register definitions 66 software interrupt assertion 65 interrupt edge select register 72 interrupt port select register 73 interrupt request 0 register 66 interrupt request 1 register 67 interrupt request 2 register 68 interrupt return 241 interrupt vector listing 62 interrupts not acknowledge 141 receive 141 SPI 131 transmit 141 UART 106 introduction 1 IR 235 Ir 235 IrDA architecture 120 block diagram 120 control register definitions 124 operation 121 receiving data 122 transmitting data 121 IRET 241 IRQ0 enable high and low bit registers 69 IRQ1 enable high and low bit registers 70 IRQ2 enable high and low bit registers 71 IRR 235 Irr 235 J JP 241 jump, conditional, relative, and relative conditional 241 L LD 240 LDC 240 LDCI 239, 240 LDE 240 LDEI 239, 240 LDX 240 LEA 240 load 240 load constant 239 load constant to/from program memory 240 load constant with auto-increment addresses 240 load effective address 240 load external data 240 load external data to/from data memory and auto- increment addresses 239 load external to/from data memory and auto-incre- ment addresses 240 load instructions 240 load using extended addressing 240 logical AND 241 logical AND/extended addressing 241 logical exclusive OR 241 logical exclusive OR/extended addressing 241 logical instructions 241 logical OR 241 logical OR/extended addressing 241 low power modes 49 LQFP 44 lead 258

Z8 Encore!® 64K Series Product Specification 275 64 lead 259 M master interrupt enable 64 master-in, slave-out and-in 127 memory program 18 MISO 127 mode capture 89 capture/compare 89 continuous 89 counter 89 gated 89 one-shot 89 PWM 89 modes 89 MOSI 127 MULT 238 multiply 238 multiprocessor mode, UART 104 N NOP (no operation) 240 not acknowledge interrupt 141 notation b 235 cc 235 DA 235 ER 235 IM 235 IR 235 Ir 235 IRR 235 Irr 235 p 235 R 235 r 235 RA 235 RR 235 rr 235 vector 235 X 235 notational shorthand 235 O OCD architecture 193 auto-baud detector/generator 196 baud rate limits 196 block diagram 193 breakpoints 197 commands 198 control register 202 data format 196 DBG pin to RS-232 Interface 194 debug mode 195 debugger break 241 interface 194 serial errors 197 status register 204 timing 227 OCD commands execute instruction (12H) 202 read data memory (0DH) 201 read OCD control register (05H) 200 read OCD revision (00H) 199 read OCD status register (02H) 199 read program counter (07H) 200 read program memory (0BH) 201 read program memory CRC (0EH) 201 read register (09H) 200 step instruction (10H) 202 stuff instruction (11H) 202 write data memory (0CH) 201 write OCD control register (04H) 199 write program counter (06H) 200 write program memory (0AH) 200 write register (08H) 200 on-chip debugger 5 on-chip debugger (OCD) 193 on-chip debugger signals 15 on-chip oscillator 205 one-shot mode 89 opcode map

Z8 Encore!® 64K Series Product Specification 276 abbreviations 254 cell description 253 first 255 second after 1FH 256 Operational Description 98 OR 241 ordering information 262 ORX 241 oscillator signals 14 P p 235 packaging LQFP 44 lead 258 64 lead 259 PDIP 257 PLCC 44 lead 259 68 lead 260 QFP 261 part number description 267 part selection guide 2 PC 236 PDIP 257 peripheral AC and DC electrical characteristics 219 PHASE=0 timing (SPI) 129 PHASE=1 timing (SPI) 130 pin characteristics 16 PLCC 44 lead 259 68-lead 260 polarity 235 POP 240 pop using extended addressing 240 POPX 240 port availability, device 51 port input timing (GPIO) 225 port output timing, GPIO 226 power supply signals 15 power-down, automatic (ADC) 172 power-on and voltage brown-out 219 power-on reset (POR) 44 problem description or suggestion 269 product information 269 program control instructions 241 program counter 236 program memory 18 PUSH 240 push using extended addressing 240 PUSHX 240 PWM mode 89 PxADDR register 55 PxCTL register 56 Q QFP 261 R R 235 r 235 RA register address 235 RCF 239, 240 receive 10-bit data format (I2C) 150 7-bit data transfer format (I2C) 149 IrDA data 122 receive interrupt 141 receiving UART data-interrupt-driven method 103 receiving UART data-polled method 102 register 136, 165, 235 ADC control (ADCCTL) 175 ADC data high byte (ADCDH) 176 ADC data low bits (ADCDL) 176 baud low and high byte (I2C) 156, 158, 160 baud rate high and low byte (SPI) 138 control (SPI) 133 control, I2C 155 data, SPI 133 DMA status (DMAA_STAT) 169 DMA_ADC address 167 DMA_ADC control DMAACTL) 168 DMAx address high nibble (DMAxH) 165 DMAx control (DMAxCTL) 164

Z8 Encore!® 64K Series Product Specification 277 DMAx end/address low byte (DMAxEND) 167 DMAx start/current address low byte register (DMAxSTART) 166 flash control (FCTL) 185 flash high and low byte (FFREQH and FRE- EQL) 189 flash page select (FPS) 187 flash status (FSTAT) 186 GPIO port A-H address (PxADDR) 55 GPIO port A-H alternate function sub-registers GPIO port A-H control address (PxCTL) 56 GPIO port A-H data direction sub-registers 57 I2C baud rate high (I2CBRH) 157, 158, 160 I2C control (I2CCTL) 155 I2C data (I2CDATA) 153 I2C status 153 I2C status (I2CSTAT) 153 I2Cbaud rate low (I2CBRL) 157 mode, SPI 136 OCD control 202 OCD status 204 SPI baud rate high byte (SPIBRH) 138 SPI baud rate low byte (SPIBRL) 138 SPI control (SPICTL) 134 SPI data (SPIDATA) 133 SPI status (SPISTAT) 135 status, I2C 153 status, SPI 135 UARTx baud rate high byte (UxBRH) 116 UARTx baud rate low byte (UxBRL) 116 UARTx Control 0 (UxCTL0) 112, 115 UARTx control 1 (UxCTL1) 113 UARTx receive data (UxRXD) 110 UARTx status 0 (UxSTAT0) 110 UARTx status 1 (UxSTAT1) 112 UARTx transmit data (UxTXD) 109 watch-dog timer control (WDTCTL) 94 watch-dog timer reload high byte (WDTH) 96 watch-dog timer reload low byte (WDTL) 97 watch-dog timer reload upper byte (WDTU) 96 register file 17 register file address map 21 register pair 235 register pointer 236 reset and STOP mode characteristics 43 and STOP mode recovery 43 carry flag 239 controller 5 sources 44 RET 241 return 241 return information 269 RL 242 RLC 242 rotate and shift instructions 242 rotate left 242 rotate left through carry 242 rotate right 242 rotate right through carry 242 RP 236 RR 235, 242 rr 235 RRC 242 S SBC 239 SCF 239, 240 SCK 127 SDA and SCL (IrDA) signals 141 second opcode map after 1FH 256 serial clock 127 serial peripheral interface (SPI) 125 set carry flag 239, 240 set register pointer 240 shift right arithmetic 242 shift right logical 242 signal descriptions 13 single-shot conversion (ADC) 173 SIO 5 slave data transfer formats (I2C) 147 slave select 128 software trap 241 source operand 236 SP 236 SPI

Z8 Encore!® 64K Series Product Specification 278 architecture 125 baud rate generator 132 baud rate high and low byte register 138 clock phase 128 configured as slave 126 control register 133 control register definitions 133 data register 133 error detection 131 interrupts 131 mode fault error 131 mode register 136 multi-master operation 130 operation 126 overrun error 131 signals 127 single master, multiple slave system 126 single master, single slave system 125 status register 135 timing, PHASE = 0 129 timing, PHASE=1 130 SPI controller signals 13 SPI mode (SPIMODE) 136 SPIBRH register 138 SPIBRL register 138 SPICTL register 134 SPIDATA register 133 SPIMODE register 136 SPISTAT register 135 SRA 242 src 236 SRL 242 SRP 240 SS, SPI signal 127 stack pointer 236 status register, I2C 153 STOP 240 STOP mode 49, 240 STOP mode recovery sources 47 using a GPIO port pin transition 48 using watch-dog timer time-out 48 SUB 239 subtract 239 subtract - extended addressing 239 subtract with carry 239 subtract with carry - extended addressing 239 SUBX 239 SWAP 242 swap nibbles 242 symbols, additional 236 system and core resets 44 T TCM 239 TCMX 239 test complement under mask 239 test complement under mask - extended addressing 239 test under mask 239 test under mask - extended addressing 239 timer signals 14 timers 5, 75 architecture 75 block diagram 76 capture mode 80, 89 capture/compare mode 83, 89 compare mode 81, 89 continuous mode 77, 89 counter mode 78 counter modes 89 gated mode 82, 89 one-shot mode 76, 89 operating mode 76 PWM mode 79, 89 reading the timer count values 84 reload high and low byte registers 85 timer control register definitions 84 timer output signal operation 84 timers 0-3 control 0 registers 88 control 1 registers 88 high and low byte registers 84, 87 TM 239 TMX 239 transmit IrDA data 121

Z8 Encore!® 64K Series Product Specification 279 transmit interrupt 141 transmitting UART data-interrupt-driven method 101 transmitting UART data-polled method 100 TRAP 241 U UART 4 architecture 98 asynchronous data format without/with parity 100 baud rate generator 108 baud rates table 117 control register definitions 109 controller signals 14 data format 99 interrupts 106 multiprocessor mode 104 receiving data using interrupt-driven method 103 receiving data using the polled method 102 transmitting data using the interrupt-driven method 101 transmitting data using the polled method 100 x baud rate high and low registers 115 x control 0 and control 1 registers 112 x status 0 and status 1 registers 110, 112 UxBRH register 116 UxBRL register 116 UxCTL0 register 112, 115 UxCTL1 register 113 UxRXD register 110 UxSTAT0 register 110 UxSTAT1 register 112 UxTXD register 109 V vector 235 voltage brown-out reset (VBR) 45 W watch-dog timer approximate time-out delay 92 approximate time-out delays 91 CNTL 46 control register 94 electrical characteristics and timing 221 interrupt in normal operation 92 interrupt in STOP mode 92 operation 91 refresh 92, 240 reload unlock sequence 93 reload upper, high and low registers 95 reset 46 reset in normal operation 93 reset in STOP mode 93 time-out response 92 WDTCTL register 94 WDTH register 96 WDTL register 97 working register 235 working register pair 235 WTDU register 96 X X 235 XOR 241 XORX 241 Z Z8 Encore! block diagram 3 features 1 introduction 1 part selection guide 2