Microcontroller

Z8F1232

Zilog, Inc.

High-Performance 8-Bit Microcontrollers

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Z8 Encore!® F0830 Series Product Specification ii DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications or technology described is intended to suggest possible uses and may be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES or TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES or TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. Warning:

Z8 Encore!® F0830 Series Product Specification iii

Revision History

Each instance in this document’s revision history reflects a change from its previous edi- tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Date Revision Level Chapter/Section Description Page No. Dec 2012

13 GPIO Modified GPIO Port D0 language in Shared

Reset Pin section and Port Alternate Func- tion Mapping table. , 36 Sep 2011

12 LED Drive Enable Register Clarified statement surrounding the Alternate

Function Register as it relates to the LED function; revised Sector Based Flash Protec- tion description; revised Packaging chapter. 115, 199 Dec 2007 11 n/a Updated all instances of Z8 Encore! XP F0830 to Z8 Encore! F0830. All Nov 2007

10 DC Characteristics, On-Chip

Peripheral AC and DC Electri- cal Characteristics Updated Tables 116 and and 122. 185 193 Sep 2007

09 Timers, PWM SINGLE OUT-

PUT Mode, PWM DUAL OUT- PUT Mode, Analog-to-Digital Converter, Reference Buffer. Updated Figures 2 and 4, Table 4. 8 , 9, 11, 68, 74, 75, 98, 101 Apr 2007

08 Optimizing NVDS Memory

Usage for Execution Speed, On-Chip Peripheral AC and DC

Electrical Characteristics

Added a note under Table 93 in Nonvolatile Data Storage chapter. Updated Table 121 and Table 122 in Electrical Characteristics chapter. Other style updates. 137 193, 193 Dec 2006 07 General Purpose Input/Output Added PD0 in Table 16. 38 Overview, Interrupt Controller Changed the number of interrupts to 17. 1,5, 53 Nonvolatile Data Storage Updated chapter. 136 Oscillator Control Register Defi- nitions, AC Characteristics, On- Chip Peripheral AC and DC Updated Tables 117 and 122. Added Figure 24. 156 189, 193 Ordering Information Updated Part Number Suffix Designations. 205 n/a Removed Preliminary stamp from footer. All

PS025113-1212 Table of Contents Z8 Encore!® F0830 Series Product Specification iv Table of Contents

PS025113-1212 Table of Contents Z8 Encore!® F0830 Series Product Specification v

PS025113-1212 Table of Contents Z8 Encore!® F0830 Series Product Specification vi

PS025113-1212 Table of Contents Z8 Encore!® F0830 Series Product Specification vii

PS025113-1212 Table of Contents Z8 Encore!® F0830 Series Product Specification viii

PS025113-1212 Table of Contents Z8 Encore!® F0830 Series Product Specification ix

Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) . . 45

Table 118. Power-On Reset and Voltage Brown- Out Electrical Characteristics and Tim-

Z8 Encore!® F0830 Series Product Specification Overview Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller products based on the 8-bit eZ8 CPU. The Z8 Encore! F0830 Series products expand on Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capabil- ity allows for faster development time and program changes in the field. The new eZ8 CPU is upward-compatible with existing Z8 CPU instructions. The rich peripheral set of Z8 Encore! F0830 Series makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices and sensors.

Features

The key features of Z8 Encore! F0830 Series MCU include:

20 MHz eZ8 CPU
Up to 12 KB Flash memory with in-circuit programming capability
Up to 256 B register RAM
64 B Nonvolatile Data Storage (NVDS)
Up to 25 I/O pins depending upon package
Internal Precision Oscillator (IPO)
External crystal oscillator
Two enhanced 16-bit timers with capture, compare and PWM capability
Watchdog Timer (WDT) with dedicated internal RC oscillator
Single-pin, On-Chip Debugger (OCD)
Optional 8-channel, 10-bit Analog-to-Digital Converter (ADC)
On-chip analog comparator
Up to 17 interrupt sources
V oltage Brown-Out (VBO) protection
Power-On Reset (POR)
2.7 V to 3.6 V operating voltage
Up to thirteen 5 V-tolerant input pins
20- and 28-pin packages
0°C to +70°C standard temperature range and –40°C to +105°C extended temperature operating ranges

Series product line. See the Ordering Information chapter on page 200 for details. Table 1. Z8 Encore! F0830 Series Family Part Selection Guide

PS025113-1212 CPU and Peripheral Overview Z8 Encore!® F0830 Series Product Specification CPU and Peripheral Overview The eZ8 CPU, Zilog’s latest 8-bit CPU, meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include:

Direct register-to-register architecture allows each register to function as an accumula- tor, improving execution time and decreasing the required program memory
Software stack allows much greater depth in subroutine calls and interrupts than hard- ware stacks
Compatible with existing Z8 CPU code
Expanded internal register file allows access up to 4 KB
New instructions improve execution efficiency for code developed using high-level programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT and SRL
New instructions support 12-bit linear addressing of the register file
Up to 10 MIPS operation
C Compiler-friendly
2 to 9 clock cycles per instruction For more information about the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download on www.zilog.com. General Purpose Input/Output The Z8 Encore! F0830 Series features up to 25 port pins (Ports A–D) for general-purpose input/output (GPIO). The number of GPIO pins available is a function of package. Each pin is individually programmable. Flash Controller The Flash Controller programs and erases the Flash memory. It also supports protection against accidental programming and erasure.

PS025113-1212 CPU and Peripheral Overview Z8 Encore!® F0830 Series Product Specification Nonvolatile Data Storage The Nonvolatile Data Storage (NVDS) function uses a hybrid hardware/software scheme to implement a byte-programmable data memory and is capable of storing about 100,000 write cycles. Internal Precision Oscillator The Internal Precision Oscillator (IPO) function, with an accuracy of ± 4% full voltage/ temperature range, is a trimmable clock source that requires no external components. External Crystal Oscillator The crystal oscillator circuit provides highly accurate clock frequencies using an external crystal, ceramic resonator or RC network. 10-Bit Analog-to-Digital Converter The optional Analog-to-Digital Converter (ADC) converts an analog input signal to a 10- bit binary number. The ADC accepts inputs from eight different analog input pins. Analog Comparator The analog comparator compares the signal at an input pin with either an internal pro- grammable reference voltage or with a signal at the second input pin. The comparator out- put is used either to drive a logic output pin or to generate an interrupt. Timers Two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in ONE-SHOT, CONTINUOUS, GATED, CAPTURE, CAPTURE RESTART, COMPARE, CAPTURE and COMPARE, PWM SINGLE OUTPUT and PWM DUAL OUTPUT Modes. Interrupt Controller The Z8 Encore! F0830 Series products support seventeen interrupt sources with sixteen interrupt vectors: up to five internal peripheral interrupts and up to twelve GPIO inter- rupts. These interrupts have three levels of programmable interrupt priority.

a reset source as well as a reset indicator. The Z8 Encore! F0830 Series products feature an integrated On-Chip Debugger (OCD). one single-pin interface for communication with an external host. Table 2. Acronyms and Expansions

Packaging chapter on page 199.

Z8F0831
Z8F0431
Z8F0131
Z8F0231
Z8F1233

Table 3. Z8 Encore! F0830 Series Package Options

Figure 4. Z8F0830 Series in 20-Pin QFN Package

Figure 5. Z8F0830 Series in 28-Pin QFN Package

on page 7 to determine the signals available for each specific package style. Table 4. Signal Descriptions PA[7:0] I/O Port A. These pins are used for general purpose I/O. available only in those devices without an ADC. PC[7:0] I/O Port C. These pins are used for general purpose I/O. PD[0] I/O Port D. This pin is used for general purpose output only. T0OUT/T1OUT O Timer output 0–1. These signa ls are the output from the timers. inputs. The T0IN signal is multiplexed T0OUT signals. COUT O Comparator output. This is the output of the comparator. and PB7 on 28-pin packages without ADC.

to provide the system clock. tal can be connected between it and the XIN pin to form the oscillator. ble drive strengths set by the GPIO block. tor to ensure proper operation. open-drain and features an enabled internal pull-up resistor. Table 4. Signal Descriptions (Continued) and PB7 on 28-pin packages without ADC.

PB6 and PB7 are available only in devices without an ADC function. Table 5. Pin Characteristics (20- and 28-pin Devices)

PS025113-1212 Address Space Z8 Encore!® F0830 Series Product Specification Address Space The eZ8 CPU can access the following three distinct address spaces:

The register file addresses access for the general purpose registers and the eZ8 CPU, peripheral and general purpose I/O port control registers
The program memory addresses access for all of the memory locations having execut- able code and/or data
The data memory addresses access for all of the memory locations containing only the data The following sections describe these three address spaces. For more information about the eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download at www.zilog.com. Register File The register file address space in the Z8 Encore! MCU is 4 KB (4096 bytes). The register file consists of two sections: control registers and general-purpose registers. When instruc- tions are executed, registers defined as source are read and registers defined as destina- tions are written. The architecture of the eZ8 CPU allows all general purpose registers to function as accumulators, address pointers, index registers, stack areas or scratch pad memory. The upper 256 bytes of the 4 KB register file address space are reserved for controlling the eZ8 CPU, on-chip peripherals and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256 B Control Register section are reserved (unavailable). Reading from a reserved register file address returns an undefined value. Writing to reserved register file addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the register file address space. The Z8 Encore! F0830 Series devices contain up to 256 B of on-chip RAM. Reading from register file addresses outside the available RAM addresses (and not within the Control Register address space), returns an undefined value. Writing to these register file addresses has no effect.

the Z8 Encore! F0830 Series products. Table 6. Z8 Encore! F0830 Series Program Memory Maps Note: *See Table 34 on page 54 for a list of interrupt vectors.

gram memory data. Access to the Flash information area is read-only. Table 7. Z8 Encore! F0830 Series Flash Memory Information Area Map

GPIO ports. Consider registers for unimplemented peripherals as reserved. Table 8. Register File Address Map Address (Hex) Register Description Mnemonic Reset (Hex) Page No.

Table 8. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page No.

Address (Hex) Register Description Mnemonic Reset (Hex) Page No.

PS025113-1212 Reset and Stop Mode Recovery Z8 Encore!® F0830 Series Product Specification Reset and Stop Mode Recovery The reset controller in the Z8 Encore! F0830 Series controls RESET and Stop Mode Recovery operations. In a typical operation, the following events can cause a reset:

Power-On Reset (POR)
V oltage Brown-Out (VBO)
Watchdog Timer time-out (when configured by the WDT_RES Flash option bit to initiate a reset)
External RESET pin assertion (when the alternate RESET function is enabled by the GPIO register)
On-Chip Debugger initiated reset (OCDCTL[0] set to 1) When the device is in STOP Mode, a Stop Mode Recovery event is initiated by either of the following occurrences:
A Watchdog Timer time-out
A GPIO port input pin transition on an enabled Stop Mode Recovery source The VBO circuitry on the device generates a VBO reset when the supply voltage drops below a minimum safe level. Reset Types The Z8 Encore! F0830 Series provides different types of Reset operations. Stop Mode Recovery is considered a form of reset. Table 9 lists the types of resets and their operating characteristics. The duration of a system reset is longer if the external crystal oscillator is enabled by the Flash option bits; the result is additional time for oscillator startup.

is enabled in the Flash option bits, the reset period is increased to about 5000 IPO cycles. period, the device remains in reset until the pin is deasserted. after which the user code may reconfigure this pin as a general purpose output. oscillator and Watchdog Timer Oscillator continues to run. that value into the program counter. Program execution begins at the reset vector address. enable and select the correct system clock source. Table 9. Reset and Stop Mode Recovery Characteristics and Latency

Table 10 lists the possible sources of a system reset. Each device in the Z8 Encore! F0830 Series contains an internal Power-On Reset circuit. Status (RSTSTAT) Register is set to 1. on page 184 for the POR threshold voltage (VPOR). Table 10. Reset Sources and Resulting Reset Type pin assertion All reset pulses less than 12 ns are ignored.

The V oltage Brown-Out circuit can be either enabled or disabled during STOP Mode. Option Bits chapter on page 124 for information about configuring VBO_AO. it configures the Watchdog Timer to cause an interrupt – not a system reset – at time-out. reset was initiated by the Watchdog Timer. Figure 7. Voltage Brown-Out Reset Operation

PS025113-1212 Stop Mode Recovery Z8 Encore!® F0830 Series Product Specification clock and reset signals, the required reset duration may be three or four clock periods. A reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four cycles in duration always triggers a reset. While the RESET input pin is asserted low, the Z8 Encore! F0830 Series devices remain in the Reset state. If the RESET pin is held low beyond the system reset time-out, the device exits the Reset state on the system clock rising edge following RESET pin deasser- tion. Following a system reset initiated by the external RESET pin, the EXT status bit in the Reset Status (RSTSTAT) Register is set to 1. External Reset Indicator During system reset or when enabled by the GPIO logic, the RESET pin functions as an open-drain (active low) RESET mode indicator in addition to the input functionality. This reset output feature allows an Z8 Encore! F0830 Series device to reset other components to which it is connected, even if that reset is caused by internal sources such as POR, VBO or WDT events. See the Port A–D Control Registers section on page 41. After an internal Reset event occurs, the internal circuitry begins driving the RESET pin low. The RESET pin is held low by the internal circuitry until the appropriate delay listed in Table 9 (see page 22) has elapsed. On-Chip Debugger Initiated Reset A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in the OCD Control Register. The OCD block is not reset, but the remainder of the chip goes through a normal system reset. The RST bit automatically clears during the system reset. Following the system reset, the POR bit in the Reset Status (RSTSTAT) Register is set. Stop Mode Recovery The device enters the STOP Mode when the STOP instruction is executed by the eZ8 CPU. See the Low-Power Modes chapter on page 30 for detailed STOP Mode informa- tion. During Stop Mode Recovery, the CPU is held in reset for about 66 IPO cycles if the crystal oscillator is disabled or about 5000 cycles if it is enabled. Stop Mode Recovery does not affect the on-chip registers other than the Reset Status (RSTSTAT) Register and the Oscillator Control Register (OSCCTL). After any Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another system clock source is required or IPO disabling is required, the Stop Mode Recovery code must reconfigure the oscillator control block such that the correct system clock source is enabled and selected.

Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting actions. services the WDT interrupt request following the normal Stop Mode Recovery sequence. tus (RSTSTAT) Register, the STOP bit is set to 1. tiating an interrupt (if enabled for that pin). Table 11. Stop Mode Recovery Sources and Resulting Action

PS025113-1212 Debug Pin Driven Low Z8 Encore!® F0830 Series Product Specification Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! F0830 Series device is in STOP Mode and the external RESET pin is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the low pulse must be greater than the minimum width specified about 12 ns or it is ignored. The EXT bit in the Reset Status (RSTSTAT) Register is set. Debug Pin Driven Low Debug reset is initiated when the On-Chip Debugger detects any of the following error conditions on the DBG pin:

Serial break (a minimum of nine continuous bits Low)
Framing error (received STOP bit is Low)
Transmit collision (simultaneous OCD and host transmission detected by the OCD) When the Z8F0830 Series device is operating in STOP Mode, the debug reset will cause a system reset. The On-Chip Debugger block is not reset, but the remainder of the chip’s operations go through a normal system reset. The POR bit in the Reset Status (RSTSTAT) Register is set to 1. Reset Register Definitions The following sections define the Reset registers. Reset Status Register The Reset Status (RSTSTAT) Register, shown in Table 12, is a read-only register that indi- cates the source of the most recent Reset event, Stop Mode Recovery event or Watchdog Timer time-out event. Reading this register resets the upper four bits to 0. This register shares its address with the Watchdog Timer Control Register, which is write- only.

Table 12. Reset Status Register (RSTSTAT) Mode Recovery occurs. Reading this register also reset this bit to 0. Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. This read must occur before clearing the WDT interrupt. These registers are reserved and must be programmed to 0000. Table 13. POR Indicator Values

PS025113-1212 Low-Power Modes Z8 Encore!® F0830 Series Product Specification Low-Power Modes The Z8 Encore! F0830 Series products contain power saving features. The highest level of power reduction is provided by the STOP Mode. The next level of power reduction is pro- vided by the HALT Mode. Further power savings can be implemented by disabling the individual peripheral blocks while in NORMAL Mode. The user must not enable the pull-up register bits for unused GPIO pins, since these ports are default output to VSS. Unused GPIOs include those missing on 20-pin packages, as well as those missing on the ADC-enabled 28-pin packages. STOP Mode Executing the eZ8 CPU’s STOP instruction places the device into STOP Mode. In STOP Mode, the operating characteristics are:

Primary crystal oscillator and Internal Precision Oscillator are stopped; XIN and XOUT (if previously enabled) are disabled and PA0/PA1 revert to the states pro- grammed by the GPIO registers
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscil- lator Control Register
If enabled, the Watchdog Timer logic continues to operate
If enabled for operation in STOP Mode by the associated Flash option bit, the V oltage Brown-Out protection circuit continues to operate
All other on-chip peripherals are idle To minimize the current in STOP Mode, all GPIO pins that are configured as digital inputs must be driven to V DD when the pull-up register bit is enabled or to one of power rail (VDD or GND) when the pull-up register bit is disabled. The device can be brought out of STOP Mode using Stop Mode Recovery. For more information about Stop Mode Recov- ery, see the Reset and Stop Mode Recovery chapter on page 21.

Z8 Encore!® F0830 Series Product Specification HALT Mode Executing the eZ8 CPU HALT instruction places the device into HALT Mode. In HALT Mode, the operating characteristics are:

Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate
If enabled, the Watchdog Timer continues to operate
All other on-chip peripherals continue to operate The eZ8 CPU can be brought out of HALT Mode by any one of the following operations:
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
V oltage Brown-Out reset
External RESET pin assertion To minimize current in HALT Mode, all GPIO pins that are configured as digital inputs must be driven to VDD when pull-up register bit is enabled or to one of power rail (VDD or GND) when pull-up register bit is disabled. Peripheral Level Power Control In addition to the STOP and HALT modes, it is possible to disable each peripheral on each of the Z8 Encore! F0830 Series devices. Disabling a given peripheral minimizes its power consumption. Power Control Register Definitions Power Control Register 0 Each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block.

Table 14. Power Control Register 0 (PWRCTL0) These registers are reserved and must be programmed to 000. This bit is reserved and must be programmed to 1. This bit is reserved and must be programmed to 0. This bit is reserved and must be programmed to 0.

capable of direct LED drive at programmable drive strengths. Table 15 lists the port pins available with each device and package type. Table 15. Port Availability by Device and Package Type Note: 20-pin and 28-pin and 10-bit ADC Enabled or Disabled can be selected via the option bits.

PS025113-1212 Direct LED Drive Z8 Encore!® F0830 Series Product Specification PA0 and PA6 contain two different Timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the TIMER mode. For more details, see the Timers chapter on page 68. Direct LED Drive The Port C pins provide a sinked current output, capable of driving an LED without requiring an external resistor. The output sinks current at programmable levels, 3 mA, 7 mA, 13 mA and 20 mA. This mode is enabled through the LED Control registers. For proper function, the LED anode must be connected to VDD and the cathode to the GPIO pin. Using all Port C pins in LED drive mode with maximum current may result in excessive total current. See the Electrical Characteristics chapter on page 184 for the maximum total current for the applicable package. Shared Reset Pin On the 20- and 28-pin devices, the Port D0 pin shares function with a bidirectional reset pin. Unlike all other I/O pins, this pin does not default to GPIO function on power-up. This pin acts as a bidirectional input/output open-drain reset with an internal pull-up until the user software reconfigures it as a GPIO PD0. When in GPIO mode, the Port D0 pin functions as output only, and must be configured as an output. PD0 supports the high drive feature, but not the stop-mode recovery feature. Crystal Oscillator Override For systems using a crystal oscillator, the pins PA0 and PA1 are connected to the crystal. When the crystal oscillator is enabled, the GPIO settings are overridden and PA0 and PA1 are disabled. See the Oscillator Control Register Definitions section on page 154.

5 V Tolerance

In the 20- and 28-pin versions of this device, any pin, which shares functionality with an ADC, crystal or comparator port is not 5 V-tolerant, including PA[1:0], PB[5:0] and PC[2:0]. All other signal pins are 5 V-tolerant and can safely handle inputs higher than VDD even with the pull-ups enabled, but with excess power consumption on pull-up resis- tor.

select the PB3 as the system clock. Table 16. Port Alternate Function Mapping

Because there is only a single alternate function for each Port A and Port D (PD0) pin, the Alternate Function
Because there are at most two choices of alternate functions for any Port B pin, the AFS2 Alternate Function Set