Z8F022ASB020EC

Z8F041APB020SC ZILOG | Alldatasheet

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ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Product Specification High-Performance 8-Bit Microcontrollers Z8 Encore! XP® 4K Series

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532 Race Street

San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

Z8 Encore! XP® 4K Series Product Specification iii

Revision History

Each instance in the following table reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table. Revision History of this Document Date Revision Level

Description

Minor corrections made throughout document. Major changes include adding Timer caution note in the Timer chapter and Flash controller caution note in the Flash Memory chapter. In the Ordering chapter, corrected NVDS size typo. Added three new CPU instructions. Added 20-pin SOIC package drawing in Packaging chapter. Changed WDT oscillator frequency to 10 KHz in the Oscillator Control chapter. Clarified NVDS read/write operations in the NVDS Code Interface section. December 2004 Minor corrections to Low-Power Modes, General Purpose I/O, Analog to Digital Converter, Comparator, Flash Option Bits, Internal Precision Oscillator, and Electrical Characteristics Chapters. 31,39, 118,119,1 20,143,14 5,146,177, 202,203 January 2005 Added 8-Pin Development Kit and USB Smart Cable Accessory Kit ordering information. 227 May 2005 Added clarifying information for using the UART Baud Rate Generator as a simplified timer. Removed 2.2VREF in Table 129. Changed VBO to LVD in Interrupt Controller. Changed PA5 T1OUT to T1OUT and added clarification of Ports A-C for 8-pin and 20/28 pin devices in Tables 21, 26 and 27 in the GPIO. Changed TPOR and TSMR typical values in Table 125, and Endurance minimum value in Table 126 in Electrical Characteristics. Removed 2.2V reference in Electrical Characteristics and Analog-to-Digital Converter chapters. Added clarifying text when writing to the Flash Control Register in Flash Memory chapter. Added Lead-Free Packaging order information 99, 129,39,50, 51,56,58, 59,61,43, 46,203, 204,206, 121,123, 126-140, 222-228 June 2005 11 Inserted missing temperature sensor chapter. Updated Figure1 to include Transimpedance Amplifier. Added Transimpedance Amplifer to Feature Description. Removed reference to VBO enable. Updated Table 124 format. Changed Temperature Sensor column in ordering information pages. 3, 5, 152, 223, 227

Z8 Encore! XP® 4K Series Product Specification iv October 2005 Added references to optional low-power operational amplifier and removed references to transimpedance amplifier. Numerous other small corrections throughout the book. 1-6, 8-12, 14-15, 17. 19, 21-22, 24-27, 29- 31, 32-40, 44, 46, 48, 57-59, 62, 67-69, 72- 73, 75-76, 78, 81-89, 99-100, 102, 104- 105, 112- 125, 129- 140, 142- 144, 146- 151, 172- 177, 182, 204-223, 231, 237- 244 November 2005 Reverted back to version 11, removing changes in version 12. Updated Flash Option Bits chapter. 142-154 December 2005 Restored version 12 changes and rectified elements to incorporate version 11 updates. 8, 84, 87, 88, 113, 124, 126, 148-161, 216, 218, 220, 221 February 2006 Updated for 8-pin QFN/MLF-S in Table 2, Figure 2, and Packaging section. Updated UART features. 7, 8, 89 Revision History of this Document Date Revision Level

Z8 Encore! XP® 4K Series Product Specification v Table of Contents

Z8 Encore! XP® 4K Series Product Specification vi

Z8 Encore! XP® 4K Series Product Specification vii

Z8 Encore! XP® 4K Series Product Specification viii

Z8 Encore! XP® 4K Series Product Specification ix

Z8 Encore! XP® 4K Series Product Specification x

Z8 Encore! XP® 4K Series Product Specification xi

Z8 Encore! XP® 4K Series Product Specification xii

Table 24. Port A–D STOP Mode Recovery Source Enable Sub-Registers (Px-

Table 104. Temperature Sensor Calibration High Byte at 003A (TSCALH). . . 162 Table 105. Temperature Sensor Calibration Low Byte at 003B (TSCALL) . . . 162 Table 114. Transconductance Values for Low, Medium, and High Gain Operating

Table 134. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Table 137. Analog-to-Digital Converter Electrical Characteristics and Timing. 221

Z8 Encore! XP® 4K Series Product Specification Overview The Z8 Encore!® MCU family of products are the first in a line of ZiLOG® microcontrol- ler products based upon the 8-bit eZ8 CPU. The Z8 Encore! XP® 4K Series products expand upon ZiLOG’s extensive line of 8-bit microcontrollers. The Flash in-circuit pro- gramming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward compatible with existing Z8® instructions. The rich periph- eral set of the Z8 Encore! XP® 4K Series makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors.

Features

20 MHz eZ8 CPU

1KB, 2KB or 4KB Flash memory with in-circuit programming capability 256B, 512B or 1KB register RAM 16B to 128B non-volatile data storage (NVDS) Up to 20 vectored interrupts 6 to 25 I/O pins depending upon package Internal precision oscillator External crystal oscillator Full-duplex UART The UART baud rate generator (BRG) can be configured and used as a basic 16-bit timer Infrared Data Association (IrDA)-compliant infrared encoder/decoders, integrated with UART Two enhanced 16-bit timers with capture, compare, and PWM capability Watch-Dog Timer (WDT) with dedicated internal RC oscillator On-chip debugger Optional 8-channel, 10-bit analog-to-digital converter (ADC) Optional On-chip temperature sensor On-chip analog comparator Optional on-chip low-power operational amplifier (LPO) Voltage brown-out protection (VBO)

Z8 Encore! XP® 4K Series product line. Note: * Advanced Analog includes ADC, temperature sensor, and low-power operational amplifer. Table 1. Z8 Encore! XP® 4K Series Family Part Selection Guide

Figure 1. Z8 Encore! XP® 4K Series Block Diagram

Z8 Encore! XP® 4K Series Product Specification CPU and Peripheral Overview eZ8 CPU Features The eZ8 CPU, ZiLOG®’s latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8® instruction set. The eZ8 CPU features include: Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8® code Expanded internal Register File allows access of up to 4KB New instructions improve execution efficiency for code developed using higher-level programming languages, including C Pipelined instruction fetch and execution New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL New instructions support 12-bit linear addressing of the Register File Up to 10 MIPS operation C-Compiler friendly 2 to 9 clock cycles per instruction For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail- able for download at www.zilog.com. General Purpose I/O The Z8 Encore! XP® 4K Series features 6 to 25 port pins (Ports A–D) for general purpose I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is indi- vidually programmable. Flash Controller The Flash Controller programs and erases Flash memory. The Flash Controller supports several protection mechanisms against accidental program and erasure.

Z8 Encore! XP® 4K Series Product Specification Non-Volatile Data Storage The non-volatile data storage (NVDS) uses a hybrid hardware/software scheme to imple- ment a byte programmable data memory and is capable of over 100,000 write cycles. Internal Precision Oscillator The internal precision oscillator (IPO) is a trimmable clock source that requires no exter- nal components. Crystal Oscillator The crystal oscillator circuit provides highly accurate clock frequencies with the use of an external crystal, ceramic resonator or RC network. 10-Bit Analog-to-Digital Converter The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from eight different analog input pins in both sin- gle-ended and differential modes. The ADC also features a unity gain buffer when high input impedance is required. Low-Power Operational Amplifier The optional low-power operational amplifier (LPO) is a general-purpose amplifier prima- rily targeted for current sense applications. The LPO output may be routed internally to the ADC or externally to a pin. Analog Comparator The analog comparator compares the signal at an input pin with either an internal pro- grammable voltage reference or a second input pin. The comparator output can be used to drive either an output pin or to generate an interrupt. Temperature Sensor The optional Temperature Sensor produces an analog output proportional to the device temperature. This signal can be sent to either the ADC or the analog comparator.

Z8 Encore! XP® 4K Series Product Specification Low Battery Detector The low battery detector (LVD) is able to generate an interrupt when the supply voltage drops below a user-programmable level. The LVD is available on 8-pin devices only. UART The UART is full-duplex and capable of handling asynchronous data transfers. The UART supports 8- and 9-bit data modes and selectable parity. The UART also supports multi- drop address processing in hardware. The UART baud rate generator (BRG) can be config- ured and used as a basic 16-bit timer. Timers Two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in One-Shot, Continuous, Gated, Capture, Capture Restart, Compare, Capture and Compare, PWM Single Output and PWM Dual Output modes. Interrupt Controller The Z8 Encore! XP® 4K Series products support up to 20 interrupts. These interrupts con- sist of 8 internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources. The interrupts have 3 levels of programmable interrupt priority. Reset Controller The Z8 Encore! XP® 4K Series products can be reset using the RESET pin, power-on reset, Watch-Dog Timer (WDT) time-out, STOP mode exit, or voltage brown-out (VBO) warning signal. The RESET pin is bi-directional, meaning it functions as reset source as well as a reset indicator. On-Chip Debugger The Z8 Encore! XP® 4K Series products feature an integrated on-chip debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing regis- ters, programming Flash memory, setting breakpoints and executing code. A single-pin interface provides communication to the OCD.

refer to the chapter Packaging on page 230. able in the Z8 Encore! XP® 4K Series. Refer to Table 3 for a description of the signals. these parts, and are replaced by PB6 and PB7. Table 2. Z8 Encore! XP® 4K Series Package Options

Z8 Encore! XP® 4K Series Product Specification Signal Descriptions Table 3 describes the Z8 Encore! XP® 4K Series signals. Refer to the section Pin Configu- rations on page 7 to determine the signals available for the specific package styles. Table 3. Signal Descriptions General-Purpose I/O Ports A–D PA[7:0] I/O Port A. These pins are used for general-purpose I/O. PB[7:0] I/O Port B. These pins are used for general-purpose I/O. PB6 and PB7 are available only in those devices without an ADC. PC[7:0] I/O Port C. These pins are used for general-purpose I/O. PD[0] I/O Port D. This pin is used for general-purpose output only. Note: PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are replaced by AVDD and AVSS. UART Controllers TXD0 O Transmit Data. This signal is the transmit output from the UART and IrDA. RXD0 I Receive Data. This signal is the receive input for the UART and IrDA. CTS0 I Clear To Send. This signal is the flow control input for the UART. DE O Driver Enable. This signal allows automatic control of external RS-485 drivers. This signal is approximately the inverse of the TXE (Transmit Empty) bit in the UART Status 0 register. The DE signal may be used to ensure the external RS-485 driver is enabled when data is transmitted by the UART. Timers T0OUT/T1OUT O Timer Output 0–1. These signals are outputs from the timers. T0OUT/T1OUT O Timer Complement Output 0–1. These signals are output from the timers in PWM Dual Output mode. T0IN/T1IN I Timer Input 0–1. These signals are used as the capture, gating and counter inputs. Comparator CINP/CINN I Comparator Inputs. These signals are the positive and negative inputs to the comparator. COUT O Comparator Output.

Z8 Encore! XP® 4K Series Product Specification Analog ANA[7:0] I Analog Port. These signals are used as inputs to the analog-to-digital converter (ADC). VREF I/O Analog-to-digital converter reference voltage input, or buffered output for internal reference. Low-Power Operational Amplifier (LPO) AMPINP/AMPINN I LPO inputs. If enabled, these pins drive the positive and negative amplifier inputs respectively. AMPOUT O LPO output. If enabled, this pin is driven by the on-chip LPO. Oscillators XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. In addition, this pin is used with external RC networks or external clock drivers to provide the system clock. XOUT O External Crystal Output. This pin is the output of the crystal oscillator. A crystal can be connected between it and the XIN pin to form the oscillator. Clock Input CLKIN I Clock Input Signal. This pin may be used to input a TTL-level signal to be used as the system clock. LED Drivers LED O Direct LED drive capability. All port C pins have the capability to drive an LED without any other external components. These pins have programmable drive strengths set by the GPIO block. On-Chip Debugger DBG I/O Debug. This signal is the control and data input and output to and from the On-Chip Debugger. The DBG pin is open-drain and requires an external pull-up resistor to ensure proper operation. Reset RESET I/O RESET. Generates a Reset when asserted (driven Low). Also serves as a reset indicator; the Z8 Encore! XP® forces this pin low when in reset. This pin is open-drain and features an enabled internal pull-up resistor. Power Supply VDD I Digital Power Supply. Table 3. Signal Descriptions (Continued) Caution:

Z8 Encore! XP® 4K Series Product Specification Pin Characteristics Table 4 provides detailed information about the characteristics for each pin available on the Z8 Encore! XP® 4K Series 20- and 28-pin devices. Data in Table 4 is sorted alphabeti- cally by the pin symbol mnemonic. Table 5 provides detailed information about the characteristics for each pin available on the Z8 Encore! XP® 4K Series 8-pin devices, All six I/O pins on the 8-pin packages are 5V-tolerant (unless the pull-up devices are enabled). The column in Table 4 below describes 5V-tolerance for the 20 and 28-pin pack- ages only. AVDD I Analog Power Supply. VSS I Digital Ground. AVSS I Analog Ground. Note: The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and PB7 on 28-pin packages without ADC. Table 4. Pin Characteristics (20- and 28-pin Devices) Note:

PB6 and PB7 are available only in those devices without ADC. Table 5. Pin Characteristics (8-Pin Devices)

Z8 Encore! XP® 4K Series Product Specification Address Space Overview The eZ8 CPU can access three distinct address spaces: The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral, and general-purpose I/O port control registers. The Program Memory contains addresses for all memory locations having executable code and/or data. The Data Memory contains addresses for all memory locations that contain data only. These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU User Manual available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore!® MCU is 4KB (4096 bytes). The Regis- ter File is composed of two sections: control registers and general-purpose registers. When instructions are executed, registers defined as sources are read, and registers defined as destinations are written. The architecture of the eZ8 CPU allows all general-purpose regis- ters to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256B control register sec- tion are reserved (unavailable). Reading from a reserved Register File address returns an undefined value. Writing to reserved Register File addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. The Z8 Encore! XP® 4K Series devices contain 256B to 1KB of on-chip RAM. Reading from Register File addresses outside the available RAM addresses (and not within the control register address space) returns an undefined value. Writing to these Register File addresses produces no effect.

Maps for the Z8 Encore! XP® 4K Series products. Table 6. Z8 Encore! XP®4K Series Series Program Memory Maps

• See Table 33 on page 51 for a list of the interrupt vectors.

rather than the Program Memory data. Access to the Flash Information Area is read-only. Table 7. Z8 Encore! XP®4K Series Flash Memory Information Area Map Table 6. Z8 Encore! XP®4K Series Series Program Memory Maps (Continued)

• See Table 33 on page 51 for a list of the interrupt vectors.

Table 8. Register File Address Map

Table 8. Register File Address Map (Continued)

Reset, STOP Mode Recovery and Low Voltage Detection Z8 Encore! XP® 4K Series Product Specification Reset, STOP Mode Recovery and Low Voltage Detection Overview The Reset Controller within the Z8 Encore! XP® 4K Series controls Reset and STOP Mode Recovery operation and provides indication of low supply voltage conditions. In typical operation, the following events cause a Reset: Power-on reset (POR) Voltage brown-out (VBO) Watch-Dog Timer time-out (when configured by the WDT_RES Flash Option Bit to initiate a reset) External RESET pin assertion (when the alternate RESET function is enabled by the GPIO register) On-chip debugger initiated Reset (OCDCTL[0] set to 1) When the device is in STOP mode, a STOP Mode Recovery is initiated by either of the following: Watch-Dog Timer time-out GPIO Port input pin transition on an enabled STOP Mode Recovery source The low voltage detection circuitry on the device (available on the 8-pin product versions only) performs the following functions: Generates the VBO reset when the supply voltage drops below a minimum safe level Generates an interrupt when the supply voltage drops below a user-defined level (8-pin de- vice only) Reset Types The Z8 Encore! XP® 4K Series provides several different types of Reset operation. STOP Mode Recovery is considered a form of Reset. Table 9 lists the types of Reset and their operating characteristics. The System Reset is longer if the external crystal oscillator is enabled by the Flash option bits, allowing additional time for oscillator start-up.

oscillator and Watch-Dog Timer oscillator continue to run. that the correct system clock source is enabled and selected. Table 9. Reset and STOP Mode Recovery Characteristics and Latency

66 Internal Precision Oscillator Cycles

5000 Internal Precision Oscillator Cycles

Table 10 lists the possible sources of a system reset. timed out. If the crystal oscillator is enabled by the option bits, this timeout is longer. Timer Control (WDTCTL) register is set to 1. page 212 for the POR threshold voltage (VPOR). Table 10. Reset Sources and Resulting Reset Type

Reset, STOP Mode Recovery and Low Voltage Detection Z8 Encore! XP® 4K Series Product Specification Figure 5.Power-On Reset Operation Voltage Brown-Out Reset The devices in the Z8 Encore! XP® 4K Series provide low voltage brown-out (VBO) pro- tection. The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO threshold voltage) and forces the device into the Reset state. While the supply voltage remains below the Power-On Reset voltage threshold (VPOR), the VBO block holds the device in the Reset. After the supply voltage again exceeds the Power-On Reset voltage threshold, the device progresses through a full System Reset sequence, as described in the Power-On Reset sec- tion. Following Power-On Reset, the POR status bit in the Reset Status (RSTSTAT) regis- ter is set to 1. Figure 6 illustrates Voltage Brown-Out operation. Refer to the chapter Electrical Characteristics on page 212 for the VBO and POR threshold voltages (VVBO and VPOR). The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode. Operation during STOP mode is set by the VBO_AO Flash Option Bit. Refer to the Flash Option Bits chapter for information about configuring VBO_AO. VCC = 0.0V VCC = 3.3V VPOR VVBO Internal Precision Internal RESET signal Program Execution Oscillator Start-up POR counter delay optional XTAL counter delay Oscillator Crystal Oscillator Note: Not to Scale

Reset, STOP Mode Recovery and Low Voltage Detection Z8 Encore! XP® 4K Series Product Specification Figure 6.Voltage Brown-Out Reset Operation The POR level is greater than the VBO level by the specified hysteresis value. This ensures that the device undergoes a Power-On Reset after recovering from a VBO condi- tion. Watch-Dog Timer Reset If the device is in NORMAL or STOP mode, the Watch-Dog Timer can initiate a System Reset at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the unprogrammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it configures the Watch-Dog Timer to cause an interrupt, not a System Reset, at time-out. The WDT bit in the Reset Status (RSTSTAT) register is set to signify that the reset was initiated by the Watch-Dog Timer. External Reset Input The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. Once the RESET pin is asserted for a minimum of four system clock cycles, the device progresses through the System Reset sequence. Because of the possible asynchronicity of the system clock and reset signals, the required reset duration may be as short as three clock periods VCC = 3.3V VPOR VVBO Internal RESET signal Program Execution Program Execution Voltage Brownout VCC = 3.3V System Clock POR counter delay Note: Not to Scale

Reset, STOP Mode Recovery and Low Voltage Detection Z8 Encore! XP® 4K Series Product Specification and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. While the RESET input pin is asserted Low, the Z8 Encore! XP® 4K Series devices remain in the Reset state. If the RESET pin is held Low beyond the System Reset time- out, the device exits the Reset state on the system clock rising edge following RESET pin deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta- tus bit in the Reset Status (RSTSTAT) register is set to 1. External Reset Indicator During System Reset or when enabled by the GPIO logic (see See Port A–D Control Reg- isters on page 42.), the RESET pin functions as an open-drain (active low) reset mode indicator in addition to the input functionality. This reset output feature allows an Z8 Encore! XP® 4K Series device to reset other components to which it is connected, even if that reset is caused by internal sources such as POR, VBO or WDT events. After an internal reset event occurs, the internal circuitry begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry until the appropriate delay listed in Table 9 has elapsed. On-Chip Debugger Initiated Reset A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip goes through a normal system reset. The RST bit automatically clears during the system reset. Following the system reset the POR bit in the WDT Control register is set. STOP Mode Recovery STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the chapter Low-Power Modes on page 29 for detailed STOP mode information. During STOP Mode Recovery, the CPU is held in reset for 66 IPO cycles if the crystal oscillator is disabled or 5000 cycles if it is enabled. The SMR delay (see Table 134 on page 219) TSMR, also includes the time required to start up the IPO. STOP Mode Recovery does not affect onchip registers other than the Watchdog Timer Control register (WDTCTL) and the Oscillator Control register (OSCCTL). After any STOP Mode Recovery, the IPO is enabled and selected as the system clock. If another sys- tem clock source is required, the STOP Mode Recovery code must reconfigure the oscilla- tor control block such that the correct system clock source is enabled and selected. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vec- tor address. Following STOP Mode Recovery, the STOP bit in the Reset Status

Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source. without initiating an interrupt (if enabled for that pin). Table 11. STOP Mode Recovery Sources and Resulting Action

Reset, STOP Mode Recovery and Low Voltage Detection Z8 Encore! XP® 4K Series Product Specification STOP Mode Recovery Using the External RESET Pin When the Z8 Encore! XP® 4K Series device is in STOP Mode and the external RESET pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See Electrical Characteristics on page 212 for details. Low Voltage Detection In addition to the Voltage Brown-out Reset (VBO) described above, it is also possible to generate an interrupt when the supply voltage drops below a user-selected value. See Trim Bit Address 0003H on page 154. for details about the Low Voltage Detection (LVD) threshold levels available. The LVD function is available on the 8-pin product versions only. When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status (RSTSTAT) register is set to one. This bit remains one until the low-voltage condition goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate an interrupt when so enabled. (See Interrupt Vectors and Priority on page 53.) The LVD bit is NOT latched, so enabling the interrupt is the only way to guarantee detection of a tran- sient low voltage event. The LVD functionality depends on circuitry shared with the VBO block; therefore dis- abling the VBO also disables the LVD. Reset Register Definitions Reset Status Register The Reset Status (RSTSTAT) register is a read-only register that indicates the source of the most recent Reset event, indicates a STOP Mode Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets the upper four bits to 0. This register shares its address with the Watch-Dog Timer control register, which is write- only (Table 12).

out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read. is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. mode. Reading this register also resets this bit. resets this bit. This read must occur before clearing the WDT interrupt. Table 12. Reset Status Register (RSTSTAT)

Z8 Encore! XP® 4K Series Product Specification Low-Power Modes Overview The Z8 Encore! XP® 4K Series products contain power-saving features. The highest level of power reduction is provided by the STOP mode. The next lower level of power reduc- tion is provided by the HALT mode. Further power savings can be implemented by disabling individual peripheral blocks while in Active mode (defined as being in neither STOP nor HALT mode). STOP Mode Executing the eZ8 CPU’s STOP instruction places the device into STOP mode. In STOP mode, the operating characteristics are: Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT (if previously enabled) are disabled, and PA0/PA1 revert to the states programmed by the GPIO registers. System clock is stopped. eZ8 CPU is stopped. Program counter (PC) stops incrementing. Watch-Dog Timer’s internal RC oscillator continues to operate if enabled by the Oscillator Control Register. If enabled, the Watch-Dog Timer logic continues to operate. If enabled for operation in STOP mode by the associated Flash Option Bit, the Voltage- Brown Out protection circuit continues to operate. Low-power operational amplifier continues to operate if enabled by the Power Control Register to do so. All other on-chip peripherals are idle. To minimize current in STOP mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (VCC or GND). Additionally, any GPIOs config- ured as outputs should also be driven to one of the supply rails. The device can be brought out of STOP mode using STOP Mode Recovery. For more information about STOP Mode Recovery refer to Reset, STOP Mode Recovery and Low Voltage Detection on page 20.

Z8 Encore! XP® 4K Series Product Specification HALT Mode Executing the eZ8 CPU’s HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are: Primary oscillator is enabled and continues to operate. System clock is enabled and continues to operate. eZ8 CPU is stopped. Program counter (PC) stops incrementing. Watch-Dog Timer’s internal RC oscillator continues to operate. If enabled, the Watch-Dog Timer continues to operate. All other on-chip peripherals continue to operate, if enabled. The eZ8 CPU can be brought out of HALT mode by any of the following operations: Interrupt Watch-Dog Timer time-out (interrupt or reset) Power-On reset Voltage-Brown out reset External RESET pin assertion To minimize current in HALT mode, all GPIO pins that are configured as inputs must be driven to one of the supply rails (VCC or GND). Peripheral-Level Power Control In addition to the STOP and Halt modes, it is possible to disable each peripheral on each of the Z8 Encore! XP® 4K Series devices. Disabling a given peripheral minimizes its power consumption. Power Control Register Definitions Power Control Register 0 Each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block. The default state of the low-power operational amplifier (LPO) is OFF. To use the LPO, clear the LPO bit, turning it ON. Clearing this bit might interfere with normal ADC mea-

surements on ANA0 (the LPO output). This bit enables the amplifier even in STOP mode. STOP mode currents greater than specified. 0 = LPO is enabled (this applies even in STOP mode). bits contained in the target block’s control registers. Table 13. Power Control Register 0 (PWRCTL0)

capable of direct LED drive at programmable drive strengths. Table 14 lists the port pins available with each device and package type. Table 14. Port Availability by Device and Package Type

Z8 Encore! XP® 4K Series Product Specification PA0 and PA6 contain two different timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the timer mode. See Timers on page 62 for more details. Direct LED Drive The Port C pins provide a current sinked output capable of driving an LED without requir- ing an external resistor. The output sinks current at programmable levels of 3 mA, 7 mA, 13 mA and 20 mA. This mode is enabled through the Alternate Function sub-register AFS1 and is programmable through the LED control registers. The LED Drive Enable (LEDEN) register turns on the drivers. The LED Drive Level (LEDLVLH and LEDLVLL) registers select the sink current. For correct function, the LED anode must be connected to VDD and the cathode to the GPIO pin. Using all Port C pins in LED drive mode with maximum current may result in excessive total current. Refer to the Electrical Characteristics on page 212 for the maximum total current for the applicable package. Shared Reset Pin On the 20 and 28-pin devices, the Port D0 pin shares function with a bi-directional reset pin. Unlike all other I/O pins, this pin does not default to GPIO function on power-up. This pin acts as a bi-directional reset until user software re-configures it. The Port D0 pin is output-only when in GPIO mode. On the 8-pin product versions, the reset pin is shared with PortA2, but the pin is not lim- ited to output-only when in GPIO mode. If PA2 on the 8-pin product is reconfigured as an input, take care that no external stim- ulus drives the pin low during any reset sequence. Since PA2 returns to its RESET al- ternate function during system resets, driving it low will hold the chip in a reset state until the pin is released. The same applies to the PDO pin on the 28-pin product. Shared Debug Pin On the 8-pin version of this device only, the Debug pin shares function with the PortA0 GPIO pin. This pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. If the unlock sequence is present, the debug function is unlocked and the pin no longer functions as a GPIO pin. If it is not present, the debug feature is disabled until/ unless another reset event occurs. For more details, see On-Chip Debugger on page 167 Caution:

Z8 Encore! XP® 4K Series Product Specification Crystal Oscillator Override For systems using a crystal oscillator, PA0 and PA1 are used to connect the crystal. When the crystal oscillator is enabled (see Oscillator Control Register Definitions on page 183), the GPIO settings are overridden and PA0 and PA1 are disabled. 5V Tolerance All six I/O pins on the 8-pin devices are 5V-tolerant, unless the programmable pull-ups are enabled. If the pull-ups are enabled and inputs higher than VDD are applied to these parts, excessive current flows through those pull-up devices and can damage the chip. In the 20- and 28-pin versions of this device, any pin which shares functionality with an ADC, crystal or comparator port is not 5V-tolerant, including PA[1:0], PB[5:0] and PC[2:0]. All other signal pins are 5V-tolerant, and can safely handle inputs higher than VDD except when the programmable pull-ups are enabled. External Clock Setup For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator Control (OSCCTL)Register (page 183) such that the external oscillator is selected as the system clock. For 8-pin devices use PA1 instead of PB3. Note:

Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) timer configuration as described in Timer Pin Signal Operation on page 75.

described in Port A–D Alternate Function Sub-Registers on page 42 must also be enabled.

• VREF is available on PB5 in 28-pin products only.

Table 15. Port Alternate Function Mapping (Continued)(Non 8-Pin Parts)

described in Port A–D Alternate Function Sub-Registers on page 42 must also be enabled.

• VREF is available on PC2 in 20-pin products only.

Table 16. Port Alternate Function Mapping (8-Pin Parts)

• Analog Functions include ADC inputs, ADC reference, comparator inputs and LPO ports.

information about interrupts using the GPIO pins. Four registers for each Port provide access to GPIO control, input data, and output data. together to provide access to sub-registers for Port configuration and control. Table 17. GPIO Port Registers and Sub-Registers Table 16. Port Alternate Function Mapping (8-Pin Parts) (Continued)

• Analog Functions include ADC inputs, ADC reference, comparator inputs and LPO ports.

vide access to all GPIO Port controls (Table 18). Table 18. Port A–D GPIO Address Registers (PxADDR) No function. Provides some protection against accidental Port reconfiguration. STOP Mode Recovery Source Enable. Table 17. GPIO Port Registers and Sub-Registers (Continued)

a Port A–D Control register transaction (Table 19). ter by writing 01H to the Port A–D Address register (Table 20). tion overrides the Data Direction register setting. 0 = Output. Data in the Port A–D Output Data register is driven onto the port pin. ister. The output driver is tristated. Table 19. Port A–D Control Registers (PxCTL) Table 20. Port A–D Data Direction Sub-Registers (PxDD)

Registers on page 45 and Port A–D Alternate Function Set 2 Sub-Registers on page 46. register determines the direction of the pin. enabled. Port pin operation is controlled by the alternate function. Table 21. Port A–D Alternate Function Sub-Registers (PxAF) Table 22. Port A–D Output Control Sub-Registers (PxOC)

1 = The source current for the associated pin is disabled (open-drain mode). the pins directly and, as a result, alternate functions are also affected. 0 = The Port pin is configured for standard output current drive. 1 = The Port pin is configured for high output current drive. through the Port A–D Control register by writing 05H to the Port A–D Address register. Table 23. Port A–D High Drive Enable Sub-Registers (PxHDE) Table 24. Port A–D STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)

pin during STOP mode do not initiate STOP Mode Recovery. this pin during STOP mode initiates STOP Mode Recovery. 0 = The weak pull-up on the Port pin is disabled. 1 = The weak pull-up on the Port pin is enabled. Alternate Function Sub-Registers on page 42. Table 25. Port A–D Pull-Up Enable Sub-Registers (PxPUE) Table 26. Port A–D Alternate Function Set 1 Sub-Registers (PxAFS1)

section GPIO Alternate Functions on page 33. Alternate Function Sub-Registers on page 42. 28-pin packages, as well as those missing on the ADC-enabled 28-pin packages. Table 27. Port A–D Alternate Function Set 2 Sub-Registers (PxAFS2) Table 28. Port A–C Input Data Registers (PxIN)

Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High). The Port A–D Output Data register (Table 29) controls the output data to the pins. 0 = Drive a logical 0 (Low). ting the corresponding Port Output Control register bit to 1. These bits determine which Port C pins are connected to an internal current sink. Table 29. Port A–D Output Data Register (PxOUT) Table 30. LED Drive Enable (LEDEN)

0 = Tristate the Port C pin. 1= Enable controlled current sink on the Port C pin. The LED Drive Level registers contain two control bits for each Port C pin (Table 31). The LED Drive Level registers contain two control bits for each Port C pin (Table 32). Table 31. LED Drive Level High Register (LEDLVLH) Table 32. LED Drive Level Low Register (LEDLVLL)

Z8 Encore! XP® 4K Series Product Specification 00 = 3 mA 01 = 7 mA 10 = 13 mA 11 = 20 mA

Z8 Encore! XP® 4K Series Product Specification Interrupt Controller Overview The interrupt controller on the Z8 Encore! XP® 4K Series products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt controller include the following: 20 unique interrupt vectors:

12 GPIO port pin interrupt sources (two are shared)

10 on-chip peripheral interrupt sources (two are shared) Flexible GPIO interrupts Eight selectable rising and falling edge GPIO interrupts Four dual-edge interrupts Three levels of individually programmable interrupt priority Watch-Dog Timer and LVD can be configured to generate an interrupt Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the CPU and the interrupting peripheral. When the service routine is com- pleted, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man- ual is available for download at www.zilog.com. Interrupt Vector Listing Table 33 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even Program Memory address and the least significant byte (LSB) at the following odd Program Memory address. Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is unavailable on devices not containing an ADC. Note:

Table 33. Trap and Interrupt Vectors in Order of Priority

Z8 Encore! XP® 4K Series Product Specification Writing a 1 to the IRQE bit in the Interrupt Control register Interrupts are globally disabled by any of the following actions: Execution of a DI (Disable Interrupt) instruction eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller Writing a 0 to the IRQE bit in the Interrupt Control register Reset Execution of a Trap instruction Illegal Instruction Trap Primary Oscillator Fail Trap Watch-Dog Oscillator Fail Trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of the interrupts are enabled with identical interrupt priority (all as Level 2 interrupts, for example), the interrupt priority is assigned from highest to lowest as specified in Table 33 on page 51. Level 3 interrupts are always assigned higher priority than Level 2 interrupts which, in turn, always are assigned higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 33, above. Reset, Watch-Dog Timer interrupt (if enabled), Primary Oscillator Fail Trap, Watchdog Oscillator Fail Trap, and Illegal Instruction Trap always have highest (level 3) priority. Interrupt Assertion Interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond- ing bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt request. The following coding style that clears bits in the Interrupt Request registers is NOT rec- ommended. All incoming interrupts received between execution of the first LDX com- mand and the final LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 Caution:

Z8 Encore! XP® 4K Series Product Specification To avoid missing interrupts, use the following coding style to clear bits in the Interrupt Request 0 register: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt Request register triggers an interrupt (assuming that interrupt is enabled). When the inter- rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is automatically cleared to 0. The following coding style used to generate software interrupts by setting bits in the In- terrupt Request registers is NOT recommended. All incoming interrupts received be- tween execution of the first LDX command and the final LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the following coding style to set bits in the Interrupt Re- quest registers: Good coding style that avoids lost interrupt requests: ORX IRQ0, MASK Interrupt Control Register Definitions For all interrupts other than the Watch-Dog Timer interrupt, the Primary Oscillator Fail Trap, and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ- ual interrupts, set interrupt priorities, and indicate interrupt requests. Interrupt Request 0 Register The Interrupt Request 0 (IRQ0) register (Table 34) stores the interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec- tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If Caution: Caution: Caution:

Request 0 register to determine if any interrupt requests are pending. 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. 0 = No interrupt request is pending for Timer 0. 1 = An interrupt request from Timer 0 is awaiting service. 0 = No interrupt request is pending for the UART 0 receiver. 1 = An interrupt request from the UART 0 receiver is awaiting service. 0 = No interrupt request is pending for the UART 0 transmitter. 1 = An interrupt request from the UART 0 transmitter is awaiting service. 0 = No interrupt request is pending for the Analog-to-Digital Converter. 1 = An interrupt request from the Analog-to-Digital Converter is awaiting service. register to determine if any interrupt requests are pending. Table 34. Interrupt Request 0 Register (IRQ0)

0 = No interrupt request is pending for GPIO Port A or LVD. 1 = An interrupt request from GPIO Port A or LVD. 0 = No interrupt request is pending for GPIO Port A or Comparator. 1 = An interrupt request from GPIO Port A or Comparator. 0 = No interrupt request is pending for GPIO Port A pin x. 1 = An interrupt request from GPIO Port A pin x is awaiting service. where x indicates the specific GPIO Port pin number (0–5). register to determine if any interrupt requests are pending. 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. where x indicates the specific GPIO Port C pin number (0–3). Table 35. Interrupt Request 1 Register (IRQ1) Table 36. Interrupt Request 2 Register (IRQ2)

Z8 Encore! XP® 4K Series Product Specification IRQ0 Enable High and Low Bit Registers Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg- isters (Tables 38 and 39) form a priority encoded enabling for interrupts in the Interrupt Request 0 register. Reserved—Must be 0. T1ENH—Timer 1 Interrupt Request Enable High Bit T0ENH—Timer 0 Interrupt Request Enable High Bit U0RENH—UART 0 Receive Interrupt Request Enable High Bit U0TENH—UART 0 Transmit Interrupt Request Enable High Bit ADCENH—ADC Interrupt Request Enable High Bit Reserved—Must be 0. Table 37. IRQ0 Enable and Priority Encoding where x indicates the register bits from 0–7. Table 38. IRQ0 Enable High Bit Register (IRQ0ENH) Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)

Z8 Encore! XP® 4K Series Product Specification T1ENL—Timer 1 Interrupt Request Enable Low Bit T0ENL—Timer 0 Interrupt Request Enable Low Bit U0RENL—UART 0 Receive Interrupt Request Enable Low Bit U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit ADCENL—ADC Interrupt Request Enable Low Bit IRQ1 Enable High and Low Bit Registers Table 40 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg- isters (Tables 41 and 42) form a priority encoded enabling for interrupts in the Interrupt Request 1 register. PA7VENH—Port A Bit[7] or LVD Interrupt Request Enable High Bit PA6CENH—Port A Bit[7] or Comparator Interrupt Request Enable High Bit PAxENH—Port A Bit[x] Interrupt Request Enable High Bit Refer to the Shared Interrupt Select (IRQSS) register for selection of either the LVD or the comparator as the interrupt source. Table 40. IRQ1 Enable and Priority Encoding where x indicates the register bits from 0–7. Table 41. IRQ1 Enable High Bit Register (IRQ1ENH)

Z8 Encore! XP® 4K Series Product Specification PA7VENL—Port A Bit[7] or LVD Interrupt Request Enable Low Bit PA6CENL—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit IRQ2 Enable High and Low Bit Registers Table 43 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg- isters (Tables 44 and 45) form a priority encoded enabling for interrupts in the Interrupt Request 2 register. Reserved—Must be 0. C3ENH—Port C3 Interrupt Request Enable High Bit C2ENH—Port C2 Interrupt Request Enable High Bit Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL) Table 43. IRQ2 Enable and Priority Encoding where x indicates the register bits from 0–7. Table 44. IRQ2 Enable High Bit Register (IRQ2ENH)

0 = An interrupt request is generated on the falling edge of the PAx input or PDx. 1 = An interrupt request is generated on the rising edge of the PAx input PDx. where x indicates the specific GPIO Port pin number (0 through 7). nate sources for the individual interrupts. Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL) Table 46. Interrupt Edge Select Register (IRQES)

disabled before switching between sources. 0 = PA7 is used for the interrupt for PA7VS interrupt request. 1 = The LVD is used for the interrupt for PA7VS interrupt request. 0 = PA6 is used for the interrupt for PA6CS interrupt request. 1 = The Comparator is used for the interrupt for PA6CS interrupt request. ter write of a 0 to this bit. 0 = Interrupts are disabled. Table 47. Shared Interrupt Select Register (IRQSS) Table 48. Interrupt Control Register (IRQCTL)

Z8 Encore! XP® 4K Series Product Specification Timers Overview These Z8 Encore! XP® 4K Series products contain two 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) sig- nals. The timers’ features include: 16-bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input, clock gating, or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. Timer output pin Timer interrupt In addition to the timers described in this chapter, the Baud Rate Generator of the UART (if unused) may also provide basic timing functionality. Refer to chapter UART on page 89 for information about using the Baud Rate Generator as an additional timer. Architecture Figure 9 illustrates the architecture of the timers.

Z8 Encore! XP® 4K Series Product Specification Figure 9.Timer Block Diagram Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload High and Low Byte registers and setting the prescale value to 128. If the Timer reaches FFFFH, the timer rolls over to 0000H and continues counting. Timer Operating Modes The timers can be configured to operate in the following modes: ONE-SHOT Mode In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H. The timer is automatically disabled and stops counting. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If 16-Bit PWM/Compare 16-Bit Counter with Prescaler 16-Bit Reload Register Timer Control Compare Compare Interrupt, PWM, and Timer Output Control Timer Timer Block System Timer Data Block Output Control Bus Clock Input Gate Input Capture Input Timer Interrupt Timer Output Complement

Z8 Encore! XP® 4K Series Product Specification it is appropriate to have the Timer Output make a state change at a One-Shot time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT mode. After starting the timer, set TPOL to the opposite bit value. The steps for configuring a timer for ONE-SHOT mode and initiating the count are as fol- lows: Write to the Timer Control register to: Disable the timer Configure the timer for ONE-SHOT mode. Set the prescale value. Set the initial output level (High or Low) if using the Timer Output alternate function. Write to the Timer High and Low Byte registers to set the starting count value. Write to the Timer Reload High and Low Byte registers to set the Reload value. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control register to enable the timer and initiate counting. In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows: Write to the Timer Control register to: Disable the timer Configure the timer for CONTINUOUS mode. Set the prescale value. One-Shot Mode Time-Out Period (s) Reload Value Start Value Prescale System Clock Frequency (Hz)

Z8 Encore! XP® 4K Series Product Specification If using the Timer Output alternate function, set the initial output level (High or Low). Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H). This action only affects the first pass in CONTINUOUS mode. After the first timer Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H. Write to the Timer Reload High and Low Byte registers to set the Reload value. Enable the timer interrupt (if appropriate) and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin (if using the Timer Output function) for the Timer Output alternate function. Write to the Timer Control register to enable the timer and initiate counting. In CONTINUOUS mode, the system clock always provides the timer input. The timer period is given by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT mode equation to determine the first time-out period. COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled. The input frequency of the Timer Input signal must not exceed one-fourth the system clock frequency. Further, the high or low state of the input signal pulse must be no less than twice the system clock period. A shorter pulse may not be captured. Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COUNTER mode and initiating the count are as fol- lows: Write to the Timer Control register to: Disable the timer Configure the timer for COUNTER mode Continuous Mode Time-Out Period (s) Reload Value Prescale System Clock Frequency (Hz) Caution:

Z8 Encore! XP® 4K Series Product Specification Select either the rising edge or falling edge of the Timer Input signal for the count. This selection also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function is not required to be enabled. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in COUNTER mode. After the first timer Reload in COUNTER mode, counting always begins at the reset value of 0001H. In COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. Write to the Timer Reload High and Low Byte registers to set the Reload value. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Input alternate function. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control register to enable the timer. In COUNTER mode, the number of Timer Input transitions since the timer start is given by the following equation: COMPARATOR COUNTER Mode In COMPARATOR COUNTER mode, the timer counts input transitions from the analog comparator output. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. In COMPAR- ATOR COUNTER mode, the prescaler is disabled. The frequency of the comparator output signal must not exceed one-fourth the system clock frequency. Further, the high or low state of the comparator output signal pulse must be no less than twice the system clock period. A shorter pulse may not be captured. After reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COMPARATOR COUNTER mode and initiating the count are as follows: Write to the Timer Control register to: Disable the timer Counter Mode Timer Input Transitions Current Count Value Start Value Caution:

Z8 Encore! XP® 4K Series Product Specification Configure the timer for COMPARATOR COUNTER mode Select either the rising edge or falling edge of the comparator output signal for the count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function is not required to be enabled. Write to the Timer High and Low Byte registers to set the starting count value. This action only affects the first pass in COMPARATOR COUNTER mode. After the first timer Reload in COMPARATOR COUNTER mode, counting always begins at the reset value of 0001H. Generally, in COMPARATOR COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. Write to the Timer Reload High and Low Byte registers to set the Reload value. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control register to enable the timer. In COMPARATOR COUNTER mode, the number of comparator output transitions since the timer start is given by the following equation: PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H. Comparator Output Transitions Current Count Value Start Value

Z8 Encore! XP® 4K Series Product Specification The steps for configuring a timer for PWM SINGLE OUTPUT mode and initiating the PWM operation are as follows: Write to the Timer Control register to: Disable the timer Configure the timer for PWM SINGLE OUTPUT mode. Set the prescale value. Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. Write to the PWM High and Low Byte registers to set the PWM value. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control register to enable the timer and initiate counting. The PWM period is represented by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT mode equation to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre- sented by: If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre- sented by: PWM Period (s) Reload Value Prescale System Clock Frequency (Hz) PWM Output High Time Ratio (%) Reload Value PWM Value Reload Value 100 PWM Output High Time Ratio (%) PWM Value Reload Value 100

Z8 Encore! XP® 4K Series Product Specification PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT mode, the timer outputs a Pulse-Width Modulated (PWM) out- put signal pair (basic PWM signal and its complement) through two GPIO Port pins. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H. The timer also generates a second PWM output signal Timer Output Complement. The Timer Output Complement is the complement of the Timer Output PWM signal. A pro- grammable deadband delay can be configured to time delay (0 to 128 system clock cycles) PWM output transitions on these two pins from a low to a high (inactive to active). This ensures a time gap between the deassertion of one PWM output to the assertion of its com- plement. The steps for configuring a timer for PWM DUAL OUTPUT mode and initiating the PWM operation are as follows: Write to the Timer Control register to: Disable the timer Configure the timer for PWM DUAL OUTPUT mode by writing the TMODE bits in the TxCTL1 register and theTMODEHI bit in TxCTL0 register. Set the prescale value. Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. Write to the PWM High and Low Byte registers to set the PWM value. Write to the PWM Control register to set the PWM dead band delay value. The deadband delay must be less than the duration of the positive phase of the PWM signal (as defined by the PWM high and low byte registers). It must also be less than the

Z8 Encore! XP® 4K Series Product Specification duration of the negative phase of the PWM signal (as defined by the difference between the PWM registers and the Timer Reload registers). Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. Configure the associated GPIO port pin for the Timer Output and Timer Output Complement alternate functions. The Timer Output Complement function is shared with the Timer Input function for both timers. Setting the timer mode to Dual PWM automatically switches the function from Timer In to Timer Out Complement. Write to the Timer Control register to enable the timer and initiate counting. The PWM period is represented by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT mode equation determines the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre- sented by: If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre- sented by: CAPTURE Mode In CAPTURE mode, the current timer count value is recorded when the appropriate exter- nal Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The INPCAP bit in TxCTL0 register is set to indicate the timer interrupt is because of an input capture event. The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an PWM Period (s) Reload Value Prescale System Clock Frequency (Hz) PWM Output High Time Ratio (%) Reload Value PWM Value Reload Value 100 PWM Output High Time Ratio (%) PWM Value Reload Value 100

Z8 Encore! XP® 4K Series Product Specification interrupt and continues counting. The INPCAP bit in TxCTL0 register clears indicating the timer interrupt is not because of an input capture event. The steps for configuring a timer for CAPTURE mode and initiating the count are as fol- lows: Write to the Timer Control register to: Disable the timer Configure the timer for CAPTURE mode. Set the prescale value. Set the Capture edge (rising or falling) for the Timer Input. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). Write to the Timer Reload High and Low Byte registers to set the Reload value. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these registers allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a Reload. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 register. Configure the associated GPIO port pin for the Timer Input alternate function. Write to the Timer Control register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: CAPTURE RESTART Mode In CAPTURE RESTART mode, the current timer count value is recorded when the accept- able external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 register is set to indicate the timer interrupt is because of an input capture event. Capture Elapsed Time (s) Capture Value Start Value Prescale System Clock Frequency (Hz)

Z8 Encore! XP® 4K Series Product Specification If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 register is cleared to indicate the timer interrupt is not caused by an input capture event. The steps for configuring a timer for CAPTURE RESTART mode and initiating the count are as follows: Write to the Timer Control register to: Disable the timer Configure the timer for CAPTURE RESTART mode by writing the TMODE bits in the TxCTL1 register and the TMODEHI bit in TxCTL0 register. Set the prescale value. Set the Capture edge (rising or falling) for the Timer Input. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). Write to the Timer Reload High and Low Byte registers to set the Reload value. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a Reload. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 register. Configure the associated GPIO port pin for the Timer Input alternate function. Write to the Timer Control register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: COMPARE Mode In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled, Capture Elapsed Time (s) Capture Value Start Value Prescale System Clock Frequency (Hz)

Z8 Encore! XP® 4K Series Product Specification the Timer Output pin changes state (from Low to High or from High to Low) upon Com- pare. If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. The steps for configuring a timer for COMPARE mode and initiating the count are as fol- lows: Write to the Timer Control register to: Disable the timer Configure the timer for COMPARE mode. Set the prescale value. Set the initial logic level (High or Low) for the Timer Output alternate function, if appropriate. Write to the Timer High and Low Byte registers to set the starting count value. Write to the Timer Reload High and Low Byte registers to set the Compare value. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. Write to the Timer Control register to enable the timer and initiate counting. In Compare mode, the system clock always provides the timer input. The Compare time can be calculated by the following equation: GATED Mode In GATED mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal remains asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset. The steps for configuring a timer for GATED mode and initiating the count are as follows: Compare Mode Time (s) Compare Value Start Value Prescale System Clock Frequency (Hz)

Z8 Encore! XP® 4K Series Product Specification Write to the Timer Control register to: Disable the timer Configure the timer for GATED mode. Set the prescale value. Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the reset value of 0001H. Write to the Timer Reload High and Low Byte registers to set the Reload value. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input deassertion and reload events. If appropriate, configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting TICONFIG field of the TxCTL0 register. Configure the associated GPIO port pin for the Timer Input alternate function. Write to the Timer Control register to enable the timer. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer Input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control Register. The timer input is the system clock. Every subsequent acceptable transition (after the first) of the Timer Input signal captures the current count value. The Capture value is written to the Timer PWM High and Low Byte Registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. The INPCAP bit in TxCTL0 register is set to indicate the timer interrupt is caused by an input capture event. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 register is cleared to indicate the timer interrupt is not because of an input capture event. The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the count are as follows: Write to the Timer Control register to: Disable the timer Configure the timer for CAPTURE/COMPARE mode. Set the prescale value.

Z8 Encore! XP® 4K Series Product Specification Set the Capture edge (rising or falling) for the Timer Input. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). Write to the Timer Reload High and Low Byte registers to set the Compare value. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers.By default, the timer interrupt are generated for both input capture and reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 register. Configure the associated GPIO port pin for the Timer Input alternate function. Write to the Timer Control register to enable the timer. Counting begins on the first appropriate transition of the Timer Input signal. No interrupt is generated by this first edge. In CAPTURE/COMPARE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: Reading the Timer Count Values The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte reg- ister is read, the contents of the Timer Low Byte register are placed in a holding register. A subsequent read from the Timer Low Byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte register returns the actual value in the counter. Timer Pin Signal Operation Timer Output is a GPIO Port pin alternate function. The Timer Output is toggled every time the counter is reloaded. The Timer Input can be used as a selectable counting source. It shares the same pin as the complementary timer output. When selected by the GPIO Alternate Function Registers, this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT mode. For this mode, there is no timer input available. Capture Elapsed Time (s) Capture Value Start Value Prescale System Clock Frequency (Hz)

reads from TxL read the register directly. Byte) at the next clock edge. The counter continues counting from the new value. These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value. Table 49. Timer 0–1 High Byte Register (TxH) Table 50. Timer 0–1 Low Byte Register (TxL)

two bytes form the 16-bit Compare value. store the Capture values for the CAPTURE and CAPTURE/COMPARE modes. Table 51. Timer 0–1 Reload High Byte Register (TxRH) Table 52. Timer 0–1 Reload Low Byte Register (TxRL) Table 53. Timer 0–1 PWM High Byte Register (TxPWMH)

operating in Capture or Capture/Compare modes. recent timer interrupt is caused by an input capture event. TxCTL1 register description for details of the full timer mode decoding. This field configures timer interrupt definition. Table 54. Timer 0–1 PWM Low Byte Register (TxPWML) Table 55. Timer 0–1 Control Register 0 (TxCTL0)

before the Timer Output and the Timer Output Complement are forced to their active state. value, and determine the timer operating mode. Operation of this bit is a function of the current operating mode of the timer. When the timer is disabled, the Timer Output signal is set to the value of this bit. Table 56. Timer 0–1 Control Register 1 (TxCTL1)

Z8 Encore! XP® 4K Series Product Specification When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. PWM SINGLE OUTPUT mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. CAPTURE mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. GATED mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal. PWM DUAL OUTPUT mode 0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. When enabled, the Timer Output Complement is forced Low (0) upon PWM count match and forced High (1) upon Reload. The PWMD field in TxCTL0 register is a programmable delay to control the

Z8 Encore! XP® 4K Series Product Specification number of cycles time delay before the Timer Output and the Timer Output Complement is forced to High (1). 1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload.When enabled, the Timer Output Complement is forced High (1) upon PWM count match and forced Low (0) upon Reload. The PWMD field in TxCTL0 register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to Low (0). CAPTURE RESTART mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARATOR COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. Also: 0 = Count is captured on the rising edge of the comparator output. 1 = Count is captured on the falling edge of the comparator output. When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, Tx- OUT will change to whatever state the TPOL bit is in.The timer does not need to be en- abled for that to happen. Also, the Port data direction sub register is not needed to be set to output on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT. PRES—Prescale value. The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The pres- caler is reset each time the Timer is disabled. This reset ensures proper clock division each time the Timer is restarted. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 TMODE—Timer mode This field along with the TMODEHI bit in TxCTL0 register determines the operating mode of the timer. TMODEHI is the most significant bit of the Timer mode selection value. Caution:

Z8 Encore! XP® 4K Series Product Specification 0000 = ONE-SHOT mode 0001 = CONTINUOUS mode 0010 = COUNTER mode 0011 = PWM SINGLE OUTPUT mode 0100 = CAPTURE mode 0101 = COMPARE mode 0110 = GATED mode 0111 = CAPTURE/COMPARE mode 1000 = PWM DUAL OUTPUT mode 1001 = CAPTURE RESTART mode 1010 = COMPARATOR COUNTER mode

Z8 Encore! XP® 4K Series Product Specification Watch-Dog Timer Overview The Watch-Dog Timer (WDT) protects against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore! XP® 4K Series devices into unsuitable operating states. The Watch-Dog Timer includes the following fea- tures: On-chip RC oscillator A selectable time-out response: reset or interrupt 24-bit programmable time-out value Operation The Watch-Dog Timer (WDT) is a one-shot timer that resets or interrupts the Z8 Encore! XP® 4K Series devices when the WDT reaches its terminal count. The Watch-Dog Timer uses a dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer operates in only two modes: ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. Perform an enable by executing the WDT instruction or by setting the WDT_AO Flash Option Bit. The WDT_AO bit forces the Watch-Dog Timer to operate immediately upon reset, even if a WDT instruction has not been executed. The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is described by the following equation: where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator frequency is 10KHz. The Watch-Dog Timer cannot be refreshed after it reaches 000002H. The WDT Reload Value must not be set to values below 000004H. Table 57 provides information about approximate time-out delays for the minimum and maximum WDT reload values. WDT Time-out Period (ms) WDT Reload Value

Z8 Encore! XP® 4K Series Product Specification Watch-Dog Timer Refresh When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog Timer Reload registers. The Watch-Dog Timer counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload registers. Counting resumes following the reload operation. When the Z8 Encore! XP® 4K Series devices are operating in DEBUG Mode (using the on-chip debugger), the Watch-Dog Timer is continuously refreshed to prevent any Watch- Dog Timer time-outs. Watch-Dog Timer Time-Out Response The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the Watch-Dog Timer generates either an interrupt or a system reset. The WDT_RES Flash Option Bit determines the time-out response of the Watch-Dog Timer. Refer to the chapter Flash Option Bits on page 148 for information regarding programming of the WDT_RES Flash Option Bit. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Reset Sta- tus (RSTSTAT) register (see page 27). If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watch-Dog Timer counter rolls over to its maximum value of FFFFFH and continues counting. The Watch- Dog Timer counter is not automatically returned to its Reload Value. The Reset Status (RSTSTAT) Register must be read before clearing the WDT interrupt. This read clears the WDT timeout flag and prevents further WDT interrupts from immedi- ately occurring. Table 57. Watch-Dog Timer Approximate Time-Out Delays 400 μs Minimum time-out delay FFFFFF 16,777,215 28 minutes Maximum time-out delay

Z8 Encore! XP® 4K Series Product Specification WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP® 4K Series devices are in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP bit in the Reset Status (RSTSTAT) register are set to 1 following a WDT time-out in STOP mode. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detection on page 20 for more information about STOP Mode Recovery. If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. WDT Reset in NORMAL Operation If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT) register is set to 1. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detection on page 20 for more information about system reset. WDT Reset in STOP Mode If configured to generate a Reset when a time-out occurs and the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the STOP bit in the Reset Status (RSTSTAT) register are set to 1 following WDT time-out in STOP mode. Refer to the chapter Reset, STOP Mode Recovery and Low Voltage Detec- tion on page 20 for more information. Watch-Dog Timer Reload Unlock Sequence Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers. The following sequence is required to unlock the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access. Write 55H to the Watch-Dog Timer Control register (WDTCTL). Write AAH to the Watch-Dog Timer Control register (WDTCTL). Write the Watch-Dog Timer Reload Upper Byte register (WDTU). Write the Watch-Dog Timer Reload High Byte register (WDTH). Write the Watch-Dog Timer Reload Low Byte register (WDTL).

when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed. ture and 3.3V supply voltage. and Timing on page 220 for details. writes to the Reload registers. This register address is shared with the read-only Reset Status Register. Table 58. Watch-Dog Timer Control Register (WDTCTL)

allowed to modify the contents of the watch-dog timer reload registers. WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate Reload Value. Reading from these registers returns the current Watch-Dog Timer count value. The 24-bit WDT Reload Value must not be set to a value less than 000004H. Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value. Middle byte, Bits[15:8], of the 24-bit WDT reload value. Table 59. Watch-Dog Timer Reload Upper Byte Register (WDTU) R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value. Table 60. Watch-Dog Timer Reload High Byte Register (WDTH) R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value.

Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value. Table 61. Watch-Dog Timer Reload Low Byte Register (WDTL) R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value.

Z8 Encore! XP® 4K Series Product Specification UART Overview The universal asynchronous receiver/transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include: 8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking Option of one or two STOP bits Separate transmit and receive interrupts Framing, parity, overrun and break detection Separate transmit and receive enables 16-bit baud rate generator (BRG) Selectable MULTIPROCESSOR (9-bit) mode with three configurable interrupt schemes Baud rate generator (BRG) can be configured and used as a basic 16-bit timer Driver enable (DE) output for external bus transceivers Architecture The UART consists of three primary functional blocks: transmitter, receiver, and baud rate generator. The UART’s transmitter and receiver function independently, but employ the same baud rate and data format. Figure 10 illustrates the UART architecture.

Z8 Encore! XP® 4K Series Product Specification Figure 10.UART Block Diagram Operation Data Format The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even or odd parity bit can be added to the data stream. Each character begins with an active Low START bit and ends with either 1 or 2 active High STOP bits. Figures 11 and 12 illustrates the asynchronous data format employed by the UART without parity and with parity, respectively. Receive Shifter Receive Data Transmit Data Transmit Shift TXD RXD System Bus Parity Checker Parity Generator Receiver Control Control Registers Transmitter Control CTS Status Register Register Register Register Baud Rate Generator DE with Address Compare

Z8 Encore! XP® 4K Series Product Specification Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data. Write the UART Control 1 register to select the outgoing address bit. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 10. Make any changes to the Multiprocessor Bit Transmitter (MPBT) value, if appropriate and MULTIPROCESSOR mode is enabled,. 11. To transmit additional bytes, return to Step 5. Transmitting Data using the Interrupt-Driven Method The UART Transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow these steps to configure the UART for interrupt- driven data transmission: Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud rate. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. Execute a DI instruction to disable interrupts. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the acceptable priority. Write to the UART Control 1 register to enable MULTIPROCESSOR (9-bit) mode functions, if MULTIPROCESSOR mode is appropriate. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR mode. Write to the UART Control 0 register to: Set the transmit enable bit (TEN) to enable the UART for data transmission Enable parity, if appropriate and if MULTIPROCESSOR mode is not enabled, and select either even or odd parity. Set or clear CTSE to enable or disable control from the remote receiver using the CTS pin. Execute an EI instruction to enable interrupts.

Z8 Encore! XP® 4K Series Product Specification The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: Write the UART Control 1 register to select the multiprocessor bit for the byte to be transmitted: Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data register to again become empty. Receiving Data using the Polled Method Follow these steps to configure the UART for polled data reception: Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud rate for the incoming data stream. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. Write to the UART Control 1 register to enable MULTIPROCESSOR mode functions, if appropriate. Write to the UART Control 0 register to: Set the receive enable bit (REN) to enable the UART for data reception Enable parity, if appropriate and if Multiprocessor mode is not enabled, and select either even or odd parity. Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 5. If the Receive Data register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data. 10. Read data from the UART Receive Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the MULTIPROCESSOR mode bits MPMD[1:0]. 11. Return to Step 4 to receive additional data.

Z8 Encore! XP® 4K Series Product Specification Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error condi- tions). Follow these steps to configure the UART receiver for interrupt-driven operation: Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud rate. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. Execute a DI instruction to disable interrupts. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the acceptable priority. Clear the UART Receiver interrupt in the applicable Interrupt Request register. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode functions, if appropriate. Set the Multiprocessor Mode Select (MPEN) to Enable MULTIPROCESSOR mode. Set the Multiprocessor Mode Bits, MPMD[1:0], to select the acceptable address matching scheme. Configure the UART to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore!® devices without a DMA block) Write the device address to the Address Compare Register (automatic MULTIPROCESSOR modes only). Write to the UART Control 0 register to: Set the receive enable bit (REN) to enable the UART for data reception Enable parity, if appropriate and if multiprocessor mode is not enabled, and select either even or odd parity. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: Checks the UART Status 0 register to determine the source of the interrupt - error, break, or received data. Reads the data from the UART Receive Data register if the interrupt was because of data available. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the MULTIPROCESSOR mode bits MPMD[1:0]. Clears the UART Receiver interrupt in the applicable Interrupt Request register.

Z8 Encore! XP® 4K Series Product Specification Executes the IRET instruction to return from the interrupt-service routine and await more data. Clear To Send (CTS) Operation The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sam- pled one system clock before beginning any new character transmission. To delay trans- mission of the next data character, an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins. For multiple character trans- missions, this action is typically performed during Stop Bit transmission. If CTS deasserts in the middle of a character transmission, the current character is sent completely. MULTIPROCESSOR (9-bit) Mode The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for selec- tive communication when a number of processors share a common UART bus. In MULTI- PROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is transmitted immediately following the 8-bits of data and immediately preceding the Stop bit(s) as illustrated in Figure 13. The character format is: Figure 13.UART Asynchronous MULTIPROCESSOR Mode Data Format In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the Multi- processor control bit. The UART Control 1 and Status 1 registers provide MULTIPRO- CESSOR (9-bit) mode control and status information. If an automatic address matching scheme is enabled, the UART Address Compare register holds the network address of the device. MULTIPROCESSOR (9-bit) Mode Receive Interrupts When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed to it. The determination of whether a frame of data is addressed to the UART can be made in hardware, software or some combination of the two, depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, because it does not require access to the UART when it receives data directed to other Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 MP Data Field lsb msb Idle State of Line Stop Bit(s)

Z8 Encore! XP® 4K Series Product Specification devices on the multi-node network. The following three MULTIPROCESSOR modes are available in hardware: Interrupt on all address bytes Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all mul- tiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software clears MPMD[0]. Each new incoming byte interrupts the CPU. The software is responsible for determining the end of the frame. It checks for the end-of-frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame is different from the UART’s address, MPMD[0] must be set to 1 causing the UART inter- rupts to go inactive until the next address byte. If the new frame’s address matches the UART’s, the data in the new frame is processed as well. The second scheme requires the following: set MPMD[1:0] to 10B and write the UART’s address into the UART Address Compare Register. This mode introduces additional hard- ware control, interrupting only on frames that match the UART’s address. When an incoming address byte does not match the UART’s address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an inter- rupt is issued and further interrupts now occur on each succesive data byte. When the first data byte in the frame is read, the NEWFRM bit of the UART Status 1 Register is asserted. All successive data bytes have NEWFRM=0. When the next address byte occurs, the hard- ware compares it to the UART’s address. If there is a match, the interrupts continues and the NEWFRM bit is set for the first byte of the new frame. If there is no match, the UART ignores all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s address into the UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame remains accompanied by a NEWFRM assertion. External Driver Enable The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This fea- ture reduces the software overhead associated with using a GPIO pin to control the trans- ceiver when communicating on a multi-transceiver bus, such as RS-485. Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 14. The Driver Enable signal asserts when a byte is written to the UART Transmit Data register. The Driver Enable signal

Z8 Encore! XP® 4K Series Product Specification asserts at least one UART bit period and no greater than two UART bit periods before the Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver Enable signal deasserts one system clock period after the final Stop bit is transmitted. This one system clock delay allows both time for data to clear the transceiver before disabling it, as well as the ability to determine if another character follows the current character. In the event of back to back characters (new data must be written to the Transmit Data Regis- ter before the previous character is completely transmitted) the DE signal is not deasserted between characters. The Depol bit in the UART Control Register 1 sets the polarity of the Driver Enable signal. Figure 14.UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) The Driver Enable to Start bit setup time is calculated as follows: UART Interrupts The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the Baud Rate Generator can also func- tion as a basic timer with interrupt capability. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit (TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans- mission. The TDRE interrupt occurs after the Transmit shift register has shifted the first bit of data out. The Transmit Data register can now be written with the next character to send. This action provides 7 bit periods of latency to load the Transmit Data register before the Transmit shift register completes shifting the current character. Writing to the UART Transmit Data register clears the TDRE bit to 0. Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity Data Field lsb msb Idle State of Line Stop Bit DE Baud Rate (Hz) DE to Start Bit Setup Time (s) Baud Rate (Hz)

Z8 Encore! XP® 4K Series Product Specification Receiver Interrupts The receiver generates an interrupt when any of the following occurs: A data byte is received and is available in the UART Receive Data register. This interrupt can be disabled independently of the other receiver interrupt sources. The received data in- terrupt occurs after the receive character has been received and placed in the Receive Data register. To avoid an overrun error, software must respond to this received data available condition before the next character is completely received. In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte. A break is received An overrun is detected A data framing error is detected UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and must be ignored. The BRKD bit indi- cates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received. UART Data and Error Handling Procedure Figure 15 illustrates the recommended procedure for use in UART receiver interrupt ser- vice routines. Note:

Z8 Encore! XP® 4K Series Product Specification Figure 15.UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the baud rate generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This condition allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed. UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans- mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value Receiver Errors? No Yes Read Status Discard Data Read Data which Interrupt Receiver Ready clears RDA bit and resets error bits Read Data

BIRQ bit in the UART Control 1 register to 1. Encoder/Decoder chapter on page 109. address with the read-only UART Receive Data register. Table 62. UART Transmit Data Register (U0TXD)

UART transmitter data byte to be shifted out through the TXDx pin. ter File address with the Write-only UART Transmit Data register. tify the current UART operating configuration and status. UART Receive Data register clears this bit. 0 = The UART Receive Data register is empty. 1 = There is a byte in the UART Receive Data register. Table 63. UART Receive Data Register (U0RXD) Table 64. UART Status 0 Register (U0STAT0)

Z8 Encore! XP® 4K Series Product Specification 102 0 = No parity error has occurred. 1 = A parity error has occurred. OE—Overrun Error This bit indicates that an overrun error has occurred. An overrun occurs when new data is received and the UART Receive Data register has not been read. If the RDA bit is reset to 0, reading the UART Receive Data register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. FE—Framing Error This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data register clears this bit. 0 = No framing error occurred. 1 = A framing error occurred. BRKD—Break Detect This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop bit(s) are all 0s this bit is set to 1. Reading the UART Receive Data register clears this bit. 0 = No break occurred. 1 = A break occurred. TDRE—Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data. Writing to the UART Transmit Data register resets this bit. 0 = Do not write to the UART Transmit Data register. 1 = The UART Transmit Data register is ready to receive an additional byte to be transmit- ted. TXE—Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is fin- ished. 0 = Data is currently transmitting. 1 = Transmission is complete. CTS—CTS signal When this bit is read it returns the level of the CTS signal. This signal is active Low.

This register contains multiprocessor control and status bits. Data register resets this bit to 0. 0 = The current byte is not the first data byte of a new frame. 1 = The current byte is the first data byte of a new frame. Receive Data register resets this bit to 0. trol registers must not be written while the UART is enabled. Table 65. UART Status 1 Register (U0STAT1) Table 66. UART Control 0 Register (U0CTL0)

This bit enables or disables the receiver. 0 = The CTS signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. This bit enables or disables parity. Even or odd is determined by the PSEL bit. 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. progress, so ensure that the transmitter has finished sending data before setting this bit. 1 = Forces a break condition by setting the output of the transmitter to zero. 0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits. 1 = All transmitted data is looped back to the receiver. 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. Table 67. UART Control 1 Register (U0CTL1)

Z8 Encore! XP® 4K Series Product Specification 105 address mismatch occurs. 11 = The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register. MPEN—MULTIPROCESSOR (9-bit) Enable This bit is used to enable MULTIPROCESSOR (9-bit) mode. 0 = Disable MULTIPROCESSOR (9-bit) mode. 1 = Enable MULTIPROCESSOR (9-bit) mode. MPBT—Multiprocessor Bit Transmit This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. The 9th bit is used by the receiving device to determine if the data byte contains address or data infor- mation. 0 = Send a 0 in the multiprocessor bit location of the data stream (data byte). 1 = Send a 1 in the multiprocessor bit location of the data stream (address byte). DEPOL—Driver Enable Polarity 0 = DE signal is Active High. 1 = DE signal is Active Low. BRGCTL—Baud Rate Control This bit causes an alternate UART behavior depending on the value of the REN bit in the UART Control 0 Register. When the UART receiver is not enabled (REN=0), this bit determines whether the Baud Rate Generator issues interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High Byte is read. RDAIRQ—Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Con- troller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request. IREN—Infrared Encoder/Decoder Enable 0 = Infrared Encoder/Decoder is disabled. UART operates normally. 1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through the Infrared Encoder/Decoder.

ister. Receive interrupts and RDA assertions only occur in the event of a match. This 8-bit value is compared to incoming address bytes. mission rate (baud rate) of the UART. Table 68. UART Address Compare Register (U0ADDR) Table 69. UART Baud Rate High Byte Register (U0BRH) Table 70. UART Baud Rate Low Byte Register (U0BRL)

For reliable communication, the UART baud rate error must never exceed 5 percent. used crystal oscillator frequencies. Table 71. UART Baud Rates

10.0 MHz System Clock

5.5296 MHz System Clock

3.579545 MHz System Clock

1.8432 MHz System Clock

Table 71. UART Baud Rates (Continued)

Z8 Encore! XP® 4K Series Product Specification 110 is passed to the Infrared Endec through the RXD pin, decoded by the Infrared Endec, and passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared Endec data rate is calculated using the following equation: Transmitting IrDA Data The data to be transmitted using the infrared transceiver is first sent to the UART. The UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared data bit is 16 clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low for the full 16 clock period. If the data to be transmitted is 0, the transmitter first out- puts a 7 clock low period, followed by a 3 clock high pulse. Finally, a 6 clock low pulse is output to complete the full 16 clock data period. Figure 17 illustrates IrDA data transmis- sion. When the Infrared Endec is enabled, the UART’s TXD signal is internal to the Z8 Encore! XP® 4K Series products while the IR_TXD signal is output through the TXD pin. Figure 17.Infrared Data Transmission Infrared Data Rate (bits/s) System Clock Frequency (Hz) UART Baud Rate Divisor Value Baud Rate IR_TXD UART’s 16 clock period Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1 7-clock delay 3 clock pulse TXD Clock

Z8 Encore! XP® 4K Series Product Specification 111 Receiving IrDA Data Data received from the infrared transceiver using the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is used by the Infrared Endec to generate the demodulated signal (RXD) that drives the UART. Each UART/Infrared data bit is 16-clocks wide. Figure 18 illustrates data recep- tion. When the Infrared Endec is enabled, the UART’s RXD signal is internal to the Z8 Encore! XP® 4K Series products while the IR_RXD signal is received through the RXD pin. Figure 18.IrDA Data Reception Infrared Data Reception The system clock frequency must be at least 1.0 MHz to ensure proper reception of the 1.4 μs minimum width pulses allowed by the IrDA standard. Endec Receiver Synchronization The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate an input stream for the UART and to create a sampling window for detection of incoming pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods with respect to the incoming IrDA data stream. When a falling edge in the input data stream is detected, the Endec counter is reset. When the count reaches a value of 8, the UART RXD value is updated to reflect the value of the decoded data. When the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. The window remains open until the count again reaches 8 (in other words, 24 baud clock periods since the previous pulse was detected), giving the Endec a sampling window of Baud Rate UART’s IR_RXD 16 clock period Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1 8 clock delay Clock RXD 16 clock period 16 clock period 16 clock period 16 clock period Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1 min. 1.4μs pulse Caution:

Z8 Encore! XP® 4K Series Product Specification 112 minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the Endec clock counter is reset, resynchronizing the Endec to the incoming signal, allowing the Endec to tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the Endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchronized to the incoming data stream when a Start bit is received. Infrared Encoder/Decoder Control Register Definitions All Infrared Endec configuration and status information is set by the UART control regis- ters as defined beginning on page 89. To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling the GPIO Port alternate function for the corresponding pin. Caution:

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 113 Analog-to-Digital Converter Overview The analog-to-digital converter (ADC) converts an analog input signal to its digital repre- sentation. The features of this sigma-delta ADC include: 11-bit resolution in DIFFERENTIAL mode 10-bit resolution in SINGLE-ENDED mode Eight single-ended analog input sources are multiplexed with general-purpose I/O ports 9th analog input obtained from temperature sensor peripheral 11 pairs of differential inputs also multiplexed with general-purpose I/O ports Low-power operational amplifier (LPO) Interrupt on conversion complete Interrupt on sample value greater than programmable high threshold Interrupt on sample value smaller than programmable low threshold Bandgap generated internal voltage reference with two selectable levels Manual in-circuit calibration is possible employing user code (offset calibration) Factory calibrated for in-circuit error compensation Architecture Figure 19 illustrates the major functional blocks of the ADC. An analog multiplexer net- work selects the ADC input from the available analog pins, ANA0 through ANA7. The input stage of the ADC allows both differential gain and buffering. The following input options are available: Unbuffered input (SINGLE-ENDED and DIFFERENTIAL modes) Buffered input with unity gain (SINGLE-ENDED and DIFFERENTIAL modes) LPO output with full pin access to the feedback path

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 114 Figure 19.Analog-to-Digital Converter Block Diagram Operation Data Format In both SINGLE-ENDED and DIFFERENTIAL modes, the effective output of the ADC is an 11- bit, signed, two’s complement digital value. In DIFFERENTIAL mode, the ADC Temp Analog Input Multiplexer Internal Voltage Reference Generator Analog In + Ref Input Sensor Analog In - VREF pin ADC IRQ ADC Data 13 bit Sigma-Delta ADC Vrefsel Analog Input Multiplexer ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 for offset calibration ANAIN Buffer Amplifier Low-Power Operational Amplifier BUFFMODE VREFEXT Amplifier tristates when disabled

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 115 can output values across the entire 11-bit range, from -1024 to +1023. In SINGLE- ENDED mode, the output generally ranges from 0 to +1023, but offset errors can cause small negative values. The ADC registers actually return 13 bits of data, but the two LSBs are intended for com- pensation use only. When the software compensation routine is performed on the 13 bit raw ADC value, two bits of resolution are lost because of a rounding error. As a result, the final value is an 11- bit number. Automatic Powerdown If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of the ADC are automatically powered down. From this powerdown state, the ADC requires 40 system clock cycles to power up. The ADC powers up when a conver- sion is requested by the ADC Control register. Single-Shot Conversion When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion are as follows: Enable the desired analog inputs by configuring the general-purpose I/O pins for alternate analog function. This configuration disables the digital input and output drivers. Write the ADC High Threshold Register and ADC Low Threshold Register if the alarm function is required. Write the ADC Control/Status Register 1 to configure the ADC Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, as well as unbuffered or buffered mode. If the alarm function is required, set ALMHEN and/or ALMLEN. Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELL bit is. contained in the ADC Control Register 0. Write to the ADC Control Register 0 to configure the ADC and begin the conversion. The bit fields in the ADC Control register can be written simultaneously (the ADC can be configured and enabled with the same write instruction): Write to the ANAIN[3:0] field to select from the available analog input sources (different input pins available depending on the device) Clear CONT to 0 to select a single-shot conversion.

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 116 If the internal voltage reference must be output to a pin, set the REFEXT bit to 1. The internal voltage reference must be enabled in this case. Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELH bit is contained in the ADC Control/Status Register 1. Set CEN to 1 to start the conversion. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered-down state, the ADC uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion. When the conversion is complete, the ADC control logic performs the following operations: 13-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:3]}. CEN resets to 0 to indicate the conversion is complete. If the High and Low alarms are disabled, an interrupt request is sent to the Interrupt Controller denoting conversion complete. If the High alarm is enabled and the ADC value is higher than the alarm threshold, an interrupt is generated. If the Low alarm is enabled and the ADC value is lower than the alarm threshold, an interrupt is generated. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered-down. Continuous Conversion When configured for continuous conversion, the ADC continuously performs an analog- to-digital conversion on the selected analog input. Each new data value over-writes the previous value stored in the ADC Data registers. An interrupt is generated after each con- version. In CONTINUOUS mode, ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not immediately detected at the next output from the ADC. The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency. Follow these steps for setting up the ADC and initiating continuous conversion: Enable the desired analog input by configuring the general-purpose I/O pins for alternate function. This action disables the digital input and output driver. Write the ADC High Threshold Register and ADC Low Threshold Register if the alarm function is required. Caution:

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 117 Write the ADC Control/Status Register 1 to configure the ADC Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, as well as unbuffered or buffered mode. If the alarm function is required, set ALMHEN and/or ALMLEN. Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELL bit is contained in the ADC Control Register 0. Write to the ADC Control Register 0 to configure the ADC for continuous conversion. The bit fields in the ADC Control register may be written simultaneously: Write to the ANAIN[3:0] field to select from the available analog input sources (different input pins available depending on the device) Set CONT to 1 to select continuous conversion. If the internal VREF must be output to a pin, set the REFEXT bit to 1. The internal voltage reference must be enabled in this case. Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELH bit is contained in ADC Control/Status Register 1. Set CEN to 1 to start the conversions. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation. An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete. The ADC writes a new data result every 256 system clock cycles. For each completed conversion, the ADC control logic performs the following operations: Writes the 13-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:3]}. If the high and low alarms are disabled, sends an interrupt request to the Interrupt Controller denoting conversion complete. If the high alarm is enabled and the ADC value is higher than the alarm threshold, generates an interrupt. If the low alarm is enabled and the ADC value is lower than the alarm threshold, generates an interrupt. To disable continuous conversion, clear the CONT bit in the ADC Control Register to 0.

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 118 Programmable Trigger Point Alarm The ADC contains two programmable trigger values, defined in the ADC High Threshold (ADCTHH) Register (Table 76 on page 128) and the ADC Low Threshold (ADCTLH) Register (Table 77 on page 128). Each of these values is 8 bits and is NOT a two’s com- plement number. The alarm is intended for single-ended operation and so the alarm values reflect positive numbers only. Both thresholds have independent control and status bits. When the ADC is enabled and the ADC value exceeds the high threshold, an ADC inter- rupt is asserted and the high threshold status bit is set. When enabled and the ADC value is less than the low threshold, an ADC interrupt is asserted and the low threshold status bit is set. Because the alarm value is positive it is compared to the most significant 8 data bits of the ADC value, excluding the sign bit. The ADC alarm bits are compared to {ADCD_H[6:0],ADCD_L[7]}. Alternatively, the alarm value is compared to the ADC value shifted left by one bit. Negative ADC values never trigger the high alarm and always trigger the low alarm. Because the ADC output is software compensated for offset, nega- tive (pre-compensated) values can occur in SINGLE-ENDED mode. The alarm is primarily intended for use in CONTINUOUS mode so that the CPU can determine threshold crossings without servicing interrupts for all ADC samples. If used in SINGLE-SHOT mode, the ADC will only interrupt the CPU if the single sample triggers an alarm. The alarm status bits are updated on each conversion, regardless of the alarm enable bit values. The alarm enable bits only determine whether or not an interrupt is generated. Interrupts The ADC is able to interrupt the CPU under three conditions: When a conversion has been completed When the 8 Most Significant Bits of a sample exceed the programmable high threshold ADCTHH[7:0] When the 8 Most Significant Bits of a sample is less than the programmable low threshold ADCTLH[7:0] The conversion interrupt occurs when the ADC is enabled and both alarms are disabled. When either or both alarms are enabled, the conversion interrupt is disabled and only the alarm interrupts may occur. When the ADC is disabled, none of the three sources can cause an interrupt to be asserted; however, an interrupt pending when the ADC is disabled is not cleared. The three interrupt events share a common CPU interrupt. The interrupt service routine must query the ADC Control/Status (ADCCTL1) Register to determine the cause of an

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 119 ADC interrupt. The register bits denoting ADC alarm status can only be set by hardware and are cleared by writing a 1. Calibration and Compensation The Z8 Encore! XP® 4K Series ADC is factory calibrated for offset error and gain error, with the compensation data stored in Flash memory. Alternatively, users can perform their own calibration, storing the values into Flash themselves. Thirdly, the user code can per- form a manual offset calibration during DIFFERENTIAL mode operation. Factory Calibration Devices that have been factory calibrated contain 30 bytes of calibration data in the Flash option bit space. This data consists of 3 bytes for each input mode, one for offset and two for gain correction. See ZiLOG Calibration Data on page 155 for a list of input modes for which calibration data exists. User Calibration If the user has precision references available, its own external calibration can be per- formed using any input modes. This calibration data will take into account buffer offset and non-linearity, so it is recommended that this calibration be performed separately for each of the ADC input modes planned for use. Manual Offset Calibration When uncalibrated, the ADC has significant offset (see Table 138, Analog-to-Digital Con- verter Electrical Characteristics and Timing, on page 221 for details). Subsequently, man- ual offset calibration capability is built into the block. When the ADC Control Register 0 sets the input mode (ANAIN[2:0]) to MANUAL OFFSET CALIBRATION mode, the differential inputs to the ADC are shorted together by an internal switch. Reading the ADC value at this point produces 0 in an ideal system. The value actually read is the ADC offset. This value can be stored in non-volatile memory (Non-Volatile Data Storage on page 163) and accessed by user code to compensate for the input offset error. There is no provision for manual gain calibration. Software Compensation Procedure Using Factory Calibration Data Overview. The value read from the ADC high and low byte registers is uncompen- sated. The user mode software must apply gain and offset correction to this uncom- pensated value for maximum accuracy. The following formula yields the compensated value: ADCcomp = (ADCuncomp - OFFCAL) + ((ADCuncomp - OFFCAL)*GAINCAL)/216

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 120 where GAINCAL is the gain calibration value, OFFCAL is the offset calibration value and ADCuncomp is the uncompensated value read from the ADC. All values are in two’s complement format. The offset compensation is performed first, followed by the gain compensation. One bit of resolution is lost because of rounding on both the offset and gain computations. As a result the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and 10 data bits. Also note that in the second term, the multiplication should be performed before the division by 216. Otherwise, the the second term will incorrectly evaluate to zero. Although the ADC can be used without the gain and offset compensation, it does exhibit non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC range but requires the ADC results to be scaled by a factor of 8/7. ADC Compensation Details High efficiency assembly code that performs this compensation is available for download on www.zilog.com. The following is a bit-specific description of the ADC compensation process used by this code. The following data bit definitions are used: 0-9, a-f = bit indices in hexadecimal s = sign bit v = overflow bit - = unused Input Data: MSB LSB s b a 9 8 7 6 5 4 3 2 1 0 - - v (ADC) ADC Output Word; if v = 1, the data is invalid s 6 5 4 3 2 1 0 Offset Correction Byte s s s s s 7 6 5 4 3 2 1 0 0 0 0 (Offset) Offset Byte shifted to align with ADC data s e d c b a 9 8 7 6 5 4 3 2 1 0 (Gain) Gain Correction Word Note: Caution:

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 121 Compensation Steps: Correct for Offset ADC MSB ADC LSB Offset MSB Offset LSB #1 MSB #1 LSB Take absolute value of the offset corrected ADC value if negative – the gain correction factor is computed assuming positive numbers, with sign restoration afterward. #2 MSB #2 LSB Also take absolute value of the gain correction word if negative. AGain MSB AGain LSB Multiply by Gain Correction Word. If in DIFFERENTIAL mode, there are two gain correction values: one for positive ADC values, another for negative ADC values. Based on the sign of #2, use the appropriate Gain Correction Word. #2 MSB #2 LSB AGain MSB AGain LSB Round the result and discard the least significant two bytes (this is equivalent to dividing by 216). 0x00 0x00 0x80 0x00 #4 MSB #4 LSB Determine sign of the gain correction factor using the sign bits from step #2. If the offset corrected ADC value AND the gain correction word have the same sign, then the factor is positive and is left unchanged. If they have differing signs, then the factor is negative and should be multiplied by -1. #5 MSB #5 LSB

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 122 Add the gain correction factor to the original offset corrected value. #5 MSB #5 LSB #1 MSB #1 LSB #6 MSB #6 LSB Shift the result to the right, using the sign bit determined in step #1 above. This will allow for the detection of computational overflow. S-> #6 MSB #6 LSB Output Data The following is the output format of the corrected ADC value. MSB LSB s v b a 9 8 7 6 5 4 3 2 1 0 - - The overflow bit in the corrected output indicates that the computed value was greater than the maximum logical value (+1023) or less than the minimum logical value (-1024). Unlike the hardware overflow bit, this is not a simple binary flag. For a normal sample (non-overflow), the sign and the overflow bit will match. If the sign bit and overflow bit do not match, a computational overflow has occurred. Input Buffer Stage Many applications require the measurement of an input voltage source with a high output impedance. This ADC provides a buffered input for such situations. The drawback of the buffered input is a limitation of the input range. When using unity gain buffered mode, the input signal must be prevented from coming too close to either VSS or VDD. See Table 138, Analog-to-Digital Converter Electrical Characteristics and Timing, on page 221 for details. This condition applies only to the input voltage level (with respect to ground) of each dif- ferential input signal. The actual differential input voltage magnitude may be less than 300 mV. The input range of the unbuffered ADC swings from VSS to VDD. Input signals smaller than 300 mV must use the unbuffered input mode. If these signals do not contain low out- put impedances, they might require off-chip buffering.

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 123 Signals outside the allowable input range can be used without instability or device dam- age. Any ADC readings made outside the input range are subject to greater inaccuracy than specified. Low-Power Operational Amplifier (LPO) The LPO is a general-purpose operational amplifier. Each of the three ports of the ampli- fier is accessible from the package pins. The LPO contains only one pin configuration: ANA0 is the output/feedback node, ANA1 is the inverting input and ANA2 is the non- inverting input. To use the LPO, it must be enabled in the Power Control Register 0 (PWRCTL0). The default state of the LPO is OFF. To use the LPO, the LPO bit must be cleared, turning it ON (Power Control Register 0 (PWRCTL0) on page 31). When making normal ADC measurements on ANA0 (measurements not involving the LPO output), the LPO bit must be OFF. Turning the LPO bit ON interferes with normal ADC measurements. Finally, this bit enables the amplifier even in STOP mode. If the amplifier is not required in STOP mode, disable it. Failing to perform this results in STOP mode currents greater than speci- fied. As with other ADC measurements, any pins used for analog purposes must be configured as such in the GPIO registers (see Port A–D Alternate Function Sub-Registers on page 42). LPO output measurements are made on ANA0, as selected by the ANAIN[3:0] bits of ADC Control Register 0. It is also possible to make single-ended measurements on ANA1 and ANA2 while the amplifier is enabled, which is often useful for determining offset con- ditions. Differential measurements between ANA0 and ANA2 may be useful for noise cancellation purposes. If the LPO output is routed to the ADC, then the BUFFMODE[2:0] bits of ADC Control/Sta- tus Register 1 must also be configured for unity-gain buffered operation. Using the LPO in an unbuffered mode is not recommended. When either input is overdriven, the amplifier output saturates at the positive or negative supply voltage. No instability results.

the analog-to-digital conversion. It also selects the voltage reference configuration. this bit to 0 when a conversion is complete. in progress, the conversion restarts. This bit remains 1 until the conversion is complete. REFOUT bit must be set to 0. Table 72. ADC Control Register 0 (ADCCTL0)

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 125 ANAIN[3:0]—Analog Input Select These bits select the analog input for conversion. Not all Port pins in this list are available in all packages for the Z8 Encore! XP® 4K Series. Refer to the chapter Pin Description on page 7 for information regarding the Port pins available with each package style. Do not enable unavailable analog inputs. Usage of these bits changes depending on the buffer mode selected in ADC Control/Status Register 1. For the reserved values, all input switches are disabled to avoid leakage or other undesir- able operation. ADC samples taken with reserved bit settings are undefined. SINGLE-ENDED: 0000 = ANA0 (transimpedance amp output when enabled) 0001 = ANA1 (transimpedance amp inverting input) 0010 = ANA2 (transimpedance amp non-inverting input) 0011 = ANA3 0100 = ANA4 0101 = ANA5 0110 = ANA6 0111 = ANA7 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = Hold transimpedance input nodes (ANA1 and ANA2) to ground. 1101 = Reserved 1110 = Temperature Sensor. 1111 = Reserved. DIFFERENTIAL (non-inverting input and inverting input respectively): 0000 = ANA0 and ANA1 0001 = ANA2 and ANA3 0010 = ANA4 and ANA5 0011 = ANA1 and ANA0 0100 = ANA3 and ANA2 0101 = ANA5 and ANA4 0110 = ANA6 and ANA5 0111 = ANA0 and ANA2 1000 = ANA0 and ANA3 1001 = ANA0 and ANA4 1010 = ANA0 and ANA5 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Manual Offset Calibration Mode

used to select the voltage reference configuration. 1= A high threshold alarm occurred. 1= A low threshold alarm occurred. the alarm threshold is passed. 1= High threshold alarm interrupt is enabled. 1= Low threshold alarm interrupt is enabled. Table 73. ADC Control/Status Register 1 (ADCCTL1)

ADC Data High Byte register latches data in the ADC Low Bits register. put is held in this register. These bits are undefined after a Reset. Table 74. ADC Data High Byte Register (ADCD_H) Table 75. ADC Data Low Bits Register (ADCD_L)

0= A hardware overflow did not occur in the ADC for the current sample. an ADC sample causes a CPU interrupt. an ADC sample causes a CPU interrupt. Table 76. ADC High Threshold High Byte (ADCTHH) Table 77. ADC Low Threshold High Byte (ADCTLH)

Analog-to-Digital Converter Z8 Encore! XP® 4K Series Product Specification 129 the ADC value drops below this value an interrupt is asserted. The alarm function is not available in DIFFERENTIAL mode.

Z8 Encore! XP® 4K Series Product Specification 130 Comparator Overview The Z8 Encore! XP® 4K Series devices feature a general purpose comparator that com- pares two analog input signals. These analog signals may be external stimulus from a pin (CINP and/or CINN) or internally generated signals. Both a programmable voltage refer- ence and the temperature sensor output voltage are available internally. The output is available as an interrupt source or can be routed to an external pin. Figure 20.Comparator Block Diagram Operation When the positive comparator input exceeds the negative input by more than the specified hysteresis, the output is a logic HIGH. When the negative input exceeds the positive by more than the hysteresis, the output is a logic LOW. Otherwise, the comparator output retains its present value. Refer to Table 140, Comparator Electrical Characteristics, on page 223 for details. CINP Pin Temperature Sensor INPSEL INNSEL CINN Pin Comparator Internal Reference REFLVL To COUT Pin To Interrupt Controller

Register 0 on page 30 for details. value of the internal voltage reference. Table 78. Comparator Control Register (CMP0)

Z8 Encore! XP® 4K Series Product Specification 132 0000 = 0.0 V 0001 = 0.2 V 0010 = 0.4 V 0011 = 0.6 V 0100 = 0.8 V 0101 = 1.0 V (Default) 0110 = 1.2 V 0111 = 1.4 V 1000 = 1.6 V 1001 = 1.8 V 1010–1111 = Reserved For 8-pin devices: 000000 = 0.00V 000001 = 0.05V 000010 = 0.10V 000011 = 0.15V 000100 = 0.20V 000101 = 0.25V 000110 = 0.30V 000111 = 0.35V 001000 = 0.40V 001001 = 0.45V 001010 = 0.50V 001011 = 0.55V 001100 = 0.60V 001101 = 0.65V 001110 = 0.70V 001111 = 0.75V 010000 = 0.80V 010001 = 0.85V 010010 = 0.90V 010011 = 0.95V 010100 = 1.00V (Default) 010101 = 1.05V 010110 = 1.10V 010111 = 1.15V 011000 = 1.20V 011001 = 1.25V 011010 = 1.30V 011011 = 1.35V 011100 = 1.40V 011101 = 1.45V 011110 = 1.50V

Z8 Encore! XP® 4K Series Product Specification 133 011111 = 1.55V 100000 = 1.60V 100001 = 1.65V 100010 = 1.70V 100011 = 1.75V 100100 = 1.80V

Z8 Encore! XP® 4K Series Product Specification 134 Temperature Sensor Overview The on-chip Temperature Sensor allows the user the ability to measure temperature on the die with either the on-board ADC or on-board comparator. This block is factory calibrated for in-circuit software correction. Uncalibrated accuracy is significantly worse, therefore the temperature sensor is not recommended for uncalibrated use. Temperature Sensor Operation The on-chip temperature sensor is a PTAT (proportional to absolute temperature) topology. A pair of Flash option bytes contain the calibration data. The temperature sensor can be disabled by a bit in the Power Control Register 0 (page 30) to reduce power consumption. The temperature sensor can be directly read by the ADC to determine the absolute value of its output. The temperature sensor output is also available as an input to the comparator for threshold type measurement determination. The accuracy of the sensor when used with the comparator is substantially less than when measured by the ADC. If the temperature sensor is routed to the ADC, the ADC must be configured in unity-gain buffered mode (See Input Buffer Stage on page 122.) The value read back from the ADC is a signed number, although it is always positive. The sensor is factory-trimmed through the ADC using the external 2.0V reference. Unless the sensor is re-trimmed for use with a different reference, it is most accurate when used with the external 2.0V reference. Because this sensor is an on-chip sensor it is recommended that the user account for the difference between ambient and die temperature when inferring ambient temperature con- ditions. During normal operation, the die undergoes heating that will cause a mismatch between the ambient temperature and that measured by the sensor. For best results, the XP device should be placed into STOP mode for sufficient time such that the die and ambient tem- peratures converge (this time will be dependent on the thermal design of the system). The temperature sensor measurement should then be made immediately after recovery from STOP mode. The following equation defines the transfer function between the temperature sensor out- put voltage and the die temperature. This is needed for comparator threshold measure- ments. V = 0.01 * T + 0.65 (where T is the temperature in C; V is the sensor output in Volts)

Z8 Encore! XP® 4K Series Product Specification 135 Assuming a compensated ADC measurement, the following equation defines the relation- ship between the ADC reading and the die temperature: T = (25/128)*(ADC - TSCAL) + 30 (where T is the temperature in C; ADC is the 10 bit compensated ADC value; and TSCAL is the temperature sensor calibration value) See Temperature Sensor Calibration Data on page 162 for the location of TSCAL. Calibration The temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30°C. Accuracy decreases as measured temperatures move further from the calibration point.

Encore! XP® 4K Series, these sectors are 512 bytes in size; each sector maps to a page. Page and sector sizes are not equal for other members of the Z8 Encore!® family. chapter Flash Option Bits on page 148 for more information about their operation. 4K Series. Figure 21 illustrates the Flash memory arrangement. Table 79. Z8 Encore! XP® 4K Series Flash Memory Configurations

Z8 Encore! XP® 4K Series Product Specification 137 Figure 21.Flash Memory Arrangement Flash Information Area The Flash information area is separate from program memory and is mapped to the address range FE00H to FFFFH. This area is readable but cannot be erased or overwritten. Factory trim values for the analog peripherals are stored here. Factory calibration data for the ADC is also stored here. 4KB Flash Program Memory 0000

8 Pages/Sectors

512 Bytes each

Addresses (hex) 03FF 0400 05FF 0600 07FF 0800 09FF 0A00 0BFF 0C00 0DFF 0E00 2KB Flash Program Memory 0000

4 Pages/Sectors

Addresses (hex) 07FF 05FF 0600 03FF 0400 01FF 0200 1KB Flash Program Memory 0000 Addresses (hex) 03FF 01FF 0200

2 Pages/Sectors

Z8 Encore! XP® 4K Series Product Specification 138 Operation The Flash Controller programs and erases Flash memory. The Flash Controller provides the proper Flash controls and timing for Byte Programming, Page Erase, and Mass Erase of Flash memory. The Flash Controller contains several protection mechanisms to prevent accidental pro- gramming or erasure. These mechanism operate on the page, sector and full-memory lev- els. The Flow Chart in Figure 22 illustrates basic Flash Controller operation. The following subsections provide details about the various operations (Lock, Unlock, Byte Program- ming, Page Protect, Page Unprotect, Page Select, Page Erase, and Mass Erase) listed in Figure 22.

Z8 Encore! XP® 4K Series Product Specification 139 Figure 22.Flash Controller Operation Flow Chart Reset Page 73H No Yes 8CH No Yes Program/Erase Enabled 95H No Yes Write FCTL Lock State 0 Lock State 1 Write FCTL Write FCTL Byte Program Page Erase Write Page Select Register Write Page Select Register Page in No No Unlocked Protected Sector? Writes to Page Select Register in Lock State 1 result in a return to Lock State 0 Page Select Yes values match? Yes

Z8 Encore! XP® 4K Series Product Specification 140 Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow programming and erasing of the Flash with system clock frequencies rang- ing from 32 KHz (32768 Hz) through 20 MHz. The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash Frequency value must contain the system clock frequency (in KHz). This value is calcu- lated using the following equation: Flash programming and erasure are not supported for system clock frequencies below 32 KHz (32768 Hz) or above 20 MHz. The Flash Frequency High and Low Byte regis- ters must be loaded with the correct value to ensure operation of the Z8 Encore! XP® 4K Series devices. Flash Code Protection Against External Access The user code contained within the Flash memory can be protected against external access by the on-chip debugger. Programming the FRP Flash Option Bit prevents reading of the user code with the On-Chip Debugger. Refer to the chapter Flash Option Bits on page 148 and the chapter On-Chip Debugger on page 167 for more information. Flash Code Protection Against Accidental Program and Erasure The Z8 Encore! XP® 4K Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by a com- bination of the Flash Option bits, the register locking mechanism, the page select redun- dancy and the sector level protection control of the Flash Controller. Flash Code Protection Using the Flash Option Bits The FRP and FWP Flash Option Bits combine to provide three levels of Flash Program Memory protection as listed in Table 80. Refer to the chapter Flash Option Bits on page 148 for more information. FFREQ[15:0] System Clock Frequency (Hz) 1000 Caution:

troller reverts to a locked state. If the two writes match, the selected page becomes active. tected. Any other value written to the Flash Control register locks the Flash Controller. Mass Erase is not allowed in the user code but only in through the Debug Port. 512 bytes, equal to the page size. Table 80. Flash Code Protection Using the Flash Option Bits

Z8 Encore! XP® 4K Series Product Specification 142 sector can no longer be written or erased. After a bit of the Sector Protect Register has been set, it can not be cleared except by powering down the device. Byte Programming The Flash Memory is enabled for byte programming after unlocking the Flash Controller and successfully enabling either Mass Erase or Page Erase. When the Flash Controller is unlocked and Mass Erase is successfully completed, all Program Memory locations are available for byte programming. In contrast, when the Flash Controller is unlocked and Page Erase is successfully completed, only the locations of the selected page are available for byte programming. An erased Flash byte contains all 1’s (FFH). The programming operation can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits) from 0 to 1 requires execution of either the Page Erase or Mass Erase commands. Byte Programming can be accomplished using the On-Chip Debugger's Write Memory command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU User Manual (available for download at www.zilog.com)for a description of the LDC and LDCI instructions. While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. To exit program- ming mode and lock the Flash, write any value to the Flash Control register, except the Mass Erase or Page Erase commands. The byte at each address of the Flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. Doing so may result in corrupted data at the target byte. Page Erase The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Flash Page Select register identi- fies the page to be erased. Only a page residing in an unprotected sector can be erased. With the Flash Controller unlocked and the active page set, writing the value 95h to the Flash Control register initiates the Page Erase operation. While the Flash Controller exe- cutes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. If the Page Erase operation is performed using the On-Chip Debug- ger, poll the Flash Status register to determine when the Page Erase operation is complete. When the Page Erase is complete, the Flash Controller returns to its locked state. Mass Erase The Flash memory can also be Mass Erased using the Flash Controller, but only by using the On-Chip Debugger. Mass Erasing the Flash memory sets all bytes to the value FFH. With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the Caution:

Z8 Encore! XP® 4K Series Product Specification 143 value 63H to the Flash Control register initiates the Mass Erase operation. While the Flash Controller executes the Mass Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Sta- tus register to determine when the Mass Erase operation is complete. When the Mass Erase is complete, the Flash Controller returns to its locked state. Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Program- ming algorithms by controlling the Flash programming signals directly. Row programming is recommended for gang programming applications and large volume customers who do not require in-circuit initial programming of the Flash memory. Page Erase operations are also supported when the Flash Controller is bypassed. Please refer to the document entitled Third-Party Flash Programming Support for Z8 Encore!® for more information about bypassing the Flash Controller. This document is available for download at www.zilog.com. Flash Controller Behavior in Debug Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger: The Flash Write Protect option bit is ignored. The Flash Sector Protect register is ignored for programming and erase operations. Programming operations are not limited to the page selected in the Page Select register. Bits in the Flash Sector Protect register can be written to one or zero. The second write of the Page Select register to unlock the Flash Controller is not necessary. The Page Select register can be written when the Flash Controller is unlocked. The Mass Erase command is enabled through the Flash Control register. For security reasons, the flash controller allows only a single page to be opened for write/erase. When writing multiple flash pages, the flash controller must go through the unlock sequence again to select another page. Caution:

8CH = Second unlock command. 95H = Page Erase command (must be third command in sequence to initiate Page Erase). 63H = Mass Erase command (must be third command in sequence to initiate Mass Erase). Table 81. Flash Control Register (FCTL)

File address with the Write-only Flash Control Register. 000000 = Flash Controller locked. 000001 = First unlock command received (73H written). 000010 = Second unlock command received (8CH written). 000011 = Flash Controller unlocked. 000100 = Sector protect register selected. 001xxx = Program operation in progress. 010xxx = Page erase operation in progress. address target the Flash Page Select Register. FPS[6:0] are chosen for program/erase operation. Table 82. Flash Status Register (FSTAT)

ory address space at addresses FE00H through FFFFH. This 7-bit field identifies the Flash memory page for Page Erase and page unlocking. devices, the upper 6 bits must always be 0. The Flash Sector Protect (FPROT) register is shared with the Flash Page Select Register. without powering down the device. Table 83. Flash Page Select Register (FPS) Table 84. Flash Sector Protect Register (FPROT)

Each bit corresponds to a 512 byte Flash sector. For the Z8F04xx devices all bits are used. form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. KHz) and is calculated using the following equation:. supported for system clock frequencies below 20 KHz or above 20 MHz. High byte of the 16-bit Flash Frequency value. Low byte of the 16-bit Flash Frequency value. Table 85. Flash Frequency High Byte Register (FFREQH) Table 86. Flash Frequency Low Byte Register (FFREQL)

Z8 Encore! XP® 4K Series Product Specification 148 Flash Option Bits Overview Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore! XP® 4K Series operation. The feature configuration data is stored in the Flash program memory and loaded into holding registers during Reset. The features available for control through the Flash Option Bits are: Watch-dog timer time-out response selection–interrupt or system reset Watch-dog timer Always on (enabled at Reset) The ability to prevent unwanted read access to user code in Program Memory The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory Voltage brown-out configuration-always enabled or disabled during STOP mode to re- duce STOP mode power consumption Oscillator mode selection-for high, medium, and low power crystal oscillators, or external RC oscillator Factory trimming information for the internal precision oscillator and low voltage detec- tion Factory calibration values for ADC, temperature sensor, and Watch-dog timer compensa- tion Factory serialization and randomized lot identifier (optional) Operation Option Bit Configuration By Reset Each time the Flash Option Bits are programmed or erased, the device must be Reset for the change to take effect. During any reset operation (System Reset, Power On Reset, or STOP Mode Recovery), the Flash Option Bits are automatically read from the Flash Pro- gram Memory and written to Option Configuration registers. The Option Configuration registers control operation of the devices within the Z8 Encore! XP® 4K Series. Option Bit control is established before the device exits Reset and the eZ8 CPU begins code execu- tion. The Option Configuration registers are not part of the Register File and are not acces- sible for read or write access.

Z8 Encore! XP® 4K Series Product Specification 149 Option Bit Types User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits has been provided because these locations contain application-specific device configurations. The information contained here is lost when page 0 of the program mem- ory is erased. Trim Option Bits The trim option bits are contained in the information page of the Flash memory. These bits are factory programmed values required to optimize the operation of onboard analog cir- cuitry and cannot be permanently altered by the user. Program memory may be erased without endangering these values. It is possible to alter working values of these bits by accessing the Trim Bit Address and Data Registers, but these working values are lost after a power loss or any other reset event. There are 32 bytes of trim data. To modify one of these values the user code must first write a value between 00H and 1FH into the Trim Bit Address Register. The next write to the Trim Bit Data register changes the working value of the target trim data byte. Reading the trim data requires the user code to write a value between 00H and 1FH into the Trim Bit Address Register. The next read from the Trim Bit Data register returns the work- ing value of the target trim data byte. The trim address range is from information address 20-3F only. The remainder of the information page is not accessible through the trim bit address and data registers. Calibration Option Bits The calibration option bits are also contained in the information page. These bits are fac- tory programmed values intended for use in software correcting the device’s analog per- formance. To read these values, the user code must employ the LDC instruction to access the information area of the address space as defined in See Flash Information Area on page 15. Serialization Bits As an optional feature, ZiLOG is able to provide factory-programmed serialization. For serialized products, the individual devices will be programmed with unique serial num- bers. These serial numbers are binary values, four bytes in length. The numbers increase in size with each device, but gaps in the serial sequence may exist. These serial numbers are stored in the flash information page (see Reading the Flash Infor- mation Page on page 150 and Serialization Data on page 159 for more details) and are unaffected by mass erasure of the device's flash memory. Note:

production lot and is not likely to be repeated. The following code example shows how to read data from the flash information area. Table 87. Trim Bit Address Register (TRMADR)

for the user-programmable Flash option bits. enabled for the eZ8 CPU to acknowledge the interrupt request. Dog Timer can not be disabled. ting is the default for unprogrammed (erased) Flash. Table 88. Trim Bit Data Register (TRMDR) Table 89. Flash Option Bits at Program Memory Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write.

00 = On-chip oscillator configured for use with external RC networks (<4MHz). 01 = Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). setting is the default for unprogrammed (erased) Flash. setting is the default for unprogrammed (erased) Flash. setting is the default for unprogrammed (erased) Flash. Table 90. Flash Options Bits at Program Memory Address 0001H Note: U = Unchanged by Reset. R/W = Read/Write.

Reserved— Altering this register may result in incorrect device operation. Reserved— Altering this register may result in incorrect device operation. Table 91. Trim Options Bits at Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write. Table 92. Trim Option Bits at 0001H Note: U = Unchanged by Reset. R/W = Read/Write.

Z8 Encore! XP® 4K Series Product Specification 154 Trim Bit Address 0002H IPO_TRIM—Internal Precision Oscillator Trim Byte Contains trimming bits for Internal Precision Oscillator. Trim Bit Address 0003H The LVD is available on 8-pin devices only. Reserved—Must be 1. LVD_TRIM—Low Voltage Detect Trim This trimming affects the low voltage detection threshold. Each LSB represents a 50mV change in the threshold level. Alternatively, the low voltage threshold may be computed from the options bit value by the following equation: LVD_LVL = 3.2V - LVD_TRIM * 0.05V Table 93. Trim Option Bits at 0002H (TIPO) Note: U = Unchanged by Reset. R/W = Read/Write. Table 94. Trim Option Bits at Address 0003H (TLVD) Note: U = Unchanged by Reset. R/W = Read/Write. 3.20 TBD Maximum LVD threshold 00001 TBD 3.15 TBD Note:

Z8 Encore! XP® 4K Series Product Specification 155 Trim Bit Address 0004H Reserved— Altering this register may result in incorrect device operation. ZiLOG Calibration Data ADC Calibration Data 00010 TBD 3.10 TBD 00011 TBD 3.05 TBD 00100 to 01010 TBD 3.00 to 2.79 TBD Default on Reset and to be programmed into Flash before customer delivery to ensure 2.7V operation. 01010 to 11111 TBD 2.70 to 1.65 TBD Minimum LVD threshold Table 95. Trim Option Bits at 0004H Note: U = Unchanged by Reset. R/W = Read/Write. Table 96. ADC Calibration Bits Note: U = Unchanged by Reset. R/W = Read/Write.

supported modes has one byte of offset calibration and two bytes of gain calibration. tion of each calibration byte is provided in Table 97. Table 97. ADC Calibration Data Location

Table 97. ADC Calibration Data Location (Continued)

WDTCALH and WDTL with WDTCALL. WDTCALH and WDTL with WDTCALL. Table 98. Watchdog Calibration High Byte at 007EH (WDTCALH) Note: U = Unchanged by Reset. R/W = Read/Write. Table 99. Watchdog Calibration Low Byte at 007FH (WDTCALL) Note: U = Unchanged by Reset. R/W = Read/Write.

The serial number is a unique four-byte binary value. The randomized lot ID is a 32-byte binary value that changes for each production lot. Table 100. Serial Number at 001C - 001F (S_NUM) Note: U = Unchanged by Reset. R/W = Read/Write. Table 101. Serialization Data Locations Table 102. Lot Identification Number (RAND_LOT) Note: U = Unchanged by Reset. R/W = Read/Write.

Table 103. Randomized Lot ID Locations

Table 103. Randomized Lot ID Locations (Continued)

tion value. For usage details, see Temperature Sensor Operation on page 134. tion value. For usage details, see Temperature Sensor Operation on page 134. Table 104. Temperature Sensor Calibration High Byte at 003A (TSCALH) Note: U = Unchanged by Reset. R/W = Read/Write. Table 105. Temperature Sensor Calibration Low Byte at 003B (TSCALL) Note: U = Unchanged by Reset. R/W = Read/Write.

Z8 Encore! XP® 4K Series Product Specification 163 Non-Volatile Data Storage Overview The Z8 Encore! XP® 4K Series devices contain a non-volatile data storage (NVDS) ele- ment of up to 128 bytes. This memory can perform over 100,000 write cycles. Operation The NVDS is implemented by special purpose ZiLOG software stored in areas of program memory not accessible to the user. These special-purpose routines use the Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maximize the write/erase endurance of the Flash. Different members of the Z8 Encore! XP® 4K Series feature multiple NVDS array sizes. See Z8 Encore! XP® 4K Series Family Part Selection Guide on page 2 for details. NVDS Code Interface Two routines are required to access the NVDS: a write routine and a read routine. Both of these routines are accessed with a CALL instruction to a pre-defined address outside of the user-accessible program memory. Both the NVDS address and data are single-byte values. Because these routines disturb the working register set, user code must ensure that any required working register values are preserved by pushing them onto the stack or by changing the working register pointer just prior to NVDS execution. During both read and write accesses to the NVDS, interrupt service is NOT disabled. Any interrupts that occur during the NVDS execution must take care not to disturb the working register and existing stack contents or else the array may become corrupted. Disabling interrupts before executing NVDS operations is recommended. Use of the NVDS requires 15 bytes of available stack space. Also, the contents of the working register set are overwritten. For correct NVDS operation, the Flash Frequency Registers must be programmed based on the system clock frequency (See Flash Operation Timing Using the Flash Frequency Registers on page 140). Note:

code should pop the address and data bytes off the stack. data pushed by the user. Sufficient memory must be available for this stack usage. effect. Illegal write operations have a 2μs execution time. Table 106. Write Status Byte

Z8 Encore! XP® 4K Series Product Specification 165 Byte Read To read a byte from the NVDS array, user code must first push the address onto the stack. User code issues a CALL instruction to the address of the byte-read routine (0x1000). At the return from the sub-routine, the read byte resides in working register R0, and the read status byte resides in working register R1. The contents of the status byte are undefined for read operations to illegal addresses. Also, the user code should pop the address byte off the stack. The read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user. Sufficient memory must be available for this stack usage. Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution time. A read operation takes between 44 μs and 489 μs (assuming a 20 MHz system clock). Slower system clock speeds result in proportionally higher execution times. NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return 0xff. Illegal read operations have a 2 μs execution time. The status byte returned by the NVDS read routine is zero for successful read, as deter- mined by a CRC check. If the status byte is non-zero, there was a corrupted value in the NVDS array at the location being read. In this case, the value returned in R0 is the byte most recently written to the array that does not have a CRC error. Power Failure Protection The NVDS routines employ error checking mechanisms to ensure a power failure endan- gers only the most recently written byte. Bytes previously written to the array are not per- turbed. A system reset (such as a pin reset or watchdog timer reset) that occurs during a write operation also perturbs the byte currently being written. All other bytes in the array are unperturbed. Optimizing NVDS Memory Usage for Execution Speed As Table 107 shows, the NVDS read time varies drastically, this discrepancy being a trade-off for minimizing the frequency of writes that require post-write page erases. The NVDS read time of address N is a function of the number of writes to addresses other than N since the most recent write to address N, as well as the number of writes since the most recent page erase. Neglecting effects caused by page erases and results caused by the ini- tial condition in which the NVDS is blank, a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 μs, up to a maximum of (511-NVDS_SIZE) μs.

time, however, actual speed benefits are not always realized. well as minimize the requirement for it. Table 107. NVDS Read Time

Z8 Encore! XP® 4K Series Product Specification 167 On-Chip Debugger Overview The Z8 Encore! XP® devices contain an integrated On-Chip Debugger (OCD) that pro- vides advanced debugging features including: Reading and writing of the register file Reading and writing of program and data memory Setting of breakpoints and watchpoints Executing eZ8 CPU instructions Debug pin sharing with general-purpose input-output function to maximize pins available to the user (8-pin product only) Architecture The on-chip debugger consists of four primary functional blocks: transmitter, receiver, auto-baud detector/generator, and debug controller. Figure 23 illustrates the architecture of the on-chip debugger Figure 23.On-Chip Debugger Block Diagram Auto-Baud System Clock Transmitter Receiver DBG Pin Debug Controller eZ8 CPU Control Detector/Generator

Z8 Encore! XP® 4K Series Product Specification 168 Operation OCD Interface The on-chip debugger uses the DBG pin for communication with an external host. This one-pin interface is a bi-directional, open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS-232. This pin creates an interface from the Z8 Encore! XP® 4K Series prod- ucts to the serial port of a host PC using minimal external hardware.Two different methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 24 and 25 . The recommended method is the buffered implementation depicted in Figure 25. The DBG pin must always be connected to VDD through an external pull-up resistor. For operation of the on-chip debugger, all power pins (VDD and AVDD) must be supplied with power, and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-drain and must always be connected to VDD through an external pull-up resistor to insure proper operation. Figure 24.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1) Caution: RS-232 TX RS-232 RX RS-232 Transceiver VDD DBG Pin 10KOhm Schottky Diode

Z8 Encore! XP® 4K Series Product Specification 169 Figure 25.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) DEBUG Mode The operating characteristics of the devices in DEBUG mode are: The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute specific instructions The system clock operates unless in STOP mode All enabled on-chip peripherals operate unless in STOP mode Automatically exits HALT mode Constantly refreshes the Watch-Dog Timer, if enabled Entering DEBUG Mode The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint) instruc- tion. If the DBG pin is held Low during the most recent clock cycle of system reset, the part enters DEBUG mode upon exiting system reset. (20-/28-pin products only.) If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/DBG pin, the DBG feature is unlocked. After releasing PA2/RESET, it will be pulled high. At this point, the PA0/DBG pin may be used to autobaud and cause the device to enter DE- BUG mude. See OCD Unlock Sequence (8-Pin Devices Only) on page 171. Exiting DEBUG Mode The device exits DEBUG mode following any of these operations: Clearing the DBGMODE bit in the OCD Control Register to 0. RS-232 TX RS-232 RX RS-232 Transceiver VDD DBG Pin 10KOhm Open-Drain Buffer

Asserting the RESET pin Low to initiate a Reset. Driving the DBG pin Low while the device is in STOP mode initiates a System Reset. and sets the OCD Baud Rate Generator accordingly. baud rates for sample crystal frequencies. Table 108. OCD Baud-Rate Limits

if the host releases the Serial Break early. the OCD is transmitting a character. DBG pin functions only as a GPIO pin.

Z8 Encore! XP® 4K Series Product Specification 172 Wait 5ms for the internal reset sequence to complete. Send the following bytes serially to the debug pin: DBG ← 80H (autobaud) DBG ← EBH DBG ← 5AH DBG ← 70H DBG ← CDH (32-bit unlock key) Release PA2/RESET. The PA0/DBG pin is now identical in function to that of the DBG pin on the 20-/28-pin device. To enter DEBUG mode, re-autobaud and write 80H to the OCD control register. (See On-Chip Debugger Commands on page 172.) Breakpoints Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are enabled, the OCD enters DEBUG mode and idles the eZ8 CPU. If Breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP instruction. Breakpoints in Flash Memory The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a byte in Flash memory. To implement a Breakpoint, write 00H to the required break address, overwriting the current instruction. To remove a Breakpoint, the corresponding page of Flash memory must be erased and reprogrammed with the original data. Runtime Counter The On-Chip Debugger contains a 16-bit Runtime Counter. It counts system clock cycles between Breakpoints. The counter starts counting when the On-Chip Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches the maximum count of FFFFH. On-Chip Debugger Commands The host communicates to the on-chip debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are avail- able. In DEBUG mode, all OCD commands become available unless the user code and control registers are protected by programming the Flash Read Protect Option bit (FRP). The Flash Read Protect Option bit prevents the code in memory from being read out of the Z8 Encore! XP® 4K Series products. When this option is enabled, several of the OCD

Z8 Encore! XP® 4K Series Product Specification 173 commands are disabled. Table 109 on page 177 is a summary of the On-chip debugger commands. Each OCD command is described in further detail in the bulleted list follow- ing this table. Table 109 also indicates those commands that operate when the device is not in DEBUG mode (normal operation) and those commands that are disabled by program- ming the Flash Read Protect Option bit. In the following bulleted list of OCD Commands, data and commands sent from the host to the On-Chip Debugger are identified by ’DBG ← Command/Data’. Data sent from the On-Chip Debugger back to the host is identified by ’DBG → Data’ Debug Command Command Byte Enabled when NOT in DEBUG mode? Disabled by Flash Read Protect Option Bit Read OCD Revision 00H Yes Reserved 01H Read OCD Status Register 02H Yes Read Runtime Counter 03H Write OCD Control Register 04H Yes Cannot clear DBGMODE bit Read OCD Control Register 05H Yes Write Program Counter 06H Disabled Read Program Counter 07H Disabled Write Register 08H Only writes of the Flash Memory Control registers are allowed. Additionally, only the Mass Erase command is allowed to be written to the Flash Control register. Read Register 09H Disabled Write Program Memory 0AH Disabled Read Program Memory 0BH Disabled Write Data Memory 0CH Yes Read Data Memory 0DH Read Program Memory CRC 0EH Reserved 0FH Step Instruction 10H Disabled Stuff Instruction 11H Disabled Execute Instruction 12H Disabled Reserved 13H–FFH

Z8 Encore! XP® 4K Series Product Specification 174 Read OCD Revision (00H)—The Read OCD Revision command determines the ver- sion of the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision number changes. DBG ← 00H DBG → OCDRev[15:8] (Major revision number) DBG → OCDRev[7:0] (Minor revision number) Read OCD Status Register (02H)—The Read OCD Status Register command reads the OCDSTAT register. DBG ← 02H DBG → OCDSTAT[7:0] Read Runtime Counter (03H)—The Runtime Counter counts system clock cycles in between Breakpoints. The 16-bit Runtime Counter counts up from 0000H and stops at the maximum count of FFFFH. The Runtime Counter is overwritten during the Write Memo- ry, Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction, Stuff Instruction, and Execute Instruction commands. DBG ← 03H DBG → RuntimeCounter[15:8] DBG → RuntimeCounter[7:0] Write OCD Control Register (04H)—The Write OCD Control Register command writes the data that follows to the OCDCTL register. When the Flash Read Protect Option Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device. DBG ← 04H DBG ← OCDCTL[7:0] Read OCD Control Register (05H)—The Read OCD Control Register command reads the value of the OCDCTL register. DBG ← 05H DBG → OCDCTL[7:0] Write Program Counter (06H)—The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the Program Counter (PC) values are discarded. DBG ← 06H DBG ← ProgramCounter[15:8] DBG ← ProgramCounter[7:0]

Z8 Encore! XP® 4K Series Product Specification 175 Read Program Counter (07H)—The Read Program Counter command reads the value in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this command returns FFFFH. DBG ← 07H DBG → ProgramCounter[15:8] DBG → ProgramCounter[7:0] Write Register (08H)—The Write Register command writes data to the Register File. Data can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If the device is not in DEBUG mode, the address and data values are discarded. If the Flash Read Protect Option bit is enabled, only writes to the Flash Control Registers are allowed and all other register write data values are discarded. DBG ← 08H DBG ← {4’h0,Register Address[11:8]} DBG ← Register Address[7:0] DBG ← Size[7:0] DBG ← 1-256 data bytes Read Register (09H)—The Read Register command reads data from the Register File. Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this com- mand returns FFH for all the data values. DBG ← 09H DBG ← {4’h0,Register Address[11:8] DBG ← Register Address[7:0] DBG ← Size[7:0] DBG → 1-256 data bytes Write Program Memory (0AH)—The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). The on-chip Flash Controller must be written to and unlocked for the programming oper- ation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the data is dis- carded. DBG ← 0AH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes Read Program Memory (0BH)—The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions.

Z8 Encore! XP® 4K Series Product Specification 176 Data can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this command returns FFH for the data. DBG ← 0BH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes Write Data Memory (0CH)—The Write Data Memory command writes data to Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be writ- ten 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the data is dis- carded. DBG ← 0CH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes Read Data Memory (0DH)—The Read Data Memory command reads from Data Mem- ory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG mode, this command returns FFH for the data. DBG ← 0DH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes Read Program Memory CRC (0EH)—The Read Program Memory CRC command computes and returns the Cyclic Redundancy Check (CRC) of Program Memory using the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command re- turns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory. DBG ← 0EH DBG → CRC[15:8] DBG → CRC[7:0]

Flash Read Protect Option bit is enabled, the OCD ignores this command. reads and discards one byte. Z8 Encore! XP® 4K Series device. a run function can be implemented by writing 40H to this register. Table 109. OCD Control Register (OCDCTL)

device. It cannot be written to 0. 0 = The Z8 Encore! XP® 4K Series device is operating in NORMAL mode. 1 = The Z8 Encore! XP® 4K Series device is in DEBUG mode. 0 = Breakpoints are disabled. 1 = Breakpoints are enabled. Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. bit is automatically cleared to 0 at the end of reset. 1 = Reset the Flash Read Protect Option Bit device. Table 110. OCD Status Register (OCDSTAT)

Z8 Encore! XP® 4K Series Product Specification 179 HALT—HALT Mode 0 = Not in HALT mode 1 = In HALT mode FRPENB—Flash Read Protect Option Bit Enable 0 = FRP bit enabled, that allows disabling of many OCD commands 1 = FRP bit has no effect Reserved—Must be 0.

Z8 Encore! XP® 4K Series Product Specification 180 Oscillator Control Overview The Z8 Encore! XP® 4K Series devices uses five possible clocking schemes, each user- selectable: Internal precision trimmed RC oscillator (IPO) On-chip oscillator using off-chip crystal or resonator On-chip oscillator using external RC network External clock drive On-chip low precision Watch-Dog Timer oscillator In addition, Z8 Encore! XP® 4K Series devices contain clock failure detection and recov- ery circuitry, allowing continued operation despite a failure of the system clock oscillator. Operation This chapter discusses the logic used to select the system clock and handle primary oscil- lator failures. A description of the specific operation of each oscillator is outlined else- where in this document. The detailed description of the Watch-Dog Timer Oscillator starts on page 83, the Internal Precision Oscillator description begins on page 190, and the chap- ter outlining the Crystal Oscillator begins on page 185 of this document. System Clock Selection The oscillator control block selects from the available clocks. Table 111 details each clock source and its usage.

trol block employs a register unlocking/locking scheme. write to or read from other registers within the unlocking/locking operation. Table 111. Oscillator Configuration and Selection

• 32.8 KHz or 5.53 MHz
• High accuracy when trimmed
• No external components required
• Unlock and write Oscillator Control Register (OSCCTL) to enable and select oscillator at either 5.53 MHz or

32.8 KHz

• 32 KHz to 20 MHz
• Very high accuracy (dependent on crystal or resonator used)
• Requires external components
• Configure Flash option bits for correct external oscillator mode
• Unlock and write OSCCTL to enable crystal oscillator, wait for it to stabilize and select as system clock (if the XTLDIS option bit has been de- asserted, no waiting is required) External RC Oscillator
• 32 KHz to 4 MHz
• Accuracy dependent on external components
• Configure Flash option bits for correct external oscillator mode
• Unlock and write OSCCTL to enable crystal oscillator and select as system clock External Clock Drive
• 0 to 20 MHz
• Accuracy dependent on external clock source
• Write GPIO registers to configure PB3 pin for external clock function
• Unlock and write OSCCTL to select external system clock
• Apply external clock signal to GPIO Internal Watchdog Timer Oscillator
• 10 KHz nominal
• Low accuracy; no external components required
• Low power consumption
• Enable WDT if not enabled and wait until WDT Oscillator is operating.
• Unlock and write Oscillator Control Register (OSCCTL) to enable and select oscillator Caution:

Z8 Encore! XP® 4K Series Product Specification 182 When selecting a new clock source, the system clock oscillator failure detection circuitry and the Watch-Dog Timer oscillator failure circuitry must be disabled. If SOFEN and WOFEN are not disabled prior to a clock switch-over, it is possible to generate an inter- rupt for a failure of either oscillator. The Failure detection circuitry can be enabled any- time after a successful write of OSCSEL in the OSCCTL register. The internal precision oscillator is enabled by default. If the user code changes to a differ- ent oscillator, it may be appropriate to disable the IPO for power savings. Disabling the IPO does not occur automatically. Clock Failure Detection and Recovery System Clock Oscillator Failure The Z8F04xA family devices can generate non-maskable interrupt-like events when the primary oscillator fails. To maintain system function in this situation, the clock failure recovery circuitry automatically forces the Watch-Dog Timer oscillator to drive the system clock. The Watch-Dog Timer oscillator must be enabled to allow the recovery. Although this oscillator runs at a much slower speed than the original system clock, the CPU contin- ues to operate, allowing execution of a clock failure vector and software routines that either remedy the oscillator failure or issue a failure alert. This automatic switch-over is not available if the Watch-Dog Timer is selected as the system clock oscillator. It is also unavailable if the Watch-Dog Timer oscillator is disabled, though it is not necessary to enable the Watch-Dog Timer reset function outlined in the Watch-Dog Timer chapter of this document on page 83. The primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1KHz ±50%. If an external signal is selected as the system oscillator, it is possible that a very slow but non-failing clock can generate a failure condition. Under these conditions, do not enable the clock failure circuitry (SOFEN must be deasserted in the OSCCTL register). Watch-Dog Timer Failure In the event of a Watch-Dog Timer oscillator failure, a similar non-maskable interrupt-like event is issued. This event does not trigger an attendant clock switch-over, but alerts the CPU of the failure. After a Watch-Dog Timer failure, it is no longer possible to detect a primary oscillator failure. The failure detection circuitry does not function if the Watch- Dog Timer is used as the system clock oscillator or if the Watch-Dog Timer oscillator has been disabled. For either of these cases, it is necessary to disable the detection circuitry by deasserting the WDFEN bit of the OSCCTL register. The Watch-Dog Timer oscillator failure detection circuit counts system clocks while look- ing for a Watch-Dog Timer clock. The logic counts 8004 system clock cycles before deter- mining that a failure has occurred. The system clock rate determines the speed at which

can only be recovered by Power-On-Reset. which becomes the system clock. is locked at successful completion of a register write to the OSCCTL. Table 112. Oscillator Control Register (OSCCTL)

Z8 Encore! XP® 4K Series Product Specification 184 WDFEN—Watchdog Timer Oscillator Failure Detection Enable 1 = Failure detection of Watch-Dog Timer oscillator is enabled 0 = Failure detection of Watch-Dog Timer oscillator is disabled SCKSEL—System Clock Oscillator Select 000 = Internal precision oscillator functions as system clock at 5.53 MHz 001 = Internal precision oscillator functions as system clock at 32 KHz 010 = Crystal oscillator or external RC oscillator functions as system clock 011 = Watch-Dog Timer oscillator functions as system 100 = External clock signal on PB3 functions as system clock 101 = Reserved 110 = Reserved 111 = Reserved

Z8 Encore! XP® 4K Series Product Specification 185 Crystal Oscillator Overview The products in the Z8 Encore! XP® 4K Series contain an on-chip crystal oscillator for use with external crystals with 32 KHz to 20 MHz frequencies. In addition, the oscillator sup- ports external RC networks with oscillation frequencies up to 4 MHz or ceramic resona- tors with frequencies up to 8MHz. The on-chip crystal oscillator can be used to generate the primary system clock for the internal eZ8 CPU and the majority of the on-chip periph- erals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32 KHz–20 MHz). If an external clock generator is used, the XOUT pin must be left uncon- nected. The Z8 Encore! XP® 4K Series products do not contain an internal clock divider. The frequency of the signal on the XIN input pin determines the frequency of the system clock. Although the XIN pin can be used as an input for an external clock generator, the CLKIN pin is better suited for such use (See System Clock Selection on page 180.) Operating Modes The Z8 Encore! XP® 4K Series products support four oscillator modes: Minimum power for use with very low frequency crystals (32 KHz–1 MHz) Medium power for use with medium frequency crystals or ceramic resonators (0.5 MHz to 8 MHz) Maximum power for use with high frequency crystals (8 MHz to 20 MHz) On-chip oscillator configured for use with external RC networks (<4 MHz) The oscillator mode is selected using user-programmable Flash Option Bits. Please refer to the chapter Flash Option Bits on page 148 for information. Crystal Oscillator Operation The Flash Option bit XTLDIS controls whether the crystal oscillator is enabled during reset. The crystal may later be disabled after reset if a new oscillator has been selected as the system clock. If the crystal is manually enabled after reset through the OSCCTL regis- ter, the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabi- lize. After this, the crystal oscillator may be selected as the system clock. Note:

Z8 Encore! XP® 4K Series Product Specification 187 Note: * Printed circuit board layout should not add more than 4 pF of stray capacitance to either XIN or XOUT pins. if no Oscillation occurs, reduce the values of the capacitors C1 and C2 to decrease the loading. Oscillator Operation with an External RC Network Figure 28 illustrates a recommended configuration for connection with an external resis- tor-capacitor (RC) network. Load Capacitance (CL) pF Maximum Shunt Capacitance (C0) pF Maximum Drive Level mW Maximum Table 114. Transconductance Values for Low, Medium, and High Gain Operating Modes

32 KHz - 1 MHz

Applications

0.02 0.04 0.09 Medium Gain (see Note)

0.5 MHz - 10 MHz

0.84 1.7 3.1 High Gain (see Note)

8 MHz - 20 MHz

1.1 2.3 4.2 Table 113. Recommended Crystal Oscillator Specifications

Z8 Encore! XP® 4K Series Product Specification 189 Figure 29.Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45KOhm Resistor When using the external RC oscillator mode, the oscillator can stop oscil- lating if the power supply drops below 2.7V, but before the power supply drops to the voltage brown-out threshold. The oscillator resumes oscilla- tion when the supply voltage exceeds 2.7V. 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 C (pF) Frequency (kHz) Caution:

Internal Precision Oscillator Z8 Encore! XP® 4K Series Product Specification 190 Internal Precision Oscillator Overview The internal precision oscillator (IPO) is designed for use without external components. The user can either manually trim the oscillator for a non-standard frequency or use the automatic factory-trimmed version to achieve a 5.53 MHz frequency. IPO features include: On-chip RC oscillator that does not require external components Output frequency of either 5.53 MHz or 32.8 KHz (contains both a fast and a slow mode) Trimmed through Flash option bits with user override Elimination of crystals or ceramic resonators in applications where very high timing accu- racy is not required. Operation An 8-bit trimming register, incorporated into the design, compensates for absolute varia- tion of oscillator frequency. Once trimmed the oscillator frequency is stable and does not require subsequent calibration. Trimming is performed during manufacturing and is not necessary for the user to repeat unless a frequency other than 5.53 MHz (fast mode) or 32.8 KHz (slow mode) is required. This trimming is done at +30ºC and a supply voltage of 3.3 V, so accuracy of this operating point will be optimal. If not used, the IPO can be disabled by the Oscillator Control Register (page 183). By default, the oscillator frequency is set by the factory trim value stored in the write-pro- tected flash information page. However, the user code can override these trim values as described in Trim Bit Address Space on page 153. Select one of two frequencies for the oscillator: 5.53 MHz and 32.8 KHz, using the OSC- SEL bits in the Oscillator Control on page 180.

Z8 Encore! XP® 4K Series Product Specification 191 eZ8 CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called state- ments. Each statement can contain labels, operations, operands and comments. Labels can be assigned to a particular instruction step in a source program. The label iden- tifies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example. Assembly Language Source Program Example JP START ; Everything after the semicolon is a comment. START: ; A label called “START”. The first instruction (JP START) in this ; example causes program execution to jump to the point within the ; program where the START label occurs. LD R4, R7 ; A Load (LD) instruction with two operands. The first operand, ; Working Register R4, is the destination. The second operand, ; Working Register R7, is the source. The contents of R7 is ; written into R4. LD 234H, #%01 ; Another Load (LD) instruction with two operands. ; The first operand, Extended Mode Register Address 234H, ; identifies the destination. The second operand, Immediate Data ; value 01H, is the source. The value 01H is written into the ; Register at address 234H.

by users that prefer manual program coding or intend to implement their own assembler. available. The register file size varies, depending on the device type. Table 115. Assembly Language Syntax Example 1 Table 116. Assembly Language Syntax Example 2

Z8 Encore! XP® 4K Series Product Specification 193 Table 118 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections. Table 117. Notational Shorthand b Bit b b represents a value from 0 to 7 (000B to 111B). cc Condition Code See Condition Codes overview in the eZ8 CPU User Manual. DA Direct Address Addrs Addrs. represents a number in the range of 0000H to FFFFH ER Extended Addressing Register Reg Reg. represents a number in the range of 000H to FFFH IM Immediate Data #Data Data is a number between 00H to FFH Ir Indirect Working Register @Rn n = 0 –15 IR Indirect Register @Reg Reg. represents a number in the range of 00H to FFH Irr Indirect Working Register Pair @RRp p = 0, 2, 4, 6, 8, 10, 12, or 14 IRR Indirect Register Pair @Reg Reg. represents an even number in the range 00H to FEH p Polarity p Polarity is a single bit binary value of either 0B or 1B. r Working Register Rn n = 0 – 15 R Register Reg Reg. represents a number in the range of 00H to FFH RA Relative Address X X represents an index in the range of +127 to – 128 which is an offset relative to the address of the next instruction rr Working Register Pair RRp p = 0, 2, 4, 6, 8, 10, 12, or 14 RR Register Pair Reg Reg. represents an even number in the range of 00H to FEH Vector Vector Address Vector Vector represents a number in the range of 00H to FFH X Indexed #Index The register or register pair to be indexed is offset by the signed Index value (#Index) in a +127 to -128 range.

Table 118. Additional Symbols

Table 119. Arithmetic Instructions

Table 120. Bit Manipulation Instructions Table 121. Block Transfer Instructions Table 122. CPU Control Instructions

Table 123. Load Instructions Table 124. Logical Instructions

Table 125. Program Control Instructions Table 126. Rotate and Shift Instructions

required for the instruction execution. Table 127. eZ8 CPU Instruction Summary

• = Value is a function of the result of the operation.

Table 127. eZ8 CPU Instruction Summary (Continued)

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

• = Value is a function of the result of the operation.

Z8 Encore! XP® 4K Series Product Specification 208 Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 30. Figures 31 and Figure 32 provide information about each of the eZ8 CPU instructions. Table 128 lists Opcode Map abbreviations. Figure 30.Opcode Map Cell Description CP 3.3 R2,R1 A Opcode Lower Nibble Second Operand After Assembly First Operand After Assembly Opcode Upper Nibble Instruction Cycles Fetch Cycles

Z8 Encore! XP® 4K Series Product Specification 209 Table 128. Opcode Map Abbreviations b Bit position IRR Indirect Register Pair cc Condition code p Polarity (0 or 1) X 8-bit signed index or displacement r 4-bit Working Register DA Destination address R 8-bit register ER Extended Addressing register r1, R1, Ir1, Irr1, IR1, rr1, RR1, IRR1, ER1 Destination address IM Immediate data value r2, R2, Ir2, Irr2, IR2, rr2, RR2, IRR2, ER2 Source address Ir Indirect Working Register RA Relative IR Indirect register rr Working Register Pair Irr Indirect Working Register Pair RR Register Pair

Z8 Encore! XP® 4K Series Product Specification 210 Figure 31.First Opcode Map CP 3.3 R2,R1 CP 3.4 IR2,R1 CP 2.3 r1,r2 CP 2.4 r1,Ir2 CPX 4.3 ER2,ER1 CPX 4.3 IM,ER1 CP 3.3 R1,IM CP 3.4 IR1,IM RRC 2.2 RRC 2.3 IR1 A B C D E F A B C D E F Lower Nibble (Hex) Upper Nibble (Hex) BRK 1.1 SRP 2.2 IM ADD 2.3 r1,r2 ADD 2.4 r1,Ir2 ADD 3.3 R2,R1 ADD 3.4 IR2,R1 ADD 3.3 R1,IM ADD 3.4 IR1,IM ADDX 4.3 ER2,ER1 ADDX 4.3 IM,ER1 DJNZ 2.3 r1,X JR 2.2 cc,X LD 2.2 r1,IM JP 3.2 cc,DA INC 1.2 NOP 1.2 RLC 2.2 RLC 2.3 IR1 ADC 2.3 r1,r2 ADC 2.4 r1,Ir2 ADC 3.3 R2,R1 ADC 3.4 IR2,R1 ADC 3.3 R1,IM ADC 3.4 IR1,IM ADCX 4.3 ER2,ER1 ADCX 4.3 IM,ER1 INC 2.2 INC 2.3 IR1 SUB 2.3 r1,r2 SUB 2.4 r1,Ir2 SUB 3.3 R2,R1 SUB 3.4 IR2,R1 SUB 3.3 R1,IM SUB 3.4 IR1,IM SUBX 4.3 ER2,ER1 SUBX 4.3 IM,ER1 DEC 2.2 DEC 2.3 IR1 SBC 2.3 r1,r2 SBC 2.4 r1,Ir2 SBC 3.3 R2,R1 SBC 3.4 IR2,R1 SBC 3.3 R1,IM SBC 3.4 IR1,IM SBCX 4.3 ER2,ER1 SBCX 4.3 IM,ER1 DA 2.2 DA 2.3 IR1 OR 2.3 r1,r2 OR 2.4 r1,Ir2 OR 3.3 R2,R1 OR 3.4 IR2,R1 OR 3.3 R1,IM OR 3.4 IR1,IM ORX 4.3 ER2,ER1 ORX 4.3 IM,ER1 POP 2.2 POP 2.3 IR1 AND 2.3 r1,r2 AND 2.4 r1,Ir2 AND 3.3 R2,R1 AND 3.4 IR2,R1 AND 3.3 R1,IM AND 3.4 IR1,IM ANDX 4.3 ER2,ER1 ANDX 4.3 IM,ER1 COM 2.2 COM 2.3 IR1 TCM 2.3 r1,r2 TCM 2.4 r1,Ir2 TCM 3.3 R2,R1 TCM 3.4 IR2,R1 TCM 3.3 R1,IM TCM 3.4 IR1,IM TCMX 4.3 ER2,ER1 TCMX 4.3 IM,ER1 PUSH 2.2 PUSH 2.3 IR2 TM 2.3 r1,r2 TM 2.4 r1,Ir2 TM 3.3 R2,R1 TM 3.4 IR2,R1 TM 3.3 R1,IM TM 3.4 IR1,IM TMX 4.3 ER2,ER1 TMX 4.3 IM,ER1 DECW 2.5 RR1 DECW 2.6 IRR1 LDE 2.5 r1,Irr2 LDEI 2.9 Ir1,Irr2 LDX 3.2 r1,ER2 LDX 3.3 Ir1,ER2 LDX 3.4 IRR2,R1 LDX 3.5 IRR2,IR1 LDX 3.4 r1,rr2,X LDX 3.4 rr1,r2,X RL 2.2 RL 2.3 IR1 LDE 2.5 r2,Irr1 LDEI 2.9 Ir2,Irr1 LDX 3.2 r2,ER1 LDX 3.3 Ir2,ER1 LDX 3.4 R2,IRR1 LDX 3.5 IR2,IRR1 LEA 3.3 r1,r2,X LEA 3.5 rr1,rr2,X INCW 2.5 RR1 INCW 2.6 IRR1 CLR 2.2 CLR 2.3 IR1 XOR 2.3 r1,r2 XOR 2.4 r1,Ir2 XOR 3.3 R2,R1 XOR 3.4 IR2,R1 XOR 3.3 R1,IM XOR 3.4 IR1,IM XORX 4.3 ER2,ER1 XORX 4.3 IM,ER1 LDC 2.5 r1,Irr2 LDCI 2.9 Ir1,Irr2 LDC 2.5 r2,Irr1 LDCI 2.9 Ir2,Irr1 JP 2.3 IRR1 LDC 2.9 Ir1,Irr2 LD 3.4 r1,r2,X PUSHX 3.2 ER2 SRA 2.2 SRA 2.3 IR1 POPX 3.2 ER1 LD 3.4 r2,r1,X CALL 2.6 IRR1 BSWAP 2.2 CALL 3.3 DA LD 3.2 R2,R1 LD 3.3 IR2,R1 BIT 2.2 p,b,r1 LD 2.3 r1,Ir2 LDX 4.2 ER2,ER1 LDX 4.2 IM,ER1 LD 3.2 R1,IM LD 3.3 IR1,IM RR 2.2 RR 2.3 IR1 MULT 2.8 RR1 LD 3.3 R2,IR1 TRAP 2.6 Vector LD 2.3 Ir1,r2 BTJ 3.3 p,b,r1,X BTJ 3.4 p,b,Ir1,X SWAP 2.2 SWAP 2.3 IR1 RCF 1.2 WDT 1.2 STOP 1.2 HALT 1.2 DI 1.2 EI 1.2 RET 1.4 IRET 1.5 SCF 1.2 CCF 1.2 Opcode See 2nd Map 1, 2 ATM

Z8 Encore! XP® 4K Series Product Specification 211 Figure 32.Second Opcode Map after 1FH CPC 4.3 R2,R1 CPC 4.4 IR2,R1 CPC 3.3 r1,r2 CPC 3.4 r1,Ir2 CPCX 5.3 ER2,ER1 CPCX 5.3 IM,ER1 CPC 4.3 R1,IM CPC 4.4 IR1,IM SRL 3.2 SRL 3.3 IR1 A B C D E F A B C D E F Lower Nibble (Hex) Upper Nibble (Hex) 3, 2 PUSH IM LDWX 5, 4 ER2,ER1

Electrical Characteristics

Z8 Encore! XP® 4K Series Product Specification 212 The data in this chapter is pre-qualification and pre-characterization and is subject to change. Additional electrical characteristics may be found in the individual chapters. Absolute Maximum Ratings Stresses greater than those listed in Table 129 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS). Table 129. Absolute Maximum Ratings

1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Port B[5:0], Port

Z8 Encore! XP® 4K Series Product Specification 213 DC Characteristics Table 130 lists the DC characteristics of the Z8 Encore! XP® 4K Series products. All volt- ages are referenced to VSS, the primary system ground. Table 130. DC Characteristics signal pins on the 8-pin devices.

Z8 Encore! XP® 4K Series Product Specification 214 CXOUT XOUT Pad Capacitance 9.52 pF TBD IPU Weak Pull-up Current 100 350 µA VDD = 3.0 - 3.6V VRAM RAM Data Retention Voltage TBD V Voltage at which RAM will retain static values; no reading or writing is allowed. 1 This condition excludes all pins that have on-chip pull-ups, when driven Low. 2 These values are provided for design guidance only and are not tested in production. Table 130. DC Characteristics (Continued)

Z8 Encore! XP® 4K Series Product Specification 215 Table 131. Power Consumption

5.5 MHz

20 MHz

10 MHz

4 MHz

Z8 Encore! XP® 4K Series Product Specification 217 AC Characteristics The section provides information about the AC characteristics and timing. All AC timing information assumes a standard load of 50pF on all outputs. Table 132. AC Characteristics

Z8 Encore! XP® 4K Series Product Specification 218 Table 133. Internal Precision Oscillator Electrical Characteristics

Z8 Encore! XP® 4K Series Product Specification 219 On-Chip Peripheral AC and DC Electrical Characteristics Table 134. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing

66 Internal Precision

5000 Internal Precision

design guidance only and are not tested in production.

Z8 Encore! XP® 4K Series Product Specification 220 Table 135. Flash Memory Electrical Characteristics and Timing Table 136. Watch-Dog Timer Electrical Characteristics and Timing

Z8 Encore! XP® 4K Series Product Specification 221 Table 137. Non Volatile Data Storage Table 138. Analog-to-Digital Converter Electrical Characteristics and Timing

1 Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling

3 LSBs are defined assuming 10-bit resolution. 4 The input impedance is inversely proportional to the system clock frequency.

Z8 Encore! XP® 4K Series Product Specification 222 Single-Shot Conversion Time 5129 System clock cycles All measurements but temperature sensor 10258 Temperature sensor measurement Continuous Conversion Time 256 System clock cycles All measurements but temperature sensor 512 Temperature sensor measurement Signal Input Bandwidth kHz As defined by -3dB point RS Analog Source Impedance kΩ In unbuffered mode 500 kΩ In buffered modes Zin Input Impedance TBD 150 kΩ In unbuffered mode at 20MHz4 TBD MΩ In buffered modes Vin Input Voltage Range VDD V Unbuffered Mode 0.3 VDD-1.1 V Buffered Modes Note: these values define the range over which the ADC performs within spec; exceeding these values does not cause damage or instability; see DC Characteristics on page 213 for absolute pin voltage limits 3 LSBs are defined assuming 10-bit resolution. 4 The input impedance is inversely proportional to the system clock frequency.

Z8 Encore! XP® 4K Series Product Specification 223 Table 140. Comparator Electrical Characteristics Table 139. Low Power Operational Amplifer Electrical Characteristics

Z8 Encore! XP® 4K Series Product Specification 224 Table 141. Temperature Sensor Electrical Characteristics the eZ8 CPU on the second rising clock edge following the change of the Port value.

Z8 Encore! XP® 4K Series Product Specification 225 Figure 34. Port Input Sample Timing Table 142. GPIO Port Input Timing

0 Latched

Z8 Encore! XP® 4K Series Product Specification 238 Figure 47 illustrates the 28-pin Small Shrink Outline Package (SSOP) available for the Z8 Encore! XP® 4K Series devices. Figure 47.28-Pin Small Shrink Outline Package (SSOP) SYMBOL A B C e MILLIMETER INCH MIN MAX MIN MAX 1.73 0.05 1.68 0.25 5.20

0.65 TYP

0.09 10.07 7.65 0.63 1.86

0.0256 TYP

0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 NOM NOM D E H L CONTROLLING DIMENSIONS: MM LEADS ARE COPLANAR WITHIN .004 INCHES. H C DETAIL A E D SEATING PLANE e A B L 0 - 8

Ordering Information

Z8 Encore! XP® 4K Series Product Specification 239 Z8 Encore! XP® with 4KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F042APB020SC 4KB 1KB 128B

1 PDIP 8-pin package

1 QFN 8-pin package

1 SOIC 8-pin package

1 SOIC 20-pin package

1 SSOP 20-pin package

1 PDIP 20-pin package

1 SOIC 28-pin package

1 SSOP 28-pin package

1 PDIP 28-pin package

Extended Temperature: -40° to 105°C Z8F042APB020EC 4KB 1KB 128B Replace C with G for Lead-Free Packaging

Z8 Encore! XP® 4K Series Product Specification 240 Z8 Encore! XP® with 4KB Flash Standard Temperature: 0° to 70°C Z8F041APB020SC 4KB 1KB 128B

0 PDIP 8-pin package

0 QFN 8-pin package

0 SOIC 8-pin package

0 SOIC 20-pin package

0 SSOP 20-pin package

0 PDIP 20-pin package

0 SOIC 28-pin package

0 SSOP 28-pin package

0 PDIP 28-pin package

Extended Temperature: -40° to 105°C Z8F041APB020EC 4KB 1KB 128B Replace C with G for Lead-Free Packaging Part Number Flash RAM NVDS I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels UART with IrDA Comparator Temperature Sensor

Z8 Encore! XP® 4K Series Product Specification 241 Z8 Encore! XP® with 2KB Flash, 10-Bit analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F022APB020SC 2KB 512B 64B Extended Temperature: -40° to 105°C Z8F022APB020EC 2KB 512B 64B Replace C with G for Lead-Free Packaging Part Number Flash RAM NVDS I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels UART with IrDA Comparator Temperature Sensor

Z8 Encore! XP® 4K Series Product Specification 242 Z8 Encore! XP® with 2KB Flash Standard Temperature: 0° to 70°C Z8F021APB020SC 2KB 512B 64B Extended Temperature: -40° to 105°C Z8F021APB020EC 2KB 512B 64B Replace C with G for Lead-Free Packaging Part Number Flash RAM NVDS I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels UART with IrDA Comparator Temperature Sensor

Z8 Encore! XP® 4K Series Product Specification 243 Z8 Encore! XP® with 1KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0° to 70°C Z8F012APB020SC 1KB 256B 16B Extended Temperature: -40° to 105°C Z8F012APB020EC 1KB 256B 16B Replace C with G for Lead-Free Packaging Part Number Flash RAM NVDS I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels UART with IrDA Comparator Temperature Sensor

Z8 Encore! XP® 4K Series Product Specification 244 Z8 Encore! XP® with 1KB Flash Standard Temperature: 0° to 70°C Z8F011APB020SC 1KB 256B 16B Extended Temperature: -40° to 105°C Z8F011APB020EC 1KB 256B 16B Replace C with G for Lead-Free Packaging Z8F04A28100KIT 20 and 28-Pin Development Kit Part Number Flash RAM NVDS I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels UART with IrDA Comparator Temperature Sensor

Z8 Encore! XP® 4K Series Product Specification 245 Z8F04A08100KIT 8-Pin Development Kit ZUSBSC0100ZAC USB Smart Cable Accessory Kit Part Number Flash RAM NVDS I/O Lines Interrupts 16-Bit Timers w/PWM 10-Bit A/D Channels UART with IrDA Comparator Temperature Sensor

Z8 Encore! XP® 4K Series Product Specification 246 Part Number Suffix Designations F 04 2A S H 020 S C Environmental Flow: C = Standard Plastic Packaging Compound G = Green Plastic Packaging Compound Temperature Range (°C): S = Standard, 0 to 70 E = Extended, -40 to +105 Speed: 020 = 20MHz Pin Count: B = 8 H = 20 J = 28 Package: H = SSOP P = PDIP Q = QFN S = SOIC Device Type Memory Size: 04 = 4KB Flash, 1KB RAM, 128B NVDS 02 = 2KB Flash, 512B RAM, 64B NVDS 01 = 1KB Flash, 256B RAM, 32B NVDS Memory Type: F = Flash Device Family

Z8 Encore! XP® 4K Series Product Specification 247 Precharacterization Product The product represented by this document is newly introduced and ZiLOG has not com- pleted the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery might be uncertain at times, because of start-up yield issues. ZiLOG, Inc. San Jose, CA 95126 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www.zilog.com Customer Support For valuable information about downloading other relevant documents or for hardware and software development tools, visit the ZiLOG web site at www.zilog.com.

Z8 Encore! XP® 4K Series Product Specification 248 Customer Feedback Form Customer Support If you experience any problems while operating this product, please check the ZiLOG Knowledge Base: http://kb.zilog.com/kb/oKBmain.asp If you cannot find an answer or have further questions, please see the ZiLOG Technical Support web page: http://support.zilog.com

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 249 Index Symbols # 194 % 194 @ 194 Numerics 10-bit ADC 4 40-lead plastic dual-inline package 237, 238 A absolute maximum ratings 212 AC characteristics 217 ADC 195 architecture 113 automatic power-down 114 block diagram 114 continuous conversion 116 control register 124, 126 control register definitions 124 data high byte register 127 data low bits register 127 electrical characteristics and timing 221 operation 114 single-shot conversion 115 ADCCTL register 124, 126 ADCDH register 127 ADCDL register 127 ADCX 195 ADD 195 add - extended addressing 195 add with carry 195 add with carry - extended addressing 195 additional symbols 194 address space 13 ADDX 195 analog signals 10 analog-to-digital converter (ADC) 113 AND 197 ANDX 197 arithmetic instructions 195 assembly language programming 191 assembly language syntax 192 B B 194 b 193 baud rate generator, UART 99 BCLR 196 binary number suffix 194 BIT 196 bit 193 clear 196 manipulation instructions 196 set 196 set or clear 196 swap 196 test and jump 198 test and jump if non-zero 198 test and jump if zero 198 bit jump and test if non-zero 198 bit swap 198 block diagram 2 block transfer instructions 196 BRK 198 BSET 196 BSWAP 196, 198 BTJ 198 BTJNZ 198 BTJZ 198 C CALL procedure 198 capture mode 80, 81 capture/compare mode 80 cc 193 CCF 196 characteristics, electrical 212 clear 197 CLR 197 COM 197

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 250 compare 80 compare - extended addressing 195 compare mode 80 compare with carry 195 compare with carry - extended addressing 195 complement 197 complement carry flag 196 condition code 193 continuous conversion (ADC) 116 continuous mode 80 control register definition, UART 100 Control Registers 13, 16 counter modes 80 CP 195 CPC 195 CPCX 195 CPU and peripheral overview 4 CPU control instructions 196 CPX 195 Customer Feedback Form 248 Customer Information 248 D DA 193, 195 data memory 15 DC characteristics 213 debugger, on-chip 167 DEC 195 decimal adjust 195 decrement 195 decrement and jump non-zero 198 decrement word 195 DECW 195 destination operand 194 device, port availability 32 DI 196 direct address 193 disable interrupts 196 DJNZ 198 dst 194 E EI 196 electrical characteristics 212 ADC 221 flash memory and timing 220 GPIO input data sample timing 224 watch-dog timer 220, 223 enable interrupt 196 ER 193 extended addressing register 193 external pin reset 24 eZ8 CPU features 4 eZ8 CPU instruction classes 194 eZ8 CPU instruction notation 192 eZ8 CPU instruction set 191 eZ8 CPU instruction summary 199 F FCTL register 144, 150, 151 features, Z8 Encore! 1 first opcode map 210 FLAGS 194 flags register 194 flash controller 4 option bit address space 151 option bit configuration - reset 148 program memory address 0000H 151 program memory address 0001H 152 flash memory 136 arrrangement 137 byte programming 142 code protection 140 configurations 136 control register definitions 144, 150 controller bypass 143 electrical characteristics and timing 220 flash control register 144, 150, 151 flash option bits 141 flash status register 145 flow chart 139 frequency high and low byte registers 147 mass erase 142

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 251 operation 138 operation timing 140 page erase 142 page select register 145, 146 FPS register 145, 146 FSTAT register 145 G gated mode 80 general-purpose I/O 32 GPIO 4, 32 alternate functions 33 architecture 33 control register definitions 40 input data sample timing 224 interrupts 40 port A-C pull-up enable sub-registers 45, port A-H address registers 41 port A-H alternate function sub-registers 42 port A-H control registers 42 port A-H data direction sub-registers 42 port A-H high drive enable sub-registers 44 port A-H input data registers 46 port A-H output control sub-registers 43 port A-H output data registers 47 port A-H stop mode recovery sub-registers port availability by device 32 port input timing 225 port output timing 226 H H 194 HALT 196 halt mode 30, 196 hexadecimal number prefix/suffix 194 I I2C 4 IM 193 immediate data 193 immediate operand prefix 194 INC 195 increment 195 increment word 195 INCW 195 indexed 193 indirect address prefix 194 indirect register 193 indirect register pair 193 indirect working register 193 indirect working register pair 193 infrared encoder/decoder (IrDA) 109 Instruction Set 191 instruction set, ez8 CPU 191 instructions ADC 195 ADCX 195 ADD 195 ADDX 195 AND 197 ANDX 197 arithmetic 195 BCLR 196 BIT 196 bit manipulation 196 block transfer 196 BRK 198 BSET 196 BSWAP 196, 198 BTJ 198 BTJNZ 198 BTJZ 198 CALL 198 CCF 196 CLR 197 COM 197 CP 195 CPC 195 CPCX 195 CPU control 196 CPX 195 DA 195 DEC 195

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 252 DECW 195 DI 196 DJNZ 198 EI 196 HALT 196 INC 195 INCW 195 IRET 198 JP 198 LD 197 LDC 197 LDCI 196, 197 LDE 197 LDEI 196 LDX 197 LEA 197 load 197 logical 197 MULT 195 NOP 196 OR 197 ORX 197 POP 197 POPX 197 program control 198 PUSH 197 PUSHX 197 RCF 196 RET 198 RL 198 RLC 198 rotate and shift 198 RR 198 RRC 198 SBC 195 SCF 196 SRA 198 SRL 199 SRP 196 STOP 197 SUB 195 SUBX 195 SWAP 199 TCM 196 TCMX 196 TM 196 TMX 196 TRAP 198 watch-dog timer refresh 197 XOR 198 XORX 198 instructions, eZ8 classes of 194 interrupt control register 61 interrupt controller 50 architecture 50 interrupt assertion types 53 interrupt vectors and priority 53 operation 52 register definitions 54 software interrupt assertion 54 interrupt edge select register 60 interrupt request 0 register 54 interrupt request 1 register 55 interrupt request 2 register 56 interrupt return 198 interrupt vector listing 50 interrupts UART 97 IR 193 Ir 193 IrDA architecture 109 block diagram 109 control register definitions 112 operation 109 receiving data 111 transmitting data 110 IRET 198 IRQ0 enable high and low bit registers 57 IRQ1 enable high and low bit registers 58 IRQ2 enable high and low bit registers 59 IRR 193 Irr 193 J JP 198 jump, conditional, relative, and relative condi-

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 253 tional 198 L LD 197 LDC 197 LDCI 196, 197 LDE 197 LDEI 196, 197 LDX 197 LEA 197 load 197 load constant 196 load constant to/from program memory 197 load constant with auto-increment addresses 197 load effective address 197 load external data 197 load external data to/from data memory and auto-increment addresses 196 load external to/from data memory and auto-in- crement addresses 197 load instructions 197 load using extended addressing 197 logical AND 197 logical AND/extended addressing 197 logical exclusive OR 198 logical exclusive OR/extended addressing 198 logical instructions 197 logical OR 197 logical OR/extended addressing 197 low power modes 29 M master interrupt enable 52 memory data 15 program 14 mode capture 80, 81 capture/compare 80 continuous 80 counter 80 gated 80 one-shot 79 PWM 80 modes 80 MULT 195 multiply 195 multiprocessor mode, UART 95 N NOP (no operation) 196 notation b 193 cc 193 DA 193 ER 193 IM 193 IR 193 Ir 193 IRR 193 Irr 193 p 193 R 193 r 193 RA 193 RR 193 rr 193 vector 193 X 193 notational shorthand 193 O OCD architecture 167 auto-baud detector/generator 170 baud rate limits 170 block diagram 167 breakpoints 172 commands 172 control register 177 data format 170 DBG pin to RS-232 Interface 168 debug mode 169

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 254 debugger break 198 interface 168 serial errors 171 status register 178 timing 227 OCD commands execute instruction (12H) 177 read data memory (0DH) 176 read OCD control register (05H) 174 read OCD revision (00H) 174 read OCD status register (02H) 174 read program counter (07H) 175 read program memory (0BH) 175 read program memory CRC (0EH) 176 read register (09H) 175 read runtime counter (03H) 174 step instruction (10H) 177 stuff instruction (11H) 177 write data memory (0CH) 176 write OCD control register (04H) 174 write program counter (06H) 174 write program memory (0AH) 175 write register (08H) 175 on-chip debugger (OCD) 167 on-chip debugger signals 10 on-chip oscillator 185 one-shot mode 79 opcode map abbreviations 209 cell description 208 first 210 second after 1FH 211 Operational Description 20, 29, 32, 50, 62, 83, 89, 109, 113, 130, 134, 136, 148, 163, 167, 180, 185, 190 OR 197 ordering information 239 ORX 197 oscillator signals 10 P p 193 packaging 20-pin PDIP 233, 234 20-pin SSOP 235, 238 28-pin PDIP 236 28-pin SOIC 237 8-pin PDIP 230 8-pin SOIC 231 PDIP 237, 238 part selection guide 2 PC 194 PDIP 237, 238 peripheral AC and DC electrical characteristics 219 pin characteristics 11 Pin Descriptions 7 polarity 193 POP 197 pop using extended addressing 197 POPX 197 port availability, device 32 port input timing (GPIO) 225 port output timing, GPIO 226 power supply signals 10 power-down, automatic (ADC) 114 power-on and voltage brown-out electrical characteristics and timing 219 power-on reset (POR) 22 program control instructions 198 program counter 194 program memory 14 PUSH 197 push using extended addressing 197 PUSHX 197 PWM mode 80 PxADDR register 41 PxCTL register 42 R R 193 r 193 RA register address 193 RCF 196 receive

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 255 IrDA data 111 receiving UART data-interrupt-driven method receiving UART data-polled method 93 register 193 ADC control (ADCCTL) 124, 126 ADC data high byte (ADCDH) 127 ADC data low bits (ADCDL) 127 flash control (FCTL) 144, 150, 151 flash high and low byte (FFREQH and FREEQL) 147 flash page select (FPS) 145, 146 flash status (FSTAT) 145 GPIO port A-H address (PxADDR) 41 GPIO port A-H alternate function sub-regis- ters 43 GPIO port A-H control address (PxCTL) 42 GPIO port A-H data direction sub-registers OCD control 177 OCD status 178 UARTx baud rate high byte (UxBRH) 106 UARTx baud rate low byte (UxBRL) 106 UARTx Control 0 (UxCTL0) 103, 106 UARTx control 1 (UxCTL1) 104 UARTx receive data (UxRXD) 101 UARTx status 0 (UxSTAT0) 101 UARTx status 1 (UxSTAT1) 103 UARTx transmit data (UxTXD) 100 watch-dog timer control (WDTCTL) 28, 86, 131, 183 watch-dog timer reload high byte (WDTH) watch-dog timer reload low byte (WDTL) watch-dog timer reload upper byte (WDTU) register file 13 register pair 193 register pointer 194 reset and stop mode characteristics 21 and stop mode recovery 20 carry flag 196 sources 22 RET 198 return 198 RL 198 RLC 198 rotate and shift instuctions 198 rotate left 198 rotate left through carry 198 rotate right 198 rotate right through carry 198 RP 194 RR 193, 198 rr 193 RRC 198 S SBC 195 SCF 196 second opcode map after 1FH 211 set carry flag 196 set register pointer 196 shift right arithmatic 198 shift right logical 199 signal descriptions 9 single-sho conversion (ADC) 115 software trap 198 source operand 194 SP 194 SRA 198 src 194 SRL 199 SRP 196 stack pointer 194 STOP 197 stop mode 29, 197 stop mode recovery sources 25, 27 using a GPIO port pin transition 26, 27 using watch-dog timer time-out 26 SUB 195 subtract 195 subtract - extended addressing 195 subtract with carry 195

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 256 subtract with carry - extended addressing 195 SUBX 195 SWAP 199 swap nibbles 199 symbols, additional 194 T TCM 196 TCMX 196 test complement under mask 196 test complement under mask - extended ad- dressing 196 test under mask 196 test under mask - extended addressing 196 timer signals 9 timers 62 architecture 62 block diagram 63 capture mode 70, 71, 80, 81 capture/compare mode 74, 80 compare mode 72, 80 continuous mode 64, 80 counter mode 65, 66 counter modes 80 gated mode 73, 80 one-shot mode 63, 79 operating mode 63 PWM mode 67, 69, 80 reading the timer count values 75 reload high and low byte registers 76 timer control register definitions 76 timer output signal operation 75 timers 0-3 control registers 78, 79 high and low byte registers 76, 77 TM 196 TMX 196 tools, hardware and software 247 transmit IrDA data 110 transmitting UART data-polled method 91 transmitting UART dat-interrupt-driven method TRAP 198 U UART 4 architecture 89 baud rate generator 99 baud rates table 107 control register definitions 100 controller signals 9 data format 90 interrupts 97 multiprocessor mode 95 receiving data using interrupt-driven meth- od 94 receiving data using the polled method 93 transmitting data usin the interrupt-driven method 92 transmitting data using the polled method x baud rate high and low registers 106 x control 0 and control 1 registers 103 x status 0 and status 1 registers 101, 103 UxBRH register 106 UxBRL register 106 UxCTL0 register 103, 106 UxCTL1 register 104 UxRXD register 101 UxSTAT0 register 101 UxSTAT1 register 103 UxTXD register 100 V vector 193 voltage brown-out reset (VBR) 23 W watch-dog timer approximate time-out delay 84 approximate time-out delays 83, 130, 134, 163, 180, 190 CNTL 23

Z8 Encore! XP® 4K Series Product Specification PS022815-0206 Index 257 control register 86, 131, 183 electrical characteristics and timing 220, 223 interrupt in noromal operation 84 interrupt in stop mode 85 operation 83, 130, 134, 163, 180, 190 refresh 84, 197 reload unlock sequence 85 reload upper, high and low registers 87 reset 24 reset in normal operation 85 reset in Stop mode 85 time-out response 84 WDTCTL register 28, 86, 131, 183 WDTH register 87 WDTL register 88 working register 193 working register pair 193 WTDU register 87 X X 193 XOR 198 XORX 198 Z Z8 Encore! block diagram 2 features 1 part selection guide 2