Microcontroller

Z8F012AQB020EG

Zilog, Inc.

High-Performance 8-Bit Microcontrollers

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PS022827-1212 P R E L I M I N A R Y Disclaimer Z8 Encore! XP® F082A Series Product Specification ii DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. Warning:

Z8 Encore! XP® F082A Series Product Specification iii

Revision History

Each instance in this document’s revision history reflects a change from its previous edi- tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Date Revision Level Chapter/Section Description Page No. Dec 2012

27 Port Alternate Function Map-

ping (Non 8-Pin Parts), Port Alternate Function Mapping (8- Pin Parts) Added missing Port D data to Table 15; cor- rected active Low status (set overlines) for PA0 (T0OUT ), PA2 (RESET) and PA5 (T1OUT) in Table 16. 40, 43 Sep 2011

26 LED Drive Enable Register Clarified statement surrounding the Alternate

Function Register as it relates to the LED function; revised Flash Sector Protect Regis- ter description; revised Packaging chapter. 157, 245 Sep 2008

25 Overview, Address Space,

Register Map, General-Pur- pose Input/Output, Available Packages, Ordering Informa- tion Added references to F042A Series back in Table 1, Table 5, Table 7 and Table 14. , 8, 16, 18, 36, 246 May 2008

24 Overview, Address Space,

Register Map, General-Pur- pose Input/Output, Available Packages, Ordering Informa- tion Changed title to Z8 Encore! XP F082A Series and removed references to F042A Series in Table 1, Table 5, Table 7 and Table 14. , 8, 16, 18, 36, 246 Dec 2007

23 Pin Description, General-Pur-

pose Input/Output, Watchdog Timer Updated Figure 3, Table 15, Tables 60 through 62. , 40, Jul 2007 sumption data. 229 Jun 2007 21 n/a Revision number update. All

PS022827-1212 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F082A Series Product Specification iv Table of Contents

PS022827-1212 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F082A Series Product Specification v

PS022827-1212 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F082A Series Product Specification vi

PS022827-1212 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F082A Series Product Specification vii

PS022827-1212 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F082A Series Product Specification viii

PS022827-1212 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F082A Series Product Specification ix

PS022827-1212 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F082A Series Product Specification x

Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) . . 49

Table 115. Transconductance Values for Low, Medium and High Gain Operating 

Table 135. Power-On Reset and Voltage Br own-Out Electrical Characteristics 

PS022827-1212 P R E L I M I N A R Y Overview Z8 Encore! XP® F082A Series Product Specification Overview Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller products based upon the 8-bit eZ8 CPU. Zilog’s Z8 Encore! XP F082A Series products expand upon Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit pro- gramming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward compatible with existing Z8 instructions. The rich peripheral set of the Z8 Encore! XP F082A Series makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices and sensors.

Features

The key features of Z8 Encore! XP F082A Series products include:

20 MHz eZ8 CPU
1 KB, 2 KB, 4 KB, or 8 KB Flash memory with in-circuit programming capability
256 B, 512 B, or 1 KB register RAM
Up to 128 B nonvolatile data storage (NVDS)
Internal precision oscillator trimmed to ±1% accuracy
External crystal oscillator, operating up to 20 MHz
Optional 8-channel, 10-bit analog-to-digital converter (ADC)
Optional on-chip temperature sensor
On-chip analog comparator
Optional on-chip low-power operational amplifier (LPO)
Full-duplex UART
The UART baud rate generator (BRG) can be configured and used as a basic 16-bit timer
Infrared Data Association (IrDA)-compliant infrared encoder/decoders, integrated with the UART
Two enhanced 16-bit timers with capture, compare and PWM capability
Watchdog Timer (WDT) with dedicated internal RC oscillator
Up to 20 vectored interrupts
6 to 25 I/O pins depending upon package
Up to thirteen 5 V-tolerant input pins

Up to 8 ports capable of direct LED drive with no current limit resistor required
On-Chip Debugger (OCD)
V oltage Brown-Out (VBO) protection
Programmable low battery detection (LVD) (8-pin devices only)
Bandgap generated precision voltage references available for the ADC, comparator, VBO and LVD
Power-On Reset (POR)
2.7 V to 3.6 V operating voltage
8-, 20- and 28-pin packages
0°C to +70°C and –40°C to +105°C for operating temperature ranges Part Selection Guide Table 1 identifies the basic features and package styles available for each device within the Z8 Encore! XP F082A Series product line.

Table 1. Z8 Encore! XP F082A Series Family Part Selection Guide

Non-volatile data storage.
Advanced Analog includes ADC, temperatur e sensor and low-power operational amplifier.

PS022827-1212 P R E L I M I N A R Y CPU and Peripheral Overview Z8 Encore! XP® F082A Series Product Specification CPU and Peripheral Overview The eZ8 CPU, Zilog’s latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The features of eZ8 CPU include:

Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory
Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks
Compatible with existing Z8 code
Expanded internal Register File allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher- level programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT and SRL
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction For more information about eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download on www.zilog.com. 10-Bit Analog-to-Digital Converter The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from eight different analog input pins in both sin- gle-ended and differential modes. The ADC also features a unity gain buffer when high input impedance is required. Low-Power Operational Amplifier The optional low-power operational amplifier (LPO) is a general-purpose amplifier pri- marily targeted for current sense applications. The LPO output may be routed internally to the ADC or externally to a pin.

PS022827-1212 P R E L I M I N A R Y CPU and Peripheral Overview Z8 Encore! XP® F082A Series Product Specification Internal Precision Oscillator The internal precision oscillator (IPO) is a trimmable clock source that requires no exter- nal components. Temperature Sensor The optional temperature sensor produces an analog output proportional to the device tem- perature. This signal can be sent to either the ADC or the analog comparator. Analog Comparator The analog comparator compares the signal at an input pin with either an internal pro- grammable voltage reference or a second input pin. The comparator output can be used to drive either an output pin or to generate an interrupt. External Crystal Oscillator The crystal oscillator circuit provides highly accurate clock frequencies with the use of an external crystal, ceramic resonator or RC network. Low Voltage Detector The low voltage detector (LVD) is able to generate an interrupt when the supply voltage drops below a user-programmable level. The LVD is available on 8-pin devices only. On-Chip Debugger The Z8 Encore! XP F082A Series products feature an integrated on-chip debugger (OCD) accessed via a single-pin interface. The OCD provides a rich-set of debugging capabilities, such as reading and writing registers, programming Flash memory, setting breakpoints and executing code. Universal Asynchronous Receiver/Transmitter The full-duplex universal asynchronous receiver/transmitter (UART) is included in all Z8 Encore! XP package types. The UART supports 8- and 9-bit data modes and selectable parity. The UART also supports multi-drop address processing in hardware. The UART baud rate generator (BRG) can be configured and used as a basic 16-bit timer. Timers Two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and

PS022827-1212 P R E L I M I N A R Y CPU and Peripheral Overview Z8 Encore! XP® F082A Series Product Specification operate in ONE-SHOT, CONTINUOUS, GATED, CAPTURE, CAPTURE RESTART, COMPARE, CAPTURE and COMPARE, PWM SINGLE OUTPUT and PWM DUAL OUTPUT modes. General-Purpose Input/Output The Product Line MCUs feature 6 to 25 port pins (Ports A–D) for general- purpose input/ output (GPIO). The number of GPIO pins available is a function of package and each pin is individually programmable. 5 V tolerant input pins are available on all  I/Os on 8-pin devices and most I/Os on other package types. Direct LED Drive The 20- and 28-pin devices support controlled current sinking output pins capable of driv- ing LEDs without the need for a current limiting resistor. These LED drivers are indepen- dently programmable to four different intensity levels. Flash Controller The Flash Controller programs and erases Flash memory. The Flash Controller supports several protection mechanisms against accidental program and erasure, plus factory serial- ization and read protection. Non-Volatile Data Storage The nonvolatile data storage (NVDS) uses a hybrid hardware/software scheme to imple- ment a byte programmable data memory and is capable of over 100,000 write cycles. Devices with 8 KB of Flash memory do not include the NVDS feature. Interrupt Controller The Z8 Encore! XP F082A Series products support up to 20 interrupts. These interrupts consist of 8 internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources. The interrupts have three levels of programmable interrupt priority. Reset Controller The Z8 Encore! XP F082A Series products can be reset using the RESET pin, Power-On Reset, Watchdog Timer (WDT) time-out, STOP Mode exit, or V oltage Brown-Out (VBO) Note:

PS022827-1212 P R E L I M I N A R Y CPU and Peripheral Overview Z8 Encore! XP® F082A Series Product Specification warning signal. The RESET pin is bidirectional, that is, it functions as reset source and as a reset indicator.

PS022827-1212 P R E L I M I N A R Y Pin Description Z8 Encore! XP® F082A Series Product Specification Pin Description The Z8 Encore! XP F082A Series products are available in a variety of packages styles and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information about physical package specifications, see the Packaging chapter on page 245. Available Packages The following package styles are available for each device in the Z8 Encore! XP F082A Series product line:

SOIC: 8-, 20- and 28-pin
PDIP: 8-, 20- and 28-pin
SSOP: 20- and 28- pin
QFN 8-pin (MLF-S, a QFN-style package with an 8-pin SOIC footprint) In addition, the Z8 Encore! XP F082A Series devices are available both with and without advanced analog capability (ADC, temperature sensor and op amp). Devices Z8F082A, Z8F042A, Z8F022A and Z8F012A contain the advanced analog, while devices Z8F081A, Z8F041A, Z8F021A and Z8F011A do not have the advanced analog capability. Pin Configurations Figure 2 through Figure 4 display the pin configurations for all the packages available in the Z8 Encore! XP F082A Series. See Table 2 on page 10 for a description of the signals. The analog input alternate functions (ANAx) are not available on the Z8F081A, Z8F041A, Z8F021A and Z8F011A devices. The analog supply pins (A VDD and A VSS) are also not available on these parts and are replaced by PB6 and PB7. At reset, all Port A, B and C pins default to an input state. In addition, any alternate func- tionality is not enabled, so the pins function as general purpose input ports until pro- grammed otherwise. At powerup, the PD0 pin defaults to the RESET alternate function. The pin configurations listed are preliminary and subject to change based on manufactur- ing limitations.

section on page 8 to determine the signals available for the specific package styles. Table 2. Signal Descriptions PA[7:0] I/O Port A. These pins are used for general-purpose I/O. available only in those devices without an ADC. PC[7:0] I/O Port C. These pins are used for general-purpose I/O. PD[0] I/O Port D. This pin is used for general-purpose output only. TXD0 O Transmit Data. This signal is the transmit output from the UART and IrDA. RXD0 I Receive Data. This signal is th e receive input for the UART and IrDA. CTS0 I Clear To Send. This signal is th e flow control input for the UART. T0OUT/T1OUT O Timer Output 0–1. These signals are outputs from the timers.

PB6 and PB7 are only available in 28-pin packages wi thout ADC. In 28-pin packages with ADC, they are
The AV DD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and PB7

on 28-pin packages without ADC.

AMPOUT O LPO output. If enabled, this pin is driven by the on-chip LPO. ers to provide the system clock. crystal can be connected between it and the XIN pin to form the oscillator. ble drive strengths set by the GPIO block. Table 2. Signal Descriptions (Continued)

PB6 and PB7 are only available in 28-pin packages wi thout ADC. In 28-pin packages with ADC, they are
The AV DD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and PB7

on 28-pin packages without ADC.

available on the Z8 Encore! XP F082A Series 8-pin devices. pin is open-drain and features an enabled internal pull-up resistor.

PB6 and PB7 are only available in 28-pin packages wi thout ADC. In 28-pin packages with ADC, they are
The AV DD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and PB7

on 28-pin packages without ADC.

PB6 and PB7 are available only in those devices without ADC. Table 3. Pin Characteristics (20- and 28-pin Devices)

PS022827-1212 P R E L I M I N A R Y Pin Characteristics Z8 Encore! XP® F082A Series Product Specification ) Table 4. Pin Characteristics (8-Pin Devices) Symbol Mnemonic Direction Reset Direction Active Low or Active High Tristate Output Internal Pull-up or Pull-down Schmitt- Trigger Input Open Drain Output 5 V Tolerance PA0/DBG I/O I (but can change during reset if key sequence detected) N/A Yes Programma- ble Pull-up Yes Yes, Programma- ble Yes, unless pull-ups enabled PA1 I/O I N/A Yes Programma- ble Pull-up Yes Yes, Programma- ble Yes, unless pull-ups enabled RESET/ PA2 I/O I/O (defaults to RESET) Low (in Reset mode) Yes Programma- ble for PA2; always on for RESET Yes Programma- ble for PA2; always on for RESET Yes, unless pull-ups enabled PA[5:3] I/O I N/A Yes Programma- ble Pull-up Yes Yes, Programma- ble Yes, unless pull-ups enabled VDD N/A N/A N/A N/A N/A N/A N/A N/A VSS N/A N/A N/A N/A N/A N/A N/A N/A

PS022827-1212 P R E L I M I N A R Y Address Space Z8 Encore! XP® F082A Series Product Specification Address Space The eZ8 CPU can access the following three distinct address spaces:

The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral and general-purpose I/O port control registers.
The Program Memory contains addresses for all memory locations having executable code and/or data.
The Data Memory contains addresses for all memory locations that contain data only. These three address spaces are covered briefly in the following subsections. For more information about eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download on www.zilog.com. Register File The Register File address space in the Z8 Encore! MCU is 4 KB (4096 bytes). The Regis- ter File is composed of two sections: control registers and general-purpose registers. When instructions are executed, registers defined as sources are read and registers defined as destinations are written. The architecture of the eZ8 CPU allows all general-purpose regis- ters to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4 KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256 B control register section are reserved (unavailable). Reading from a reserved Register File address returns an undefined value. Writing to reserved Register File addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. The Z8 Encore! XP™ F082A Series devices contain 256 B to 1 KB of on-chip RAM. Reading from Register File addresses outside the available RAM addresses (and not within the con- trol register address space) returns an undefined value. Writing to these Register File addresses produces no effect. Program Memory The eZ8 CPU supports 64 KB of Program Memory address space. The Z8 Encore! XP F082A Series devices contain 1 KB to 8 KB of on-chip Flash memory in the Program Memory address space, depending on the device. Reading from Program Memory

gram Memory Maps for the Z8 Encore! XP F082A Series products. Table 5. Z8 Encore! XP F082A Series Program Memory Maps Note: *See Table 32 on page 56 for a list of the interrupt vectors.

rather than the Program Memory data. Access to the Flash Information Area is read-only. Table 6. Z8 Encore! XP F082A Series Flash Memory Information Area Map Table 5. Z8 Encore! XP F082A Series Program Memory Maps (Continued) Note: *See Table 32 on page 56 for a list of the interrupt vectors.

Table 7. Register File Address Map

Refer to the eZ8 CPU Core User Manual (UM0128).

Table 7. Register File Address Map (Continued)

Refer to the eZ8 CPU Core User Manual (UM0128).

Refer to the eZ8 CPU Core User Manual (UM0128).

Refer to the eZ8 CPU Core User Manual (UM0128).

PS022827-1212 P R E L I M I N A R Y Reset, Stop Mode Recovery and Low Z8 Encore! XP® F082A Series Product Specification Reset, Stop Mode Recovery and Low Voltage Detection The Reset Controller within the Z8 Encore! XP F082A Series controls Reset and Stop Mode Recovery operation and provides indication of low supply voltage conditions. In typical operation, the following events cause a Reset:

Power-On Reset (POR)
V oltage Brown-Out (VBO)
Watchdog Timer time-out (when configured by the WDT_RES Flash option bit to ini- tiate a reset)
External RESET pin assertion (when the alternate RESET function is enabled by the GPIO Register)
On-chip debugger initiated Reset (OCDCTL[0] set to 1) When the device is in STOP Mode, a Stop Mode Recovery is initiated by either of the fol- lowing occurrences:
Watchdog Timer time-out
GPIO Port input pin transition on an enabled Stop Mode Recovery source The low voltage detection circuitry on the device (available on the 8-pin product versions only) performs the following functions:
Generates the VBO reset when the supply voltage drops below a minimum safe level.
Generates an interrupt when the supply voltage drops below a user-defined level (8-pin devices only). Reset Types The Z8 Encore! XP F082A Series provides several different types of Reset operation. Stop Mode Recovery is considered as a form of Reset. Table 8 lists the types of Reset and their operating characteristics. The System Reset is longer if the external crystal oscillator is enabled by the Flash option bits, allowing additional time for oscillator start-up.

oscillator and Watchdog Timer oscillator continue to run. correct system clock source is enabled and selected. Table 8. Reset and Stop Mode Recovery Characteristics and Latency

Table 9 lists the possible sources of a system reset. timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer. Status (RSTSTAT) Register is set to 1. for the POR threshold voltage (VPOR). Table 9. Reset Sources and Resulting Reset Type

block holds the device in the Reset. The V oltage Brown-Out circuit can be either enabled or disabled during STOP Mode. Option Bits chapter on page 159 for information about configuring VBO_AO. Figure 5. Power-On Reset Operation

configures the Watchdog Timer to cause an interrupt, not a System Reset, at time-out. initiated by the Watchdog Timer. Figure 6. Voltage Brown-Out Reset Operation

PS022827-1212 P R E L I M I N A R Y Stop Mode Recovery Z8 Encore! XP® F082A Series Product Specification and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. While the RESET input pin is asserted Low, the Z8 Encore! XP F082A Series devices remain in the Reset state. If the RESET pin is held Low beyond the System Reset time- out, the device exits the Reset state on the system clock rising edge following RESET pin deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta- tus bit in the Reset Status (RSTSTAT) Register is set to 1. External Reset Indicator During System Reset or when enabled by the GPIO logic (see Table 20 on page 46), the RESET pin functions as an open-drain (active Low) reset mode indicator in addition to the input functionality. This reset output feature allows a Z8 Encore! XP F082A Series device to reset other components to which it is connected, even if that reset is caused by internal sources such as POR, VBO or WDT events. After an internal reset event occurs, the internal circuitry begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry until the appropriate delay listed in Table 8 has elapsed. On-Chip Debugger Initiated Reset A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in the OCD Control Register. The On-Chip Debugger block is not reset but the rest of the chip goes through a normal system reset. The RST bit automatically clears during the sys- tem reset. Following the system reset the POR bit in the Reset Status (RSTSTAT) Register is set. Stop Mode Recovery STOP Mode is entered by execution of a STOP instruction by the eZ8 CPU. See the Low- Power Modes chapter on page 32 for detailed STOP Mode information. During Stop Mode Recovery (SMR), the CPU is held in reset for 66 IPO cycles if the crystal oscillator is disabled or 5000 cycles if it is enabled. The SMR delay (see Table 135 on page 233) TSMR, also includes the time required to start up the IPO. Stop Mode Recovery does not affect on-chip registers other than the Watchdog Timer Control Register (WDTCTL) and the Oscillator Control Register (OSCCTL). After any Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another sys- tem clock source is required, the Stop Mode Recovery code must reconfigure the oscillator control block such that the correct system clock source is enabled and selected. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vec-

Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions. (from High to Low or from Low to High) initiates Stop Mode Recovery. SMR pulses shorter than specified do not trigger a recovery (see Table 135 on page 233). In this instance, the STOP bit in the Reset Status (RSTSTAT) Register is set to 1. Table 10. Stop Mode Recovery Sources and Resulting Action

PS022827-1212 P R E L I M I N A R Y Low Voltage Detection Z8 Encore! XP® F082A Series Product Specification without initiating an interrupt (if enabled for that pin). Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! XP F082A Series device is in STOP Mode and the external RESET pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See the Electrical Characteristics chapter on page 226 for details. Low Voltage Detection In addition to the V oltage Brown-Out (VBO) Reset described above, it is also possible to generate an interrupt when the supply voltage drops below a user-selected value. For details about configuring the Low V oltage Detection (LVD) and the threshold levels avail- able, see the Trim Option Bits at Address 0003H (TLVD) Register on page 166. The LVD function is available on the 8-pin product versions only. When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status (RSTSTAT) Register is set to one. This bit remains one until the low-voltage condition goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate an interrupt when so enabled, see the GPIO Mode Interrupt Controller chapter on page 55. The LVD bit is not latched; therefore, enabling the interrupt is the only way to guarantee detection of a transient low voltage event. The LVD functionality depends on circuitry shared with the VBO block; therefore, dis- abling the VBO also disables the LVD. Reset Register Definitions The following sections define the Reset registers. Reset Status Register The read-only Reset Status (RSTSTAT) Register, shown in Table 11, indicates the source of the most recent Reset event, indicates a Stop Mode Recovery event and indicates a Watchdog Timer time-out. Reading this register resets the upper four bits to 0. This regis- ter shares its address with the write-only Watchdog Timer Control Register. Table 12 lists the bit settings for Reset and Stop Mode Recovery events.

Table 11. Reset Status Register (RSTSTAT) Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read. must occur before clearing the WDT interrupt. These bits are reserved and must be programmed to 000. threshold. This value is not latched but is a real-time indicator of the supply voltage level.

Table 12. Reset and Stop Mode Recovery Bit Descriptions

PS022827-1212 P R E L I M I N A R Y Low-Power Modes Z8 Encore! XP® F082A Series Product Specification Low-Power Modes The Z8 Encore! XP F082A Series products contain power-saving features. The highest level of power reduction is provided by the STOP Mode, in which nearly all device func- tions are powered down. The next lower level of power reduction is provided by the HALT Mode, in which the CPU is powered down. Further power savings can be implemented by disabling individual peripheral blocks while in Active mode (defined as being in neither STOP nor HALT Mode). STOP Mode Executing the eZ8 CPU’s STOP instruction places the device into STOP Mode, powering down all peripherals except the V oltage Brown-Out detector, the Low-power Operational Amplifier and the Watchdog Timer. These three blocks may also be disabled for additional power savings. Specifically, the operating characteristics are:

Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT (if previously enabled) are disabled and PA0/PA1 revert to the states programmed by the GPIO registers
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscil- lator Control Register
If enabled, the Watchdog Timer logic continues to operate
If enabled for operation in STOP Mode by the associated Flash option bit, the V oltage Brown-Out protection circuit continues to operate
Low-power operational amplifier continues to operate if enabled by the Power Control Register
All other on-chip peripherals are idle To minimize current in STOP Mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (VCC or GND). Additionally, any GPIOs config- ured as outputs must also be driven to one of the supply rails. The device can be brought out of STOP Mode using Stop Mode Recovery. For more information about Stop Mode Recovery, see the Reset, Stop Mode Recovery and Low V oltage Detection chapter on page 22.

PS022827-1212 P R E L I M I N A R Y HALT Mode Z8 Encore! XP® F082A Series Product Specification HALT Mode Executing the eZ8 CPU’s HALT instruction places the device into HALT Mode, which powers down the CPU but leaves all other peripherals active. In HALT Mode, the operat- ing characteristics are:

Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate
If enabled, the Watchdog Timer continues to operate
All other on-chip peripherals continue to operate, if enabled The eZ8 CPU can be brought out of HALT Mode by any of the following operations:
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
V oltage Brown-Out reset
External RESET pin assertion To minimize current in HALT Mode, all GPIO pins that are configured as inputs must be driven to one of the supply rails (VCC or GND). Peripheral-Level Power Control In addition to the STOP and HALT modes, it is possible to disable each peripheral on each of the Z8 Encore! XP F082A Series devices. Disabling a given peripheral minimizes its power consumption. Power Control Register Definitions The following sections define the Power Control registers. Power Control Register 0 Each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block. The default state of the low-power

operational amplifier (LPO) is OFF. To use the LPO, clear the LPO bit, turning it ON. This register is only reset during a POR sequence. Other system reset events do not affect it. Table 13. Power Control Register 0 (PWRCTL0) 0 = LPO is enabled (this applies even in STOP Mode). These bits are reserved and must be programmed to 00. This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be active. 0 = Temperature Sensor enabled. 1 = Temperature Sensor disabled. 0 = Analog-to-Digital Converter enabled. 1 = Analog-to-Digital Converter disabled. This bit is reserved and must be programmed to 0.

PS022827-1212 P R E L I M I N A R Y Power Control Register Definitions Z8 Encore! XP® F082A Series Product Specification Asserting any power control bit disables the targeted block regardless of any enable bits contained in the target block’s control registers. Note:

capable of direct LED drive at programmable drive strengths. Table 14 lists the port pins available with each device and package type. Table 14. Port Availability by Device and Package Type

PS022827-1212 P R E L I M I N A R Y Direct LED Drive Z8 Encore! XP® F082A Series Product Specification PA0 and PA6 contain two different timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the timer mode. See the Timers chapter on page 70 for more details. For pins with multiple alternate functions, Zilog recommends writing to the AFS1 and AFS2 subregisters before enabling the alternate function via the AF subregister. As a re- sult, spurious transitions through unwanted alternate function modes will be prevented. Direct LED Drive The Port C pins provide a current sinked output capable of driving an LED without requir- ing an external resistor. The output sinks current at programmable levels of 3 mA, 7 mA, 13 mA and 20 mA. This mode is enabled through the LED control registers. The LED Drive Enable (LEDEN) Register turns on the drivers. The LED Drive Level (LEDLVLH and LEDLVLL) registers select the sink current. For correct function, the LED anode must be connected to VDD and the cathode to the GPIO pin. Using all Port C pins in LED drive mode with maximum current may result in excessive total current. See the Electrical Characteristics chapter on page 226 for the max- imum total current for the applicable package. Shared Reset Pin On the 20- and 28-pin devices, the PD0 pin shares function with a bidirectional reset pin. Unlike all other I/O pins, this pin does not default to GPIO function on power-up. This pin acts as a bidirectional input/open-drain output reset until the software reconfigures it. The PD0 pin is an output-only open drain when in GPIO mode. There are no pull-up, High Drive, or Stop Mode Recovery source features associated with the PD0 pin. On the 8-pin product versions, the reset pin is shared with PA2, but the pin is not limited to output-only when in GPIO mode. If PA2 on the 8-pin product is reconfigured as an input, ensure that no external stimulus drives the pin low during any reset sequence. Since PA2 returns to its RESET alternate function during system resets, driving it Low holds the chip in a reset state until the pin is released. Caution: Caution:

PS022827-1212 P R E L I M I N A R Y Shared Debug Pin Z8 Encore! XP® F082A Series Product Specification Shared Debug Pin On the 8-pin version of this device only, the Debug pin shares function with the PA0 GPIO pin. This pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. If the unlock sequence is present, the debug function is unlocked and the pin no longer func- tions as a GPIO pin. If it is not present, the debug feature is disabled until/unless another reset event occurs. For more details, see the On-Chip Debugger chapter on page 180. Crystal Oscillator Override For systems using a crystal oscillator, PA0 and PA1 are used to connect the crystal. When the crystal oscillator is enabled, the GPIO settings are overridden and PA0 and PA1 are disabled. See the Oscillator Control Register Definitions section on page 196 for details.

5 V Tolerance

All six I/O pins on the 8-pin devices are 5 V-tolerant, unless the programmable pull-ups are enabled. If the pull-ups are enabled and inputs higher than VDD are applied to these parts, excessive current flows through those pull-up devices and can damage the chip. In the 20- and 28-pin versions of this device, any pin which shares functionality with an ADC, crystal or comparator port is not 5 V-tolerant, including PA[1:0], PB[5:0] and PC[2:0]. All other signal pins are 5 V-tolerant and can safely handle inputs higher than VDD except when the programmable pull-ups are enabled. External Clock Setup For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator Control (OSCCTL) Register such that the external oscillator is selected as the system clock. See the Oscillator Control Register Definitions section on page 196 for details. For 8-pin devices, use PA1 instead of PB3. Note:

Table 15. Port Alternate Function Mapping (Non 8-Pin Parts)

Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not

function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

Whether PA0/PA6 takes on the timer input or timer outp ut complement function depends on the timer configura-

tion. See the Timer Pin Signal Operation section on page 84 for details.

Because there are at most two choice s of alternate function for any pin of Port B, the Alternate Function Set

A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

V REF is available on PB5 in 28-pin products and on PC2 in 20-pin parts.
Because there are at most two choice s of alternate function for any pin of Port C, the Alternate Function Set

A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

Because there is only a single alternate function for t he Port PD0 pin, the Alternate Function Set registers are

nate function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

4 ADC Voltage Reference AFS1[5]: 1

Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)

Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not

function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

Whether PA0/PA6 takes on the timer input or timer outp ut complement function depends on the timer configura-

tion. See the Timer Pin Signal Operation section on page 84 for details.

Because there are at most two choice s of alternate function for any pin of Port B, the Alternate Function Set

A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

V REF is available on PB5 in 28-pin products and on PC2 in 20-pin parts.
Because there are at most two choice s of alternate function for any pin of Port C, the Alternate Function Set

A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

Because there is only a single alternate function for t he Port PD0 pin, the Alternate Function Set registers are

nate function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

4 ADC Analog Input or ADC Voltage Refer-

Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not

function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

Whether PA0/PA6 takes on the timer input or timer outp ut complement function depends on the timer configura-

tion. See the Timer Pin Signal Operation section on page 84 for details.

Because there are at most two choice s of alternate function for any pin of Port B, the Alternate Function Set

A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

V REF is available on PB5 in 28-pin products and on PC2 in 20-pin parts.
Because there are at most two choice s of alternate function for any pin of Port C, the Alternate Function Set

A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

Because there is only a single alternate function for t he Port PD0 pin, the Alternate Function Set registers are

nate function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.

PS022827-1212 P R E L I M I N A R Y External Clock Setup Z8 Encore! XP® F082A Series Product Specification Table 16. Port Alternate Function Mapping (8-Pin Parts)

Description

Port A PA0 T0IN Timer 0 Input AFS1[0]: 0 AFS2[0]: 0 Reserved AFS1[0]: 0 AFS2[0]: 1 Reserved AFS1[0]: 1 AFS2[0]: 0 T0OUT Timer 0 Output Complement AFS1[0]: 1 AFS2[0]: 1 PA1 T0OUT Timer 0 Output AFS1[1]: 0 AFS2[1]: 0 Reserved AFS1[1]: 0 AFS2[1]: 1 CLKIN External Clock Input AFS1[1]: 1 AFS2[1]: 0 Analog Functions

1 ADC Analog Input/VREF AFS1[1]: 1 AFS2[1]: 1

PA2 DE0 UART 0 Driver Enable AFS1[2]: 0 AFS2[2]: 0 RESET External Reset AFS1[2]: 0 AFS2[2]: 1 T1OUT Timer 1 Output AFS1[2]: 1 AFS2[2]: 0 Reserved AFS1[2]: 1 AFS2[2]: 1 PA3 CTS0 UART 0 Clear to Send AFS1[3]: 0 AFS2[3]: 0 COUT Comparator Output AFS1[3]: 0 AFS2[3]: 1 T1IN Timer 1 Input AFS1[3]: 1 AFS2[3]: 0 Analog Functions

2 ADC Analog Input/LPO Input (P) AFS1[3]: 1 AFS2[3]: 1

PA4 RXD0 UART 0 Receive Data AFS1[4]: 0 AFS2[4]: 0 Reserved AFS1[4]: 0 AFS2[4]: 1 Reserved AFS1[4]: 1 AFS2[4]: 0 Analog Functions2 ADC/Comparator Input (N)/LPO Input (N) AFS1[4]: 1 AFS2[4]: 1 PA5 TXD0 UART 0 Transmit Da ta AFS1[5]: 0 AFS2[5]: 0 T1OUT Timer 1 Output Complement AFS1[5]: 0 AFS2[5]: 1 Reserved AFS1[5]: 1 AFS2[5]: 0 Analog Functions2 ADC/Comparator Input (P) LPO Output AFS1[5]: 1 AFS2[5]: 1 Notes: 1. Analog functions include ADC inputs, ADC reference, comparator inputs and LPO ports. 2. The alternate function selection must be enabled; see the Port A–D Alternate Function Subregisters (PxAF) sec- tion on page 47 for details.

more information about interrupts using the GPIO pins. Four registers for each port provide access to GPIO control, input data and output data. together to provide access to subregisters for port configuration and control. Table 17. GPIO Port Registers and Subregisters PxADDR Port A–D Address Regist er; selects subregisters. PxCTL Port A–D Control Register; prov ides access to subregisters. PxIN Port A–D Input Data Register. PxOUT Port A–D Output Data Register. PxOC Output Control (Open-Drain). PxSMRE Stop Mode Recovery Source Enable. PxAFS1 Alternate Function Set 1. PxAFS2 Alternate Function Set 2.

vide access to all GPIO port controls; see Tables 18 and 19. Table 18. Port A–D GPIO Address Registers (PxADDR) The Port Address selects one of the subregisters accessible through the Port Control Register. Note: x indicates the specific GPIO port pin number (7–0). Table 19. Port A–D GPIO Address Registers by Bit Description 00H No function. Provides some protection against accidental port reconfiguration. 03H Output Control (Open-Drain). 05H Stop Mode Recove ry Source Enable. 07H Alternate Function Set 1. 08H Alternate Function Set 2.

a Port A–D Control Register transaction; see Table 20. ter by writing 01H to the Port A–D Address Register; see Table 21. Table 20. Port A–D Control Registers (PxCTL) Note: x indicates the specific GPIO port pin number (7–0). Table 21. Port A–D Data Direction Subregisters (PxDD) overrides the Data Direction Register setting. 0 = Output. Data in the Port A–D Output Data Register is driven onto the port pin. 1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Register. The output driver is tristated. Note: x indicates the specific GPIO port pin number (7–0).

ternate function. Failure to follow this guideline can result in unpredictable operation. Table 22. Port A–D Alternate Function Subregisters (PxAF) determines the direction of the pin. 1 = The alternate function selected through Alternate Function Set subregisters is enabled. Port pin operation is controlled by the alternate function. Note: x indicates the specific GPIO port pin number (7–0).

affects the pins directly and, as a result, alternate functions are also affected. Table 23. Port A–D Output Control Subregisters (PxOC) 1 = The source current for the associated pin is disabled (open-drain mode). Note: x indicates the specific GPIO port pin number (7–0). Table 24. Port A–D High Drive Enable Subregisters (PxHDE) 0 = The port pin is configured for standard output current drive. 1 = The port pin is configured for high output current drive. Note: x indicates the specific GPIO port pin number (7–0).

Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) ing STOP Mode do not initiate Stop Mode Recovery. during STOP Mode initiates Stop Mode Recovery. Note: x indicates the specific GPIO port pin number (7–0).

through the Port A–D Control Register by writing 07H to the Port A–D Address Register. the GPIO Alternate Functions section on page 37. D Alternate Function Subregisters section on page 47. Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE) 0 = The weak pull-up on the port pin is disabled. 1 = The weak pull-up on the port pin is enabled. Note: x indicates the specific GPIO port pin number (7–0).

through the Port A–D Control Register by writing 08H to the Port A–D Address Register. nate Function Subregisters section on page 47 for details. Table 27. Port A–D Alternate Function Set 1 Subregisters (PxAFS1) 0 = Port Alternate Function selected, as defined in Tables 15 and 16 on page 43. 1 = Port Alternate Function selected, as defined in Tables 15 and 16 on page 43. Note: x indicates the specific GPIO port pin number (7–0). Table 28. Port A–D Alternate Function Set 2 Subregisters (PxAFS2) 0 = Port Alternate Function selected, as defined in Table 16. 1 = Port Alternate Function selected, as defined in Table 16. Note: x indicates the specific GPIO port pin number (7–0).

values from the corresponding port pins. The Port A–C Input Data registers are read-only. and 28-pin packages, as well as those missing on the ADC-enabled 28-pin packages. The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins. Table 29. Port A–C Input Data Registers (PxIN) Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High). Note: x indicates the specific GPIO port pin number (7–0). Table 30. Port A–D Output Data Register (PxOUT) sponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = Drive a logical 0 (Low). the corresponding Port Output Control Register bit to 1. Note: x indicates the specific GPIO port pin number (7–0).

The LED Drive Enable Register, shown in Table 31, activates the controlled current drive. [7:0] correspond to Port C bits [7:0], respectively. Table 32. These two bits select between four programmable drive levels. Each pin is indi- Table 31. LED Drive Enable (LEDEN) These bits determine which Port C pins are connected to an internal current sink. 0 = Tristate the Port C pin. 1 = Enable controlled current sink on the Port C pin. Note: x indicates the specific GPIO port pin number (7–0). Table 32. LED Drive Level High Register (LEDLVLH) {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin. Note: x indicates the specific GPIO port pin number (7–0).

The LED Drive Level registers contain two control bits for each Port C pin (Table 33). Table 33. LED Drive Level Low Register (LEDLVLL) Note: x indicates the specific GPIO port pin number (7–0).

PS022827-1212 P R E L I M I N A R Y GPIO Mode Interrupt Controller Z8 Encore! XP® F082A Series Product Specification GPIO Mode Interrupt Controller The interrupt controller on the Z8 Encore! XP F082A Series products prioritizes the inter- rupt requests from the on-chip peripherals and the GPIO port pins. The features of inter- rupt controller include:

20 possible interrupt sources with 18 unique interrupt vectors: – Twelve GPIO port pin interrupt sources (two interrupt vectors are shared) – Eight on-chip peripheral interrupt sources (two interrupt vectors are shared)
Flexible GPIO interrupts: – Eight selectable rising and falling edge GPIO interrupts – Four dual-edge interrupts
Three levels of individually programmable interrupt priority
Watchdog Timer and LVD can be configured to generate an interrupt
Supports vectored and polled interrupts Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the CPU and the interrupting peripheral. When the service routine is com- pleted, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information about interrupt servicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is available for download on www.zilog.com. Interrupt Vector Listing Table 34 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most-significant byte (MSB) at the even Program Memory address and the least-significant byte (LSB) at the following odd Program Memory address. Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is unavailable on devices not containing an ADC. Note:

Table 34. Trap and Interrupt Vectors in Order of Priority

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification

Writing a 1 to the IRQE bit in the Interrupt Control Register Interrupts are globally disabled by any of the following actions:
Execution of a Disable Interrupt (DI) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
Execution of a Trap instruction
Illegal Instruction Trap
Primary Oscillator Fail Trap
Watchdog Oscillator Fail Trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority and Level 1 is the lowest priority. If all of the interrupts are enabled with identical interrupt priority (all as Level 2 interrupts, for example), the interrupt priority is assigned from highest to lowest as specified in Table 34 on page 56. Level 3 interrupts are always assigned higher priority than Level 2 interrupts which, in turn, always are assigned higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 34, above. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail Trap, Watchdog Oscillator Fail Trap and Illegal Instruction Trap always have highest (level 3) priority. Interrupt Assertion Interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond- ing bit in the Interrupt Request Register is cleared until the next interrupt occurs. Writing a 0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt request. Zilog recommends not using a coding style that clears bits in the Interrupt Request reg- isters. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 1, which follows. Caution:

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification Example 1. A poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt Request 0 Register: Example 2. A good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt Request Register triggers an interrupt (assuming that interrupt is enabled). When the inter- rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request Register is automatically cleared to 0. Zilog recommends not using a coding style to generate software interrupts by setting bits in the Interrupt Request registers. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 3, which fol- lows. Example 3. A poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt Request registers: Example 4. A good coding style that avoids lost interrupt requests: ORX IRQ0, MASK Watchdog Timer Interrupt Assertion The Watchdog Timer interrupt behavior is different from interrupts generated by other sources. The Watchdog Timer continues to assert an interrupt as long as the time-out con- dition continues. As it operates on a different (and usually slower) clock domain than the rest of the device, the Watchdog Timer continues to assert this interrupt for many system clocks until the counter rolls over. Caution:

the RSTSTAT Register until the WDT bit is cleared as shown in the following example. ual interrupts, set interrupt priorities and indicate interrupt requests. Interrupt Request 0 Register to determine if any interrupt requests are pending. Table 35. Interrupt Request 0 Register (IRQ0) This bit is reserved and must be programmed to 0. 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. 1 = An interrupt request from Timer 0 is awaiting service.

Request 1 Register to determine if any interrupt requests are pending. 1 = An interrupt request from the UART 0 receiver is awaiting service. 1 = An interrupt request from the UART 0 transmitter is awaiting service. These bits are reserved and must be programmed to 00. 1 = An interrupt request from the Analog-to-Digital Converter is awaiting service. Table 36. Interrupt Request 1 Register (IRQ1) 1 = An interrupt request from GPIO Port A or LVD. 1 = An interrupt request from GPIO Port A or Comparator. 1 = An interrupt request from GPIO Port A pin x is awaiting service. Note: x indicates the specific GPIO port pin number (0–5).

Request 2 Register to determine if any interrupt requests are pending. Interrupt Request 0 Register. Table 37. Interrupt Request 2 Register (IRQ2) These bits are reserved and must be programmed to 0000. 1 = An interrupt request from GPIO Port C pin x is awaiting service. Note: x indicates the specific GPIO Port C pin number (0–3). Table 38. IRQ0 Enable and Priority Encoding Note: x indicates register bits 0–7.

Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) This bit is reserved and must be programmed to 0. These bits are reserved and must be programmed to 00. Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL) This bit is reserved and must be programmed to 0.

Interrupt Request 1 Register. These bits are reserved and must be programmed to 00. Table 41. IRQ1 Enable and Priority Encoding Note: x indicates register bits 0–7.

either the LVD or the comparator as the interrupt source. Interrupt Request 2 Register. Table 42. IRQ1 Enable High Bit Register (IRQ1ENH) Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL)

Table 44. IRQ2 Enable and Priority Encoding Note: x indicates register bits 0–7. Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) These bits are reserved and must be programmed to 0000.

Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL) These bits are reserved and must be programmed to 0000. Table 47. Interrupt Edge Select Register (IRQES) 1 = An interrupt request is generated on the rising edge of the PAx input. Note: x indicates the specific GPIO port pin number (0–7).

alternate sources for the individual interrupts. disabled before switching between sources. Table 48. Shared Interrupt Select Register (IRQSS) 1 = The LVD is used for the interrupt for PA7VS interrupt request. 1 = The Comparator is used for the interrupt for PA6CS interrupt request. These bits are reserved and must be programmed to 000000.

Table 49. Interrupt Control Register (IRQCTL) These bits are reserved and must be programmed to 0000000.

PS022827-1212 P R E L I M I N A R Y Timers Z8 Encore! XP® F082A Series Product Specification Timers These Z8 Encore! XP F082A Series products contain two 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) sig- nals. The timers’ feature include:

16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency
Timer output pin
Timer interrupt In addition to the timers described in this chapter, the Baud Rate Generator of the UART (if unused) may also provide basic timing functionality. For information about using the Baud Rate Generator as an additional timer, see the Universal Asynchronous Receiver/ Transmitter chapter on page 99. Architecture Figure 9 displays the architecture of the timers.

FFFFH, the timer rolls over to 0000H and continues counting. Figure 9. Timer Block Diagram

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification it is appropriate to have the Timer Output make a state change at a One-Shot time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT Mode. After starting the timer, set TPOL to the opposite bit value. Observe the following steps for configuring a timer for ONE-SHOT Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for ONE-SHOT Mode. – Set the prescale value. – Set the initial output level (High or Low) if using the Timer Output alternate func- tion. 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In ONE-SHOT Mode, the system clock always provides the timer input. The timer period is computed via the following equation: CONTINUOUS Mode In CONTINUOUS Mode, the timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. Observe the following steps for configuring a timer for CONTINUOUS Mode and initiat- ing the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CONTINUOUS Mode ONE-SHOT Mode Time-Out Period s Reload Value S tart Value– Prescale System Clock Frequency Hz

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification – Set the prescale value – If using the Timer Output alternate function, set the initial output level (High or Low) 2. Write to the Timer High and Low Byte regist ers to set the starting count value (usually 0001H). This action only affects the first pass in CONTINUOUS Mode. After the first timer Reload in CONTINUOUS Mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Enable the timer interrupt (if appropriate) an d set the timer interrupt priority by writ- ing to the relevant interrupt registers. 5. Configure the associated GPIO port pin (i f using the Timer Output function) for the Timer Output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In CONTINUOUS Mode, the system clock always provides the timer input. The timer period is computed via the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT Mode equation to determine the first time-out period. COUNTER Mode In COUNTER Mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO port pin Timer Input alternate function. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal. In COUNTER Mode, the prescaler is disabled. The input frequency of the Timer Input signal must not exceed one-fourth the system clock frequency. Further, the high or low state of the input signal pulse must be no less than twice the system clock period. A shorter pulse may not be captured. Upon reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is CONTINUOUS Mode Time-Out Period (s) Reload Value Prescale Caution:

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. Observe the following steps for configuring a timer for COUNTER Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer. – Configure the timer for COUNTER Mode. – Select either the rising edge or falling edge of the Timer Input signal for the count. This selection also sets the initial logic level (High or Low) for the Timer Output alternate function. Ho wever, the Timer Output func tion is not required to be enabled. 2. Write to the Timer High and Low Byte regi sters to set the starting count value. This only affects the first pass in COUNTER Mode. After the first timer Reload in COUN- TER Mode, counting always begins at the reset value of 0001H. In COUNTER Mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control Re gister to enable the timer. In COUNTER Mode, the number of Timer Input transitions since the timer start is com- puted via the following equation: COMPARATOR COUNTER Mode In COMPARATOR COUNTER Mode, the timer counts input transitions from the analog comparator output. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. In COMPAR- ATOR COUNTER Mode, the prescaler is disabled. COUNTER Mode Timer Input Transitions Current Count Value -Start Value=

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification The frequency of the comparator output signal must not exceed one-fourth the system clock frequency. Further, the high or low state of the comparator output signal pulse must be no less than twice the system clock period. A shorter pulse may not be captured. After reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. Observe the following steps for configuring a timer for COMPARATOR COUNTER Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer. – Configure the timer for COMPARATOR COUNTER Mode. – Select either the rising edge or falling edge of the comparator output signal for the count. This also sets the initial logic le vel (High or Low) for the Timer Output alternate function. Ho wever, the Timer Output func tion is not required to be enabled. 2. Write to the Timer High and Low Byte regi sters to set the starting count value. This action only affects the first pass in COMPARATOR COUNTER Mode. After the first timer Reload in COMPARATOR COUNTER Mode, counting always begins at the reset value of 0001H. Generally, in COMPARATOR COUNTER Mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control Re gister to enable the timer. In COMPARATOR COUNTER Mode, the number of comparator output transitions since the timer start is computed via the following equation: Caution: Comparator Output Transitions Current Count Value Start Value–=

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT Mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an inter- rupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the reload value and is reset to 0001H. If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the reload value and is reset to 0001H. Observe the following steps for configuring a timer for PWM SINGLE OUTPUT Mode and initiating the PWM operation: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for PWM SINGLE OUTPUT Mode – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 5. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting.

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification The PWM period is represented by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre- sented by: If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre- sented by: PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT Mode, the timer outputs a Pulse-Width Modulated (PWM) out- put signal pair (basic PWM signal and its complement) through two GPIO port pins. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the reload value and is reset to 0001H. If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the reload value and is reset to 0001H. The timer also generates a second PWM output signal Timer Output Complement. The Timer Output Complement is the complement of the Timer Output PWM signal. A pro- grammable deadband delay can be configured to time delay (0 to 128 system clock cycles) PWM output transitions on these two pins from a low to a high (inactive to active). This PWM Period (s) Reload Value Prescale PWM Output High Time Ratio (%) Reload Value PWM Value– PWM Output High Time Ratio (%) PWM Value

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification delay ensures a time gap between the deassertion of one PWM output to the assertion of its complement. Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and initiating the PWM operation: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for PWM DUAL OUTPUT Mode by writing the TMODE bits in the TxCTL1 Register and the TMODEHI bit in TxCTL0 Register – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the PWM Control Register to set the PWM dead band delay value. The dead- band delay must be less than the duration of the positive phase of the PWM signal (as defined by the PWM high and low byte registers). It must also be less than the dura- tion of the negative phase of the PWM signal (as defined by the difference between the PWM registers and the Timer Reload registers). 5. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 6. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. Configure the associated GPIO port pin fo r the Timer Output and Timer Output Com- plement alternate functions. The Timer Output Complement function is shared with the Timer Input function for both timers. Setting the timer mode to Dual PWM auto- matically switches the function from Timer In to Timer Out Complement. 8. Write to the Timer Control Register to enable the timer and initiate counting. The PWM period is represented by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT Mode equation determines the first PWM time-out period. PWM Period (s) Reload Value xPrescale

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre- sented by: If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre- sented by: CAPTURE Mode In CAPTURE Mode, the current timer count value is recorded when the appropriate exter- nal Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer Control Register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The INPCAP bit in TxCTL0 Register is set to indicate the timer interrupt is because of an input capture event. The timer continues counting up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an inter- rupt and continues counting. The INPCAP bit in TxCTL0 Register clears indicating the timer interrupt is not because of an input capture event. Observe the following steps for configuring a timer for CAPTURE Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE Mode – Set the prescale value – Set the Capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these regis- ters allows the software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a Reload. PWM Output High Time Ratio (%) Reload Value PWM Value– PWM Output High Time Ratio (%) PWM Value

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt to be gen- erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 Register. 6. Configure the associated GPIO port pi n for the Timer Input alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. In CAPTURE Mode, the elapsed time from timer start to Capture event can be calculated using the following equation: CAPTURE RESTART Mode In CAPTURE RESTART Mode, the current timer count value is recorded when the acceptable external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer Control Register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 Register is set to indicate the timer interrupt is because of an input capture event. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 Register is cleared to indicate the timer interrupt is not caused by an input capture event. Observe the following steps for configuring a timer for CAPTURE RESTART Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE RESTART Mode by writing the TMODE bits in the TxCTL1 Register and the TMODEHI bit in TxCTL0 Register – Set the prescale value – Set the Capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). Capture Elapsed Time (s) Capture Value Start Value– Prescale

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows the soft- ware to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a Reload. 5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt to be gen- erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 Register. 6. Configure the associated GPIO port pi n for the Timer Input alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. In CAPTURE Mode, the elapsed time from timer start to Capture event can be calculated using the following equation: COMPARE Mode In COMPARE Mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon  Compare. If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. Observe the following steps for configuring a timer for COMPARE Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for COMPARE Mode – Set the prescale value Capture Elapsed Time (s) Capture Value Start Value– Prescale

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification – Set the initial logic level (High or Low) for the Timer Output alternate function, if appropriate 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In COMPARE Mode, the system clock always provides the timer input. The Compare time can be calculated by the following equation: GATED Mode In GATED Mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control Register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal remains asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset. Observe the following steps for configuring a timer for GATED Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer COMPARE Mode Time (s) Compare Value Start Value– Prescale

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification – Configure the timer for GATED Mode – Set the prescale value 2. Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED Mode. After the first timer reset in GATED Mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input deassertion and reload events. If appropriate, configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting TICONFIG field of the TxCTL0 Register. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. Write to the Timer Control Re gister to enable the timer. 7. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE Mode, the timer begins counting on the first external Timer Input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control Register. The timer input is the system clock. Every subsequent acceptable transition (after the first) of the Timer Input signal captures the current count value. The Capture value is written to the Timer PWM High and Low Byte registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 Register is set to indicate the timer interrupt is caused by an input capture event. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL0 Register is cleared to indicate the timer interrupt is not because of an input capture event. Observe the following steps for configuring a timer for CAPTURE/COMPARE Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE/COMPARE Mode – Set the prescale value

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification – Set the Capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers.By default, the timer interrupt are generated for both input capture and reload events. If appropriate, configure the timer interrupt to be gen- erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL0 Register. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. Write to the Timer Control Re gister to enable the timer. 7. Counting begins on the first appropriate tr ansition of the Timer Input signal. No inter- rupt is generated by this first edge. In CAPTURE/COMPARE Mode, the elapsed time from timer start to Capture event can be calculated using the following equation: Reading the Timer Count Values The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte Reg- ister is read, the contents of the Timer Low Byte Register are placed in a holding register. A subsequent read from the Timer Low Byte Register returns the value in the holding reg- ister. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte Register returns the actual value in the counter. Timer Pin Signal Operation The timer output function is a GPIO port pin alternate function. The Timer Output is tog- gled every time the counter is reloaded. Capture Elapsed Time (s) Capture Value Start Value– Prescale System Clock Frequency (Hz)

mode. For this mode, there is no timer input available. This section defines the features of the following Timer Control registers. bit to identify if the most recent timer interrupt is caused by an input capture event. Table 50. Timer 0–1 Control Register 0 (TxCTL0)

timers, set the prescaler value and determine the timer operating mode. This field configures timer interrupt definition. 11 = Timer Interrupt only on defined Reload/Compare Events. This bit is reserved and must be programmed to 0. before the Timer Output and the Timer Output Complement are forced to their active state. This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event. 1 = Previous timer interrupt is a result of Timer Input Capture Event. Table 51. Timer 0–1 Control Register 1 (TxCTL1)

PS022827-1212 P R E L I M I N A R Y Timer Control Register Definitions Z8 Encore! XP® F082A Series Product Specification [6] TPOL Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. COUNTER Mode If the timer is enabled the Timer Output signal is complemented after timer reload. 0 = Count occurs on the rising edge of the Timer Input signal. 1 = Count occurs on the falling edge of the Timer Input signal. PWM SINGLE OUTPUT Mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Out- put is forced Low (0) upon PWM count match and forced High (1) upon reload. CAPTURE Mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. Bit Description (Continued)

PS022827-1212 P R E L I M I N A R Y Timer Control Register Definitions Z8 Encore! XP® F082A Series Product Specification [6] TPOL (cont’d) GATED Mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE Mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal. PWM DUAL OUTPUT Mode 0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon reload. When enabled, the Timer Output Complement is forced Low (0) upon PWM count match and forced High (1) upon reload. The PWMD field in TxCTL0 Register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to High (1). 1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon reload.When enabled, the Timer Output Complement is forced High (1) upon PWM count match and forced Low (0) upon reload. The PWMD field in TxCTL0 Register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to Low (0). CAPTURE RESTART Mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARATOR COUNTER Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. Also: 0 = Count is captured on the rising edge of the comparator output. 1 = Count is captured on the falling edge of the comparator output. Caution: When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, TxOUT changes to whatever state the TPOL bit is in.The timer does not need to be enabled for that to happen. Also, the Port Data Direction Subregister is not required to be set to output on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT. Bit Description (Continued)

PS022827-1212 P R E L I M I N A R Y Timer Control Register Definitions Z8 Encore! XP® F082A Series Product Specification Timer 0–1 High and Low Byte Registers The Timer 0–1 High and Low Byte (TxH and TxL) registers, shown in Tables 52 and 53, contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TxL always returns this temporary register when the timers are enabled. When the timer is dis- abled, reads from TxL read the register directly. Writing to the Timer High and Low Byte registers while the timer is enabled is not recom- mended. There are no temporary holding registers available for write operations, so simul- taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low Byte) at the next clock edge. The counter continues counting from the new value. [5:3] PRES Prescale value The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the Timer is disabled. This reset ensures proper clock division each time the Timer is restarted. 000 = Divide by 1. 001 = Divide by 2. 010 = Divide by 4. 011 = Divide by 8. 100 = Divide by 16. 101 = Divide by 32. 110 = Divide by 64. 111 = Divide by 128. [2:0] TMODE Timer Mode This field, along with the TMODEHI bit in the TxCTL0 Register, determines the operating mode of the timer. TMODEHI is the most significant bit of the Timer mode selection value. The entire operating mode bits are expressed as {TMODEHI, TMODE[2:0]}. The TMODEHI is bit 7 of the TxCTL0 Register while TMODE[2:0] is the lower 3 bits of the TxCTL1 Register. 0000 = ONE-SHOT Mode. 0001 = CONTINUOUS Mode. 0010 = COUNTER Mode. 0011 = PWM SINGLE OUTPUT Mode. 0100 = CAPTURE Mode. 0101 = COMPARE Mode. 0110 = GATED Mode. 0111 = CAPTURE/COMPARE Mode. 1000 = PWM DUAL OUTPUT Mode. 1001 = CAPTURE RESTART Mode. 1010 = COMPARATOR COUNTER Mode. Bit Description (Continued)

Table 52. Timer 0–1 High Byte Register (TxH) Table 53. Timer 0–1 Low Byte Register (TxL) These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.

the 16-bit Timer reload value. Table 54. Timer 0–1 Reload High Byte Register (TxRH) Table 55. Timer 0–1 Reload Low Byte Register (TxRL) bytes form the 16-bit Compare value.

store the Capture values for the CAPTURE and CAPTURE/COMPARE modes. operating in CAPTURE or CAPTURE/COMPARE modes. Table 56. Timer 0–1 PWM High Byte Register (TxPWMH) Table 57. Timer 0–1 PWM Low Byte Register (TxPWML) value is set by the TPOL bit in the Timer Control Register (TxCTL1) Register.

On-chip RC oscillator
A selectable time-out response: reset or interrupt
24-bit programmable time-out value Operation The Watchdog Timer is a one-shot timer that resets or interrupts the Z8 Encore! XP F082A Series devices when the WDT reaches its terminal count. The Watchdog Timer uses a ded- icated on-chip RC oscillator as its clock source. The Watchdog Timer operates in only two modes: ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. Perform an enable by executing the WDT instruction or by setting the WDT_AO Flash option bit. The WDT_AO bit forces the Watchdog Timer to operate immediately upon reset, even if a WDT instruction has not been executed. The Watchdog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is described by the following equation: where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator frequency is 10 kHz. The Watchdog Timer cannot be refreshed after it reaches 000002H. The WDT reload value must not be set to values below 000004H. Table 58 provides infor- mation about approximate time-out delays for the minimum and maximum WDT reload values.

Table 58. Watchdog Timer Approximate Time-Out Delays

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification Watchdog Timer Refresh When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers. The Watchdog Timer counts down to 000000H unless a WDT instruc- tion is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcoun- ter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload registers. Counting resumes following the reload operation. When the Z8 Encore! XP F082A Series devices are operating in DEBUG Mode (using the on-chip debugger), the Watchdog Timer is continuously refreshed to prevent any Watch- dog Timer time-outs. Watchdog Timer Time-Out Response The Watchdog Timer times out when the counter reaches 000000H. A time-out of the Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash option bit determines the time-out response of the Watchdog Timer. For information about programming the WDT_RES Flash option bit, see the Flash Option Bits chapter on page 159. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Reset Sta- tus (RSTSTAT) Register; see the Reset Status Register on page 29. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watchdog Timer counter rolls over to its maximum value of FFFFFH and continues counting. The Watchdog Timer counter is not automatically returned to its reload value. The Reset Status (RSTSTAT) Register must be read before clearing the WDT interrupt. This read clears the WDT time-out Flag and prevents further WDT interrupts from imme- diately occurring. WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP F082A Series devices are in STOP Mode, the Watchdog Timer automatically initiates a Stop Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP bit in the Reset Status (RSTSTAT) Register are set to 1 following a WDT time-out in STOP Mode. For more information about Stop Mode Recovery, see the Reset, Stop Mode Recovery and Low V oltage Detection chapter on page 22. If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe- cuting code from the vector address.

PS022827-1212 P R E L I M I N A R Y Watchdog Timer Calibration Z8 Encore! XP® F082A Series Product Specification WDT Reset in Normal Operation If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT) Register is set to 1. For more information about system reset, see the Reset, Stop Mode Recovery and Low V oltage Detection chapter on page 22. WDT Reset in STOP Mode If configured to generate a Reset when a time-out occurs and the device is in STOP Mode, the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the STOP bit in the Reset Status (RSTSTAT) Register are set to 1 following WDT time-out in STOP Mode. Watchdog Timer Reload Unlock Sequence Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register address unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL Register address produce no effect on the bits in the WDTCTL Register. The locking mechanism prevents spurious writes to the Reload registers. Observe the following steps to unlock the Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) for write access. 1. Write 55H to the Watchdog Timer Control Register (WDTCTL). 2. Write AAH to the Watchdog Timer Control Register (WDTCTL). 3. Write the Watchdog Timer Reload Upper Byte Register (WDTU) with the appropriate time-out value. 4. Write the Watchdog Timer Reload High Byte Register (WDTH) with the appropriate time-out value. 5. Write the Watchdog Timer Reload Low Byte Register (WDTL) with the appropriate time-out value. All three Watchdog Timer Reload registers must be written in the order just listed. There must be no other register writes between each of these operations. If a register write occurs, the lock state machine resets and no further writes can occur unless the sequence is restarted. The value in the Watchdog Timer Reload registers is loaded into the counter when the Watchdog Timer is first enabled and every time a WDT instruction is executed. Watchdog Timer Calibration Due to its extremely low operating current, the Watchdog Timer oscillator is somewhat inaccurate. This variation can be corrected using the calibration data stored in the Flash Information Page; see Tables 100 and 101 on page 173 for details. Loading these values

scaling the calibration values up or down as required. Table 137 on page 235 for details. This section defines the features of the following Watchdog Timer Control registers. Table 59. Watchdog Timer Control Register (WDTCTL) to modify the contents of the Watchdog Timer reload registers.

returns the current Watchdog Timer count value. The 24-bit WDT reload value must not be set to a value less than 000004H. Table 60. Watchdog Timer Reload Upper Byte Register (WDTU) Note: A read returns the current WDT count val ue; a write sets the appropriate reload value. Most-significant byte (MSB); bits[23:16] of the 24-bit WDT reload value. Table 61. Watchdog Timer Reload High Byte Register (WDTH) Note: A read returns the current WDT count value; a write sets the appropriate reload value. Middle byte; bits[15:8] of the 24-bit WDT reload value.

Table 62. Watchdog Timer Reload Low Byte Register (WDTL) Note: A read returns the current WDT count value; a write sets the appropriate reload value. Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.

PS022827-1212 P R E L I M I N A R Y Universal Asynchronous Receiver/ Z8 Encore! XP® F082A Series Product Specification Universal Asynchronous Receiver/ Transmitter The universal asynchronous receiver/transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include:

8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two STOP bits
Separate transmit and receive interrupts
Framing, parity, overrun and break detection
Separate transmit and receive enables
16-bit baud rate generator (BRG)
Selectable MULTIPROCESSOR (9-bit) Mode with three configurable interrupt schemes
Baud rate generator (BRG) can be configured and used as a basic 16-bit timer
Driver enable (DE) output for external bus transceivers Architecture The UART consists of three primary functional blocks: transmitter, receiver and baud rate generator. The UART’s transmitter and receiver function independently, but employ the same baud rate and data format. Figure 10 displays the UART architecture.

Figure 10. UART Block Diagram

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 102 – Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin 6. Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data Register is empty (indicated by a 1). If empty, continue to Step 7. If the Transmit Data Register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data Register becomes available to receive new data. 7. Write the UART Control 1 Register to select the outgoing address bit. 8. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 9. Write the data byte to the UART Transm it Data Register. The transmitter automati- cally transfers the data to the Transmit Shift Register and transmits the data. 10. Make any changes to the Multiprocessor Bit Transmitter (MPBT) value, if appropriate and MULTIPROCESSOR Mode is enabled. 11. To transmit additional bytes, return to Step 5. Transmitting Data using the Interrupt-Driven Method The UART Transmitter interrupt indicates the availability of the Transmit Data Register to accept new data for transmission. Observe the following steps to configure the UART for interrupt-driven data transmission: 1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud rate. 2. Enable the UART pin functions by config uring the associated GPIO port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the acceptable priority. 5. Write to the UART Control 1 Register to enable MULTIPROCESSOR (9-bit) Mode functions, if MULTIPROCESSOR Mode is appropriate. 6. Set the MULTIPROCESSOR Mode Select ( MPEN) to Enable MULTIPROCESSOR Mode. 7. Write to the UART Control 0 Register to: – Set the transmit enable bit (TEN) to enable the UART for data transmission – Enable parity, if appropriate and if MULTIPROCESSOR Mode is not enabled and select either even or odd parity

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 103 – Set or clear CTSE to enable or disable control from the remote receiver using the CTS pin 8. Execute an EI instruc tion to enable interrupts. The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data Register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write the UART Control 1 Register to select the multiprocessor bit for the byte to be transmitted: 2. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 3. Write the data byte to the UART Transm it Data Register. The transmitter automati- cally transfers the data to the Transmit Shift Register and transmits the data. 4. Clear the UART Transmit interrupt bit in the applicable Interrupt Request Register. 5. Execute the IRET instruction to return from the interrupt-s ervice routine and wait for the Transmit Data Register to again become empty. Receiving Data using the Polled Method Observe the following steps to configure the UART for polled data reception: 1. Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud rate for the incoming data stream. 2. Enable the UART pin functions by config uring the associated GPIO port pins for alternate function operation. 3. Write to the UART Control 1 Register to enable MULTIPROCESSOR Mode func- tions, if appropriate. 4. Write to the UART Control 0 Register to: – Set the receive enable bit (REN) to enable the UART for data reception – Enable parity, if appropriate and if Multiprocessor mode is not enabled and select either even or odd parity. 5. Check the RDA bit in the UART Status 0 Register to determine if the Receive Data Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 5. If the Receive Data Register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data.

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 104 6. Read data from the UART Receive Data Register. If operating in MULTIPROCES- SOR (9-bit) Mode, further actions may be required depending on the MULTIPRO- CESSOR Mode bits MPMD[1:0]. 7. Return to Step 4 to receive additional data. Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (and error conditions). Observe the following steps to configure the UART receiver for interrupt-driven opera- tion: 1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud rate. 2. Enable the UART pin functions by config uring the associated GPIO port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the acceptable priority. 5. Clear the UART Receiver interrupt in th e applicable Interrupt Request Register. 6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode func- tions, if appropriate. – Set the Multiprocessor Mode Select ( MPEN) to Enable MULTIPROCESSOR Mode. – Set the Multiprocessor Mode Bits, MPMD[1:0] , to select the acceptable address matching scheme. – Configure the UART to interrupt on received data and errors or errors only (inter- rupt on errors only is unlikely to be useful for Z8 Encore! devices without a DMA block) 7. Write the device address to the Address Compare Register (automatic MULTIPRO- CESSOR Modes only). 8. Write to the UART Control 0 Register to: – Set the receive enable bit ( REN) to enable the UART for data reception – Enable parity, if appropriate and if multip rocessor mode is not enabled and select either even or odd parity 9. Execute an EI instruc tion to enable interrupt s.

Checks the UART Status 0 Register to dete rmine the source of the interrupt - error,
Reads the data from the UART Receive Data Register if the interrupt was because of

be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0].

Clears the UART Receiver interrupt in th e applicable Interrupt Request Register.
Executes the IRET instruction to return from the interrupt-service routine and await

in the middle of a character transmission, the current character is sent completely. Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 106 In MULTIPROCESSOR (9-bit) Mode, the Parity (9th) bit location becomes the multipro- cessor control bit. The UART Control 1 and Status 1 registers provide MULTIPROCES- SOR (9-bit) Mode control and status information. If an automatic address matching scheme is enabled, the UART Address Compare Register holds the network address of the device. MULTIPROCESSOR (9-bit) Mode Receive Interrupts When MULTIPROCESSOR Mode is enabled, the UART only processes frames addressed to it. The determination of whether a frame of data is addressed to the UART can be made in hardware, software or some combination of the two, depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, because it does not require access to the UART when it receives data directed to other devices on the multi-node network. The following three MULTIPROCESSOR Modes are available in hardware:

Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all mul- tiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software clears MPMD[0]. Each new incoming byte interrupts the CPU. The software is responsible for determining the end of the frame. It checks for the end-of-frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame is different from the UART’s address, MPMD[0] must be set to 1 causing the UART inter- rupts to go inactive until the next address byte. If the new frame’s address matches the UART’s, the data in the new frame is processed as well. The second scheme requires the following: set MPMD[1:0] to 10B and write the UART’s address into the UART Address Compare Register. This mode introduces additional hard- ware control, interrupting only on frames that match the UART’s address. When an incoming address byte does not match the UART’s address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an inter- rupt is issued and further interrupts now occur on each successive data byte. When the first data byte in the frame is read, the NEWFRM bit of the UART Status 1 Register is asserted. All successive data bytes have NEWFRM=0. When the next address byte occurs, the hard- ware compares it to the UART’s address. If there is a match, the interrupts continues and the NEWFRM bit is set for the first byte of the new frame. If there is no match, the UART ignores all incoming bytes until the next address match.

frame remains accompanied by a NEWFRM assertion. ceiver when communicating on a multi-transceiver bus, such as RS-485. Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 108 UART Interrupts The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the Baud Rate Generator can also func- tion as a basic timer with interrupt capability. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit (TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans- mission. The TDRE interrupt occurs after the Transmit Shift Register has shifted the first bit of data out. The Transmit Data Register can now be written with the next character to send. This action provides 7 bit periods of latency to load the Transmit Data Register before the Transmit Shift Register completes shifting the current character. Writing to the UART Transmit Data Register clears the TDRE bit to 0. Receiver Interrupts The receiver generates an interrupt when any of the following actions occur:

A data byte is received and is available in the UART Receive Data Register. This inter- rupt can be disabled independently of the other receiver interrupt sources. The received data interrupt occurs after the receive character has been received and placed in the Re- ceive Data Register. To avoid an overrun error, software must respond to this received data available condition before the next character is completely received. In MULTIPROCESSOR Mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte.
A break is received.
An overrun is detected.
A data framing error is detected. UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data Register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 Register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data Register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and must be ignored. The BRKD bit indi- cates if the overrun was caused by a break condition on the line. After reading the status Note:

PS022827-1212 P R E L I M I N A R Y UART Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 110 Rate Generator to function as an additional counter if the UART functionality is not employed. UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans- mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data rate is calculated using the following equation: When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit timer with an interrupt upon time-out. Observe the following steps to configure the Baud Rate Generator as a timer with an interrupt upon time-out: 1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register to 0. 2. Load the acceptable 16-bit count value into the UART Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer fu nction and associated interrupt by setting the BRGCTL bit in the UART Control 1 Register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation: UART Control Register Definitions The UART Control registers support the UART and the associated Infrared Encoder/ Decoders. For more information about infrared operation, see the Infrared Encoder/ Decoder chapter on page 120. UART Control 0 and Control 1 Registers The UART Control 0 (UxCTL0) and Control 1 (UxCTL1) registers, shown in Tables 63 and 64, configure the properties of the UART’s transmit and receive operations. The UART Control registers must not be written while the UART is enabled. UART Data Rate (bits/s) System Clock Frequency (Hz) Interrupt Interval s System Clock Period (s) BRG 15:0=

Table 63. UART Control 0 Register (U0CTL0) 1 = The UART recognizes the CTS signal as an enable control from the transmitter. 1 = Odd parity is transmitted and expected on all received data. 1 = Forces a break condition by setting the output of the transmitter to zero. 1 = The transmitter sends two stop bits. 1 = All transmitted data is looped back to the receiver.

Table 64. UART Control 1 Register (U0CTL1) 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. recent address byte matched the value in the Address Compare Register. 1 = Enable MULTIPROCESSOR (9-bit) Mode. 1 = Send a 1 in the multiprocessor bit location of the data stream (address byte). 1 = DE signal is Active Low.

PS022827-1212 P R E L I M I N A R Y UART Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 113 [2] BRGCTL Baud Rate Control This bit causes an alternate UART behavior depending on the value of the REN bit in the UART Control 0 Register. When the UART receiver is not enabled (REN=0), this bit deter- mines whether the Baud Rate Generator issues interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG reload value. 1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate reg- isters to return the BRG count value instead of the reload value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG reload value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High Byte is read. [1] RDAIRQ Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Con- troller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request. [0] IREN Infrared Encoder/Decoder Enable 0 = Infrared Encoder/Decoder is disabled. UART operates normally. 1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through the Infrared Encoder/Decoder. Bit Description (Continued)

66, identify the current UART operating configuration and status. Table 65. UART Status 0 Register (U0STAT0) Receive Data Register clears this bit. 0 = The UART Receive Data Register is empty. 1 = There is a byte in the UART Receive Data Register. 0 = No parity error has occurred. 1 = A parity error has occurred. reading the UART Receive Data Register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data Register clears this bit. 1 = A framing error occurred. are all 0s this bit is set to 1. Reading the UART Receive Data Register clears this bit.

This register contains multiprocessor control and status bits. ister File address with the read-only UART Receive Data Register. This bit indicates that the UART Transmit Data Register is empty and ready for additional data. Writing to the UART Transmit Data Register resets this bit. 0 = Do not write to the UART Transmit Data Register. 1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted. This bit indicates that the Transmit Shift Register is empty and character transmission is finished. 0 = Data is currently transmitting. 1 = Transmission is complete. When this bit is read it returns the level of the CTS signal. This signal is active Low. Table 66. UART Status 1 Register (U0STAT1) These bits are reserved and must be programmed to 000000. 1 = The current byte is the first data byte of a new frame. Receive Data Register resets this bit to 0.

shares a Register File address with the Write-only UART Transmit Data Register. ister. Receive interrupts and RDA assertions only occur in the event of a match. Table 67. UART Transmit Data Register (U0TXD) UART transmitter data byte to be shifted out through the TXDx pin. Table 68. UART Receive Data Register (U0RXD) UART receiver data byte from the RXDx pin.

the data transmission rate (baud rate) of the UART. Table 69. UART Address Compare Register (U0ADDR) This 8-bit value is compared to incoming address bytes. Table 70. UART Baud Rate High Byte Register (U0BRH) Table 71. UART Baud Rate Low Byte Register (U0BRL)

For reliable communication, the UART baud rate error must never exceed 5 percent. monly used crystal oscillator frequencies. Table 72. UART Baud Rates

Table 72. UART Baud Rates (Continued)

Figure 17. Infrared Data Transmission

UART. Each UART/Infrared data bit is 16-clocks wide. Figure 18 displays data reception. XP F082A Series products while the IR_RXD signal is received through the RXD pin. 1.4 µs minimum width pulses allowed by the IrDA standard. reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. Figure 18. IrDA Data Reception

PS022827-1212 P R E L I M I N A R Y Infrared Encoder/Decoder Control Register Z8 Encore! XP® F082A Series Product Specification 123 The window remains open until the count again reaches 8 (that is, 24 baud clock periods since the previous pulse was detected), giving the Endec a sampling window of minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the Endec clock counter is reset, resynchronizing the Endec to the incoming signal, allowing the Endec to tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the Endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchro- nized to the incoming data stream when a Start bit is received. Infrared Encoder/Decoder Control Register Definitions All infrared endec configuration and status information is set by the UART Control regis- ters as defined in the Universal Asynchronous Receiver/Transmitter section on page 99. To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling the GPIO Port alternate function for the corresponding pin. Caution:

PS022827-1212 P R E L I M I N A R Y Analog-to-Digital Converter Z8 Encore! XP® F082A Series Product Specification 124 Analog-to-Digital Converter The analog-to-digital converter (ADC) converts an analog input signal to its digital repre- sentation. The features of this sigma-delta ADC include:

11-bit resolution in DIFFERENTIAL Mode
10-bit resolution in SINGLE-ENDED Mode
Eight single-ended analog input sources are multiplexed with general-purpose I/O ports
9th analog input obtained from temperature sensor peripheral
11 pairs of differential inputs also multiplexed with general-purpose I/O ports
Low-power operational amplifier (LPO)
Interrupt on conversion complete
Bandgap generated internal voltage reference with two selectable levels
Manual in-circuit calibration is possible employing user code (offset calibration)
Factory calibrated for in-circuit error compensation Architecture Figure 19 displays the major functional blocks of the ADC. An analog multiplexer net- work selects the ADC input from the available analog pins, ANA0 through ANA7. The input stage of the ADC allows both differential gain and buffering. The following input options are available:
Unbuffered input (SINGLE-ENDED and DIFFERENTIAL modes)
Buffered input with unity gain (SINGLE-ENDED and DIFFERENTIAL modes)
LPO output with full pin access to the feedback path

Figure 19. Analog-to-Digital Converter Block Diagram

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 126 The ADC registers actually return 13 bits of data, but the two LSBs are intended for com- pensation use only. When the software compensation routine is performed on the 13 bit raw ADC value, two bits of resolution are lost because of a rounding error. As a result, the final value is an 11-bit number. Hardware Overflow When the hardware overflow bit (OVF) is set in ADC Data Low Byte (ADCD_L) Regis- ter, all other data bits are invalid. The hardware overflow bit is set for values greater than VREF and less than –VREF (DIFFERENTIAL Mode). Automatic Powerdown If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of the ADC are automatically powered down. From this powerdown state, the ADC requires 40 system clock cycles to power up. The ADC powers up when a conver- sion is requested by the ADC Control Register. Single-Shot Conversion When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. Observe the following steps for setting up the ADC and initiating a sin- gle-shot conversion: 1. Enable the appropriate analog inputs by co nfiguring the general-purpose I/O pins for alternate analog function. This configuration disables the digital input and output drivers. 2. Write the ADC Control/Status Register 1 to configure the ADC. – Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, plus unbuffered or buffered mode. – Write the REFSELH bit of the pair { REFSELH, REFSELL} to select the internal voltage reference level or to disa ble the internal reference. The REFSELL bit is. contained in the ADC Control Register 0. 3. Write to the ADC Control Register 0 to configure the ADC and begin the conversion. The bit fields in the ADC Control Register can be written simultaneously (the ADC can be configured and enabled with the same write instruction): – Write to the ANAIN[3:0] field to select from the avai lable analog input sources (different input pins available depending on the device). – Clear CONT to 0 to select a single-shot conversion.

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 127 – If the internal voltage reference mu st be output to a pin, set the REFEXT bit to 1. The internal voltage reference must be enabled in this case. – Write the REFSELL bit of the pair { REFSELH, REFSELL} to select the internal voltage reference level or to disa ble the internal reference. The REFSELH bit is contained in the ADC Control/Status Register 1. – Set CEN to 1 to start the conversion. 4. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered down state, the ADC uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion. 5. When the conversion is co mplete, the ADC control logic performs the following oper- ations: – 13-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:3]} – Sends an interrupt request to the Interrupt Controlle r denoting conversion com- plete – CEN resets to 0 to indicate the conversion is complete 6. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered down. Continuous Conversion When configured for continuous conversion, the ADC continuously performs an analog- to-digital conversion on the selected analog input. Each new data value overwrites the pre- vious value stored in the ADC Data registers. An interrupt is generated after each conver- sion. In CONTINUOUS Mode, ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not immediately detected at the next output from the ADC. The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency. Observe the following steps for setting up the ADC and initiating continuous conversion: 1. Enable the appropriate analog input by configuring the general-purpose I/O pins for alternate function. This action disables the digital input and output driver. 2. Write the ADC Control/Status Register 1 to configure the ADC. Caution:

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 128 – Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, plus unbuffered or buffered mode. – Write the REFSELH bit of the pair { REFSELH, REFSELL} to select the internal voltage reference level or to disa ble the internal reference. The REFSELL bit is contained in the ADC Control Register 0. 3. Write to the ADC Control Register 0 to co nfigure the ADC for continuous conversion. The bit fields in the ADC Control Register may be written simultaneously: – Write to the ANAIN[3:0] field to select from the avai lable analog input sources (different input pins available depending on the device). – Set CONT to 1 to select continuous conversion. – If the internal VREF must be output to a pin, set the REFEXT bit to 1. The internal voltage reference must be enabled in this case. – Write the REFSELL bit of the pair { REFSELH, REFSELL} to select the internal voltage reference level or to disa ble the internal reference. The REFSELH bit is contained in ADC Control/Status Register 1. – Set CEN to 1 to start the conversions. 4. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: – CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation – An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete 5. The ADC writes a new data result every 256 system clock cycles. For each completed conversion, the ADC control logic performs the following operations: – Writes the 13-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:3]} – Sends an interrupt request to the Interrupt Controlle r denoting conversion com- plete 6. To disable continuous conversion, clear the CONT bit in the ADC Control Register to 0. Interrupts The ADC is able to interrupt the CPU when a conversion has been completed. When the ADC is disabled, no new interrupts are asserted; however, an interrupt pending when the ADC is disabled is not cleared.

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 129 Calibration and Compensation The Z8 Encore! XP F082A Series ADC is factory calibrated for offset error and gain error, with the compensation data stored in Flash memory. Alternatively, you can perform your own calibration, storing the values into Flash themselves. Thirdly, the user code can per- form a manual offset calibration during DIFFERENTIAL Mode operation. Factory Calibration Devices that have been factory calibrated contain 30 bytes of calibration data in the Flash option bit space. This data consists of 3 bytes for each input mode, one for offset and two for gain correction. For a list of input modes for which calibration data exists, see the Zilog Calibration Data section on page 168. User Calibration If you have precision references available, its own external calibration can be performed using any input modes. This calibration data takes into account buffer offset and nonlin- earity; therefore Zilog recommends that this calibration be performed separately for each of the ADC input modes planned for use. Manual Offset Calibration When uncalibrated, the ADC has significant offset (see Table 139 on page 236). Subse- quently, manual offset calibration capability is built into the block. When the ADC Con- trol Register 0 sets the input mode (ANAIN[2:0]) to MANUAL OFFSET CALIBRATION Mode, the differential inputs to the ADC are shorted together by an inter- nal switch. Reading the ADC value at this point produces 0 in an ideal system. The value actually read is the ADC offset. This value can be stored in nonvolatile memory (see the Nonvolatile Data Storage chapter on page 176) and accessed by user code to compensate for the input offset error. There is no provision for manual gain calibration. Software Compensation Procedure Using Factory Calibration Data The value read from the ADC high and low byte registers is uncompensated. The user mode software must apply gain and offset correction to this uncompensated value for maximum accuracy. The following equation yields the compensated value: where GAINCAL is the gain calibration value, OFFCAL is the offset calibration value and ADCuncomp is the uncompensated value read from the ADC. All values are in two’s com- plement format. ADC comp ADC uncomp OFFCAL– ADC uncomp OFFCAL– GAINCAL 216+=

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 130 The offset compensation is performed first, followed by the gain compensation. One bit of resolution is lost because of rounding on both the offset and gain computations. As a result the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and 10 data bits. Also note that in the second term, the multiplication must be performed before the divi- sion by 216. Otherwise, the second term incorrectly evaluates to zero. Although the ADC can be used without the gain and offset compensation, it does exhibit nonunity gain. Designing the ADC with sub-unity gain reduces noise across the ADC range but requires the ADC results to be scaled by a factor of 8/7. ADC Compensation Details High-efficiency assembly code that performs ADC compensation is available for down- load on www.zilog.com. This section offers a bit-specific description of the ADC compen- sation process used by this code. The following data bit definitions are used: 0–9, a–f = bit indices in hexadecimal s = sign bit v = overflow bit – = unused Input Data MSB LSB s b a 9 8 7 6 5 4 3 2 1 0 – – v (ADC) ADC Output Word; if v = 1, the data is invalid s 6 5 4 3 2 1 0 Offset Correction Byte s s s s s 7 6 5 4 3 2 1 0 0 0 0 (Offset) Offset Byte shifted to align with ADC data s e d c b a 9 8 7 6 5 4 3 2 1 0 (Gain) Gain Correction Word Note: Caution:

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 131 Compensation Steps: 1. Correct for Offset: 2. Compute the absolute value of the offset-corrected ADC value if negative; the gain correction factor is computed assuming positive numbers, with sign restoration after- ward. Also compute the absolute value of the gain correction word, if negative. 3. Multiply by the Gain Correction Word. If operating in DIFFERENTIAL Mode, there are two gain correction values: one for positive ADC values, another for negative ADC values. Use the appropriate Gain Correction Word based on the sign computed by byte #2. ADC MSB ADC LSB Offset MSB Offset LSB #1 MSB #1 LSB #2 MSB #2 LSB AGain MSB AGain LSB #2 MSB #2 LSB AGain MSB AGain LSB

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 132 4. Round the result and discard the least significant two bytes (equivalent to dividing by 216). 5. Determine the sign of the gain correc tion factor using the sign bits from Step 2. If the offset-corrected ADC value and the gain correction word both have the same sign, then the factor is positive and remains unchanged. If they have differing signs, then the factor is negative and must be multiplied by –1. 6. Add the gain correction factor to the original offset corrected value. 7. Shift the result to the right, using the sign bit determined in Step 1, to allow for the detection of computational overflow. #3 #3 #3 #3 #3 #3 #3 #3 0x00 0x00 0x80 0x00 #4 MSB #4 LSB #5 MSB #5 LSB #5 MSB #5 LSB #1 MSB #1 LSB #6 MSB #6 LSB S → #6 MSB #6 LSB

PS022827-1212 P R E L I M I N A R Y ADC Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 133 Output Data The output format of the corrected ADC value is shown below. The overflow bit in the corrected output indicates that the computed value was greater than the maximum logical value (+1023) or less than the minimum logical value (–1024). Unlike the hardware overflow bit, this is not a simple binary flag. For a normal (nonover- flow) sample, the sign and the overflow bit match. If the sign bit and overflow bit do not match, a computational overflow has occurred. Input Buffer Stage Many applications require the measurement of an input voltage source with a high output impedance. This ADC provides a buffered input for such situations. The drawback of the buffered input is a limitation of the input range. When using unity gain buffered mode, the input signal must be prevented from coming too close to either VSS or VDD. See Table 139 on page 236 for details. This condition applies only to the input voltage level (with respect to ground) of each dif- ferential input signal. The actual differential input voltage magnitude may be less than 300 mV . The input range of the unbuffered ADC swings from V SS to VDD. Input signals smaller than 300 mV must use the unbuffered input mode. If these signals do not contain low out- put impedances, they might require off-chip buffering. Signals outside the allowable input range can be used without instability or device dam- age. Any ADC readings made outside the input range are subject to greater inaccuracy than specified. ADC Control Register Definitions This section defines the features of the following ADC Control registers. ADC Control Register 0 (ADCCTL0): see page 134 ADC Control/Status Register 1 (ADCCTL1): see page 136 ADC Data High Byte Register (ADCD_H): see page 137 ADC Data Low Byte Register (ADCD_L): see page 137 MSB LSB s v b a 9 8 7 6 5 4 3 2 1 0 – –

the analog-to-digital conversion. It also selects the voltage reference configuration. Table 73. ADC Control Register 0 (ADCCTL0) this bit to 0 when a conversion is complete. progress, the conversion restarts. This bit remains 1 until the conversion is complete. SELH, REFSELL}; note that this reference is independent of the Comparator reference. 0 = Reference buffer is disabled; Vref pin is available for GPIO or analog functions. the REFOUT bit must be set to 0. cycles (measurements of the internal temperature sensor take twice as long). ADC Control/Status Register 1.

PS022827-1212 P R E L I M I N A R Y ADC Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 135 For the reserved values, all input switches are disabled to avoid leakage or other undesir- able operation. ADC samples taken with reserved bit settings are undefined. SINGLE-ENDED Mode: 0000 = ANA0 (transimpedance amp output when enabled) 0001 = ANA1 (transimpedance amp inverting input) 0010 = ANA2 (transimpedance amp noninverting input) 0011 = ANA3 0100 = ANA4 0101 = ANA5 0110 = ANA6 0111 = ANA7 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = Hold transimpedance input nodes (ANA1 and ANA2) to ground. 1101 = Reserved 1110 = Temperature Sensor. 1111 = Reserved. DIFFERENTIAL Mode (noninverting input and inverting input respectively): 0000 = ANA0 and ANA1 0001 = ANA2 and ANA3 0010 = ANA4 and ANA5 0011 = ANA1 and ANA0 0100 = ANA3 and ANA2 0101 = ANA5 and ANA4 0110 = ANA6 and ANA5 0111 = ANA0 and ANA2 1000 = ANA0 and ANA3 1001 = ANA0 and ANA4 1010 = ANA0 and ANA5 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Manual Offset Calibration Mode ADC Control/Status Register 1 The ADC Control/Status Register 1 (ADCCTL1) configures the input buffer stage, enables the threshold interrupts and contains the status of both threshold triggers. It is also used to select the voltage reference configuration.

ADC Data High Byte Register latches data in the ADC Low Bits Register. Table 74. ADC Control/Status Register 1 (ADCCTL1) REFSELL}; this reference is independent of the Comparator reference. These bits are reserved and must be programmed to 0000.

Table 75. ADC Data High Byte Register (ADCD_H) held in this register. These bits are undefined after a Reset. Table 76. ADC Data Low Byte Register (ADCD_L)

PS022827-1212 P R E L I M I N A R Y ADC Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 138 [2:1] Reserved These bits are reserved and must be undefined. [0] OVF Overflow Status 0 = A hardware overflow did not occur in the ADC for the current sample. 1= A hardware overflow did occur in the ADC for the current sample, therefore the current sample is invalid. Bit Description (Continued)

PS022827-1212 P R E L I M I N A R Y Low Power Operational Amplifier Z8 Encore! XP® F082A Series Product Specification 139 Low Power Operational Amplifier The LPO is a general-purpose low power operational amplifier. Each of the three ports of the amplifier is accessible from the package pins. The LPO contains only one pin configu- ration: ANA0 is the output/feedback node, ANA1 is the inverting input and ANA2 is the noninverting input. Operation To use the LPO, it must be enabled in the Power Control Register 0 (PWRCTL0). The default state of the LPO is OFF. To use the LPO, the LPO bit must be cleared by turning it ON (for details, see the Power Control Register 0 section on page 33). When making normal ADC measurements on ANA0 (i.e., measurements not involving the LPO output), the LPO bit must be turned OFF. Turning the LPO bit ON interferes with normal ADC measurements. The LPO bit enables the amplifier even in STOP Mode. If the amplifier is not required in STOP Mode, disable it. Failing to perform this results in STOP Mode currents higher than necessary. As with other ADC measurements, any pins used for analog purposes must be configured as such in the GPIO registers. See the Port A–D Alternate Function Subregisters section on page 47 for details. LPO output measurements are made on ANA0, as selected by the ANAIN[3:0] bits of ADC Control Register 0. It is also possible to make single-ended measurements on ANA1 and ANA2 while the amplifier is enabled, which is often useful for determining offset con- ditions. Differential measurements between ANA0 and ANA2 may be useful for noise cancellation purposes. If the LPO output is routed to the ADC, then the BUFFMODE[2:0] bits of ADC Control/Sta- tus Register 1 must also be configured for unity-gain buffered operation. Sampling the LPO in an unbuffered mode is not recommended. When either input is overdriven, the amplifier output saturates at the positive or negative supply voltage. No instability results. Caution:

available as an interrupt source or can be routed to an external pin. retains its present value. See Table 141 on page 238 for details. Register 0 section on page 33 for details. comparator output to settle. Doing so can result in spurious interrupts. Figure 20. Comparator Block Diagram

value of the internal voltage reference. Table 77. Comparator Control Register (CMP0) 0 = GPIO pin used as positive comparator input. 1 = Temperature sensor used as positive comparator input. 0 = Internal reference disabled, GPIO pin used as negative comparator input. 1 = Internal reference enabled as negative comparator input.

PS022827-1212 P R E L I M I N A R Y Comparator Control Register Definition Z8 Encore! XP® F082A Series Product Specification 142 [5:2] REFLVL Internal Reference Voltage Level This reference is independent of the ADC voltage reference. Note: 8-pin devices contain two additional LSBs for increased resolution. For 20-/28-pin devices: 0000 = 0.0 V 0001 = 0.2 V 0010 = 0.4 V 0011 = 0.6 V 0100 = 0.8 V 0101 = 1.0 V (Default) 0110 = 1.2 V 0111 = 1.4 V 1000 = 1.6 V 1001 = 1.8 V 1010–1111 = Reserved Bit Description (Continued)

PS022827-1212 P R E L I M I N A R Y Comparator Control Register Definition Z8 Encore! XP® F082A Series Product Specification 143 [1:0] For 8-pin devices, the following voltages can be configured; for 20- and 28-pin devices, these bits are reserved. 000000 = 0.00 V 000001 = 0.05 V 000010 = 0.10 V 000011 = 0.15 V 000100 = 0.20 V 000101 = 0.25 V 000110 = 0.30 V 000111 = 0.35 V 001000 = 0.40 V 001001 = 0.45 V 001010 = 0.50 V 001011 = 0.55 V 001100 = 0.60 V 001101 = 0.65 V 001110 = 0.70 V 001111 = 0.75 V 010000 = 0.80 V 010001 = 0.85 V 010010 = 0.90 V 010011 = 0.95 V 010100 = 1.00 V (Default) 010101 = 1.05 V 010110 = 1.10 V 010111 = 1.15 V 011000 = 1.20 V 011001 = 1.25 V 011010 = 1.30 V 011011 = 1.35 V 011100 = 1.40 V 011101 = 1.45 V 011110 = 1.50 V 011111 = 1.55 V 100000 = 1.60 V 100001 = 1.65 V 100010 = 1.70 V 100011 = 1.75 V 100100 = 1.80 V Bit Description (Continued)

PS022827-1212 P R E L I M I N A R Y Temperature Sensor Z8 Encore! XP® F082A Series Product Specification 144 Temperature Sensor The on-chip Temperature Sensor allows you to measure temperature on the die with either the on-board ADC or on-board comparator. This block is factory calibrated for in-circuit software correction. Uncalibrated accuracy is significantly worse, therefore the tempera- ture sensor is not recommended for uncalibrated use. Temperature Sensor Operation The on-chip temperature sensor is a Proportional to Absolute Temperature (PTAT) topol- ogy. A pair of Flash option bytes contain the calibration data. The temperature sensor can be disabled by a bit in the Power Control Register 0 section on page 33 to reduce power consumption. The temperature sensor can be directly read by the ADC to determine the absolute value of its output. The temperature sensor output is also available as an input to the comparator for threshold type measurement determination. The accuracy of the sensor when used with the comparator is substantially less than when measured by the ADC. If the temperature sensor is routed to the ADC, the ADC must be configured in unity-gain buffered mode (for details, see the Input Buffer Stage section on page 133). The value read back from the ADC is a signed number, although it is always positive. The sensor is factory-trimmed through the ADC using the external 2.0 V reference. Unless the sensor is retrimmed for use with a different reference, it is most accurate when used with the external 2.0 V reference. Because this sensor is an on-chip sensor, Zilog recommends that the user account for the difference between ambient and die temperature when inferring ambient temperature con- ditions. During normal operation, the die undergoes heating that causes a mismatch between the ambient temperature and that measured by the sensor. For best results, the Z8 Encore! XP device must be placed into STOP Mode for sufficient time such that the die and ambient temperatures converge (this time is dependent on the thermal design of the system). The temperature sensor measurement must then be made immediately after recovery from STOP Mode. The following equation defines the transfer function between the temperature sensor out- put voltage and the die temperature. This is needed for comparator threshold measure- ments. V 0.01 T 0.65 +=

PS022827-1212 P R E L I M I N A R Y Temperature Sensor Operation Z8 Encore! XP® F082A Series Product Specification 145 In the above equation, T is the temperature in °C; V is the sensor output in volts. Assuming a compensated ADC measurement, the following equation defines the relation- ship between the ADC reading and the die temperature: In the above equation, T is the temperature in C; ADC is the 10-bit compensated ADC value; and TSCAL is the temperature sensor calibration value, ignoring the two least sig- nificant bits of the 12-bit value. See the Temperature Sensor Calibration Data section on page 171 for the location of TSCAL. Calibration The temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30°C. Accuracy decreases as measured temperatures move further from the calibration point.

8 KB (8192), 4 KB (4096), 2 KB (2048 bytes), or 1 KB (1024) with read/write/erase capa-

User controlled read and write protect capability
Sector-based write protection scheme
Additional protection schemes against accidental program and erasure Architecture The Flash memory array is arranged in pages with 512 bytes per page. The 512-byte page is the minimum Flash block size that can be erased. Each page is divided into 8 rows of 64 bytes. For program or data protection, the Flash memory is also divided into sectors. In the Z8 Encore! XP F082A Series, these sectors are either 1024 bytes (in the 8 KB devices) or 512 bytes (all other memory sizes) in size. Page and sector sizes are not generally equal. The first 2 bytes of Flash Program memory are used as Flash option bits. For more infor- mation about their operation, see the Flash Option Bits chapter on page 159. Table 78 describes the Flash memory configuration for each device in the Z8 Encore! XP F082A Series. Figure 21 displays the Flash memory arrangement.

Table 78. Z8 Encore! XP F082A Series Flash Memory Configurations

address range FE00H to FFFFH. This area is readable but cannot be erased or overwritten. the ADC is also stored here. ming or erasure. These mechanism operate on the page, sector and full-memory levels. Figure 21. Flash Memory Arrangement

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 149 Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory, you must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis- ters allow programming and erasing of the Flash with system clock frequencies ranging from 32 kHz (32768 Hz) through 20 MHz. The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash Frequency value must contain the system clock frequency (in kHz). This value is calcu- lated using the following equation: Flash programming and erasure are not supported for system clock frequencies below 32 kHz (32768 Hz) or above 20 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure operation of the Z8 Encore! XP F082A Series devices. Flash Code Protection Against External Access The user code contained within the Flash memory can be protected against external access by the on-chip debugger. Programming the FRP Flash option bit prevents reading of the user code with the On-Chip Debugger. See the Flash Option Bits chapter on page 159 and the On-Chip Debugger chapter on page 180 for more information. Flash Code Protection Against Accidental Program and Erasure The Z8 Encore! XP F082A Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by a com- bination of the Flash option bits, the register locking mechanism, the page select redun- dancy and the sector level protection control of the Flash Controller. Flash Code Protection Using the Flash Option Bits The FRP and FWP Flash option bits combine to provide three levels of Flash Program Memory protection, as shown in Table 79. See the Flash Option Bits chapter on page 159 for more information. FFREQ[15:0] System Clock Frequency (Hz) Caution:

active. See Figure 22 on page 148 for details. tected. Any other value written to the Flash Control Register locks the Flash Controller. Mass Erase is not allowed in the user code but only in through the Debug Port. fer to enable sector protection. Table 79. Flash Code Protection Using the Flash Option Bits

0 Programming and erasing disabled for all of Flash Program Mem-

disabled. Mass Erase is available through the On-Chip Debugger.

1 Programming, Page Erase and Mass Erase are enabled for all of

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 151 ter with 5EH. After the Flash Sector Protect Register is selected, it can be accessed at the Page Select Register address. When user code writes the Flash Sector Protect Register, bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than 5EH to the Flash Control Register deselects the Flash Sector Protect Register and reenables access to the Page Select Register. Observe the following procedure to setup the Flash Sector Protect Register from user code: 1. Write 00H to the Flash Control Register to reset the Flash Controller. 2. Write 5EH to the Flash Control Register to select the Flash Sector Protect Register. 3. Read and/or write the Flash Sector Protect Register which is now at Register File address FF9H. 4. Write 00H to the Flash Control Register to return the Flash Controller to its reset state. The Sector Protect Register is initialized to 0 on reset, putting each sector into an unpro- tected state. When a bit in the Sector Protect Register is written to 1, the corresponding sector is no longer written or erased by the CPU. External Flash programming through the OCD or via the Flash Controller Bypass mode are unaffected. After a bit of the Sector Pro- tect Register has been set, it cannot be cleared except by powering down the device. Byte Programming Flash Memory is enabled for byte programming after unlocking the Flash Controller and successfully enabling either Mass Erase or Page Erase. When the Flash Controller is unlocked and Mass Erase is successfully completed, all Program Memory locations are available for byte programming. In contrast, when the Flash Controller is unlocked and Page Erase is successfully completed, only the locations of the selected page are available for byte programming. An erased Flash byte contains all 1’s (FFH). The programming operation can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits) from 0 to 1 requires execution of either the Page Erase or Mass Erase commands. Byte Programming can be accomplished using the On-Chip Debugger’s Write Memory command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU Core User Manual (UM0128), available for download on www.zilog.com, for a descrip- tion of the LDC and LDCI instructions. While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to oper- ate. To exit programming mode and lock the Flash, write any value to the Flash Control Register, except the Mass Erase or Page Erase commands.

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 152 The byte at each address of the Flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. Doing so may result in corrupted data at the target byte. Page Erase The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Flash Page Select Register identi- fies the page to be erased. Only a page residing in an unprotected sector can be erased. With the Flash Controller unlocked and the active page set, writing the value 95h to the Flash Control Register initiates the Page Erase operation. While the Flash Controller exe- cutes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. If the Page Erase operation is performed using the On-Chip Debug- ger, poll the Flash Status Register to determine when the Page Erase operation is complete. When the Page Erase is complete, the Flash Controller returns to its locked state. Mass Erase The Flash memory can also be Mass Erased using the Flash Controller, but only by using the On-Chip Debugger. Mass Erasing the Flash memory sets all bytes to the value FFH. With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the value 63H to the Flash Control Register initiates the Mass Erase operation. While the Flash Controller executes the Mass Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Status Register to determine when the Mass Erase operation is complete. When the Mass Erase is complete, the Flash Controller returns to its locked state. Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Program- ming algorithms by controlling the Flash programming signals directly. Row programming is recommended for gang programming applications and large volume customers who do not require in-circuit initial programming of the Flash memory. Page Erase operations are also supported when the Flash Controller is bypassed. For more information about bypassing the Flash Controller, refer to the Third-Party Flash Programming Support for Z8 Encore! MCUs Application Note (AN0117), which is avail- able for download on www.zilog.com. Caution:

PS022827-1212 P R E L I M I N A R Y Flash Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 153 Flash Controller Behavior in DEBUG Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger:

The Flash Write Protect option bit is ignored.
The Flash Sector Protect Register is ignored for programming and erase operations.
Programming operations are not limited to the page selected in the Page Select Register.
Bits in the Flash Sector Protect Register can be written to one or zero.
The second write of the Page Select Register to unlock the Flash Controller is not necessary.
The Page Select Register can be written when the Flash Controller is unlocked.
The Mass Erase command is enabled through the Flash Control Register. For security reasons, the Flash controller allows only a single page to be opened for write/ erase. When writing multiple Flash pages, the flash controller must go through the unlock sequence again to select another page. Flash Control Register Definitions This section defines the features of the following Flash Control registers. Flash Control Register: see page 153 Flash Status Register: see page 155 Flash Page Select Register: see page 156 Flash Sector Protect Register: see page 157 Flash Frequency High and Low Byte Registers: see page 157 Flash Control Register The Flash Controller must be unlocked using the Flash Control (FCTL) Register before programming or erasing the Flash memory. Writing the sequence 73H 8CH, sequentially, to the Flash Control Register unlocks the Flash Controller. When the Flash Controller is unlocked, the Flash memory can be enabled for Mass Erase or Page Erase by writing the appropriate enable command to the FCTL. Page Erase applies only to the active page selected in Flash Page Select Register. Mass Erase is enabled only through the On-Chip Caution:

PS022827-1212 P R E L I M I N A R Y Flash Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 154 Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state. The Write-only Flash Control Register shares its Register File address with the read-only Flash Status Register.

File address with the Write-only Flash Control Register. Table 80. Flash Control Register (FCTL) 8CH = Second unlock command. 95H = Page Erase command (must be third command in sequence to initiate Page Erase). 63H = Mass Erase command (must be third command in sequence to initiate Mass Erase). Table 81. Flash Status Register (FSTAT) [7:6] These bits are reserved and must be programmed to 00. 000011 = Flash Controller unlocked. 000100 = Sector protect register selected. 001xxx = Program operation in progress. 010xxx = Page erase operation in progress. 100xxx = Mass erase operation in progress.

address target the Flash Page Select Register. FPS[6:0] are chosen for program/erase operation. Table 82. Flash Page Select Register (FPS) 0 = Information Area us not selected. address space at addresses FE00H through FFFFH. Memory Address[15:9] = PAGE[6:0]. For the Z8F08xx devices, the upper 3 bits must be zero. must always be 0. For the Z8F01xx devices, the upper 6 bits must always be 0.

The Flash Sector Protect (FPROT) Register is shared with the Flash Page Select Register. without powering down the device. form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. Table 83. Flash Sector Protect Register (FPROT) on page 146 and to Figure 21, which follows the table.

For Z8F08xA and Z8F04xA devices, all bits are used.
For Z8F02xA devices, the upper 4 bits are unused.
For Z8F01xA devices, the upper 6 bits are unused. FFREQ[15:0] FFREQH[ 7:0],FFREQL[7:0] System Clock Frequency

ported for system clock frequencies below 20 kHz or above 20 MHz. Table 84. Flash Frequency High Byte Register (FFREQH) High byte of the 16-bit Flash Frequency value. Table 85. Flash Frequency Low Byte Register (FFREQL) Low byte of the 16-bit Flash Frequency value.

PS022827-1212 P R E L I M I N A R Y Flash Option Bits Z8 Encore! XP® F082A Series Product Specification 159 Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore! XP F082A Series operation. The feature configuration data is stored in Flash program memory and loaded into holding registers during Reset. The features available for control through the Flash option bits include:

Watchdog Timer time-out response selection–interrupt or system reset
Watchdog Timer always on (enabled at Reset)
The ability to prevent unwanted read access to user code in Program Memory
The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory
V oltage Brown-Out configuration-always enabled or disabled during STOP Mode to reduce STOP Mode power consumption
Oscillator mode selection-for high, medium and low power crystal oscillators, or exter- nal RC oscillator
Factory trimming information for the internal precision oscillator and low voltage de- tection
Factory calibration values for ADC, temperature sensor and Watchdog Timer compen- sation
Factory serialization and randomized lot identifier (optional) Operation This section describes the type and configuration of the programmable Flash option bits. Option Bit Configuration By Reset Each time the Flash option bits are programmed or erased, the device must be Reset for the change to take effect. During any reset operation (System Reset, Power-On Reset, or Stop Mode Recovery), the Flash option bits are automatically read from Flash program memory and written to the Option Configuration registers. The Option Configuration reg- isters control the operation of the devices within the Z8 Encore! XP F082A Series. Option bit control is established before the device exits Reset and the eZ8 CPU begins code exe- cution. The Option Configuration registers are not part of the Register File and are not accessible for read or write access.

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 160 Option Bit Types This section describes the five types of Flash option bits. User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits has been provided because these locations contain application-specific device configurations. The information contained here is lost when page 0 of the program mem- ory is erased. Trim Option Bits The trim option bits are contained in the information page of the Flash memory. These bits are factory programmed values required to optimize the operation of onboard analog cir- cuitry and cannot be permanently altered. Program Memory may be erased without endan- gering these values. It is possible to alter working values of these bits by accessing the Trim Bit Address and Data registers, but these working values are lost after a power loss or any other reset event. There are 32 bytes of trim data. To modify one of these values the user code must first write a value between 00H and 1FH into the Trim Bit Address Register. The next write to the Trim Bit Data Register changes the working value of the target trim data byte. Reading the trim data requires the user code to write a value between 00H and 1FH into the Trim Bit Address Register. The next read from the Trim Bit Data Register returns the working value of the target trim data byte. The trim address range is from information address 20–3F only. The remainder of the information page is not accessible through the trim bit address and data registers. Calibration Option Bits The calibration option bits are also contained in the information page. These bits are fac- tory-programmed values intended for use in software correcting the device’s analog per- formance. To read these values, the user code must employ the LDC instruction to access the information area of the address space as defined in See the Flash Information Area sec- tion on page 17. Serialization Bits As an optional feature, Zilog is able to provide factory-programmed serialization. For seri- alized products, the individual devices are programmed with unique serial numbers. These serial numbers are binary values, four bytes in length. The numbers increase in size with each device, but gaps in the serial sequence may exist. Note:

below and the Serialization Data section on page 173 for more details. tion lot and is not likely to be repeated. The following code example shows how to read data from the Flash information area. This section briefly describes the features of the Trim Bit Address and Data registers. trim option bits (Table 86). Table 86. Trim Bit Address Register (TRMADR)

trim option bits (Table 87). for the user-programmable Flash option bits. Table 87. Trim Bit Data Register (TRMDR) Table 88. Flash Option Bits at Program Memory Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write. enabled for the eZ8 CPU to acknowledge the interrupt request. dog Timer can not be disabled. setting is the default for unprogrammed (erased) Flash.

PS022827-1212 P R E L I M I N A R Y Flash Option Bit Address Space Z8 Encore! XP® F082A Series Product Specification 163 [5:4] OSC_SEL[1:0] Oscillator Mode Selection 00 = On-chip oscillator configured for use with external RC networks (<4 MHz). 01 = Minimum power for use with very low frequency crystals (32 kHz to 1.0 MHz). 10 = Medium power for use with medium frequency crystals or ceramic resonators (0.5 MHz to 5.0 MHz). 11 = Maximum power for use with high frequency crystals (5.0 MHz to 20.0 MHz). This setting is the default for unprogrammed (erased) Flash. [3] VBO_AO Voltage Brown-Out Protection Always On 0 = Voltage Brown-Out Protection can be disabled in STOP Mode to reduce total power consumption. For the block to be disabled, the power control register bit must also be written (see the Power Control Register Definitions section on page 33). 1 = Voltage Brown-Out Protection is always enabled including during STOP Mode. This setting is the default for unprogrammed (erased) Flash. [2] FRP Flash Read Protect 0 = User program code is inaccessible. Limited control features are available through the On-Chip Debugger. 1 = User program code is accessible. All On-Chip Debugger commands are enabled. This setting is the default for unprogrammed (erased) Flash. [1] Reserved This bit is reserved and must be programmed to 1. [0] FWP Flash Write Protect This Option Bit provides Flash Program Memory protection: 0 = Programming and erasure disabled for all of Flash Program Memory. Programming, Page Erase and Mass Erase through User Code is disabled. Mass Erase is available using the On-Chip Debugger. 1 = Programming, Page Erase and Mass Erase are enabled for all of Flash program memory. Bit Description (Continued)

Table 89. Flash Options Bits at Program Memory Address 0001H Note: U = Unchanged by Reset. R/W = Read/Write. These bits are reserved and must be programmed to 111. 0 = Crystal oscillator is enabled during reset, resulting in longer reset timing. debugging or Flash programming is not required. These bits are reserved and must be programmed to 1111.

Table 90. Trim Options Bits at Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write. These bits are reserved; altering this register may result in incorrect device operation. Table 91. Trim Option Bits at 0001H Note: U = Unchanged by Reset. R/W = Read/Write. These bits are reserved; altering this register may result in incorrect device operation.

The LVD is available on 8-pin devices only. Table 92. Trim Option Bits at 0002H (TIPO) Note: U = Unchanged by Reset. R/W = Read/Write. Contains trimming bits for the Internal Precision Oscillator. Table 93. Trim Option Bits at Address 0003H (TLVD) Note: U = Unchanged by Reset. R/W = Read/Write. These bits are reserved and must be programmed to 111. These values are tabulated in Table 94.

Table 94. LVD Trim Values

1.65 Minimum LVD threshold

Table 95. Trim Option Bits at 0004H Note: U = Unchanged by Reset. R/W = Read/Write. These bits are reserved; altering this register may result in incorrect device operation.

Table 96. ADC Calibration Bits Note: U = Unchanged by Reset. R/W = Read/Write. The location of each calibration byte is provided in Table 97. Table 97. ADC Calibration Data Location

Table 97. ADC Calibration Data Location (Continued)

Table 98. Temperature Sensor Calibration High Byte at 003A (TSCALH) Note: U = Unchanged by Reset. R/W = Read/Write. tion value. For more details, see Temperature Sensor Operation on page 139. Table 99. Temperature Sensor Calibration Low Byte at 003B (TSCALL) Note: U = Unchanged by Reset. R/W = Read/Write. tion value. For usage details, see the Temperature Sensor Operation section on page 144.

Table 100. Watchdog Calibration High Byte at 007EH (WDTCALH) Note: U = Unchanged by Reset. R/W = Read/Write.

Table 101. Watchdog Calibration Low Byte at 007FH (WDTCALL) Note: U = Unchanged by Reset. R/W = Read/Write. Table 102. Serial Number at 001C - 001F (S_NUM) Note: U = Unchanged by Reset. R/W = Read/Write. The serial number is a unique four-byte binary value. See Table 103. Table 103. Serialization Data Locations 1C FE1C Serial Number Byte 3 (most significant). 1D FE1D Serial Number Byte 2. 1E FE1E Serial Number Byte 1. 1F FE1F Serial Number Byte 0 (least significant).

Table 104. Lot Identification Number (RAND_LOT) Note: U = Unchanged by Reset. R/W = Read/Write. Table 105. Randomized Lot ID Locations 3C FE3C Randomized Lot ID Byte 31 (most significant). 3D FE3D Randomized Lot ID Byte 30. 3E FE3E Randomized Lot ID Byte 29. 3F FE3F Randomized Lot ID Byte 28. 58 FE58 Randomized Lot ID Byte 27. 59 FE59 Randomized Lot ID Byte 26. 5A FE5A Randomized Lot ID Byte 25. 5B FE5B Randomized Lot ID Byte 24. 5C FE5C Randomized Lot ID Byte 23. 5D FE5D Randomized Lot ID Byte 22. 5E FE5E Randomized Lot ID Byte 21. 5F FE5F Randomized Lot ID Byte 20. 61 FE61 Randomized Lot ID Byte 19. 62 FE62 Randomized Lot ID Byte 18. 64 FE64 Randomized Lot ID Byte 17. 65 FE65 Randomized Lot ID Byte 16. 67 FE67 Randomized Lot ID Byte 15. 68 FE68 Randomized Lot ID Byte 14.

6A FE6A Randomized Lot ID Byte 13. 6B FE6B Randomized Lot ID Byte 12. 6D FE6D Randomized Lot ID Byte 11. 6E FE6E Randomized Lot ID Byte 10. 70 FE70 Randomized Lot ID Byte 9. 71 FE71 Randomized Lot ID Byte 8. 73 FE73 Randomized Lot ID Byte 7. 74 FE74 Randomized Lot ID Byte 6. 76 FE76 Randomized Lot ID Byte 5. 77 FE77 Randomized Lot ID Byte 4. 79 FE79 Randomized Lot ID Byte 3. 7A FE7A Randomized Lot ID Byte 2. 7C FE7C Randomized Lot ID Byte 1. 7D FE7D Randomized Lot ID Byte 0 (least significant). Table 105. Randomized Lot ID Locations (Continued)

PS022827-1212 P R E L I M I N A R Y Nonvolatile Data Storage Z8 Encore! XP® F082A Series Product Specification 176 Nonvolatile Data Storage The Z8 Encore! XP F082A Series devices contain a nonvolatile data storage (NVDS) ele- ment of up to 128 bytes. This memory can perform over 100,000 write cycles. Operation The NVDS is implemented by special purpose Zilog software stored in areas of program memory, which are not user-accessible. These special-purpose routines use the Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maxi- mize the write/erase endurance of the Flash. Different members of the Z8 Encore! XP F082A Series feature multiple NVDS array sizes; see the Part Selection Guide section on page 2 for details. Devices containing 8 KB of Flash memory do not include the NVDS feature. NVDS Code Interface Two routines are required to access the NVDS: a write routine and a read routine. Both of these routines are accessed with a CALL instruction to a predefined address outside of the user-accessible program memory. Both the NVDS address and data are single-byte values. Because these routines disturb the working register set, user code must ensure that any required working register values are preserved by pushing them onto the stack or by changing the working register pointer just prior to NVDS execution. During both read and write accesses to the NVDS, interrupt service is NOT disabled. Any interrupts that occur during the NVDS execution must take care not to disturb the working register and existing stack contents or else the array may become corrupted. Disabling interrupts before executing NVDS operations is recommended. Use of the NVDS requires 15 bytes of available stack space. Also, the contents of the working register set are overwritten. For correct NVDS operation, the Flash Frequency registers must be programmed based on the system clock frequency (see the Flash Operation Timing Using the Flash Frequency Registers section on page 149). Note:

code must pop the address and data bytes off the stack. data pushed by the user. Sufficient memory must be available for this stack usage. effect. Illegal write operations have a 2 µs execution time. Table 106. Write Status Byte These bits are reserved and must be programmed to 0000. An address byte failure occurred during the most recent attempted write to the NVDS array. A data byte failure occurred during the most recent attempted write to the NVDS array.

PS022827-1212 P R E L I M I N A R Y NVDS Code Interface Z8 Encore! XP® F082A Series Product Specification 178 Byte Read To read a byte from the NVDS array, user code must first push the address onto the stack. User code issues a CALL instruction to the address of the byte-read routine (0x1000). At the return from the sub-routine, the read byte resides in working register R0 and the read status byte resides in working register R1. The contents of the status byte are undefined for read operations to illegal addresses. Also, the user code must pop the address byte off the stack. The read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user. Sufficient memory must be available for this stack usage. Because of the Flash memory architecture, NVDS reads exhibit a nonuniform execution time. A read operation takes between 44 s and 489 s (assuming a 20 MHz system clock). Slower system clock speeds result in proportionally higher execution times. NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return 0xff. Illegal read operations have a 2 s execution time. The status byte returned by the NVDS read routine is zero for successful read, as deter- mined by a CRC check. If the status byte is nonzero, there was a corrupted value in the NVDS array at the location being read. In this case, the value returned in R0 is the byte most recently written to the array that does not have a CRC error. Power Failure Protection The NVDS routines employ error checking mechanisms to ensure a power failure endan- gers only the most recently written byte. Bytes previously written to the array are not per- turbed. A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write operation also perturbs the byte currently being written. All other bytes in the array are unperturbed. Optimizing NVDS Memory Usage for Execution Speed NVDS read time can vary drastically. This discrepancy is a trade-off for minimizing the frequency of writes that require post-write page erases, as indicated in Table 107. The NVDS read time of address N is a function of the number of writes to addresses other than N since the most recent write to address N, plus the number of writes since the most recent page erase. Neglecting effects caused by page erases and results caused by the initial con- dition in which the NVDS is blank, a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 s up to a max- imum of (511-NVDS_SIZE) s.

code for speed. Try the first suggestion below before attempting the second.

Periodically refresh all addresses that are used. The optimal use of NVDS in terms of

than the write time, however, actual speed benefits are not always realized.

Use as few unique addresses as possible to optimize the impact of refreshing, plus

minimize the requirement for it. Table 107. NVDS Read Time

Single pin interface
Reading and writing of the register file
Reading and writing of program and data memory
Setting of breakpoints and watchpoints
Executing eZ8 CPU instructions
Debug pin sharing with general-purpose input-output function to maximize pins avail- able to the user (8-pin product only) Architecture The on-chip debugger consists of four primary functional blocks: transmitter, receiver, auto-baud detector/generator and debug controller. Figure 23 displays the architecture of the on-chip debugger.

Figure 23. On-Chip Debugger Block Diagram

This section describes the interface and modes of operation of the On-Chip Debugger. one-pin interface is a bidirectional, open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. Figure 25. The DBG pin has a internal pull-up resistor which is sufficient for some appli- pull-up resistor is recommended. pin is open-drain and may require an external pull-up resistor to ensure proper operation. Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface; #1 of 2

10 KOhmSchottky

The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex- ecute specific instructions
The system clock operates unless in STOP Mode
All enabled on-chip peripherals operate unless in STOP Mode
Automatically exits HALT Mode
Constantly refreshes the Watchdog Timer, if enabled Entering DEBUG Mode The operating characteristics of the devices entering DEBUG Mode are:
The device enters DEBUG Mode after the eZ8 CPU executes a BRK (Breakpoint) in- struction
If the DBG pin is held Low during the final clock cycle of system reset, the part enters DEBUG Mode immediately (20-/28-pin products only) Holding the DBG pin Low for an additional 5000 (minimum) clock cycles after reset (making sure to account for any specified frequency error if using an internal oscillator) prevents a false interpretation of an Autobaud sequence (see the OCD Auto-Baud Detector/Generator section on page 183).

Figure 25. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface; #2 of 2

If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/ DBG pin, the DBG feature is unlocked. After releasing PA2/RESET, it is pulled High. At this point, the PA0/DBG pin may be used to autobaud and cause the device to enter DEBUG Mode. See the OCD Unlock Sequence (8-Pin Devices Only) section on page 185. Exiting DEBUG Mode The device exits DEBUG Mode following any of these operations:
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-On Reset
V oltage Brown-Out reset
Watchdog Timer reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in STOP Mode initiates a System Reset OCD Data Format The OCD interface uses the asynchronous data format defined for RS-232. Each character transmitted and received by the OCD consists of 1 Start bit, 8 data bits (least-significant bit first) and 1 Stop bit as displayed in Figure 26. When responding to a request for data, the OCD may commence transmitting immediately after receiving the stop bit of an incoming frame. Therefore, when sending the stop bit, the host must not actively drive the DBG pin High for more than 0.5 bit times. Zilog recom- mends that, if possible, the host drives the DBG pin using an open drain output to avoid this issue. OCD Auto-Baud Detector/Generator To run over a range of baud rates (data bits per second) with various system clock frequen- cies, the On-Chip Debugger contains an Auto-Baud Detector/Generator. After a reset, the OCD is idle until it receives data. The OCD requires that the first character sent from the

Figure 26. OCD Data Format

and sets the OCD Baud Rate Generator accordingly. baud rates for sample crystal frequencies.

Serial Break (a minimum of nine continuous bits Low)
Framing Error (received Stop bit is Low)
Transmit Collision (OCD and host simultaneous transmission detected by the OCD) When the OCD detects one of these errors, it aborts any command currently in progress, transmits a four character long Serial Break back to the host and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the interface, returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host transmits a Serial Break on the DBG pin when first connecting to the Z8 Encore! XP F082A Series devices or when recovering from an error. A Serial Break from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Control Register. A

Table 108. OCD Baud-Rate Limits

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 185 Serial Break leaves the device in DEBUG Mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character. OCD Unlock Sequence (8-Pin Devices Only) Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the DBG pin. If this sequence is not completed during a system reset, then the PA0/ DBG pin functions only as a GPIO pin. The following sequence unlocks the DBG pin: 1. Hold PA2/RESET Low. 2. Wait 5ms for the internal reset sequence to complete. 3. Send the following bytes serially to the debug pin: DBG ← 80H (autobaud) DBG ← EBH DBG ←5AH DBG ←70H DBG ←CDH (32-bit unlock key) 4. Release PA2/RESET . The PA0/DBG pin is now identical in function to that of the DBG pin on the 20-/28-pin device. To enter DEBUG Mode, reautobaud and write 80H to the OCD Control Register (see the On-Chip Debugger Commands section on page 186). Between Steps 3 and 4, there is an interval during which the 8-pin device is neither in RE- SET nor DEBUG Mode. If a device has been erased or has not yet been programmed, all program memory bytes contain FFH. The CPU interprets this value as an illegal instruc- tion; therefore some irregular behavior can occur before entering DEBUG Mode, and the register values after entering DEBUG Mode will differ from their specified reset values. However, none of these irregularities prevent the programming of Flash memory. Before beginning system debug, Zilog recommends that some legal code be programmed into the 8-pin device and that a RESET occurs. Breakpoints Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are enabled, the OCD enters DEBUG Mode and idles the eZ8 CPU. If Breakpoints are not Caution:

page of Flash memory must be erased and reprogrammed with the original data. control registers are protected by programming the Flash Read Protect Option bit (FRP). commands are disabled. See Table 109. Table 109. Debug Command Enable/Disable Write OCD Control Register 04H Yes Cannot clear DBGMODE bit.

Chip Debugger back to the host is identified by DBG → Data. Write Program Counter 06H – Disabled. Read Program Counter 07H – Disabled. be written to the Flash Control Register. Read Register 09H – Disabled. Write Program Memory 0AH – Disabled. Read Program Memory 0BH – Disabled. Write Data Memory 0CH – Yes. Step Instruction 10H – Disabled. Stuff Instruction 11H – Disabled. Execute Instruction 12H – Disabled. Table 109. Debug Command Enable/Disable (Continued)

PS022827-1212 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F082A Series Product Specification 188 Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction, Stuff Instruction and Execute Instruction commands. DBG ← 03H DBG → RuntimeCounter[15:8] DBG → RuntimeCounter[7:0] Write OCD Control Register (04H). The Write OCD Control Register command writes the data that follows to the OCDCTL Register. When the Flash Read Protect Option Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device. DBG ← 04H DBG ← OCDCTL[7:0] Read OCD Control Register (05H). The Read OCD Control Register command reads the value of the OCDCTL Register. DBG ← 05H DBG → OCDCTL[7:0] Write Program Counter (06H). The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, the Program Counter (PC) values are discarded. DBG ← 06H DBG ← ProgramCounter[15:8] DBG ← ProgramCounter[7:0] Read Program Counter (07H). The Read Program Counter command reads the value in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, this command returns FFFFH. DBG ← 07H DBG → ProgramCounter[15:8] DBG → ProgramCounter[7:0] Write Register (08H). The Write Register command writes data to the Register File. Data can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If the device is not in DEBUG Mode, the address and data values are discarded. If the Flash Read Protect Option bit is enabled, only writes to the Flash Control registers are allowed and all other register write data values are discarded. DBG ← 08H DBG ← {4’h0,Register Address[11:8]} DBG ← Register Address[7:0] DBG ← Size[7:0] DBG ← 1-256 data bytes

PS022827-1212 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F082A Series Product Specification 189 Read Register (09H). The Read Register command reads data from the Register File. Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, this com- mand returns FFH for all the data values. DBG ← 09H DBG ← {4’h0,Register Address[11:8] DBG ← Register Address[7:0] DBG ← Size[7:0] DBG → 1-256 data bytes Write Program Memory (0AH). The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). The on-chip Flash Controller must be written to and unlocked for the programming opera- tion to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, the data is dis- carded. DBG ← 0AH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes Read Program Memory (0BH). The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, this com- mand returns FFH for the data. DBG ← 0BH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes Write Data Memory (0CH). The Write Data Memory command writes data to Data Mem- ory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, the data is dis- carded. DBG ← 0CH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0]

PS022827-1212 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F082A Series Product Specification 190 DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1-65536 data bytes Read Data Memory (0DH). The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG Mode, this command returns FFH for the data. DBG ← 0DH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1-65536 data bytes Read Program Memory CRC (0EH). The Read Program Memory CRC command com- putes and returns the Cyclic Redundancy Check (CRC) of Program Memory using the 16- bit CRC-CCITT polynomial. If the device is not in DEBUG Mode, this command returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory. DBG ← 0EH DBG → CRC[15:8] DBG → CRC[7:0] Step Instruction (10H). The Step Instruction command steps one assembly instruction at the current Program Counter (PC) location. If the device is not in DEBUG Mode or the Flash Read Protect Option bit is enabled, the OCD ignores this command. DBG ← 10H Stuff Instruction (11H). The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint. If the device is not in DEBUG Mode or the Flash Read Protect Option bit is enabled, the OCD ignores this command. DBG ← 11H DBG ← opcode[7:0] Execute Instruction (12H). The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over Breakpoints. The number of bytes to send for the instruction depends on the opcode. If the device is not

This section describes the features of the On-Chip Debugger Control and Status registers. Z8 Encore! XP F082A Series device. a run function can be implemented by writing 40H to this register. Table 110. OCD Control Register (OCDCTL) device. It cannot be written to 0. 0 = The Z8 Encore! XP F082A Series device is operating in NORMAL Mode. 1 = The Z8 Encore! XP F082A Series device is in DEBUG Mode. 0 = Breakpoints are disabled. 1 = Breakpoints are enabled.

Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. These bits are reserved and must be programmed to 0000. bit is automatically cleared to 0 at the end of reset. 1 = Reset the Flash Read Protect Option Bit device. Table 111. OCD Status Register (OCDSTAT) 0 = FRP bit enabled, that allows disabling of many OCD commands. These bits are reserved and must be programmed to 00000.

PS022827-1212 P R E L I M I NA R Y Oscillator Control Z8 Encore! XP® F082A Series Product Specification 193 Oscillator Control The Z8 Encore! XP F082A Series devices uses five possible clocking schemes, each user- selectable:

Internal precision trimmed RC oscillator (IPO)
On-chip oscillator using off-chip crystal or resonator
On-chip oscillator using external RC network
External clock drive
On-chip low power Watchdog Timer oscillator
Clock failure detection circuitry In addition, Z8 Encore! XP F082A Series devices contain clock failure detection and recovery circuitry, allowing continued operation despite a failure of the system clock oscillator. Operation This chapter discusses the logic used to select the system clock and handle primary oscil- lator failures. System Clock Selection The oscillator control block selects from the available clocks. Table 112 details each clock source and its usage.

block employs a register unlocking/locking scheme. write to or read from other registers within the unlocking/locking operation. Table 112. Oscillator Configuration and Selection

32.8 kHz or 5.53 MHz
High accuracy
No external components required
Unlock and write Oscillator Control Register (OSCCTL) to enable and select oscillator at either 5.53 MHz or 32.8 kHz External Crystal/ Resonator
32 kHz to 20 MHz
Very high accuracy (dependent on crystal or resonator used)
Requires external components
Configure Flash option bits for correct external oscillator mode
Unlock and write OSCCTL to enable crystal oscillator, wait for it to stabilize and select as system clock (if the XTLDIS option bit has been deas- serted, no waiting is required) External RC Oscilla- tor
32 kHz to 4 MHz
Accuracy dependent on external com- ponents
Configure Flash option bits for correct external oscillator mode
Unlock and write OSCCTL to enable crystal oscillator and select as system clock External Clock Drive
0 to 20 MHz
Accuracy dependent on external clock source
Write GPIO registers to configure PB3 pin for external clock function
Unlock and write OSCCTL to select external system clock
Apply external clock signal to GPIO Internal Watchdog Timer Oscillator
10 kHz nominal
Low accuracy; no external compo- nents required
Very low power consumption
Enable WDT if not enabled and wait until WDT Oscillator is operating
Unlock and write Oscillator Control Register (OSCCTL) to enable and select oscillator Caution:

PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 195 When selecting a new clock source, the system clock oscillator failure detection circuitry and the Watchdog Timer oscillator failure circuitry must be disabled. If SOFEN and WOFEN are not disabled prior to a clock switch-over, it is possible to generate an inter- rupt for a failure of either oscillator. The Failure detection circuitry can be enabled any- time after a successful write of OSCSEL in the OSCCTL Register. The internal precision oscillator is enabled by default. If the user code changes to a differ- ent oscillator, it may be appropriate to disable the IPO for power savings. Disabling the IPO does not occur automatically. Clock Failure Detection and Recovery Should an oscillator or timer fail, there are methods of recovery, as this section describes. System Clock Oscillator Failure The Z8F04xA family devices can generate nonmaskable interrupt-like events when the primary oscillator fails. To maintain system function in this situation, the clock failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the system clock. The Watchdog Timer oscillator must be enabled to allow the recovery. Although this oscillator runs at a much slower speed than the original system clock, the CPU contin- ues to operate, allowing execution of a clock failure vector and software routines that either remedy the oscillator failure or issue a failure alert. This automatic switch-over is not available if the Watchdog Timer is selected as the system clock oscillator. It is also unavailable if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the Watchdog Timer reset function (see the Watchdog Timer chapter on page 93). The primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is pos- sible that a very slow but nonfailing clock can generate a failure condition. Under these conditions, do not enable the clock failure circuitry (SOFEN must be deasserted in the OSCCTL Register). Watchdog Timer Failure In the event of a Watchdog Timer oscillator failure, a similar nonmaskable interrupt-like event is issued. This event does not trigger an attendant clock switch-over, but alerts the CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a pri- mary oscillator failure. The failure detection circuitry does not function if the Watchdog Timer is used as the system clock oscillator or if the Watchdog Timer oscillator has been disabled. For either of these cases, it is necessary to disable the detection circuitry by deas- serting the WDFEN bit of the OSCCTL Register. The Watchdog Timer oscillator failure detection circuit counts system clocks while look- ing for a Watchdog Timer clock. The logic counts 8004 system clock cycles before deter- mining that a failure has occurred. The system clock rate determines the speed at which

only be recovered by Power-On-Reset. which becomes the system clock. locked at successful completion of a register write to the OSCCTL. Table 113. Oscillator Control Register (OSCCTL) 1 = Internal precision oscillator is enabled. 0 = Internal precision oscillator is disabled. 1 = Crystal oscillator is enabled. 0 = Crystal oscillator is disabled. 1 = Watchdog Timer oscillator is enabled. 0 = Watchdog Timer oscillator is disabled. 1 = Failure detection and recovery of system clock oscillator is enabled. 0 = Failure detection and recovery of system clock oscillator is disabled.

PS022827-1212 P R E L I M I N A R Y Oscillator Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 197 [3] WDFEN Watchdog Timer Oscillator Failure Detection Enable 1 = Failure detection of Watchdog Timer oscillator is enabled. 0 = Failure detection of Watchdog Timer oscillator is disabled. [2:0] SCKSEL System Clock Oscillator Select 000 = Internal precision oscillator functions as system clock at 5.53 MHz. 001 = Internal precision oscillator functions as system clock at 32 kHz. 010 = Crystal oscillator or external RC oscillator functions as system clock. 011 = Watchdog Timer oscillator functions as system. 100 = External clock signal on PB3 functions as system clock. 101 = Reserved. 110 = Reserved. 111 = Reserved. Bit Description (Continued)

PS022827-1212 P R E L I M I N A R Y Crystal Oscillator Z8 Encore! XP® F082A Series Product Specification 198 Crystal Oscillator The products in the Z8 Encore! XP F082A Series contain an on-chip crystal oscillator for use with external crystals with 32 kHz to 20 MHz frequencies. In addition, the oscillator supports external RC networks with oscillation frequencies up to 4 MHz or ceramic reso- nators with frequencies up to 8 MHz. The on-chip crystal oscillator can be used to generate the primary system clock for the internal eZ8 CPU and the majority of the on-chip periph- erals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32 kHz–20 MHz). If an external clock generator is used, the XOUT pin must be left uncon- nected. The Z8 Encore! XP F082A Series products do not contain an internal clock divider. The frequency of the signal on the X IN input pin determines the frequency of the system clock. Although the XIN pin can be used as an input for an external clock generator, the CLKIN pin is better suited for such use (see the System Clock Selection section on page 193). Operating Modes The Z8 Encore! XP F082A Series products support four oscillator modes:

Minimum power for use with very low frequency crystals (32 kHz – 1 MHz)
Medium power for use with medium frequency crystals or ceramic resonators (0.5 MHz to 8 MHz)
Maximum power for use with high frequency crystals (8 MHz to 20 MHz)
On-chip oscillator configured for use with external RC networks (<4 MHz) The oscillator mode is selected via user-programmable Flash option bits. See the Flash Option Bits chapter on page 159 for information. Crystal Oscillator Operation The XTLDIS Flash option bit controls whether the crystal oscillator is enabled during reset. The crystal may later be disabled after reset if a new oscillator has been selected as the system clock. If the crystal is manually enabled after reset through the OSCCTL Reg- ister, the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabi- lize. After this, the crystal oscillator may be selected as the system clock. Note:

Table 114. Recommended Crystal Oscillator Specifications Table 115. Transconductance Values for Low, Medium and High Gain Operating Modes Note: *Printed circuit board layouts must not add more than 4 pF of stray capacitance to either the XIN or XOUT pins. if no oscillation occurs, reduce the values of the capacitors C1 and C2 to decrease the loading.

circuit board must be included in the estimation of the oscillator frequency. capacitance values in excess of 20 pF are recommended. Figure 28. Connecting the On-Chip Oscillator to an External RC Network

Out threshold. The oscillator resumes oscillation when the supply voltage exceeds 2.7 V . Figure 29. Typical RC Oscillator Frequency as a Function of the External Capacitance

PS022827-1212 P R E L I M I N A R Y Internal Precision Oscillator Z8 Encore! XP® F082A Series Product Specification 203 Internal Precision Oscillator The internal precision oscillator (IPO) is designed for use without external components. You can either manually trim the oscillator for a nonstandard frequency or use the auto- matic factory-trimmed version to achieve a 5.53 MHz frequency. IPO features include:

On-chip RC oscillator that does not require external components
Output frequency of either 5.53 MHz or 32.8 kHz (contains both a fast and a slow mode)
Trimmed through Flash option bits with user override
Elimination of crystals or ceramic resonators in applications where very high timing accuracy is not required Operation An 8-bit trimming register, incorporated into the design, compensates for absolute varia- tion of oscillator frequency. Once trimmed the oscillator frequency is stable and does not require subsequent calibration. Trimming is performed during manufacturing and is not necessary for you to repeat unless a frequency other than 5.53 MHz (fast mode) or 32.8 kHz (slow mode) is required. This trimming is done at +30ºC and a supply voltage of 3.3 V , so accuracy of this operating point is optimal. If not used, the IPO can be disabled by the Oscillator Control Register (see the Oscillator Control Register Definitions section on page 196). By default, the oscillator frequency is set by the factory trim value stored in the write-pro- tected Flash information page. However, the user code can override these trim values as described in the Trim Bit Address Space section on page 165. Select one of two frequencies for the oscillator (5.53 MHz and 32.8 kHz) using the OSC- SEL bits in the the Oscillator Control chapter on page 193.

PS022827-1212 P R E L I M I N A R Y eZ8 CPU Instruction Set Z8 Encore! XP® F082A Series Product Specification 204 eZ8 CPU Instruction Set This chapter describes the following features of the eZ8 CPU instruction set: Assembly Language Programming Introduction: see page 204 Assembly Language Syntax: see page 205 eZ8 CPU Instruction Notation: see page 206 eZ8 CPU Instruction Classes: see page 207 eZ8 CPU Instruction Summary: see page 212 Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called state- ments. Each statement can contain labels, operations, operands and comments. Labels can be assigned to a particular instruction step in a source program. The label iden- tifies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example.

if manual program coding is preferred or if you intend to implement your own assembler. JP START ; Everything after the semicolon is a comment. ; program where the START label occurs. LD 234H, #%01 ; Another Load (LD) instruction with two operands. Table 116. Assembly Language Syntax Example 1 Table 117. Assembly Language Syntax Example 2

XP Product Specification to determine the exact register file range available. Table 118. Notational Shorthand b Bit b b represents a value from 0 to 7 (000B to 111B). CPU Core User Manual (UM0128). IM Immediate data #Data Data is a number between 00H to FFH. Ir Indirect working register @Rn n = 0–15. Irr Indirect working register pair @RRp p = 0, 2, 4, 6, 8, 10, 12, or 14. r Working register Rn n = 0 – 15.

Instruction Set Description sections. Assignment of a value is indicated by an arrow, as shown in the following example. stored in the destination location.

Arithmetic
Bit Manipulation Vector Vector address Vector Vector represents a number in the range of 00H to FFH. X Indexed #Index The register or register pair to be indexed is off- set by the signed Index value (#Index) in a +127 to –128 range.

Table 119. Additional Symbols Table 118. Notational Shorthand (Continued)

Block Transfer
CPU Control
Load
Logical
Program Control
Rotate and Shift Tables 120 through 127 list the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category. Within these tables, the source operand is identified as src, the destination operand is dst and a condi- tion code is cc.

Table 120. Arithmetic Instructions

Table 121. Bit Manipulation Instructions Table 122. Block Transfer Instructions Table 123. CPU Control Instructions

Table 124. Load Instructions Table 125. Logical Instructions Table 123. CPU Control Instructions (Continued)

Table 126. Program Control Instructions Table 127. Rotate and Shift Instructions

required for the instruction execution. Table 128. eZ8 CPU Instruction Summary

Table 128. eZ8 CPU Instruction Summary (Continued)

A description of the opcode map data and the abbreviations are provided in Figure 30. Figure 30. Opcode Map Cell Description

Table 129. Opcode Map Abbreviations b Bit position. IRR Indirect register pair. cc Condition code. p Polarity (0 or 1). 8-bit signed index or displacement. r 4-bit working register. DA Destination address. R 8-bit register. Ir Indirect working register. RA Relative. IR Indirect register. rr Working register pair. Irr Indirect working register pair. RR Register pair.

Figure 31. First Opcode Map

Figure 32. Second Opcode Map after 1FH

Z8 Encore! XP® F082A Series Product Specification 226

Electrical Characteristics

The data in this chapter represents all known data prior to qualification and characteriza- tion of the F082A Series of products, and is therefore subject to change. Additional electri- cal characteristics may be found in the individual chapters of this document. Absolute Maximum Ratings Stresses greater than those listed in Table 130 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS). Table 130. Absolute Maximum Ratings

voltages are referenced to VSS, the primary system ground. Notes: Operating temper ature is specified in DC Characteristics.

This voltage applies to all pins except the following: V DD, AVDD, pins supporting analog input (Port B[5:0], Port
This voltage applies to pins on the 20-/28-pin packages supporting analog input (Port B[5:0], Port C[2:0]) and

pins supporting the crystal oscillator (PA0 and PA1). Table 131. DC Characteristics nal pins on the 8-pin devices.

This condition excludes all pins that have on-chip pull-ups, when driven Low.
These values are provided for design guid ance only and are not tested in production.

Table 130. Absolute Maximum Ratings (Continued)

Table 131. DC Characteristics (Continued)

This condition excludes all pins that have on-chip pull-ups, when driven Low.
These values are provided for design guid ance only and are not tested in production.

Table 132. Power Consumption For 8-pin devices; See Note 4.

Typical conditions are defined as V DD = 3.3 V and +30°C.
Standard temperature is defined as T A = 0°C to +70°C; these values not tested in production for worst case

behavior, but are derived from product characterization and provided for design guidance only.

Extended temperature is defined as T A = –40°C to +105°C; these values not tested in production for worst case

behavior, but are derived from product characterization and provided for design guidance only.

For this block to operate, the bandgap circuit is automa tically turned on and must be added to the total supply

current. This bandgap current is only added once, regardless of how many peripherals are using it.

3 5 5 µA Driving a high-impedance load. Table 132. Power Consumption (Continued)

Typical conditions are defined as V DD = 3.3 V and +30°C.
Standard temperature is defined as T A = 0°C to +70°C; these values not tested in production for worst case

behavior, but are derived from product characterization and provided for design guidance only.

Extended temperature is defined as T A = –40°C to +105°C; these values not tested in production for worst case

behavior, but are derived from product characterization and provided for design guidance only.

For this block to operate, the bandgap circuit is automa tically turned on and must be added to the total supply

current. This bandgap current is only added once, regardless of how many peripherals are using it.

information assumes a standard load of 50 pF on all outputs. Table 133. AC Characteristics Table 134. Internal Precision Oscillator Electrical Characteristics

5.53 MHz V

Table 135 tabulates the electrical characteristics of the POR and VBO blocks. Table 135. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing ance only and are not tested in production.

Table 136. Flash Memory Electrical Characteristics and Timing ance only and are not tested in production.

Table 137. Watchdog Timer Electrical Characteristics and Timing Table 138. Non-Volatile Data Storage

Table 139. Analog-to-Digital Converter Electrical Characteristics and Timing

850 W When the internal ref-

10258 Temperature sensor

Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
Devices are factory calibrated at V DD = 3.3 V and TA = +30°C, so the ADC is maximally accurate under these
LSBs are defined assuming 10-bit resolution.
This is the maximum recommended resistance seen by the ADC input pin.
The input impedance is inversely proportional to the system clock frequency.

512 Temperature sensor

20 MHz

Table 139. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)

Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
Devices are factory calibrated at V DD = 3.3 V and TA = +30°C, so the ADC is maximally accurate under these
LSBs are defined assuming 10-bit resolution.
This is the maximum recommended resistance seen by the ADC input pin.
The input impedance is inversely proportional to the system clock frequency.

Table 140. Low Power Operational Amplifier Electrical Characteristics VOUT Output Voltage Range 0.3 VDD–1 V I OUT = 45 µA. Table 141. Comparator Electrical Characteristics

Table 142. Temperature Sensor Electrical Characteristics near the new calibration point.

the eZ8 CPU on the second rising clock edge following the change of the Port value. Figure 34. Port Input Sample Timing Table 143. GPIO Port Input Timing

0 Latched

PS022827-1212 P R E L I M I N A R Y Packaging Z8 Encore! XP® F082A Series Product Specification 245 Packaging Zilog’s Product Line of MCUs includes the Z8F011A, Z8F012A, Z8F021A, Z8F022A, Z8F041A, Z8F042A, Z8F081A and Z8F082A devices, which are available in the follow- ing packages:

8-pin Plastic Dual-Inline Package (PDIP)
8-Pin Quad Flat No-Lead Package (QFN)/MLF-S1
8-pin Small Outline Integrated Circuit Package (SOIC)
20-pin Small Outline Integrated Circuit Package (SOIC)
20-pin Small Shrink Outline Package (SSOP)
20-pin Plastic Dual-Inline Package (PDIP)
28-pin Small Outline Integrated Circuit Package (SOIC)
28-pin Small Shrink Outline Package (SSOP)
28-pin Plastic Dual-Inline Package (PDIP) Current diagrams for each of these packages are published in Zilog’s Packaging Product Specification (PS0072), which is available free for download from the Zilog website. 1. The footprint of the QFN)/MLF-S packag e is identical to that of the 8-pin SOIC package, but with a lower profile.

Z8 Encore! XP® F082A Series Product Specification 246

Ordering Information

Order your F082A Series products from Zilog using the part numbers shown in Table 148. For more information about ordering, please consult your local Zilog sales office. The Sales Location page on the Zilog website lists all regional offices. Table 148. Z8 Encore! XP F082A Series Ordering Matrix Z8 Encore! XP F082A Series with 8 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F082APB020SG 8 KB 1 KB 0 6 14 2 4 1 1 1 PDIP 8-pin package Z8F082AQB020SG 8 KB 1 KB 0 6 14 2 4 1 1 1 QFN 8-pin package Z8F082ASB020SG 8 KB 1 KB 0 6 14 2 4 1 1 1 SOIC 8-pin package Z8F082ASH020SG 8 KB 1 KB 0 17 20 2 7 1 1 1 SOIC 20-pin package Z8F082AHH020SG 8 KB 1 KB 0 17 20 2 7 1 1 1 SSOP 20-pin package Z8F082APH020SG 8 KB 1 KB 0 17 20 2 7 1 1 1 PDIP 20-pin package Z8F082ASJ020SG 8 KB 1 KB 0 23 20 2 8 1 1 1 SOIC 28-pin package Z8F082AHJ020SG 8 KB 1 KB 0 23 20 2 8 1 1 1 SSOP 28-pin package Z8F082APJ020SG 8 KB 1 KB 0 23 20 2 8 1 1 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F082APB020EG 8 KB 1 KB 0 6 14 2 4 1 1 1 PDIP 8-pin package Z8F082AQB020EG 8 KB 1 KB 0 6 14 2 4 1 1 1 QFN 8-pin package Z8F082ASB020EG 8 KB 1 KB 0 6 14 2 4 1 1 1 SOIC 8-pin package Z8F082ASH020EG 8 KB 1 KB 0 17 20 2 7 1 1 1 SOIC 20-pin package Z8F082AHH020EG 8 KB 1 KB 0 17 20 2 7 1 1 1 SSOP 20-pin package Z8F082APH020EG 8 KB 1 KB 0 17 20 2 7 1 1 1 PDIP 20-pin package Z8F082ASJ020EG 8 KB 1 KB 0 23 20 2 8 1 1 1 SOIC 28-pin package Z8F082AHJ020EG 8 KB 1 KB 0 23 20 2 8 1 1 1 SSOP 28-pin package Z8F082APJ020EG 8 KB 1 KB 0 23 20 2 8 1 1 1 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 247 Z8 Encore! XP F082A Series with 8 KB Flash Standard Temperature: 0°C to 70°C Z8F081APB020SG 8 KB 1 KB 0 6 13 2 0 1 1 0 PDIP 8-pin package Z8F081AQB020SG 8 KB 1 KB 0 6 13 2 0 1 1 0 QFN 8-pin package Z8F081ASB020SG 8 KB 1 KB 0 6 13 2 0 1 1 0 SOIC 8-pin package Z8F081ASH020SG 8 KB 1 KB 0 17 19 2 0 1 1 0 SOIC 20-pin package Z8F081AHH020SG 8 KB 1 KB 0 17 19 2 0 1 1 0 SSOP 20-pin package Z8F081APH020SG 8 KB 1 KB 0 17 19 2 0 1 1 0 PDIP 20-pin package Z8F081ASJ020SG 8 KB 1 KB 0 25 19 2 0 1 1 0 SOIC 28-pin package Z8F081AHJ020SG 8 KB 1 KB 0 25 19 2 0 1 1 0 SSOP 28-pin package Z8F081APJ020SG 8 KB 1 KB 0 25 19 2 0 1 1 0 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F081APB020EG 8 KB 1 KB 0 6 13 2 0 1 1 0 PDIP 8-pin package Z8F081AQB020EG 8 KB 1 KB 0 6 13 2 0 1 1 0 QFN 8-pin package Z8F081ASB020EG 8 KB 1 KB 0 6 13 2 0 1 1 0 SOIC 8-pin package Z8F081ASH020EG 8 KB 1 KB 0 17 19 2 0 1 1 0 SOIC 20-pin package Z8F081AHH020EG 8 KB 1 KB 0 17 19 2 0 1 1 0 SSOP 20-pin package Z8F081APH020EG 8 KB 1 KB 0 17 19 2 0 1 1 0 PDIP 20-pin package Z8F081ASJ020EG 8 KB 1 KB 0 25 19 2 0 1 1 0 SOIC 28-pin package Z8F081AHJ020EG 8 KB 1 KB 0 25 19 2 0 1 1 0 SSOP 28-pin package Z8F081APJ020EG 8 KB 1 KB 0 25 19 2 0 1 1 0 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 248 Z8 Encore! XP F082A Series with 4 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F042APB020SG 4 KB 1 KB 128 B 6 14 2 4 1 1 1 PDIP 8-pin package Z8F042AQB020SG 4 KB 1 KB 128 B 6 14 2 4 1 1 1 QFN 8-pin package Z8F042ASB020SG 4 KB 1 KB 128 B 6 14 2 4 1 1 1 SOIC 8-pin package Z8F042ASH020SG 4 KB 1 KB 128 B 17 20 2 7 1 1 1 SOIC 20-pin package Z8F042AHH020SG 4 KB 1 KB 128 B 17 20 2 7 1 1 1 SSOP 20-pin package Z8F042APH020SG 4 KB 1 KB 128 B 17 20 2 7 1 1 1 PDIP 20-pin package Z8F042ASJ020SG 4 KB 1 KB 128 B 23 20 2 8 1 1 1 SOIC 28-pin package Z8F042AHJ020SG 4 KB 1 KB 128 B 23 20 2 8 1 1 1 SSOP 28-pin package Z8F042APJ020SG 4 KB 1 KB 128 B 23 20 2 8 1 1 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F042APB020EG 4 KB 1 KB 128 B 6 14 2 4 1 1 1 PDIP 8-pin package Z8F042AQB020EG 4 KB 1 KB 128 B 6 14 2 4 1 1 1 QFN 8-pin package Z8F042ASB020EG 4 KB 1 KB 128 B 6 14 2 4 1 1 1 SOIC 8-pin package Z8F042ASH020EG 4 KB 1 KB 128 B 17 20 2 7 1 1 1 SOIC 20-pin package Z8F042AHH020EG 4 KB 1 KB 128 B 17 20 2 7 1 1 1 SSOP 20-pin package Z8F042APH020EG 4 KB 1 KB 128 B 17 20 2 7 1 1 1 PDIP 20-pin package Z8F042ASJ020EG 4 KB 1 KB 128 B 23 20 2 8 1 1 1 SOIC 28-pin package Z8F042AHJ020EG 4 KB 1 KB 128 B 23 20 2 8 1 1 1 SSOP 28-pin package Z8F042APJ020EG 4 KB 1 KB 128 B 23 20 2 8 1 1 1 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 249 Z8 Encore! XP F082A Series with 4 KB Flash Standard Temperature: 0°C to 70°C Z8F041APB020SG 4 KB 1 KB 128 B 6 13 2 0 1 1 0 PDIP 8-pin package Z8F041AQB020SG 4 KB 1 KB 128 B 6 13 2 0 1 1 0 QFN 8-pin package Z8F041ASB020SG 4 KB 1 KB 128 B 6 13 2 0 1 1 0 SOIC 8-pin package Z8F041ASH020SG 4 KB 1 KB 128 B 17 19 2 0 1 1 0 SOIC 20-pin package Z8F041AHH020SG 4 KB 1 KB 128 B 17 19 2 0 1 1 0 SSOP 20-pin package Z8F041APH020SG 4 KB 1 KB 128 B 17 19 2 0 1 1 0 PDIP 20-pin package Z8F041ASJ020SG 4 KB 1 KB 128 B 25 19 2 0 1 1 0 SOIC 28-pin package Z8F041AHJ020SG 4 KB 1 KB 128 B 25 19 2 0 1 1 0 SSOP 28-pin package Z8F041APJ020SG 4 KB 1 KB 128 B 25 19 2 0 1 1 0 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F041APB020EG 4 KB 1 KB 128 B 6 13 2 0 1 1 0 PDIP 8-pin package Z8F041AQB020EG 4 KB 1 KB 128 B 6 13 2 0 1 1 0 QFN 8-pin package Z8F041ASB020EG 4 KB 1 KB 128 B 6 13 2 0 1 1 0 SOIC 8-pin package Z8F041ASH020EG 4 KB 1 KB 128 B 17 19 2 0 1 1 0 SOIC 20-pin package Z8F041AHH020EG 4 KB 1 KB 128 B 17 19 2 0 1 1 0 SSOP 20-pin package Z8F041APH020EG 4 KB 1 KB 128 B 17 19 2 0 1 1 0 PDIP 20-pin package Z8F041ASJ020EG 4 KB 1 KB 128 B 25 19 2 0 1 1 0 SOIC 28-pin package Z8F041AHJ020EG 4 KB 1 KB 128 B 25 19 2 0 1 1 0 SSOP 28-pin package Z8F041APJ020EG 4 KB 1 KB 128 B 25 19 2 0 1 1 0 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 250 Z8 Encore! XP F082A Series with 2 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F022APB020SG 2 KB 512 B 64 B 6 14 2 4 1 1 1 PDIP 8-pin package Z8F022AQB020SG 2 KB 512 B 64 B 6 14 2 4 1 1 1 QFN 8-pin package Z8F022ASB020SG 2 KB 512 B 64 B 6 14 2 4 1 1 1 SOIC 8-pin package Z8F022ASH020SG 2 KB 512 B 64 B 17 20 2 7 1 1 1 SOIC 20-pin package Z8F022AHH020SG 2 KB 512 B 64 B 17 20 2 7 1 1 1 SSOP 20-pin package Z8F022APH020SG 2 KB 512 B 64 B 17 20 2 7 1 1 1 PDIP 20-pin package Z8F022ASJ020SG 2 KB 512 B 64 B 23 20 2 8 1 1 1 SOIC 28-pin package Z8F022AHJ020SG 2 KB 512 B 64 B 23 20 2 8 1 1 1 SSOP 28-pin package Z8F022APJ020SG 2 KB 512 B 64 B 23 20 2 8 1 1 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F022APB020EG 2 KB 512 B 64 B 6 14 2 4 1 1 1 PDIP 8-pin package Z8F022AQB020EG 2 KB 512 B 64 B 6 14 2 4 1 1 1 QFN 8-pin package Z8F022ASB020EG 2 KB 512 B 64 B 6 14 2 4 1 1 1 SOIC 8-pin package Z8F022ASH020EG 2 KB 512 B 64 B 17 20 2 7 1 1 1 SOIC 20-pin package Z8F022AHH020EG 2 KB 512 B 64 B 17 20 2 7 1 1 1 SSOP 20-pin package Z8F022APH020EG 2 KB 512 B 64 B 17 20 2 7 1 1 1 PDIP 20-pin package Z8F022ASJ020EG 2 KB 512 B 64 B 23 20 2 8 1 1 1 SOIC 28-pin package Z8F022AHJ020EG 2 KB 512 B 64 B 23 20 2 8 1 1 1 SSOP 28-pin package Z8F022APJ020EG 2 KB 512 B 64 B 23 20 2 8 1 1 1 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 251 Z8 Encore! XP F082A Series with 2 KB Flash Standard Temperature: 0°C to 70°C Z8F021APB020SG 2 KB 512 B 64 B 6 13 2 0 1 1 0 PDIP 8-pin package Z8F021AQB020SG 2 KB 512 B 64 B 6 13 2 0 1 1 0 QFN 8-pin package Z8F021ASB020SG 2 KB 512 B 64 B 6 13 2 0 1 1 0 SOIC 8-pin package Z8F021ASH020SG 2 KB 512 B 64 B 17 19 2 0 1 1 0 SOIC 20-pin package Z8F021AHH020SG 2 KB 512 B 64 B 17 19 2 0 1 1 0 SSOP 20-pin package Z8F021APH020SG 2 KB 512 B 64 B 17 19 2 0 1 1 0 PDIP 20-pin package Z8F021ASJ020SG 2 KB 512 B 64 B 25 19 2 0 1 1 0 SOIC 28-pin package Z8F021AHJ020SG 2 KB 512 B 64 B 25 19 2 0 1 1 0 SSOP 28-pin package Z8F021APJ020SG 2 KB 512 B 64 B 25 19 2 0 1 1 0 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F021APB020EG 2 KB 512 B 64 B 6 13 2 0 1 1 0 PDIP 8-pin package Z8F021AQB020EG 2 KB 512 B 64 B 6 13 2 0 1 1 0 QFN 8-pin package Z8F021ASB020EG 2 KB 512 B 64 B 6 13 2 0 1 1 0 SOIC 8-pin package Z8F021ASH020EG 2 KB 512 B 64 B 17 19 2 0 1 1 0 SOIC 20-pin package Z8F021AHH020EG 2 KB 512 B 64 B 17 19 2 0 1 1 0 SSOP 20-pin package Z8F021APH020EG 2 KB 512 B 64 B 17 19 2 0 1 1 0 PDIP 20-pin package Z8F021ASJ020EG 2 KB 512 B 64 B 25 19 2 0 1 1 0 SOIC 28-pin package Z8F021AHJ020EG 2 KB 512 B 64 B 25 19 2 0 1 1 0 SSOP 28-pin package Z8F021APJ020EG 2 KB 512 B 64 B 25 19 2 0 1 1 0 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 252 Z8 Encore! XP F082A Series with 1 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F012APB020SG 1 KB 256 B 16 B 6 14 2 4 1 1 1 PDIP 8-pin package Z8F012AQB020SG 1 KB 256 B 16 B 6 14 2 4 1 1 1 QFN 8-pin package Z8F012ASB020SG 1 KB 256 B 16 B 6 14 2 4 1 1 1 SOIC 8-pin package Z8F012ASH020SG 1 KB 256 B 16 B 17 20 2 7 1 1 1 SOIC 20-pin package Z8F012AHH020SG 1 KB 256 B 16 B 17 20 2 7 1 1 1 SSOP 20-pin package Z8F012APH020SG 1 KB 256 B 16 B 17 20 2 7 1 1 1 PDIP 20-pin package Z8F012ASJ020SG 1 KB 256 B 16 B 23 20 2 8 1 1 1 SOIC 28-pin package Z8F012AHJ020SG 1 KB 256 B 16 B 23 20 2 8 1 1 1 SSOP 28-pin package Z8F012APJ020SG 1 KB 256 B 16 B 23 20 2 8 1 1 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F012APB020EG 1 KB 256 B 16 B 6 14 2 4 1 1 1 PDIP 8-pin package Z8F012AQB020EG 1 KB 256 B 16 B 6 14 2 4 1 1 1 QFN 8-pin package Z8F012ASB020EG 1 KB 256 B 16 B 6 14 2 4 1 1 1 SOIC 8-pin package Z8F012ASH020EG 1 KB 256 B 16 B 17 20 2 7 1 1 1 SOIC 20-pin package Z8F012AHH020EG 1 KB 256 B 16 B 17 20 2 7 1 1 1 SSOP 20-pin package Z8F012APH020EG 1 KB 256 B 16 B 17 20 2 7 1 1 1 PDIP 20-pin package Z8F012ASJ020EG 1 KB 256 B 16 B 23 20 2 8 1 1 1 SOIC 28-pin package Z8F012AHJ020EG 1 KB 256 B 16 B 23 20 2 8 1 1 1 SSOP 28-pin package Z8F012APJ020EG 1 KB 256 B 16 B 23 20 2 8 1 1 1 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 253 Z8 Encore! XP F082A Series with 1 KB Flash Standard Temperature: 0°C to 70°C Z8F011APB020SG 1 KB 256 B 16 B 6 13 2 0 1 1 0 PDIP 8-pin package Z8F011AQB020SG 1 KB 256 B 16 B 6 13 2 0 1 1 0 QFN 8-pin package Z8F011ASB020SG 1 KB 256 B 16 B 6 13 2 0 1 1 0 SOIC 8-pin package Z8F011ASH020SG 1 KB 256 B 16 B 17 19 2 0 1 1 0 SOIC 20-pin package Z8F011AHH020SG 1 KB 256 B 16 B 17 19 2 0 1 1 0 SSOP 20-pin package Z8F011APH020SG 1 KB 256 B 16 B 17 19 2 0 1 1 0 PDIP 20-pin package Z8F011ASJ020SG 1 KB 256 B 16 B 25 19 2 0 1 1 0 SOIC 28-pin package Z8F011AHJ020SG 1 KB 256 B 16 B 25 19 2 0 1 1 0 SSOP 28-pin package Z8F011APJ020SG 1 KB 256 B 16 B 25 19 2 0 1 1 0 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F011APB020EG 1 KB 256 B 16 B 6 13 2 0 1 1 0 PDIP 8-pin package Z8F011AQB020EG 1 KB 256 B 16 B 6 13 2 0 1 1 0 QFN 8-pin package Z8F011ASB020EG 1 KB 256 B 16 B 6 13 2 0 1 1 0 SOIC 8-pin package Z8F011ASH020EG 1 KB 256 B 16 B 17 19 2 0 1 1 0 SOIC 20-pin package Z8F011AHH020EG 1 KB 256 B 16 B 17 19 2 0 1 1 0 SSOP 20-pin package Z8F011APH020EG 1 KB 256 B 16 B 17 19 2 0 1 1 0 PDIP 20-pin package Z8F011ASJ020EG 1 KB 256 B 16 B 25 19 2 0 1 1 0 SOIC 28-pin package Z8F011AHJ020EG 1 KB 256 B 16 B 25 19 2 0 1 1 0 SSOP 28-pin package Z8F011APJ020EG 1 KB 256 B 16 B 25 19 2 0 1 1 0 PDIP 28-pin package

Z8 Encore! XP® F082A Series Product Specification 254 Z8 Encore! XP F082A Series Development Kit Z8F08A28100KITG Z8 Encore! XP F082A Series 28-Pin Development Kit Z8F04A28100KITG Z8 Encore! XP F042A Series 28-Pin Development Kit Z8F04A08100KITG Z8 Encore! XP F042A Series 8-Pin Development Kit ZUSBSC00100ZACG USB Smart Cable Accessory Kit ZUSBOPTSC01ZACG USB Opto-Isolate d Smart Cable Accessory Kit ZENETSC0100ZACG Ethernet Smart Cable Accessory Kit

Z8 Encore! XP® F082A Series Product Specification 255 Part Number Suffix Designations Zilog part numbers consist of a number of components, as indicated in the following example. Example. Part number Z8F042ASH020SG is an 8-bit Flash MCU with 4 KB of Program Memory, equipped with advanced analog peripherals in a 20-pin SOIC package, operating within a 0ºC to +70ºC temperature range and built using lead-free solder. Z8 F 04 2A S H 020 S G Environmental Flow G = Green Plastic Packaging Compound Temperature Range S = Standard, 0°C to 70°C E = Extended, –40°C to +105°C Speed 020 = 20 MHz Pin Count B = 8 H = 20 J = 28 Package H = SSOP P = PDIP Q = QFN S = SOIC Device Type 2A = Contains Advanced Analog Peripherals 1A = Does Not Contain Advanced Analog Peripherals Memory Size 08 = 8 KB Flash, 1 KB RAM, 0 B NVDS 04 = 4 KB Flash, 1 KB RAM, 128 B NVDS 02 = 2 KB Flash, 512 B RAM, 64 B NVDS 01 = 1 KB Flash, 256 B RAM, 16 B NVDS Memory Type F = Flash Device Family Z8 = Zilog’s 8-Bit Microcontroller

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 256 Index Numerics 10-bit ADC 6 A absolute maximum ratings 226 AC characteristics 232 ADC 208 architecture 124 block diagram 125 continuous conversion 127 control register 134, 135 control register definitions 133 data high byte register 136 data low bits register 137 electrical characteristics and timing 236 operation 125 single-shot conversion 126 ADCCTL register 134, 135 ADCDH register 136 ADCDL register 137 ADCX 208 ADD 208 add - extended addressing 208 add with carry 208 add with carry - extended addressing 208 additional symbols 207 address space 15 ADDX 208 analog signals 11 analog-to-digital converter (ADC) 124 AND 210 ANDX 210 arithmetic instructions 208 assembly language programming 204 assembly language syntax 205 B B 207 b 206 baud rate generator, UART 110 BCLR 209 binary number suffix 207 BIT 209 bit 206 clear 209 manipulation instructions 209 set 209 set or clear 209 swap 209 test and jump 211 test and jump if non-zero 211 test and jump if zero 211 bit jump and test if non-zero 211 bit swap 211 block diagram 3 block transfer instructions 209 BRK 211 BSET 209 BSWAP 209, 211 BTJ 211 BTJNZ 211 BTJZ 211 C CALL procedure 211 CAPTURE mode 87, 88 CAPTURE/COMPARE mode 88 cc 206 CCF 209 characteristics, electrical 226 clear 210 CLR 210 COM 210 compare 87 compare - extended addressing 208 COMPARE mode 87 compare with carry 208

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 257 compare with carry - extended addressing 208 complement 210 complement carry flag 209 condition code 206 continuous conversion (ADC) 127 CONTINUOUS mode 87 control register definition, UART 110 Control Registers 15, 18 COUNTER modes 87 CP 208 CPC 208 CPCX 208 CPU and peripheral overview 4 CPU control instructions 209 CPX 208 Customer Feedback Form 265 D DA 206, 208 data memory 17 DC characteristics 227 debugger, on-chip 180 DEC 208 decimal adjust 208 decrement 208 decrement and jump non-zero 211 decrement word 208 DECW 208 destination operand 207 device, port availability 36 DI 209 direct address 206 disable interrupts 209 DJNZ 211 dst 207 E EI 209 electrical characteristics 226 ADC 236 flash memory and timing 234 GPIO input data sample timing 240 Watchdog Timer 235, 238 enable interrupt 209 ER 206 extended addressing register 206 external pin reset 26 eZ8 CPU features 4 eZ8 CPU instruction classes 207 eZ8 CPU instruction notation 206 eZ8 CPU instruction set 204 eZ8 CPU instruction summary 212 F FCTL register 155, 161, 162 features, Z8 Encore! 1 first opcode map 224 FLAGS 207 flags register 207 flash controller 6 option bit address space 162 option bit configuration - reset 159 program memory address 0000H 162 program memory address 0001H 164 flash memory 146 arrangement 147 byte programming 151 code protection 149 configurations 146 control register definitions 153, 161 controller bypass 152 electrical characteristics and timing 234 flash control register 155, 161, 162 flash option bits 150 flash status register 155 flow chart 148 frequency high and low byte registers 157 mass erase 152 operation 147 operation timing 149 page erase 152 page select register 156, 157 FPS register 156, 157 FSTAT register 155

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 258 G GATED mode 88 general-purpose I/O 36 GPIO 6, 36 alternate functions 37 architecture 37 control register definitions 44 input data sample timing 240 interrupts 44 port A-C pull-up enable sub-registers 50, 51 port A-H address registers 45 port A-H alternate function sub-registers 47 port A-H control registers 46 port A-H data direction sub-registers 46 port A-H high drive enable sub-registers 48 port A-H input data registers 52 port A-H output control sub-registers 47 port A-H output data registers 52, 53 port A-H stop mode recovery sub-registers 49 port availability by device 36 port input timing 240 port output timing 241 H H 207 HALT 209 halt mode 33, 209 hexadecimal number prefix/suffix 207 I I2C 6 IM 206 immediate data 206 immediate operand prefix 207 INC 208 increment 208 increment word 208 INCW 208 indexed 207 indirect address prefix 207 indirect register 206 indirect register pair 206 indirect working register 206 indirect working register pair 206 infrared encoder/decoder (IrDA) 120 Instruction Set 204 instruction set, eZ8 CPU 204 instructions ADC 208 ADCX 208 ADD 208 ADDX 208 AND 210 ANDX 210 arithmetic 208 BCLR 209 BIT 209 bit manipulation 209 block transfer 209 BRK 211 BSET 209 BSWAP 209, 211 BTJ 211 BTJNZ 211 BTJZ 211 CALL 211 CCF 209 CLR 210 COM 210 CP 208 CPC 208 CPCX 208 CPU control 209 CPX 208 DA 208 DEC 208 DECW 208 DI 209 DJNZ 211 EI 209 HALT 209 INC 208 INCW 208 IRET 211 JP 211

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 259 LD 210 LDC 210 LDCI 209, 210 LDE 210 LDEI 209 LDX 210 LEA 210 logical 210 MULT 208 NOP 209 OR 210 ORX 210 POP 210 POPX 210 program control 211 PUSH 210 PUSHX 210 RCF 209, 210 RET 211 RL 211 RLC 211 rotate and shift 211 RR 211 RRC 211 SBC 208 SCF 209, 210 SRA 211 SRL 211 SRP 210 STOP 210 SUB 208 SUBX 208 SWAP 211 TCM 209 TCMX 209 TM 209 TMX 209 TRAP 211 Watchdog Timer refresh 210 XOR 210 XORX 210 instructions, eZ8 classes of 207 interrupt control register 69 interrupt controller 55 architecture 55 interrupt assertion types 58 interrupt vectors and priority 58 operation 57 register definitions 60 software interrupt assertion 59 interrupt edge select register 67 interrupt request 0 register 60 interrupt request 1 register 61 interrupt request 2 register 62 interrupt return 211 interrupt vector listing 55 interrupts UART 108 IR 206 Ir 206 IrDA architecture 120 block diagram 120 control register definitions 123 operation 120 receiving data 122 transmitting data 121 IRET 211 IRQ0 enable high and low bit registers 62 IRQ1 enable high and low bit registers 64 IRQ2 enable high and low bit registers 65 IRR 206 Irr 206 J JP 211 jump, conditional, relative, and relative conditional 211 L LD 210 LDC 210 LDCI 209, 210 LDE 210 LDEI 209, 210 LDX 210

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 260 LEA 210 load 210 load constant 209 load constant to/from program memory 210 load constant with auto-increment addresses 210 load effective address 210 load external data 210 load external data to/from data memory and auto- increment addresses 209 load external to/from data memory and auto-incre- ment addresses 210 load using extended addressing 210 logical AND 210 logical AND/extended addressing 210 logical exclusive OR 210 logical exclusive OR/extended addressing 210 logical instructions 210 logical OR 210 logical OR/extended addressing 210 low power modes 32 M master interrupt enable 57 memory data 17 program 15 mode CAPTURE 87, 88 CAPTURE/COMPARE 88 CONTINUOUS 87 COUNTER 87 GATED 88 ONE-SHOT 87 PWM 87, 88 modes 87 MULT 208 multiply 208 multiprocessor mode, UART 105 N NOP (no operation) 209 notation b 206 cc 206 DA 206 ER 206 IM 206 IR 206 Ir 206 IRR 206 Irr 206 p 206 R 206 r 206 RA 206 RR 206 rr 206 vector 207 X 207 notational shorthand 206 O OCD architecture 180 auto-baud detector/generator 183 baud rate limits 184 block diagram 180 breakpoints 185 commands 186 control register 191 data format 183 DBG pin to RS-232 Interface 181 debug mode 182 debugger break 211 interface 181 serial errors 184 status register 192 timing 242 OCD commands execute instruction (12H) 190 read data memory (0DH) 190 read OCD control register (05H) 188 read OCD revision (00H) 187 read OCD status register (02H) 187 read program counter (07H) 188

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 261 read program memory (0BH) 189 read program memory CRC (0EH) 190 read register (09H) 189 read runtime counter (03H) 187 step instruction (10H) 190 stuff instruction (11H) 190 write data memory (0CH) 189 write OCD control register (04H) 188 write program counter (06H) 188 write program memory (0AH) 189 write register (08H) 188 on-chip debugger (OCD) 180 on-chip debugger signals 11 on-chip oscillator 198 ONE-SHOT mode 87 opcode map abbreviations 223 cell description 222 first 224 second after 1FH 225 Operational Description 22, 32, 36, 55, 70, 93, 99, 120, 124, 139, 140, 144, 146, 159, 176, 180, 193, 198, 203 OR 210 ordering information 246 ORX 210 oscillator signals 11 P p 206 Packaging 245 part selection guide 2 PC 207 peripheral AC and DC electrical characteristics 233 pin characteristics 12 Pin Descriptions 8 polarity 206 POP 210 pop using extended addressing 210 POPX 210 port availability, device 36 port input timing (GPIO) 240 port output timing, GPIO 241 power supply signals 12 Power-on and Voltage Brownout electrical charac- teristics and timing 233 Power-On Reset (POR) 24 program control instructions 211 program counter 207 program memory 15 PUSH 210 push using extended addressing 210 PUSHX 210 PWM mode 87, 88 PxADDR register 45 PxCTL register 46 R R 206 r 206 RA register address 206 RCF 209, 210 receive IrDA data 122 receiving UART data-interrupt-driven method 104 receiving UART data-polled method 103 register 206 ADC control (ADCCTL) 134, 135 ADC data high byte (ADCDH) 136 ADC data low bits (ADCDL) 137 flash control (FCTL) 155, 161, 162 flash high and low byte (FFREQH and FRE- EQL) 157 flash page select (FPS) 156, 157 flash status (FSTAT) 155 GPIO port A-H address (PxADDR) 45 GPIO port A-H alternate function sub-registers GPIO port A-H control address (PxCTL) 46 GPIO port A-H data direction sub-registers 46 OCD control 191 OCD status 192 UARTx baud rate high byte (UxBRH) 117 UARTx baud rate low byte (UxBRL) 117 UARTx Control 0 (UxCTL0) 111, 117

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 262 UARTx control 1 (UxCTL1) 112 UARTx receive data (UxRXD) 116 UARTx status 0 (UxSTAT0) 114 UARTx status 1 (UxSTAT1) 115 UARTx transmit data (UxTXD) 116 Watchdog Timer control (WDTCTL) 30, 96, 141, 196 Watchdog Timer reload high byte (WDTH) 97 Watchdog Timer reload low byte (WDTL) 98 Watchdog Timer reload upper byte (WDTU) register file 15 register pair 206 register pointer 207 reset and stop mode characteristics 23 and Stop Mode Recovery 22 carry flag 209 sources 24 RET 211 return 211 RL 211 RLC 211 rotate and shift instuctions 211 rotate left 211 rotate left through carry 211 rotate right 211 rotate right through carry 211 RP 207 RR 206, 211 rr 206 RRC 211 S SBC 208 SCF 209, 210 second opcode map after 1FH 225 set carry flag 209, 210 set register pointer 210 shift right arithmatic 211 shift right logical 211 signal descriptions 10 single-shot conversion (ADC) 126 software trap 211 source operand 207 SP 207 SRA 211 src 207 SRL 211 SRP 210 stack pointer 207 STOP 210 STOP mode 32 stop mode 210 Stop Mode Recovery sources 27 using a GPIO port pin transition 28 using Watchdog Timer time-out 28 stop mode recovery sources 29 using a GPIO port pin transition 29 SUB 208 subtract 208 subtract - extended addressing 208 subtract with carry 208 subtract with carry - extended addressing 208 SUBX 208 SWAP 211 swap nibbles 211 symbols, additional 207 T TCM 209 TCMX 209 test complement under mask 209 test complement under mask - extended addressing 209 test under mask 209 test under mask - extended addressing 209 timer signals 10 timers 70 architecture 70 block diagram 71 CAPTURE mode 79, 80, 87, 88 CAPTURE/COMPARE mode 83, 88 COMPARE mode 81, 87

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 263 CONTINUOUS mode 72, 87 COUNTER mode 73, 74 COUNTER modes 87 GATED mode 82, 88 ONE-SHOT mode 71, 87 operating mode 71 PWM mode 76, 77, 87, 88 reading the timer count values 84 reload high and low byte registers 91 timer control register definitions 85 timer output signal operation 84 timers 0-3 control registers 85, 86 high and low byte registers 89, 92 TM 209 TMX 209 transmit IrDA data 121 transmitting UART data-polled method 101 transmitting UART dat-interrupt-driven method 102 TRAP 211 U UART 6 architecture 99 baud rate generator 110 baud rates table 118 control register definitions 110 controller signals 10 interrupts 108 multiprocessor mode 105 receiving data using interrupt-driven method 104 receiving data using the polled method 103 transmitting data usin the interrupt-driven method 102 transmitting data using the polled method 101 x baud rate high and low registers 117 x control 0 and control 1 registers 110 x status 0 and status 1 registers 114, 115 UxBRH register 117 UxBRL register 117 UxCTL0 register 111, 117 UxCTL1 register 112 UxRXD register 116 UxSTAT0 register 114 UxSTAT1 register 115 UxTXD register 116 V vector 207 Voltage Brownout reset (VBR) 25 W Watchdog Timer approximate time-out delay 93 approximate time-out delays 140 CNTL 25 control register 96 electrical characteristics and timing 235, 238 interrupt in normal operation 94 interrupt in STOP mode 94 operation 140 refresh 94, 210 reload unlock sequence 95 reload upper, high and low registers 97 reset 26 reset in normal operation 95 reset in STOP mode 95 time-out response 94 WDTCTL register 30, 96, 141, 196 WDTH register 97 WDTL register 98 working register 206 working register pair 206 WTDU register 97 X X 207 XOR 210 XORX 210

PS022827-1212 P R E L I M I N A R Y Index Z8 Encore! XP® F082A Series Product Specification 264 Z Z8 Encore! block diagram 3 features 1 part selection guide 2

PS022827-1212 P R E L I M I N A R Y Customer Support Z8 Encore! XP® F082A Series Product Specification 265 Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at  http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other fac- ets about Zilog product offerings, please visit the Zilog Knowledge Base at http:// zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com.

Product Information

Z8F012AQB020EG specifications and overview.

Summary

High-Performance 8-Bit Microcontrollers

Description

High-Performance 8-Bit Microcontrollers

Source title Z8F012AQB020EG Datasheet(PDF) - Zilog, Inc.

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