Microcontroller

Z8F0113

Zilog, Inc.

High-Performance 8-Bit Microcontrollers

Manufacturer: Zilog, Inc.

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PS024315-1011 P R E L I M I N A R Y Disclaimer Z8 Encore! XP® F0823 Series Product Specification ii DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2011 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. Warning:

Z8 Encore! XP® F0823 Series Product Specification iii

Revision History

Each instance in this document’s revision history reflects a change from its previous edi- tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Date Revision Level Chapter/Section Description Page No. Sep 15 LED Drive Enable Register Clarifie d statement surrounding the Alternate Function Register as it relates to the LED function; revised Flash Sector Protect Regis- ter description; revised Packaging chapter. 144, 210 Mar 2008 14 n/a Changed branding to Z8 Encore! XP F0823 Series where appropriate. All Dec 2007

13 Pin Description, General-Pur-

pose Input/Output, Interrupt Controller, Watchdog Timer, Electrical Characteristics, and

Ordering Information

Updated title from Z8 Encore! 8K and 4K Series to Z8 Encore! XP Z8F0823 Series. Updated Figure 3, Table 15, Table 35, Tables 59 through 61, Table 119 and Part Number Suffix Designations section. , 36, 60, 95, 199, and 220 Aug 2007

12 Part Selection Guide, External

Clock Setup, and Program Memory Updated Table 1, Table 16, and Program Memory section. , 35, and 13 Jun 2007 11 n/a Updated to combine Z8 Encore! 8K and Z8 Encore! 4K Series. All Dec 2006

PS024315-1011 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F0823 Series Product Specification iv Table of Contents

PS024315-1011 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F0823 Series Product Specification v

PS024315-1011 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F0823 Series Product Specification vi

PS024315-1011 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F0823 Series Product Specification vii

PS024315-1011 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F0823 Series Product Specification viii

PS024315-1011 P R E L I M I N A R Y Table of Contents Z8 Encore! XP® F0823 Series Product Specification ix

Table 26. Port A–C Stop Mode Recovery Source Enable Subregisters (PSMREx) . . 46

Table 125. Power-On Reset and Voltage Br own-Out Electrical Characteristics 

PS024315-1011 P R E L I M I N A R Y Overview Z8 Encore! XP® F0823 Series Product Specification Overview Zilog’s Z8 Encore! XP microcontroller unit (MCU) family of products are the first Zilog microcontroller products based on the 8-bit eZ8 CPU core. Z8 Encore! XP F0823 Series products expand upon Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward compatible with existing Z8 instructions. The rich peripheral set of Z8 Encore! XP F0823 Series makes it suitable for a variety of applica- tions including motor control, security systems, home appliances, personal electronic devices, and sensors.

Features

The key features of Z8 Encore! XP F0823 Series include:

5 MHz eZ8 CPU
1 KB, 2 KB, 4 KB, or 8 KB Flash memory with in-circuit programming capability
256 B, 512 B, or 1 KB register RAM
6 to 24 I/O pins depending upon package
Internal precision oscillator (IPO)
Full-duplex UART
The universal asynchronous receiver/transmitter (UART) baud rate generator (BRG) can be configured and used as a basic 16-bit timer
Infrared data association (IrDA)-compliant infrared encoder/decoders, integrated with UART
Two enhanced 16-bit timers with capture, compare, and PWM capability
Watchdog Timer (WDT) with dedicated internal RC oscillator
On-Chip Debugger (OCD)
Optional 8-channel, 10-bit Analog-to-Digital Converter (ADC)
On-Chip analog comparator
Up to 20 vectored interrupts
Direct LED drive with programmable drive strengths
V oltage Brown-Out (VBO) protection
Power-On Reset (POR)

2.7 V to 3.6 V operating voltage
Up to thirteen 5 V-tolerant input pins
8-, 20-, and 28-pin packages
0°C to +70°C and –40°C to +105°C for operating temperature ranges Part Selection Guide Table 1 lists the basic features and package styles available for each device within the Z8 Encore! XP® F0823 Series product line.

Table 1. F0823 Series Family Part Selection Guide

PS024315-1011 P R E L I M I N A R Y CPU and Peripheral Overview Z8 Encore! XP® F0823 Series Product Specification CPU and Peripheral Overview The eZ8 CPU, Zilog’s latest 8-bit central processing unit (CPU), meets the continuing demand for faster and code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include:

Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory
Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks
Compatible with existing Z8 code
Expanded internal Register File allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-level programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction For more information about the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128) available for download at www.zilog.com. General-Purpose I/O F0823 Series features 6 to 24 port pins (Ports A–C) for general-purpose I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is individually program- mable. 5 V-tolerant input pins are available on all I/Os on 8-pin devices, most I/Os on other package types. Flash Controller The Flash Controller programs and erases Flash memory. The Flash Controller supports protection against accidental program and erasure, as well as factory serialization and read protection.

PS024315-1011 P R E L I M I N A R Y CPU and Peripheral Overview Z8 Encore! XP® F0823 Series Product Specification Internal Precision Oscillator The internal precision oscillator (IPO) is a trimmable clock source that requires no exter- nal components. 10-Bit Analog-to-Digital Converter The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from eight different analog input pins in both sin- gle-ended and differential modes. Analog Comparator The analog comparator compares the signal at an input pin with either an internal pro- grammable voltage reference or a second input pin. The comparator output can be used to drive either an output pin or to generate an interrupt. Universal Asynchronous Receiver/Transmitter The UART is full-duplex and capable of handling asynchronous data transfers. The UART supports 8- and 9-bit data modes and selectable parity. The UART also supports multi- drop address processing in hardware. The UART baud rate generator can be configured and used as a basic 16-bit timer. Timers Two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in ONE-SHOT, CONTINUOUS, GATED, CAPTURE, CAPTURE RESTART, COMPARE, CAPTURE AND COMPARE, PWM SINGLE OUTPUT, and PWM DUAL OUTPUT modes. Interrupt Controller Z8 Encore! XP® F0823 Series products support up to 20 interrupts. These interrupts con- sist of eight internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources. The interrupts have three levels of programmable interrupt priority. Reset Controller Z8 Encore! XP® F0823 Series products can be reset using the RESET pin, POR, WDT time-out, STOP Mode exit, or V oltage Brown-Out warning signal. The RESET pin is bidi- rectional, that is, it functions as reset source as well as a reset indicator.

PS024315-1011 P R E L I M I N A R Y CPU and Peripheral Overview Z8 Encore! XP® F0823 Series Product Specification On-Chip Debugger F0823 Series products feature an integrated On-Chip Debugger. The OCD provides a rich- set of debugging capabilities, such as reading and writing registers, programming Flash memory, setting breakpoints and executing code. A single-pin interface provides commu- nication to the OCD.

Packaging chapter on page 210. AVSS) are also not available on these parts, and are replaced by PB6 and PB7. Table 2. F0823 Series Package Options

*Analog input alternate functions (ANA) are not available on Z8F0x13 devices. for the specific package styles, see the Pin Configurations section on page 7. Table 3. Signal Descriptions PA[7:0] I/O Port A. These pins are used for general-purpose I/O. available only in those devices without an ADC. PC[7:0] I/O Port C. These pins are used for general-purpose I/O. TXD0 O Transmit Data. This signal is the transmit output from the UART and IrDA. RXD0 I Receive Data. This signal is th e receive input for the UART and IrDA. CTS0 I Clear To Send. This signal is th e flow control input for the UART. T0OUT/T1OUT O Timer Output 0–1. These signals are output from the timers. ter inputs. The T0IN signal is multiplexed T0OUT signals.

PB6 and PB7 are only available in 28-pin packages wi thout ADC. In 28-pin packages with ADC, they are
The AV DD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and

PB7 on 28-pin packages without ADC.

COUT O Comparator Output. This is the output of the comparator. grated transimpedance amplifier. VREF I/O Analog-to-Digital Converter reference voltage input. ble drive strengths set by the GPIO block. resistor to ensure proper operation. pin is open-drain and features an enabled internal pull-up resistor. Table 3. Signal Descriptions (Continued)

PB6 and PB7 are only available in 28-pin packages wi thout ADC. In 28-pin packages with ADC, they are
The AV DD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and

PB7 on 28-pin packages without ADC.

cally by the pin symbol mnemonic. Table 4. Pin Characteristics (20- and 28-pin Devices)* Note: PB6 and PB7 are available only in the devices without ADC.

Z8 Encore! XP F0823 Series 8-pin devices. Table 5. Pin Characteristics (8-Pin Devices)

PS024315-1011 P R E L I M I N A R Y Address Space Z8 Encore! XP® F0823 Series Product Specification Address Space The eZ8 CPU can access three distinct address spaces:

The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral, and general-purpose I/O Port Control Registers
The Program Memory contains addresses for all memory locations having executable code and/or data
The Data Memory contains addresses for all memory locations that contain data only These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual (UM0128), available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore! XP™ MCU is 4 KB (4096 bytes). The Register File is composed of two sections: control registers and general-purpose registers. When instructions are executed, registers defined as sources are read, and registers defined as destinations are written. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4 KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256 B control register section are reserved (unavailable). Reading from a reserved Register File address returns an undefined value. Writing to reserved Register File addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. Z8 Encore! XP F0823 Series devices contain 256 B–1 KB of on-chip RAM. Reading from Register File addresses outside the available RAM addresses (and not within the control register address space) returns an undefined value. Writing to these Register File addresses produces no effect. Program Memory The eZ8 CPU supports 64 KB of Program Memory address space. F0823 Series devices contain 1 KB to 8 KB of on-chip Flash memory in the Program Memory address space. Reading from Program Memory addresses outside the available Flash memory addresses

Table 6. Z8 Encore! XP F0823 Series Program Memory Maps for a list of the interrupt vectors and traps.

the Program Memory data. Access to the Flash Information Area is read-only. Table 7. F0823 Series Flash Memory Information Area Map FE00–FE3F Zilog Option Bits. Left-justified and filled with FH. FE60–FE7F Zilog Calibration Data. Table 6. Z8 Encore! XP F0823 Series Program Memory Maps (Continued) for a list of the interrupt vectors and traps.

GPIO ports. Consider registers for unimplemented peripherals to be reserved. Table 8. Register File Address Map

Table 8. Register File Address Map (Continued)

Power-On Reset (POR)
V oltage Brown-Out (VBO)
Watchdog Timer time-out (when configured by the WDT_RES Flash Option Bit to initiate a reset)
External RESET pin assertion (when the alternate RESET function is enabled by the GPIO register)
On-chip Debugger initiated Reset (OCDCTL[0] set to 1) When the device is in STOP Mode, a Stop Mode Recovery is initiated by either of the fol- lowing:
Watchdog Timer time-out
GPIO port input pin transition on an enabled Stop Mode Recovery source The VBO circuitry on the device performs the following function:
Generates the VBO reset when the supply voltage drops below a minimum safe level Reset Types F0823 Series MCUs provide several different types of Reset operations. Stop Mode Recovery is considered a form of Reset. Table 9 lists the types of Reset and their operating characteristics. The duration of a System Reset is longer if the external crystal oscillator is enabled by the Flash option bits; this configuration allows additional time for oscillator startup.

Table 9. Reset and Stop Mode Recovery Characteristics and Latency

PS024315-1011 P R E L I M I N A R Y Reset Types Z8 Encore! XP® F0823 Series Product Specification During a System Reset or Stop Mode Recovery, the IPO requires 4 µs to start up. Then the Z8 Encore! XP F0823 Series device is held in Reset for 66 cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because of a low voltage condition or Power-On Reset, this delay is measured from the time that the supply voltage first exceeds the POR level. If the external pin reset remains asserted at the end of the reset period, the device remains in reset until the pin is deasserted. At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis- abled. During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal oscillator and Watchdog Timer oscillator continue to run. Upon Reset, control registers within the Register File that have a defined Reset value are loaded with their reset values. Other control registers (including the Stack Pointer, Regis- ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vector address. When the control registers are re-initialized by a system reset, the system clock after reset is always the IPO. The software must reconfigure the oscillator control block, such that the correct system clock source is enabled and selected.

Table 10 lists the possible sources of a System Reset. timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer. (WDTCTL) Register is set to 1. cal Characteristics chapter on page 196. Table 10. Reset Sources and Resulting Reset Type

below the POR voltage threshold (VPOR), the VBO block holds the device in the Reset. VBO_AO, see the Flash Option Bits chapter on page 146. Figure 5. Power-On Reset Operation

ensures that the device undergoes a POR after recovering from a VBO condition. configures the Watchdog Timer to cause an interrupt, not a System Reset, at time-out. Figure 6. Voltage Brown-Out Reset Operation

PS024315-1011 P R E L I M I N A R Y Stop Mode Recovery Z8 Encore! XP® F0823 Series Product Specification clock and reset signals, the required reset duration can be as short as three clock periods and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. While the RESET input pin is asserted Low, the Z8 Encore! XP F0823 Series devices remain in the Reset state. If the RESET pin is held Low beyond the System Reset time- out, the device exits the Reset state on the system clock rising edge following RESET pin deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta- tus bit in the WDT Control (WDTCTL) register is set to 1. External Reset Indicator During System Reset or when enabled by the GPIO logic (see the Port A–C Control Reg- isters section on page 42), the RESET pin functions as an open-drain (active Low) reset mode indicator in addition to the input functionality. This reset output feature allows an Z8 Encore! XP F0823 Series device to reset other components to which it is connected, even if that reset is caused by internal sources such as POR, VBO, or WDT events. After an internal reset event occurs, the internal circuitry begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry until the appropriate delay listed in Table 9 has elapsed. On-Chip Debugger Initiated Reset A POR is initiated using the On-Chip Debugger by setting the RST bit in the OCD Control Register. The OCD block is not reset but the rest of the chip goes through a normal system reset. The RST bit automatically clears during the System Reset. Following the System Reset, the POR bit in the Reset Status (RSTSTAT) Register is set. Stop Mode Recovery The device enters into STOP Mode when eZ8 CPU executes a STOP instruction. For more details about STOP Mode, see the Low-Power Modes section on page 30. During Stop Mode Recovery, the CPU is held in reset for 66 IPO cycles if the crystal oscillator is dis- abled or 5000 cycles if it is enabled. The SMR delay also included the time required to start up the IPO. Stop Mode Recovery does not affect on-chip registers other than the Watchdog Timer Control Register (WDTCTL) and the Oscillator Control Register (OSCCTL). After any Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another sys- tem clock source is required or IPO disabling is required, the Stop Mode Recovery code must reconfigure the oscillator control block such that the correct system clock source is enabled and selected.

Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting actions. the Watchdog Timer interrupt request following the normal Stop Mode Recovery sequence. (from High to Low or from Low to High) initiates Stop Mode Recovery. STOP bit in the Reset Status (RSTSTAT) Register is set to 1. tiating an interrupt (if enabled for that pin). Table 11. Stop Mode Recovery Sources and Resulting Action

more details, see the Electrical Characteristics chapter on page 196. The following sections define the Reset registers. Watchdog Timer time-out. Reading this register resets the upper four bits to 0. Table 12. Reset Status Register (RSTSTAT) POR/Stop Mode Recover event values, please see Table 13. resets this bit. For POR/Stop Mode Recover event values, please see Table 13.

resets this bit. For POR/Stop Mode Recover event values, please see Table 13. These bits are reserved and must be programmed to 0000 when read. Table 13. POR Indicator Values

PS024315-1011 P R E L I M I N A R Y Low-Power Modes Z8 Encore! XP® F0823 Series Product Specification Low-Power Modes Z8 Encore! XP F0823 Series products contain power-saving features. The highest level of power reduction is provided by the STOP Mode, in which nearly all device functions are powered down. The next lower level of power reduction is provided by the HALT Mode, in which the CPU is powered down. Further power savings can be implemented by disabling individual peripheral blocks while in ACTIVE mode (defined as being in neither STOP nor HALT Mode). STOP Mode Executing the eZ8 CPU’s Stop instruction places the device into STOP Mode, powering down all peripherals except the V oltage Brown-Out detector, and the Watchdog Timer. These two blocks may also be disabled for additional power savings. In STOP Mode, the operating characteristics are:

Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT (if previously enabled) are disabled, and PA0/PA1 revert to the states programmed by the GPIO registers
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscil- lator Control Register
If enabled, the Watchdog Timer logic continues to operate
If enabled for operation in STOP Mode by the associated Flash Option Bit, the V oltage Brown-Out protection circuit continues to operate
All other on-chip peripherals are idle To minimize current in STOP Mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (V CC or GND). Additionally, any GPIOs config- ured as outputs must also be driven to one of the supply rails. The device can be brought out of STOP Mode using Stop Mode Recovery. For more information about Stop Mode Recovery, see the Reset and Stop Mode Recovery chapter on page 21.

PS024315-1011 P R E L I M I N A R Y HALT Mode Z8 Encore! XP® F0823 Series Product Specification HALT Mode Executing the eZ8 CPU’s HALT instruction places the device into HALT Mode, which powers down the CPU but leaves all other peripherals active. In HALT Mode, the operat- ing characteristics are:

Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate
If enabled, the Watchdog Timer continues to operate
All other on-chip peripherals continue to operate The eZ8 CPU can be brought out of HALT Mode by any of the following operations:
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
V oltage Brown-Out reset
External RESET pin assertion To minimize current in HALT Mode, all GPIO pins that are configured as inputs must be driven to one of the supply rails (VCC or GND). Peripheral-Level Power Control In addition to the STOP and HALT modes, it is possible to disable each peripheral on each of the Z8 Encore! XP F0823 Series devices. Disabling a given peripheral minimizes its power consumption. Power Control Register Definitions The following sections describe the power control registers. Power Control Register 0 Each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block.

Table 14. Power Control Register 0 (PWRCTL0) This bit is reserved and must be programmed to 1. These bits are reserved and must be programmed to 00. This bit is reserved and must be programmed to 0. 1 = Analog-to-Digital Converter disabled. This bit is reserved and must be programmed to 0.

capable of direct LED drive at programmable drive strengths. Table 15 lists the port pins available with each device and package type. Table 15. Port Availability by Device and Package Type

PS024315-1011 P R E L I M I N A R Y GPIO Alternate Functions Z8 Encore! XP® F0823 Series Product Specification PA0 and PA6 contain two different timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the timer mode. For more details, see the Timers chapter on page 69. For pins with multiple alternate functions, Zilog recommends writing to the AFS1 and AFS2 subregisters before enabling the alternate function via the AF Subregister. This prevents spurious transitions through unwanted alternate function modes. Table 16. Port Alternate Function Mapping (8-Pin Parts)

Description

Port A PA0 T0IN Timer 0 Input AFS1[0]: 0 AFS2[0]: 0 Reserved AFS1[0]: 0 AFS2[0]: 1 Reserved AFS1[0]: 1 AFS2[0]: 0 T0OUT Timer 0 Output Comp lement AFS1[0]: 1 AFS2[0]: 1 PA1 T0OUT Timer 0 Output AFS1[1]: 0 AFS2[1]: 0 Reserved AFS1[1]: 0 AFS2[1]: 1 CLKIN External Clock Input AFS1[1]: 1 AFS2[1]: 0 Analog Functions* ADC Analog Input/V REF AFS1[1]: 1 AFS2[1]: 1 PA2 DE0 UART 0 Driver Enable AFS1[2]: 0 AFS2[2]: 0 RESET External Reset AFS1[2]: 0 AFS2[2]: 1 T1OUT Timer 1 Output AFS1[2]: 1 AFS2[2]: 0 Reserved AFS1[2]: 1 AFS2[2]: 1 PA3 CTS0 UART 0 Clear to Send AFS1[3]: 0 AFS2[3]: 0 COUT Comparator Output AFS1[3]: 0 AFS2[3]: 1 T1IN Timer 1 Input AFS1[3]: 1 AFS2[3]: 0 Analog Functions* ADC Analog Input AFS1[3]: 1 AFS2[3]: 1 PA4 RXD0 UART 0 Receive Da ta AFS1[4]: 0 AFS2[4]: 0 Reserved AFS1[4]: 0 AFS2[4]: 1 Reserved AFS1[4]: 1 AFS2[4]: 0 Analog Functions* ADC/Comparator Input (N) AFS1[4]: 1 AFS2[4]: 1 PA5 TXD0 UART 0 Transmit Data AFS1[5]: 0 AFS2[5]: 0 T1OUT Timer 1 Output Comp lement AFS1[5]: 0 AFS2[5]: 1 Reserved AFS1[5]: 1 AFS2[5]: 0 Analog Functions* ADC/Comparator Input (P) AFS1[5]: 1 AFS2[5]: 1 Note: *Analog Functions include ADC inputs, ADC reference and comparator inputs. Also, alternate function selection as described in the Port A–C Alternate Function Subregisters section on page 43 must be enabled. Caution:

Table 17. Port Alternate Function Mapping (Non 8-Pin Parts)

Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not

Subregisters section on page 43 automatically enables the associated alternate function.

Whether PA0/PA6 take on the timer input or timer out put complement function depends on the timer configura-

tion as described in the Timer Pin Signal Operation section on page 83.

Because there are at most two choice s of alternate function for any pin of Port B, the Alternate Function Set reg-

the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.

V REF is available on PB5 in 28-pin products only.
Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set reg-

the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.

V REF is available on PC2 in 20-pin parts only.

4 ADC Voltage Reference AFS1[5]: 1

Table 17. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)

Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not

Subregisters section on page 43 automatically enables the associated alternate function.

Whether PA0/PA6 take on the timer input or timer out put complement function depends on the timer configura-

tion as described in the Timer Pin Signal Operation section on page 83.

Because there are at most two choice s of alternate function for any pin of Port B, the Alternate Function Set reg-

the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.

V REF is available on PB5 in 28-pin products only.
Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set reg-

the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.

V REF is available on PC2 in 20-pin parts only.

and LEDLVLL) registers select the sink current.

6 ADC Analog Input or ADC Voltage Refer-

Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not

Subregisters section on page 43 automatically enables the associated alternate function.

Whether PA0/PA6 take on the timer input or timer out put complement function depends on the timer configura-

tion as described in the Timer Pin Signal Operation section on page 83.

Because there are at most two choice s of alternate function for any pin of Port B, the Alternate Function Set reg-

the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.

V REF is available on PB5 in 28-pin products only.
Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set reg-

the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.

V REF is available on PC2 in 20-pin parts only.

PS024315-1011 P R E L I M I N A R Y Shared Reset Pin Z8 Encore! XP® F0823 Series Product Specification For correct operation, the LED anode must be connected to VDD and the cathode must be connected to the GPIO pin. Using all Port C pins in LED Drive Mode with maximum cur- rent can result in excessive total current. For the maximum total current for the applicable package, see the Electrical Characteristics chapter on page 196. Shared Reset Pin On the 8-pin product versions, the reset pin is shared with PA2, but the pin is not limited to output-only when in GPIO Mode. If PA2 on the 8-pin product is reconfigured as an input, ensure that no external stimulus drives the pin Low during any reset sequence. Because PA2 returns to its RESET alternate function during system resets, driving it Low holds the chip in a reset state until the pin is released. Shared Debug Pin On the 8-pin version of this device only, the Debug pin shares function with the PA0 GPIO pin. This pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. If the unlock sequence is present, the debug function is unlocked and the pin no longer func- tions as a GPIO pin. If it is not present, the debug feature is disabled until/unless another reset event occurs. For more details, see the On-Chip Debugger chapter on page 156. Crystal Oscillator Override For systems using a crystal oscillator, PA0 and PA1 are used to connect the crystal. When the crystal oscillator is enabled (see the Oscillator Control Register Definitions section on page 171), the GPIO settings are overridden and PA0 and PA1 are disabled.

5 V Tolerance

All six I/O pins on the 8-pin devices are 5 V-tolerant, unless the programmable pull-ups are enabled. If the pull-ups are enabled and inputs higher than VDD are applied to these parts, excessive current flows through those pull-up devices and can damage the chip. In the 20- and 28-pin versions of this device, any pin which shares functionality with an ADC, crystal or comparator port is not 5 V-tolerant, including PA[1:0], PB[5:0], and Caution: Note:

VDD even with the pull-ups enabled. nterrupt Controller chapter on page 54. Four registers for each port provide access to GPIO control, input data, and output data. together to provide access to subregisters for port configuration and control. Table 18. GPIO Port Registers and Subregisters PxADDR Port A–C Address Register (Selects subregisters). PxCTL Port A–C Control Register (P rovides access to subregisters). PxIN Port A–C Input Data Register. PxOUT Port A–C Output Data Register. PxOC Output Control (Open-Drain).

vide access to all GPIO port controls (Table 19). PxSMRE Stop Mode Recovery Source Enable. PxAFS1 Alternate Function Set 1. PxAFS2 Alternate Function Set 2. Table 19. Port A–C GPIO Address Registers (PxADDR) The Port Address selects one of the subregisters accessible through the Port Control Register. See Table 20 for each subregister function. Table 20. PADDR[7:0] Subregister Functions 00H No function. Provides some protection against accidental Port reconfiguration. 03H Output Control (Open-Drain). Table 18. GPIO Port Registers and Subregisters (Continued)

a Port A–C Control Register transaction; see Table 21. 05H Stop Mode Recove ry Source Enable. 07H Alternate Function Set 1. 08H Alternate Function Set 2. Table 21. Port A–C Control Registers (PxCTL)

ter by writing 01H to the Port A–C Address Register; see Table 22. alternate function associated with each port pin. ternate function. Failure to follow this guideline can result in unpredictable operation. Table 22. Port A–C Data Direction Subregisters (PxDD) Address If 01H in Port A–C Address Register, accessible through the Port A–C Control Register. overrides the Data Direction register setting. 0 = Output. Data in the Port A–C Output Data Register is driven onto the port pin. 1 = Input. The port pin is sampled and the value written into the Port A–C Input Data Register. The output driver is tristated. Note: x indicates the specific GPIO port pin number (7–0).

Table 23. Port A–C Alternate Function Subregisters (PxAF) ter determines the direction of the pin. 1 = The alternate function selected through Alternate Function Set subregisters is enabled. Port pin operation is controlled by the alternate function. Note: x indicates the specific GPIO port pin number (7–0). Table 24. Port A–C Output Control Subregisters (PxOC) 0 = The drains are enabled for any output mode (unless overridden by the alternate function). 1 = The drain of the associated pin is disabled (open-drain mode). Note: x indicates the specific GPIO port pin number (7–0).

pins directly and, as a result, alternate functions are also affected. Table 25. Port A–C High Drive Enable Subregisters (PHDEx) 0 = The Port pin is configured for standard output current drive. 1 = The Port pin is configured for high output current drive. Note: x indicates the specific GPIO port pin number (7–0).

through the Port A–C Control Register by writing 05H to the Port A–C Address Register. Table 26. Port A–C Stop Mode Recovery Source Enable Subregisters (PSMREx) Port Stop Mode Recovery Source Enabled. ing STOP Mode do not initiate Stop Mode Recovery. during STOP Mode initiates Stop Mode Recovery. Note: x indicates the specific GPIO port pin number (7–0).

Table 27. Port A–C Pull-Up Enable Subregisters (PPUEx) 0 = The weak pull-up on the Port pin is disabled. 1 = The weak pull-up on the Port pin is enabled. Note: x indicates the specific GPIO port pin number (7–0).

C Alternate Function Subregisters section on page 43. Table 28. Port A–C Alternate Function Set 1 Subregisters (PAFS1x) Note: x indicates the specific GPIO port pin number (7–0).

section the GPIO Alternate Functions section on page 34. Table 29. Port A–C Alternate Function Set 2 Subregisters (PxAFS2) Alternate Functions section on page 34). 1 = Port Alternate Function selected as defined in Table 15. Note: x indicates the specific GPIO port pin number (7–0).

28-pin packages, as well as those missing on the ADC-enabled 28-pin packages. Table 30. Port A–C Input Data Registers (PxIN) Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High). Note: x indicates the specific GPIO port pin number (7–0).

The Port A–C Output Data Register (Table 31) controls the output data to the pins. The LED Drive Enable Register, shown in Table 32, activates the controlled current drive. [7:0] correspond to Port C bits [7:0], respectively. Table 31. Port A–C Output Data Register (PxOUT) 0 = Drive a logical 0 (Low). the corresponding Port Output Control Register bit to 1. Note: x indicates the specific GPIO port pin number (7–0). Table 32. LED Drive Enable (LEDEN) These bits determine which Port C pins are connected to an internal current sink. 0 = Tristate the Port C pin. 1= Connect controlled current sink to the Port C pin.

The LED Drive Level registers contain two control bits for each Port C pin (Table 33). Table 33. LED Drive Level High Register (LEDLVLH)

The LED Drive Level registers contain two control bits for each Port C pin (Table 34). Table 34. LED Drive Level Low Register (LEDLVLL) {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin.

PS024315-1011 P R E L I M I N A R Y Interrupt Controller Z8 Encore! XP® F0823 Series Product Specification Interrupt Controller The interrupt controller on the Z8 Encore! XP F0823 Series products prioritizes the inter- rupt requests from the on-chip peripherals and the GPIO port pins. The features of inter- rupt controller include:

20 unique interrupt vectors – 12 GPIO port pin interrupt sources (two are shared) – 8 on-chip peripheral interrupt sources (two are shared)
Flexible GPIO interrupts – Eight selectable rising and falling edge GPIO interrupts – Four dual-edge interrupts
Three levels of individually programmable interrupt priority
Watchdog Timer can be configured to generate an interrupt Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the CPU and the interrupting peripheral. When the service routine is com- pleted, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information about interrupt servicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128) available for download at www.zilog.com. Interrupt Vector Listing Table 35 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most-significant byte (MSB) at the even Program Memory address and the least-significant byte (LSB) at the following odd Program Memory address. Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is unavailable on devices not containing an ADC. Note:

Table 35. Trap and Interrupt Vectors in Order of Priority

Execution of an Return from Interrupt (IRET) instruction
Writing a 1 to the IRQE bit in the Interrupt Control Register Interrupts are globally disabled by any of the following actions:
Execution of a Disable Interrupt (DI) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
Execution of a Trap instruction
Illegal Instruction Trap
Primary Oscillator Fail Trap
Watchdog Timer Oscillator Fail Trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all interrupts are enabled with identical interrupt priority (for example, all as Level 2 inter- rupts), the interrupt priority is assigned from highest to lowest as specified in Table 35 on page 55. Level 3 interrupts are always assigned higher priority than Level 2 interrupts which, in turn, always are assigned higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2 or Level 3), priority is assigned as specified in

Table 35. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail Trap, and the final LDX command are lost. See Example 1, which follows.

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification Example 1. A poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt Request 0 Register: Example 2. A good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program code generates interrupts directly. Writing a 1 to the correct bit in the Interrupt Request register triggers an interrupt (assuming that interrupt is enabled). When the inter- rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is automatically cleared to 0. Zilog recommends not using a coding style to generate software interrupts by setting bits in the Interrupt Request registers. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 3, which fol- lows. Example 3. A poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt Request registers: Example 4. A good coding style that avoids lost interrupt requests: ORX IRQ0, MASK Watchdog Timer Interrupt Assertion The Watchdog Timer interrupt behavior is different from interrupts generated by other sources. The Watchdog Timer continues to assert an interrupt as long as the timeout condi- tion continues. As it operates on a different (and usually slower) clock domain than the rest of the device, the Watchdog Timer continues to assert this interrupt for many system clocks until the counter rolls over. Caution:

the RSTSTAT register until the WDT bit is cleared as shown in the following example. individual interrupts, set interrupt priorities, and indicate interrupt requests. Request 0 register to determine if any interrupt requests are pending. Table 36. Interrupt Request 0 Register (IRQ0) This bit is reserved and must be programmed to 0. 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. 0 = No interrupt request is pending for Timer 0. 1 = An interrupt request from Timer 0 is awaiting service.

Request 1 Register to determine if any interrupt requests are pending. 0 = No interrupt request is pending for the UART 0 receiver. 1 = An interrupt request from the UART 0 receiver is awaiting service. 0 = No interrupt request is pending for the UART 0 transmitter. 1 = An interrupt request from the UART 0 transmitter is awaiting service. These bits are reserved and must be programmed to 00. 0 = No interrupt request is pending for the ADC. 1 = An interrupt request from the ADC is awaiting service. Table 37. Interrupt Request 1 Register (IRQ1) 0 = No interrupt request is pending for GPIO Port A. 1 = An interrupt request from GPIO Port A. 0 = No interrupt request is pending for GPIO Port A or Comparator. 1 = An interrupt request from GPIO Port A or Comparator. 0 = No interrupt request is pending for GPIO Port A pin x. 1 = An interrupt request from GPIO Port A pin x is awaiting service. Note: x indicates the specific GPIO Port pin number (0–5).

Request 2 Register to determine if any interrupt requests are pending. rupt Request 0 Register. Priority is generated by setting bits in each register. Table 38. Interrupt Request 2 Register (IRQ2) These bits are reserved and must be programmed to 0000. 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. Note: x indicates the specific GPIO Port C pin number (3–0). Table 39. IRQ0 Enable and Priority Encoding Note: where x indicates the register bits from 0–7.

Table 40. IRQ0 Enable High Bit Register (IRQ0ENH) This bit is reserved and must be programmed to 0. These bits are reserved and must be programmed to 00. Table 41. IRQ0 Enable Low Bit Register (IRQ0ENL) This bit is reserved and must be programmed to 0 when read.

rupt Request 1 Register. Priority is generated by setting bits in each register. These bits are reserved and must be programmed to 00. Table 42. IRQ1 Enable and Priority Encoding Note: x indicates register bits 0–7.

Table 43. IRQ1 Enable High Bit Register (IRQ1ENH) Note: x indicates the specific GPIO Port A pin number (5–0). Table 44. IRQ1 Enable Low Bit Register (IRQ1ENL) Note: x indicates the specific GPIO Port A pin number (5–0).

rupt Request 2 register. Priority is generated by setting bits in each register. Table 45. IRQ2 Enable and Priority Encoding Note: where x indicates the register bits from 0–7. Table 46. IRQ2 Enable High Bit Register (IRQ2ENH) These bits are reserved and must be programmed to 0000.

Table 47. IRQ2 Enable Low Bit Register (IRQ2ENL) These bits are reserved and must be programmed to 0000. Table 48. Interrupt Edge Select Register (IRQES) 0 = An interrupt request is generated on the falling edge of the PAx input or PDx. 1 = An interrupt request is generated on the rising edge of the PAx input PDx. Note: x indicates the specific GPIO port pin number (7–0).

alternate sources for the individual interrupts. disabled before switching between sources. Table 49. Shared Interrupt Select Register (IRQSS) This bit is reserved and must be programmed to 0. 0 = PA6 is used for the interrupt for PA6CS interrupt request. 1 = The comparator is used as an interrupt for PA6CS interrupt requests. These bits are reserved and must be programmed to 000000.

Table 50. Interrupt Control Register (IRQCTL) 0 = Interrupts are disabled. These bits are reserved and must be programmed to 0000000 when read.

PS024315-1011 P R E L I M I N A R Y Timers Z8 Encore! XP® F0823 Series Product Specification Timers Z8 Encore! XP F0823 Series products contain up to two 16-bit reloadable timers that are used for timing, event counting or generation of PWM signals. The timers’ features include:

16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal; external input pin sig- nal frequency is limited to a maximum of one-fourth the system clock frequency
Timer output pin
Timer interrupt In addition to the timers described in this chapter, the baud rate generator of the UART (if unused) also provides basic timing functionality. For information about using the baud rate generator as an additional timer, see the Universal Asynchronous Receiver/Transmit- ter chapter on page 97.

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state for one system clock cycle (from Low to High or from High to Low) upon timer reload. If it is appropriate to have the Timer Output make a state change at a One-Shot time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT Mode. After starting the timer, set TPOL to the opposite bit value. Observe the following steps to configure a timer for ONE-SHOT Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for ONE-SHOT Mode – Set the prescale value – Set the initial output level (High or Low) if using the Timer Output alternate func- tion 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In ONE-SHOT Mode, the system clock always provides the timer input. The timer period is computed via the following equation: CONTINUOUS Mode In CONTINUOUS Mode, the timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reload. Observe the following steps to configure a timer for CONTINUOUS Mode and to initiate the count: ONE-SHOT Mode Time-Out Period (s) Reload Value S tart Value– Prescale

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CONTINUOUS Mode – Set the prescale value – If using the Timer Output alternate function, set the initial output level (High or Low) 2. Write to the Timer High and Low Byte regist ers to set the starting count value (usually 0001H). This action only affects the first pass in CONTINUOUS Mode. After the first timer reload in CONTINUOUS Mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Enable the timer interrupt (if appropriate) an d set the timer interrupt priority by writ- ing to the relevant interrupt registers. 5. Configure the associated GPIO port pin (i f using the Timer Output function) for the Timer Output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In CONTINUOUS Mode, the system clock always provides the timer input. The timer period is computed via the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT Mode equation to determine the first time-out period. COUNTER Mode In COUNTER Mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO port pin Timer Input alternate function. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the timer input signal. In COUNTER Mode, the prescaler is disabled. The input frequency of the timer input signal must not exceed one-fourth the system clock frequency. Upon reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is CONTINUOUS Mode Time-Out Period (s) Reload Value Prescale Caution:

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reload. Observe the following steps to configure a timer for COUNTER Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer. – Configure the timer for COUNTER Mode. – Select either the rising edge or falling edge of the Timer Input signal for the count. This selection also sets the initial logic level (High or Low) for the Timer Output alternate function. Ho wever, the Timer Output func tion is not required to be enabled. 2. Write to the Timer High and Low Byte regi sters to set the starting count value. This only affects the first pass in COUNTER Mode. After the first timer reload in COUN- TER Mode, counting always begins at the reset value of 0001H. In COUNTER Mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control Re gister to enable the timer. In COUNTER Mode, the number of timer input transitions since the timer start is com- puted via the following equation: COMPARATOR COUNTER Mode In COMPARATOR COUNTER Mode, the timer counts input transitions from the analog comparator output. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. In COMPAR- ATOR COUNTER Mode, the prescaler is disabled. COUNTER Mode Timer Input Transitions Current Count Value Start Value–=

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification The frequency of the comparator output signal must not exceed one-fourth the system clock frequency. After reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reload. Observe the following steps to configure a timer for COMPARATOR COUNTER Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer. – Configure the timer for COMPARATOR COUNTER Mode. – Select either the rising edge or falling edge of the comparator output signal for the count. This also sets the initial logic le vel (High or Low) for the Timer Output alternate function. Ho wever, the Timer Output func tion is not required to be enabled. 2. Write to the Timer High and Low Byte regi sters to set the starting count value. This action only affects the first pass in COMPARATOR COUNTER Mode. After the first timer reload in COMPARATOR COUNTER Mode, counting always begins at the reset value of 0001H. Generally, in COMPARATOR COUNTER Mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control Re gister to enable the timer. In COMPARATOR COUNTER Mode, the number of comparator output transitions since the timer start is computed via the following equation: Caution: Comparator Output Transitions Current Count Value Start Value–=

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT Mode, the timer outputs a PWM output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the reload value and is reset to 0001H. If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the reload value and is reset to 0001H. Observe the following steps to configure a timer for PWM Single Output mode and initiat- ing the PWM operation: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for PWM Mode – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H); this write only affects the first pass in PWM Mode. After the first timer reset in PWM Mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 5. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. The PWM period is represented by the following equation:

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is represented by the following equation: If TPOL is set to 1, the ratio of the PWM output High time to the total period is represented by the following equation: PWM Dual Output Mode In PWM DUAL OUTPUT Mode, the timer outputs a PWM output signal pair (basic PWM signal and its complement) through two GPIO port pins. The timer input is the sys- tem clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the reload value and is reset to 0001H. If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the reload value and is reset to 0001H. The timer also generates a second PWM output signal Timer Output Complement. The Timer Output Complement is the complement of the Timer Output PWM signal. A pro- grammable deadband delay can be configured to time delay (0 to 128 system clock cycles) PWM output transitions on these two pins from a low to a high (inactive to active). This ensures a time gap between the deassertion of one PWM output to the assertion of its com- plement. PWM Period (s) Reload Value Prescale PWM Output High Time Ratio (%) Reload Value PWM Value– PWM Output High Time Ratio (%) PWM Value

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification Observe the following steps to configure a timer for PWM DUAL OUTPUT Mode and initiating the PWM operation: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for PWM DUAL OUTPUT Mode. Setting the mode also involves writing to the TMODEHI bit in the TxCTL1 Register – Set the prescale value – Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H); this write only affects the first pass in PWM Mode. After the first timer reset in PWM Mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the PWM Control Register to set the PWM dead band delay value. The dead- band delay must be less than the duration of the positive phase of the PWM signal (as defined by the PWM high and low byte registers). It must also be less than the dura- tion of the negative phase of the PWM signal (as defined by the difference between the PWM registers and the Timer Reload registers). 5. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM period). The reload value must be greater than the PWM value. 6. If appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. Configure the associated GPIO port pin fo r the Timer Output and Timer Output Com- plement alternate functions. The Timer Output Complement function is shared with the Timer Input function for both timers. Setting the timer mode to Dual PWM auto- matically switches the function from Timer In to Timer Out Complement. 8. Write to the Timer Control Register to enable the timer and initiate counting. The PWM period is represented by the following equation: If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT Mode equation determines the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is represented by: PWM Period (s) Reload Value Prescale

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification If TPOL is set to 1, the ratio of the PWM output High time to the total period is represented by: CAPTURE Mode In CAPTURE Mode, the current timer count value is recorded when the appropriate exter- nal Timer Input transition occurs. The capture count value is written to the Timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer Control Register determines if the capture occurs on a rising edge or a falling edge of the Timer Input signal. When the capture event occurs, an interrupt is generated and the timer continues counting. The INPCAP bit in TxCTL1 Register is set to indicate the timer interrupt is because of an input capture event. The timer continues counting up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an inter- rupt and continues counting. The INPCAP bit in TxCTL1 Register clears indicating the timer interrupt is not because of an input capture event. Observe the following steps to configure a timer for CAPTURE Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE Mode – Set the prescale value – Set the capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these registers allows the software to determine if interrupts were generated by either a capture or a reload event. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a reload. 5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both PWM Output High Time Ratio (%) Reload Value PWM Value– PWM Output High Time Ratio (%) PWM Value

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification input capture and reload events. If appropriate, configure the timer interrupt to be gen- erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL1 Register. 6. Configure the associated GPIO port pi n for the Timer Input alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. In CAPTURE Mode, the elapsed time from timer start to capture event can be calculated using the following equation: CAPTURE RESTART Mode In CAPTURE RESTART Mode, the current timer count value is recorded when the acceptable external Timer Input transition occurs. The capture count value is written to the Timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer Control Register determines if the capture occurs on a rising edge or a fall- ing edge of the Timer Input signal. When the capture event occurs, an interrupt is gener- ated and the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL1 Register is set to indicate the timer inter- rupt is because of an input capture event. If no capture event occurs, the timer counts up to the 16-bit compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL1 Register is cleared to indicate the timer interrupt is not caused by an input capture event. Observe the following steps to configure a timer for CAPTURE RESTART Mode and ini- tiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE R ESTART Mode; setting the mode also involves writing to TMODEHI bit in TxCTL1 Register – Set the prescale value – Set the capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the reload value. Capture Elapsed Time (s) Capture Value Start Value– Prescale

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these registers allows the software to determine if interrupts were generated by either a capture or a reload event. If the PWM High and Low Byte registers still contain 0000H after the interrupt, the interrupt was generated by a reload. 5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt to be gen- erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL1 Register. 6. Configure the associated GPIO port pi n for the Timer Input alternate function. 7. Write to the Timer Control Register to enable the timer and initiate counting. In CAPTURE Mode, the elapsed time from timer start to capture event can be calculated using the following equation: COMPARE Mode In COMPARE Mode, the timer counts up to the 16-bit maximum compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon com- pare. If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. Observe the following steps to configure a timer for COMPARE Mode and to initiate the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for COMPARE Mode – Set the prescale value – Set the initial logic level (High or Low) for the Timer Output alternate function, if appropriate 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the compare value. 4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. Capture Elapsed Time (s) Capture Value Start Value– Prescale

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control Register to enable the timer and initiate counting. In COMPARE Mode, the system clock always provides the timer input. The compare time can be calculated by the following equation: GATED Mode In GATED Mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control Register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal remains asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset. Observe the following steps to configure a timer for GATED Mode and to initiate the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for Gated mode – Set the prescale value 2. Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED Mode. After the first timer reset in GATED Mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input deassertion and reload events. If appropriate, configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting TICONFIG field of the TxCTL1 Register. COMPARE Mode Time (s) Compare Value Start Value– Prescale

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. Write to the Timer Control Re gister to enable the timer. 7. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE Mode, the timer begins counting on the first external Timer Input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control Register. The timer input is the system clock. Every subsequent acceptable transition (after the first) of the Timer Input signal captures the current count value. The capture value is written to the Timer PWM High and Low Byte registers. When the capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. The INPCAP bit in TxCTL1 Register is set to indicate the timer interrupt is caused by an input capture event. If no capture event occurs, the timer counts up to the 16-bit compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The INPCAP bit in TxCTL1 Register is cleared to indicate the timer interrupt is not because of an input capture event. Observe the following steps to configure a timer for CAPTURE/COMPARE Mode and initiating the count: 1. Write to the Timer Control Register to: – Disable the timer – Configure the timer for CAPTURE/COMPARE Mode – Set the prescale value – Set the capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte regi sters to set the starting count value (typi- cally 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the compare value. 4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers.By default, the timer interrupt are generated for both input capture and reload events. If appropriate, configure the timer interrupt to be gen- erated only at the input capture event or the reload event by setting TICONFIG field of the TxCTL1 Register. 5. Configure the associated GPIO port pi n for the Timer Input alternate function. 6. Write to the Timer Control Re gister to enable the timer.

PS024315-1011 P R E L I M I N A R Y Timer Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 7. Counting begins on the first appropriate transition of the Timer Input signal. No inter- rupt is generated by this first edge. In CAPTURE/COMPARE Mode, the elapsed time from timer start to capture event can be calculated using the following equation: Reading the Timer Count Values The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte Reg- ister is read, the contents of the Timer Low Byte register are placed in a holding register. A subsequent read from the Timer Low Byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte register returns the actual value in the counter. Timer Pin Signal Operation Timer Output is a GPIO port pin alternate function. The Timer Output is toggled every time the counter is reloaded. The timer input can be used as a selectable counting source. It shares the same pin as the complementary timer output. When selected by the GPIO Alternate Function registers, this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT mode. For this mode, there is no timer input available. Timer Control Register Definitions This section defines the features of the following Timer Control registers. Timer 0–1 High and Low Byte Registers: see page 83 Timer Reload High and Low Byte Registers: see page 84 Timer 0–1 PWM High and Low Byte Registers: see page 86 Timer 0–1 Control Registers: see page 86 Timer 0–1 High and Low Byte Registers The Timer 0–1 High and Low Byte (TxH and TxL) registers (Table 51 and Table 52) con- tain the current 16-bit timer count value. When the timer is enabled, a read from TxH Capture Elapsed Time (s) Capture Value Start Value– Prescale System Clock Frequency (Hz)

abled, reads from the TxL reads the register directly. Byte) at the next clock edge. The counter continues counting from the new value. store the 16-bit compare value. Table 51. Timer 0–1 High Byte Register (TxH) Table 52. Timer 0–1 Low Byte Register (TxL) These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.

these two bytes form the 16-bit compare value. Table 53. Timer 0–1 Reload High Byte Register (TxRH) Table 54. Timer 0–1 Reload Low Byte Register (TxRL)

the capture values for the CAPTURE and CAPTURE/COMPARE modes. Table 55. Timer 0–1 PWM High Byte Register (TxPWMH) Table 56. Timer 0–1 PWM Low Byte Register (TxPWML) ating in CAPTURE or CAPTURE/COMPARE modes.

recent timer interrupt is caused by an input capture event. value, and determine the timer operating mode. Table 57. Timer 0–1 Control Register 0 (TxCTL0) the timer. This is the most-significant bit of the Timer mode selection value. This field configures timer interrupt definition. 0x = Timer Interrupt occurs on all defined reload, compare and input events. 10 = Timer Interrupt only on defined input capture/deassertion events. 11 = Timer Interrupt only on defined reload/compare events. This bit is reserved and must be programmed to 0. before the Timer Output and the Timer Output Complement are forced to their active state. This bit indicates if the most recent timer interrupt is caused by a Timer Input capture event. 0 = Previous timer interrupt is not a result of Timer Input capture event. 1 = Previous timer interrupt is a result of Timer Input capture event.

Table 58. Timer 0–1 Control Register 1 (TxCTL1) Operation of this bit is a function of the current operating mode of the timer. timer is enabled, the Timer Output signal is complemented upon timer reload. timer is enabled, the Timer Output signal is complemented upon timer reload.

PS024315-1011 P R E L I M I N A R Y Timer Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification [6] TPOL (cont’d.) COUNTER Mode If the timer is enabled the Timer Output signal is complemented after timer reload. 0 = Count occurs on the rising edge of the Timer Input signal. 1 = Count occurs on the falling edge of the Timer Input signal. PWM SINGLE OUTPUT Mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Out- put is forced Low (0) upon PWM count match and forced High (1) upon reload. CAPTURE Mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer reload. GATED Mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE Mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal. PWM DUAL OUTPUT Mode 0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon reload. When enabled, the Timer Output Complement is forced Low (0) upon PWM count match and forced High (1) upon reload. The PWMD field in TxCTL0 register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to High (1). 1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon reload.When enabled, the Timer Output Complement is forced High (1) upon PWM count match and forced Low (0) upon reload. The PWMD field in TxCTL0 register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to Low (0). CAPTURE RESTART Mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. Bit Description (Continued)

PS024315-1011 P R E L I M I N A R Y Timer Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification [6] TPOL (cont’d.) COMPARATOR COUNTER Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer reload. Caution: When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, TxOUT changes to whatever state the TPOL bit is in. The timer does not need to be enabled for that to happen. Also, the port data direction sub register is not needed to be set to output on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT. [5:3] PRES Prescale Value The timer input clock is divided by 2 PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the timer is disabled. This reset ensures proper clock division each time the timer is restarted. 000 = Divide by 1. 001 = Divide by 2. 010 = Divide by 4. 011 = Divide by 8. 100 = Divide by 16. 101 = Divide by 32. 110 = Divide by 64. 111 = Divide by 128. [2:0] TMODE Timer Mode This field, along with the TMODEHI bit in TxCTL0 Register, determines the operating mode of the timer. TMODEHI is the most significant bit of the timer mode selection value. 0000 = ONE-SHOT Mode. 0001 = CONTINUOUS Mode. 0010 = COUNTER Mode. 0011 = PWM SINGLE OUTPUT Mode. 0100 = CAPTURE Mode. 0101 = COMPARE Mode. 0110 = GATED Mode. 0111 = CAPTURE/COMPARE Mode. 1000 = PWM DUAL OUTPUT Mode. 1001 = CAPTURE RESTART Mode. 1010 = COMPARATOR COUNTER Mode. Bit Description (Continued)

On-chip RC oscillator
A selectable time-out response: reset or interrupt
24-bit programmable time-out value Operation The WDT is a retriggerable one-shot timer that resets or interrupts F0823 Series devices when the WDT reaches its terminal count. The Watchdog Timer uses a dedicated on-chip RC oscillator as its clock source. The Watchdog Timer operates in only two modes: ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. Per- form an enable by executing the WDT instruction or by setting the WDT_AO Flash Option Bit. The WDT_AO bit forces the Watchdog Timer to operate immediately upon reset, even if a WDT instruction has not been executed. The Watchdog Timer is a 24-bit reloadable down counter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is described by the following equation: where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator frequency is 10 kHz. The Watchdog Timer cannot be refreshed after it reaches 000002H. The WDT Reload Value must not be set to values below 000004H. Table 59 provides information about approximate time-out delays for the minimum and maximum WDT reload values.

Table 59. Watchdog Timer Approximate Time-Out Delays

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification Watchdog Timer Refresh When first enabled, the WDT is loaded with the value in the Watchdog Timer Reload reg- isters. The Watchdog Timer counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the down counter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload registers. Counting resumes following the reload operation. When Z8 Encore! XP F0823 Series devices are operating in DEBUG Mode (using the OCD), the Watchdog Timer is continuously refreshed to prevent any Watchdog Timer time-outs. Watchdog Timer Time-Out Response The Watchdog Timer times out when the counter reaches 000000H. A time-out of the Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash Option Bit determines the time-out response of the Watchdog Timer. For information about programming of the WDT_RES Flash Option Bit, see the Flash Option Bits chapter on page 146. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog Timer Control Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executing code from the vec- tor address. After time-out and interrupt generation, the Watchdog Timer counter rolls over to its maximum value of FFFFFH and continues counting. The Watchdog Timer counter is not automatically returned to its Reload Value. The Reset Status Register (see the Reset Status Register section on page 28) must be read before clearing the WDT interrupt. This read clears the WDT time-out Flag and prevents further WDT interrupts for immediately occurring. WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and F0823 Series are in STOP Mode, the Watchdog Timer automatically initiates a Stop Mode Recovery and gen- erates an interrupt request. Both the WDT status bit and the STOP bit in the Watchdog Timer Control Register are set to 1 following a WDT time-out in STOP Mode. For more information about Stop Mode Recovery, see the Reset and Stop Mode Recovery chapter on page 21. If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe- cuting code from the vector address.

PS024315-1011 P R E L I M I N A R Y Watchdog Timer Control Register Z8 Encore! XP® F0823 Series Product Specification WDT Reset in NORMAL Operation If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Watchdog Timer Control Register is set to 1. For more information about System Reset, see the Reset and Stop Mode Recovery chapter on page 21. WDT Reset in STOP Mode If configured to generate a Reset when a time-out occurs and the device is in STOP Mode, the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the STOP bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in STOP Mode. For more information, see the Reset and Stop Mode Recovery chapter on page 21. Watchdog Timer Reload Unlock Sequence Writing the unlock sequence to the Watchdog Timer Control Register (WDTCTL) address unlocks the three Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL Register address produce no effect on the bits in the WDTCTL Register. The locking mechanism prevents spurious writes to the Reload registers. The following sequence is required to unlock the Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL) for write access. 1. Write 55H to the Watchdog Timer Control Register (WDTCTL). 2. Write AAH to the Watchdog Timer Control Register (WDTCTL). 3. Write the Watchdog Timer Reload Upper Byte register (WDTU). 4. Write the Watchdog Timer Reload High Byte register (WDTH). 5. Write the Watchdog Timer Relo ad Low Byte register (WDTL). All three Watchdog Timer Reload registers must be written in the order just listed. There must be no other register writes between each of these operations. If a register write occurs, the lock state machine resets and no further writes can occur unless the sequence is restarted. The value in the Watchdog Timer Reload registers is loaded into the counter when the Watchdog Timer is first enabled and every time a WDT instruction is executed. Watchdog Timer Control Register Definitions This section defines the features of the following Watchdog Timer Control registers. Watchdog Timer Control Register (WDTCTL): see page 94 Watchdog Timer Reload Upper Byte Register (WDTU): see page 95

writes to the Reload registers. This register address is shared with the read-only Reset Status Register. returns the current Watchdog Timer count value. The 24-bit WDT Reload Value must not be set to a value less than 000004H. Table 60. Watchdog Timer Control Register (WDTCTL) to modify the contents of the Watchdog Timer reload registers.

Table 61. Watchdog Timer Reload Upper Byte Register (WDTU) Note: R/W*—Read returns the current WDT count val ue. Write sets the appropriate Reload Value. Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value. Table 62. Watchdog Timer Reload High Byte Register (WDTH) Note: R/W*—Read returns the current WDT count val ue. Write sets the appropriate Reload Value. Middle byte, Bits[15:8], of the 24-bit WDT reload value. Table 63. Watchdog Timer Reload Low Byte Register (WDTL) Note: R/W*—Read returns the current WDT count val ue. Write sets the appropriate Reload Value.

PS024315-1011 P R E L I M I N A R Y Watchdog Timer Control Register Z8 Encore! XP® F0823 Series Product Specification Bit Description [7:0] WDTL WDT Reload Low Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.

PS024315-1011 P R E L I M I N A R Y Universal Asynchronous Receiver/ Z8 Encore! XP® F0823 Series Product Specification Universal Asynchronous Receiver/ Transmitter The universal asynchronous receiver/transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. The features of UART include:

8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two STOP bits
Separate transmit and receive interrupts
Framing, parity, overrun, and break detection
Separate transmit and receive enables
16-bit baud rate generator (BRG)
Selectable MULTIPROCESSOR (9-bit) Mode with three configurable interrupt schemes
BRG can be configured and used as a basic 16-bit timer
Driver Enable output for external bus transceivers Architecture The UART consists of three primary functional blocks: transmitter, receiver, and baud rate generator. The UART’s transmitter and receiver function independently, but employ the same baud rate and data format. Figure 10 displays the UART architecture.

ity and with parity, respectively. Figure 10. UART Block Diagram

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 100 – Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin 6. Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data Register is empty (indicated by a 1). If empty, continue to Step 7. If the Transmit Data Register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data Register becomes available to receive new data. 7. Write the UART Control 1 Register to select the outgoing address bit. 8. Set the Multiprocessor Bit Transmitter ( MPBT) if sending an address byte, clear it if sending a data byte. 9. Write the data byte to the UART Transm it Data Register. The transmitter automati- cally transfers the data to the Transmit Shift register and transmits the data. 10. Make any changes to the Multiprocessor Bit Transmitter (MPBT) value, if appropriate and MULTIPROCESSOR Mode is enabled,. 11. To transmit additional bytes, return to Step 5. Transmitting Data Using the Interrupt-Driven Method The UART Transmitter interrupt indicates the availability of the Transmit Data Register to accept new data for transmission. Observe the following steps to configure the UART for  interrupt-driven data transmission: 1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud rate. 2. Enable the UART pin functions by config uring the associated GPIO port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the acceptable priority. 5. Write to the UART Control 1 Register to enable MULTIPROCESSOR (9-bit) Mode functions, if MULTIPROCESSOR Mode is appropriate. 6. Set the MULTIPROCESSOR Mode Select ( MPEN) to Enable MULTIPROCESSOR Mode. 7. Write to the UART Control 0 Register to: – Set the transmit enable bit (TEN) to enable the UART for data transmission. – Enable parity, if appropriate and if MULTIPROCESSOR Mode is not enabled, and select either even or odd parity.

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 101 – Set or clear CTSE to enable or disable control fro m the remote receiver using the CTS pin. 8. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data Register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write the UART Control 1 Register to select the multiprocessor bit for the byte to be transmitted: Set the Multiprocessor Bit Transmitter ( MPBT) if sending an address byte, clear it if sending a data byte. 2. Write the data byte to the UART Transm it Data Register. The transmitter automati- cally transfers the data to the Transmit Shift register and transmits the data. 3. Clear the UART Transmit interrupt bit in th e applicable Interrupt Request register. 4. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data Register to again become empty. Receiving Data Using the Polled Method Observe the following steps to configure the UART for polled data reception: 1. Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud rate for the incoming data stream. 2. Enable the UART pin functions by config uring the associated GPIO port pins for alternate function operation. 3. Write to the UART Control 1 Register to enable MULTIPROCESSOR Mode func- tions, if appropriate. 4. Write to the UART Control 0 Register to: – Set the receive enable bit (REN) to enable the UART for data reception – Enable parity, if appropriate and if Multiprocessor mode is not enabled, and select either even or odd parity 5. Check the RDA bit in the UART Status 0 Register to determine if the Receive Data Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 6. If the Receive Data Register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data. 6. Read data from the UART Receive Data Register. If operating in MULTIPROCES- SOR (9-bit) Mode, further actions may be required depending on the MULTIPRO- CESSOR Mode bits MPMD[1:0].

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 102 7. Return to Step 4 to receive additional data. Receiving Data Using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error condi- tions). Observe the following steps to configure the UART receiver for interrupt-driven operation: 1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud rate. 2. Enable the UART pin functions by config uring the associated GPIO port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the acceptable priority. 5. Clear the UART Receiver interrupt in th e applicable Interrupt Request register. 6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode func- tions, if appropriate. – Set the Multiprocessor Mode Select ( MPEN) to Enable MULTIPROCESSOR Mode – Set the Multiprocessor Mode Bits, MPMD[1:0], to select the acceptable address matching scheme – Configure the UART to interrupt on received data and errors or errors only (inter- rupt on errors only is unlikel y to be useful for Z8 En core! XP devices without a DMA block) 7. Write the device address to the Address Compare Register (automatic MULTIPRO- CESSOR modes only). 8. Write to the UART Control 0 Register to: – Set the receive enable bit ( REN) to enable the UART for data reception – Enable parity, if appropriate and if multip rocessor mode is not enabled, and select either even or odd parity 9. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following:

Checks the UART Status 0 Register to dete rmine the source of the interrupt - error,
Reads the data from the UART Receive Data Register if the interrupt was because of

be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0].

Clears the UART Receiver interrupt in the applicable Interrupt Request register.
Executes the IRET instruction to return from the interrupt-service routine and await

in the middle of a character transmission, the current character is sent completely. Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 104 scheme is enabled, the UART Address Compare register holds the network address of the device. MULTIPROCESSOR (9-bit) Mode Receive Interrupts When MULTIPROCESSOR Mode is enabled, the UART only processes frames addressed to it. The determination of whether a frame of data is addressed to the UART can be made in hardware, software or some combination of the two, depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, because it does not require access to the UART when it receives data directed to other devices on the multi-node network. The following three MULTIPROCESSOR modes are available in hardware:

Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all multi- processor modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software clears MPMD[0]. Each new incoming byte interrupts the CPU. The software is responsible for determining the end of the frame. It checks for the end-of-frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX = 1, a new frame has begun. If the address of this new frame is different from the UART’s address, MPMD[0] must be set to 1 causing the UART inter- rupts to go inactive until the next address byte. If the new frame’s address matches the UART’s, the data in the new frame is processed as well. The second scheme requires the following: set MPMD[1:0] to 10B and write the UART’s address into the UART Address Compare register. This mode introduces additional hard- ware control, interrupting only on frames that match the UART’s address. When an incoming address byte does not match the UART’s address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an inter- rupt is issued and further interrupts now occur on each successive data byte. When the first data byte in the frame is read, the NEWFRM bit of the UART Status 1 Register is asserted. All successive data bytes have NEWFRM = 0. When the next address byte occurs, the hard- ware compares it to the UART’s address. If there is a match, the interrupts continues and the NEWFRM bit is set for the first byte of the new frame. If there is no match, the UART ignores all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s address into the UART Address Compare Register. This mode is identical to the second

frame remains accompanied by a NEWFRM assertion. ceiver when communicating on a multi-transceiver bus, such as RS-485. tion as a basic timer with interrupt capability. Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 106 Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit (TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans- mission. The TDRE interrupt occurs after the Transmit shift register has shifted the first bit of data out. The Transmit Data Register can now be written with the next character to send. This action provides 7 bit periods of latency to load the Transmit Data Register before the Transmit shift register completes shifting the current character. Writing to the UART Transmit Data Register clears the TDRE bit to 0. Receiver Interrupts The receiver generates an interrupt when any of the following occurs:

A data byte is received and is available in the UART Receive Data Register. This inter- rupt can be disabled independently of the other receiver interrupt sources. The received data interrupt occurs after the receive character has been received and placed in the Re- ceive Data Register. To avoid an overrun error, software must respond to this received data available condition before the next character is completely received. In MULTIPROCESSOR Mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte.
A break is received
An overrun is detected
A data framing error is detected UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data Register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 Register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data Register contains a data byte. However, because the overrun error  DE to Start Bit Setup Time (s) 2  Note:

PS024315-1011 P R E L I M I N A R Y UART Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 108 Baud Rate Generator Interrupts If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This condition allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed. UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans- mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data rate is calculated using the following equation: When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit timer with interrupt on time-out. Observe the following steps to configure the Baud Rate Gener- ator as a timer with interrupt on time-out: 1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register to 0. 2. Load the acceptable 16-bit count value into the UART Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer fu nction and associated interrupt by setting the BIRQ bit in the UART Control 1 Register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation: UART Control Register Definitions The UART control registers support the UART and the associated infrared encoder/decod- ers. For more information about the infrared operation, see the Infrared Encoder/Decoder chapter on page 117. UART Data Rate (bits/s) System Clock Frequency (Hz) Interrupt Interval (s) Syste m Clock Period (s) BRG[15:0]=

with the read-only UART Receive Data Register. with the Write-only UART Transmit Data Register. Table 64. UART Transmit Data Register (U0TXD) UART transmitter data byte to be shifted out through the TXDx pin. Table 65. UART Receive Data Register (U0RXD) UART receiver data byte from the RXDx pin.

UART operating configuration and status. Table 66. UART Status 0 Register (U0STAT0) Receive Data Register clears this bit. 0 = The UART Receive Data Register is empty. 1 = There is a byte in the UART Receive Data Register. 0 = No parity error has occurred. 1 = A parity error has occurred. reading the UART Receive Data Register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data Register clears this bit. 0 = No framing error occurred. 1 = A framing error occurred. bit(s) are all 0s this bit is set to 1. Reading the UART Receive Data Register clears this bit.

This register contains multiprocessor control and status bits. This bit indicates that the UART Transmit Data Register is empty and ready for additional data. Writing to the UART Transmit Data Register resets this bit. 0 = Do not write to the UART Transmit Data Register. 1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted. This bit indicates that the transmit shift register is empty and character transmission is finished. 0 = Data is currently transmitting. 1 = Transmission is complete. When this bit is read, it returns the level of the CTS signal. This signal is active Low. Table 67. UART Status 1 Register (U0STAT1) 0 = The current byte is not the first data byte of a new frame. 1 = The current byte is the first data byte of a new frame. Receive Data Register resets this bit to 0.

must not be written while the UART is enabled. Table 68. UART Control 0 Register (U0CTL0) and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is enabled. This bit enables or disables the receiver. signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. This bit enables or disables parity. Even or odd is determined by the PSEL bit. 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. progress, so ensure that the transmitter has finished sending data before setting this bit. 1 = Forces a break condition by setting the output of the transmitter to zero.

0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits. 1 = All transmitted data is looped back to the receiver. Table 69. UART Control 1 Register (U0CTL1) If MULTIPROCESSOR (9-bit) Mode is enabled. 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. recent address byte matched the value in the Address Compare Register. This bit is used to enable MULTIPROCESSOR (9-bit) Mode. 0 = Disable MULTIPROCESSOR (9-bit) Mode. 1 = Enable MULTIPROCESSOR (9-bit) Mode. 0 = Send a 0 in the multiprocessor bit location of the data stream (data byte). 1 = Send a 1 in the multiprocessor bit location of the data stream (address byte). 0 = DE signal is Active High. 1 = DE signal is Active Low.

PS024315-1011 P R E L I M I N A R Y UART Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 114 [2] BRGCTL Baud Rate Control This bit causes an alternate UART behavior depending on the value of the REN bit in the UART Control 0 Register. When the UART receiver is not enabled (REN=0), this bit determines whether the Baud Rate Generator issues interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate Reg- isters to return the BRG count value instead of the Reload Value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High Byte is read. [1] RDAIRQ Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Con- troller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request. [0] IREN Infrared Encoder/Decoder Enable 0 = Infrared encoder/decoder is disabled. UART operates normally. 1 = Infrared encoder/decoder is enabled. The UART transmits and receives data through the infrared encoder/decoder. Bit Description (Continued)

The UART Address Compare Register stores the multinode network address of the UART. RDA assertions only occur in the event of a match. Table 70. UART Address Compare Register (U0ADDR) This 8-bit value is compared to incoming address bytes. Table 71. UART Baud Rate High Byte Register (U0BRH) Table 72. UART Baud Rate Low Byte Register (U0BRL)

For reliable communication, the UART baud rate error must never exceed five percent. Table 73 provides information about data rate errors for a 5.5296 MHz System Clock. Table 73. UART Baud Rates

5.5296 MHz System Clock

1250.0 N/A N/A N/A

625.0 N/A N/A N/A

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 118 passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART’s baud rate generator and supports IrDA standard baud rates from 9600 baud to 115.2 kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to use the infrared endec. The infrared endec data rate is calculated using the following equation: Transmitting IrDA Data The data to be transmitted using the infrared transceiver is first sent to the UART. The UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared data bit is 16 clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low for the full 16 clock period. If the data to be transmitted is 0, the transmitter first out- puts a 7 clock low period, followed by a 3 clock high pulse. Finally, a 6 clock low pulse is output to complete the full 16 clock data period. Figure 17 displays IrDA data transmis- sion. When the infrared endec is enabled, the UART’s TXD signal is internal to Z8 Encore! XP F0823 Series products while the IR_TXD signal is output through the TXD pin. Figure 17. Infrared Data Transmission Infrared Data Rate (bits/s) System Clock Frequency (Hz) Baud Rate IR_TXD UART’s 16 clock period Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1 7-clock delay 3 clock pulse TXD Clock

UART. Each UART/Infrared data bit is 16-clocks wide. Figure 18 displays data reception. XP F0823 Series products while the IR_RXD signal is received through the RXD pin. 1.4 µs minimum width pulses allowed by the IrDA standard. reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. Figure 18. IrDA Data Reception

PS024315-1011 P R E L I M I N A R Y Infrared Encoder/Decoder Control Register Z8 Encore! XP® F0823 Series Product Specification 120 The window remains open until the count again reaches 8 (that is, 24 baud clock periods since the previous pulse was detected), giving the endec a sampling window of minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the endec clock counter is reset, resynchronizing the endec to the incoming signal, allowing the endec to tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchro- nized to the incoming data stream when a Start bit is received. Infrared Encoder/Decoder Control Register Definitions All infrared endec configuration and status information is set by the UART control regis- ters as defined in the Universal Asynchronous Receiver/Transmitter chapter on page 97. To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART Control 1 Register to 1 to enable the endec before enabling the GPIO port alternate func- tion for the corresponding pin. Caution:

PS024315-1011 P R E L I M I N A R Y Analog-to-Digital Converter Z8 Encore! XP® F0823 Series Product Specification 121 Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) converts an analog input signal to its digital rep- resentation. The features of this sigma-delta ADC include:

10-bit resolution
Eight single-ended analog input sources are multiplexed with general-purpose I/O ports
Interrupt upon conversion complete
Bandgap generated internal voltage reference generator with two selectable levels
Factory offset and gain calibration Architecture Figure 19 displays the major functional blocks of the ADC. An analog multiplexer net- work selects the ADC input from the available analog pins, ANA0 through ANA7.

generally ranges from 0 to +1023, but offset errors can cause small negative values. Figure 19. Analog-to-Digital Converter Block Diagram

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 123 Automatic Powerdown If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of the ADC are automatically powered down. From this powerdown state, the ADC requires 40 system clock cycles to powerup. The ADC powers up when a conversion is requested by the ADC Control Register. Single-Shot Conversion When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. Observe the following steps for setting up the ADC and initiating a sin- gle-shot conversion: 1. Enable the acceptable analog inputs by co nfiguring the general-purpose I/O pins for alternate function. This configuration disables the digital input and output drivers. 2. Write the ADC Control/Status Register 1 to configure the ADC – Write the REFSELH bit of the pair { REFSELH, REFSELL} to select the internal voltage reference level or to disa ble the internal reference. The REFSELH bit is contained in the ADC Control/Status Register 1. 3. Write to the ADC Control Register 0 to configure the ADC and begin the conversion. The bit fields in the ADC Control Register can be written simultaneously: – Write to the ANAIN[3:0] field to select from the available analog input sources (different input pins available depending on the device). – Clear CONT to 0 to select a single-shot conversion. – If the internal voltage reference mu st be output to a pin, set the REFEXT bit to 1. The internal voltage reference must be enabled in this case. – Write the REFSELL bit of the pair { REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELL bit is contained in the ADC Control Register 0. – Set CEN to 1 to start the conversion. 4. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered-down state, the ADC uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 5. When the conversion is co mplete, the ADC control logic performs the following oper- ations: – 11-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:5]}

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 124 – CEN resets to 0 to indicate the conversion is complete 6. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered-down. Continuous Conversion When configured for continuous conversion, the ADC continuously performs an analog- to-digital conversion on the selected analog input. Each new data value over-writes the previous value stored in the ADC Data registers. An interrupt is generated after each con- version. In CONTINUOUS Mode, ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not detected at the next output from the ADC. The response of the ADC (in all modes) is lim- ited by the input signal bandwidth and the latency. Observe the following steps for setting up the ADC and initiating continuous conversion: 1. Enable the acceptable analog input by conf iguring the general-purpose I/O pins for alternate function. This action disables the digital input and output driver. 2. Write the ADC Control/Status Register 1 to configure the ADC: – Write the REFSELH bit of the pair { REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELH bit is contained in the ADC Control/Status Register 1. 3. Write to the ADC Control Register 0 to co nfigure the ADC for continuous conversion. The bit fields in the ADC Control Register can be written simultaneously: – Write to the ANAIN[3:0] field to select from the available analog input sources (different input pins available depending on the device). – Set CONT to 1 to select continuous conversion. – If the internal VREF must be output to a pin, set the REFEXT bit to 1. The inter- nal voltage reference must be enabled in this case. – Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal voltage reference level or to disable the internal reference. The REFSELL bit is contained in ADC Control Register 0. – Set CEN to 1 to start the conversions. Caution:

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 125 4. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: – CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation – An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete 5. The ADC writes a new data result every 256 system clock cycles. For each completed conversion, the ADC control logic performs the following operations: – Writes the 11-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:5]} – An interrupt request to the Interrupt Controller denoting conversion complete 6. To disable continuous conversion, clear the CONT bit in the ADC Control Register to 0. Interrupts The ADC is able to interrupt the CPU whenever a conversion has been completed and the ADC is enabled. When the ADC is disabled, an interrupt is not asserted; however, an interrupt pending when the ADC is disabled is not cleared. Calibration and Compensation Z8 Encore! XP F0823 Series ADC can be factory calibrated for offset error and gain error, with the compensation data stored in Flash memory. Alternatively, user code can perform its own calibration, storing the values into Flash themselves. Factory Calibration Devices that have been factory calibrated contain nine bytes of calibration data in the Flash option bit space. This data consists of three bytes for each reference type. For a list of input modes for which calibration data exists, see the Zilog Calibration Data section on page 152. There is 1 byte for offset, and there are 2 bytes for gain correction. User Calibration If you have precision references available, its own external calibration can be performed, storing the values into Flash themselves.

PS024315-1011 P R E L I M I N A R Y ADC Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 126 Software Compensation Procedure The value read from the ADC high and low byte registers are uncompensated. The user mode software must apply gain and offset correction to this uncompensated value for maximum accuracy. The following formula yields the compensated value: where GAINCAL is the gain calibration byte, OFFCAL is the offset calibration byte and ADCuncomp is the uncompensated value read from the ADC. The OFFCAL value is in two’s complement format, as are the compensated and uncompensated ADC values. The offset compensation is performed first, followed by the gain compensation. One bit of resolution is lost because of rounding on both the offset and gain computations. As a result the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and 10 data bits. Also note that in the second term, the multiplication must be performed before the division by 216. Otherwise, the second term evaluates to zero incorrectly. Although the ADC can be used without the gain and offset compensation, it does exhibit non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC range but requires the ADC results to be scaled by a factor of 8/7. ADC Control Register Definitions The following sections define the ADC Control registers. ADC Control Register 0 The ADC Control Register selects the analog input channel and initiates the analog-to-dig- ital conversion. ADC comp ADC uncomp OFFCAL– ADC uncomp OFFCAL– GAINCAL 21+= Note: Caution:

Table 74. ADC Control Register 0 (ADCCTL0) this bit to 0 when a conversion is complete. progress, the conversion restarts. This bit remains 1 until the conversion is complete. SELH, REFSELL}. This reference is independent of the Comparator reference. 00 = Internal Reference Disabled, reference comes from external pin. 01 = Internal Reference set to 1.0 V. 10 = Internal Reference set to 2.0 V (default). REF pin is available for GPIO functions. 1 = The internal ADC reference is buffered and connected to the VREF pin. 1 = Continuous conversion. ADC data updated every 256 system clock cycles.

PS024315-1011 P R E L I M I N A R Y ADC Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 128 [3:0] ANAIN Analog Input Select These bits select the analog input for conversion. Not all port pins in this list are available in all packages for Z8 Encore! XP F0823 Series. For information about the port pins available with each package style, see the Pin Description section on page 7. Do not enable unavail- able analog inputs. Usage of these bits changes depending on the buffer mode selected in ADC Control/Status Register 1. For the reserved values, all input switches are disabled to avoid leakage or other undesir- able operation. ADC samples taken with reserved bit settings are undefined. Single-Ended: 0000 = ANA0. 0001 = ANA1. 0010 = ANA2. 0011 = ANA3. 0100 = ANA4. 0101 = ANA5. 0110 = ANA6. 0111 = ANA7. 1000 = Reserved. 1001 = Reserved. 1010 = Reserved. 1011 = Reserved. 1100 = Reserved. 1101 = Reserved. 1110 = Reserved. 1111 = Reserved. Bit Description (Continued)

The second ADC Control Register contains the voltage reference level selection bit. Table 75. ADC Control/Status Register 1 (ADCCTL1) REFSELL}; this reference is independent of the Comparator reference. 00 = Internal Reference Disabled, reference comes from external pin. 10 = Internal Reference set to 2.0 V (default). These bits are reserved and must be programmed to 0000000.

High Byte Register latches data in the ADC Low Bits Register. Table 76. ADC Data High Byte Register (ADCD_H) held in this register. These bits are undefined after a Reset.

conversion, this value is invalid. Access to the ADC Data Low Byte register is read-only. Reading the ADC Data High Byte register latches data in the ADC Low Bits Register. Table 77. ADC Data Low Bits Register (ADCD_L) These bits are reserved and are undefined when read. 0 = An overflow did not occur in the digital filter for the current sample. 1 = An overflow did occur in the digital filter for the current sample.

PS024315-1011 P R E L I M I N A R Y Comparator Z8 Encore! XP® F0823 Series Product Specification 132 Comparator Z8 Encore! XP F0823 Series devices feature a general purpose comparator that compares two analog input signals. A GPIO (CINP) pin provides the positive comparator input. The negative input (CINN) can be taken from either an external GPIO pin or an internal refer- ence. The output is available as an interrupt source or can be routed to an external pin using the GPIO multiplex. The features of the comparator include:

Two inputs which can be connected up using the GPIO multiplex (MUX)
One input can be connected to a programmable internal reference
One input can be connected to the on-chip temperature sensor
Output can be either an interrupt source or an output to an external pin Operation One of the comparator inputs can be connected to an internal reference which is a user selectable reference that is user programmable with 200 mV resolution. The comparator can be powered down to save on supply current. For details, see the Power Control Register 0 section on page 31. Because of the propagation delay of the comparator, Zilog does not recommend enabling or reconfiguring the comparator without first disabling the interrupts and waiting for the comparator output to settle. Doing so can result in spurious interrupts. The following example shows how to safely enable the comparator: di ld cmp0 nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei Caution:

the value of the internal voltage reference. Table 78. Comparator Control Register (CMP0) 0 = GPIO pin used as positive comparator input. 1 = temperature sensor used as positive comparator input. 0 = internal reference disabled, GPIO pin used as negative comparator input. 1 = internal reference enabled as negative comparator input. Note: This reference is independent of the ADC voltage reference.

2 KB (2048) or 1 KB (1024) of nonvolatile Flash memory with read/write/erase capability. information about their operation, see the Flash Option Bits chapter on page 146. F0823 Series. Figure 20 displays the Flash memory arrangement. Table 79. Z8 Encore! XP F0823 Series Flash Memory Configurations

Figure 21. Flash Controller Operation Flowchart

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 137 Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory, you must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis- ters allow programming and erasing of the Flash with system clock frequencies ranging from 32 kHz (32768 Hz) through 20 MHz. The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash Fre- quency value must contain the system clock frequency (in kHz). This value is calculated using the following equation: Flash programming and erasure are not supported for system clock frequencies below 32 kHz (32768 Hz) or above 20 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure operation of Z8 Encore! XP F0823 Series devices. Flash Code Protection Against External Access The user code contained within the Flash memory can be protected against external access with the On-Chip Debugger. Programming the FRP Flash Option Bit prevents reading of the user code with the On-Chip Debugger. For more information, see the Flash Option Bits section on page 146 and the On-Chip Debugger chapter on page 156. Flash Code Protection Against Accidental Program and Erasure F0823 Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by a combination of the Flash Option bits, the register locking mechanism, the page select redundancy and the sector level protection control of the Flash Controller. Flash Code Protection Using the Flash Option Bits The FRP and FWP Flash Option Bits combine to provide three levels of Flash Program Memory protection as listed in Table 80. For more information, see the Flash Option Bits section on page 146. FFREQ[15:0] System Clock Frequency (Hz) Caution:

selected page becomes active. For more details, see Figure 21. tected. Any other value written to the Flash Control Register locks the Flash Controller. Mass Erase is not allowed in the user code but only in through the Debug Port. fer to enable sector protection. Table 80. Flash Code Protection Using the Flash Option Bits 1 Programming, Page Erase, and Mass Erase are enabled for all of Flash Program Memory.

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 139 bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than 5EH to the Flash Control Register deselects the Flash Sector Protect Register and reenables access to the Page Select Register. Observe the following procedure to setup the Flash Sector Protect Register from user code: 1. Write 00H to the Flash Control Register to reset the Flash Controller. 2. Write 5EH to the Flash Control Register to select the Flash Sector Protect Register. 3. Read and/or write the Flash Sector Protect Register which is now at Register File address FF9H. 4. Write 00H to the Flash Control Register to return the Flash Controller to its reset state. The Sector Protect Register is initialized to 0 on reset, putting each sector into an unpro- tected state. When a bit in the Sector Protect Register is written to 1, the corresponding sector can no longer be written or erased by the CPU. External Flash programming through the OCD or via the Flash Controller Bypass mode are unaffected. After a bit of the Sector Protect Register has been set, it cannot be cleared except by powering down the device. Byte Programming The Flash Memory is enabled for byte programming after unlocking the Flash Controller and successfully enabling either Mass Erase or Page Erase. When the Flash Controller is unlocked and Mass Erase is successfully completed, all Program Memory locations are available for byte programming. In contrast, when the Flash Controller is unlocked and Page Erase is successfully enabled, only the locations of the selected page are available for byte programming. An erased Flash byte contains all 1’s ( FFH). The programming opera- tion can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits) from 0 to 1 requires execution of either the Page Erase or Mass Erase commands. Byte Programming is accomplished using the On-Chip Debugger's Write Memory com- mand or eZ8 CPU execution of the LDC or LDCI instructions. For a description of the LDC and LDCI instructions, refer to the eZ8 CPU Core User Manual (UM0128), available for download at www.zilog.com. While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. To exit programming mode and lock the Flash, write any value to the Flash Control Register, except the Mass Erase or Page Erase commands. The byte at each address of the Flash memory cannot be programmed (any bits written to 0) more than twice before an erase cycle occurs. Doing so may result in corrupted data at the target byte. Caution:

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 140 Page Erase The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Flash Page Select register identi- fies the page to be erased. Only a page residing in an unprotected sector can be erased. With the Flash Controller unlocked and the active page set, writing the value 95h to the Flash Control Register initiates the Page Erase operation. While the Flash Controller exe- cutes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. If the Page Erase operation is performed using the On-Chip Debug- ger, poll the Flash Status Register to determine when the Page Erase operation is complete. When the Page Erase is complete, the Flash Controller returns to its locked state. Mass Erase The Flash memory can also be Mass Erased using the Flash Controller, but only by using the On-Chip Debugger. Mass Erasing the Flash memory sets all bytes to the value FFH. With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the value 63H to the Flash Control Register initiates the Mass Erase operation. While the Flash Controller executes the Mass Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Status Register to determine when the Mass Erase operation is complete. When the Mass Erase is complete, the Flash Controller returns to its locked state. Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Program- ming algorithms by controlling the Flash programming signals directly. Row programing is recommended for gang programming applications and large volume customers who do not require in-circuit initial programming of the Flash memory. Page Erase operations are also supported when the Flash Controller is bypassed. For more information about bypassing the Flash Controller, refer to the Zilog application note titled, Third-Party Flash Programming Support for Z8 Encore! MCUs (AN0117), available for download at www.zilog.com. Flash Controller Behavior in DEBUG Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger:

The Flash Write Protect option bit is ignored
The Flash Sector Protect register is ignored for programming and erase operations

PS024315-1011 P R E L I M I N A R Y Flash Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 141

Programming operations are not limited to the page selected in the Page Select register
Bits in the Flash Sector Protect register can be written to one or zero
The second write of the Page Select register to unlock the Flash Controller is not necessary
The Page Select register can be written when the Flash Controller is unlocked
The Mass Erase command is enabled through the Flash Control Register For security reasons, the Flash Controller allows only a single page to be opened for write/erase. When writing multiple Flash pages, the Flash controller must repeat the un- lock sequence to select another page. Flash Control Register Definitions This section defines the features of the following Flash Control registers. Flash Control Register: see page 141 Flash Status Register: see page 143 Flash Page Select Register: see page 143 Flash Sector Protect Register: see page 145 Flash Frequency High and Low Byte Registers: see page 145 Flash Control Register The Flash Controller must be unlocked using the Flash Control (FTCTL) Register before programming or erasing the Flash memory. Writing the sequence 73H 8CH, sequentially, to the Flash Control Register unlocks the Flash Controller. When the Flash Controller is unlocked, the Flash memory can be enabled for Mass Erase or Page Erase by writing the appropriate enable command to the FCTL. Page Erase applies only to the active page selected in Flash Page Select register. Mass Erase is enabled only through the On-Chip Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state. The Write-only Flash Control Register shares its Register File address with the read-only Flash Status Register. Caution:

Table 81. Flash Control Register (FCTL) 8CH = Second unlock command. 95H = Page Erase command (must be third command in sequence to initiate Page Erase). 63H = Mass Erase command (must be third command in sequence to initiate Mass Erase). 5EH = Enable Flash Sector Protect Register Access.

address with the write-only Flash Control Register. address target the Flash Page Select Register. by FPS[6:0] are chosen for program/erase operation. Table 82. Flash Status Register (FSTAT) These bits are reserved and must be programmed to 0 when read. 000000 = Flash Controller locked. 000001 = First unlock command received (73H written). 000010 = Second unlock command received (8CH written). 000011 = Flash Controller unlocked. 000100 = Sector protect register selected. 001xxx = Program operation in progress. 010xxx = Page erase operation in progress. 100xxx = Mass erase operation in progress.

Table 83. Flash Page Select Register (FPS) 0 = Information Area us not selected. address space at addresses FE00H through FFFFH. This 7-bit field identifies the Flash memory page for Page Erase and page unlocking.

Program Memory Address[15:9] = PAGE[6:0].
For Z8F04x3 devices, the upper 4 bits must always be 0.
For Z8F02x3 devices, the upper 5 bits must always be 0.
For Z8F01x3 devices, the upper 6 bits must always be 0.

The Flash Sector Protect (FPROT) Register is shared with the Flash Page Select Register. without powering down the device. form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. Table 84. Flash Sector Protect Register (FPROT) on page 134 and to Figure 20, which follows the table.

For Z8F08x3 and Z8F04x3 devices, all bits are used.
For Z8F02x3 devices, the upper 4 bits are unused.
For Z8F01x3 devices, the upper 6 bits are unused. Note: n indicates the specific Flash sector (7–0). FFREQ[15:0] FFREQH[ 7:0],FFREQL[7:0] System Clock Frequency

ported for system clock frequencies below 20 kHz or above 20 MHz. Table 85. Flash Frequency High Byte Register (FFREQH) High byte of the 16-bit Flash Frequency value. Table 86. Flash Frequency Low Byte Register (FFREQL) Low byte of the 16-bit Flash Frequency value.

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 147 Option Bit Types This section describes the five types of Flash option bits offered in the F083A Series. User Option Bits The user option bits are contained in the first two bytes of program memory. Access to these bits has been provided because these locations contain application-specific device configurations. The information contained here is lost when page 0 in program memory is erased. Trim Option Bits The trim option bits are contained in a Flash memory information page. These bits are fac- tory programmed values required to optimize the operation of onboard analog circuitry and cannot be permanently altered. Program memory may be erased without endangering these values. It is possible to alter working values of these bits by accessing the Trim Bit Address and Data Registers, but these working values are lost after a power loss or any other reset event. There are 32 bytes of trim data. To modify one of these values the user code must first write a value between 00H and 1FH into the Trim Bit Address Register. The next write to the Trim Bit Data Register changes the working value of the target trim data byte. Reading the trim data requires the user code to write a value between 00H and 1FH into the Trim Bit Address Register. The next read from the Trim Bit Data Register returns the working value of the target trim data byte. The trim address range is from information address 20–3F only. The remainder of the information page is not accessible through the trim bit address and data registers. Calibration Option Bits The calibration option bits are also contained in the information page. These bits are fac- tory programmed values intended for use in software correcting the device’s analog per- formance. To read these values, the user code must employ the LDC instruction to access the information area of the address space as defined in the Flash Information Area section on page 15. Serialization Bits As an optional feature, Zilog is able to provide factory-programmed serialization. For seri- alized products, the individual devices are programmed with unique serial numbers. These serial numbers are binary values, four bytes in length. The numbers increase in size with each device, but gaps in the serial sequence may exist. Note:

tion on page 154) and are unaffected by mass erasure of the device’s Flash memory. tion lot and is not likely to be repeated. of the device’s flash memory. The following code example shows how to read data from the Flash Information Area. This section briefly describes the features of the Trim Bit Address and Data registers. Table 87. Trim Bit Address Register (TRMADR)

for the user-programmable Flash option bits. Table 88. Trim Bit Data Register (TRMDR) Table 89. Flash Option Bits at Program Memory Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write. enabled for the eZ8 CPU to acknowledge the interrupt request. the default for unprogrammed (erased) Flash. These bits are reserved and must be programmed to 11 during writes, and to 11 when read.

ting is the default for unprogrammed (erased) Flash. setting is the default for unprogrammed (erased) Flash. This bit is reserved and must be programmed to 1. Table 90. Flash Options Bits at Program Memory Address 0001H Note: U = Unchanged by Reset. R/W = Read/Write.

All available trim bit addresses and their functions are listed in Tables 91 through 93. These bits are reserved and must be programmed to 111 during writes and to 111 when read. 0 = The crystal oscillator is enabled during reset, resulting in longer reset timing. no further debugging or Flash programming is required. These bits are reserved and must be programmed to 1111 during writes and to 1111 when read. Table 91. Trim Options Bits at Address 0000H Note: U = Unchanged by Reset. R/W = Read/Write. These bits are reserved. Altering this register may result in incorrect device operation.

Table 92. Trim Option Bits at 0001H Note: U = Unchanged by Reset. R/W = Read/Write. These bits are reserved. Altering this register may result in incorrect device operation. Table 93. Trim Option Bits at 0002H (TIPO) Note: U = Unchanged by Reset. R/W = Read/Write. Contains trimming bits for the Internal Precision Oscillator.

Table 94. ADC Calibration Bits Note: U = Unchanged by Reset. R/W = Read/Write. Table 95. ADC Calibration Data Location

Table 96. Serial Number at 001C–001F (S_NUM) Note: U = Unchanged by Reset. R/W = Read/Write. The serial number is a unique four-byte binary value; see Table 97. Table 97. Serialization Data Locations 1C FE1C Serial Number Byte 3 (most significant). 1D FE1D Serial Number Byte 2. 1E FE1E Serial Number Byte 1. 1F FE1F Serial Number Byte 0 (least significant). Table 98. Lot Identification Number (RAND_LOT) Note: U = Unchanged by Reset. R/W = Read/Write.

Table 99. Randomized Lot ID Locations

58 FE58 Randomized Lot ID Byte 27

59 FE59 Randomized Lot ID Byte 26

61 FE61 Randomized Lot ID Byte 19

62 FE62 Randomized Lot ID Byte 18

64 FE64 Randomized Lot ID Byte 17

65 FE65 Randomized Lot ID Byte 16

67 FE67 Randomized Lot ID Byte 15

68 FE68 Randomized Lot ID Byte 14

70 FE70 Randomized Lot ID Byte 9

71 FE71 Randomized Lot ID Byte 8

73 FE73 Randomized Lot ID Byte 7

74 FE74 Randomized Lot ID Byte 6

76 FE76 Randomized Lot ID Byte 5

77 FE77 Randomized Lot ID Byte 4

79 FE79 Randomized Lot ID Byte 3

Single pin interface
Reading and writing of the register file
Reading and writing of program and data memory
Setting of breakpoints and watchpoints
Executing eZ8 CPU instructions
Debug pin sharing with general-purpose input-output function to maximize the pins available Architecture The on-chip debugger consists of four primary functional blocks: transmitter, receiver, auto-baud detector/generator, and debug controller. Figure 22 displays the architecture of the OCD.

Figure 22. On-Chip Debugger Block Diagram

The following section describes the operation of the OCD.

This pin creates an interface from the F0823 Series products to the serial port of a

higher data rates or in noisy systems, Zilog recommends an external pull-up resistor. drain and may require an external pull-up resistor to ensure proper operation. Figure 23. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, # 1 of 2

The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex- ecute specific instructions
The system clock operates unless in STOP Mode
All enabled on-chip peripherals operate unless in STOP Mode
Automatically exits HALT Mode
Constantly refreshes the Watchdog Timer, if enabled. Entering DEBUG Mode The device enters DEBUG Mode following the operations below:
The device enters DEBUG Mode after the eZ8 CPU executes a BRK (breakpoint) in- struction
If the DBG pin is held Low during the most recent clock cycle of System Reset, the part enters DEBUG Mode upon exiting System Reset Holding the DBG pin Low for an additional 5000 (minimum) clock cycles after reset (making sure to account for any specified frequency error if using an internal oscillator) prevents a false interpretation of an autobaud sequence (see the OCD Autobaud Detector/ Generator section on page 159).

Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, # 2 of 2

If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/ DBG pin, the DBG feature is unlocked. After releasing PA2/RESET, it is pulled high. At this point, the PA0/DBG pin can be used to autobaud and cause the device to enter  DEBUG Mode. For more details, see the OCD Unlock Sequence (8-Pin Devices Only) section on page 161. Exiting DEBUG Mode The device exits DEBUG Mode following any of these operations:
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-On Reset
V oltage Brown-Out reset
Watchdog Timer reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in STOP Mode initiates a system reset OCD Data Format The OCD interface uses the asynchronous data format defined for RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit as dis- played in Figure 25. When responding to a request for data, the OCD may commence transmitting immediately after receiving the stop bit of an incoming frame. Therefore, when sending the stop bit, the host must not actively drive the DBG pin High for more than 0.5 bit times. Zilog recom- mends that, if possible, the host drives the DBG pin using an open-drain output. OCD Autobaud Detector/Generator To run over a range of baud rates (data bits per second) with various system clock frequen- cies, the OCD contains an auto-baud detector/generator. After a reset, the OCD is idle until it receives data. The OCD requires that the first character sent from the host is the character 80H. The character 80H has eight continuous bits Low (one Start bit plus 7 data

Figure 25. OCD Data Format

OCD baud rate generator accordingly. baud rates for sample crystal frequencies. detector/generator resets. Reconfigure the auto-baud detector/generator by sending 80H.

Serial Break (a minimum of nine continuous bits Low)
Framing Error (received Stop bit is Low)
Transmit Collision (OCD and host simultaneous transmission detected by the OCD) When the OCD detects one of these errors, it aborts any command currently in progress, transmits a four character long Serial Break back to the host, and resets the auto-baud detector/generator. A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the interface, returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host transmits a Serial Break on the DBG pin when first connecting to the F0823 Series devices or when recovering from an error. A Serial Break from the host resets the auto- baud generator/detector but does not reset the OCD Control Register. A Serial Break leaves the device in DEBUG Mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the open- drain nature of the DBG pin, the host sends a Serial Break to the OCD even if the OCD is transmitting a character.

Table 100. OCD Baud-Rate Limits

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 161 OCD Unlock Sequence (8-Pin Devices Only) Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the DBG pin. If this sequence is not completed during a system reset, then the PA0/ DBG pin functions only as a GPIO pin. The following sequence unlocks the DBG pin: 1. Hold PA2/RESET Low. 2. Wait 5 ms for the internal reset sequence to complete. 3. Send the following bytes serially to the debug pin: DBG ← 80H (autobaud) DBG ← EBH DBG ←5AH DBG ←70H DBG ←CDH (32-bit unlock key) 4. Release PA2/RESET . The PA0/DBG pin is now identical in function to that of the DBG pin on the 20- or 28-pin device. To enter DEBUG Mode, reautobaud and write 80H to the OCD Control Register (see the On-Chip Debugger Commands section on page 162). Breakpoints Execution breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the OCD. If breakpoints are enabled, the OCD enters DEBUG Mode and idles the eZ8 CPU. If breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP instruction. Breakpoints in Flash Memory The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a byte in Flash memory. To implement a breakpoint, write 00H to the required break address, overwriting the current instruction. To remove a breakpoint, the corresponding page of Flash memory must be erased and reprogrammed with the original data. Runtime Counter The OCD contains a 16-bit Runtime Counter. It counts system clock cycles between breakpoints. The counter starts counting when the OCD leaves DEBUG Mode and stops counting when it enters DEBUG Mode again or when it reaches the maximum count of FFFFH.

The host communicates to the OCD by sending OCD commands using the DBG interface. Series products. When this option is enabled, several of the OCD commands are disabled. those commands that are disabled by programming the Flash Read Protect Option bit. Table 101. OCD Commands Write OCD Control Register 04H Yes Cannot clear DBGMODE bit. Write Program Counter 06H – Disabled. Read Program Counter 07H – Disabled. Read Register 09H – Disabled. Write Program Memory 0AH – Disabled. Read Program Memory 0BH – Disabled. Write Data Memory 0CH – Yes. Step Instruction 10H – Disabled. Stuff Instruction 11H – Disabled. Execute Instruction 12H – Disabled.

PS024315-1011 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F0823 Series Product Specification 163 In the following list of OCD Commands, data and commands sent from the host to the OCD are identified by ’DBG ← Command/Data’. Data sent from the OCD back to the host is identified by ’DBG → Data’. Read OCD Revision (00H). The Read OCD Revision command determines the version of the OCD. If OCD commands are added, removed, or changed, this revision number changes. DBG ← 00H DBG → OCDRev[15:8] (Major revision number) DBG → OCDRev[7:0] (Minor revision number) Read OCD Status Register (02H). The Read OCD Status Register command reads the OCDSTAT Register. DBG ← 02H DBG → OCDSTAT[7:0] Read Runtime Counter (03H). The Runtime Counter counts system clock cycles in between breakpoints. The 16-bit Runtime Counter counts up from 0000H and stops at the maximum count of FFFFH. The Runtime Counter is overwritten during the Write Memory, Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction, Stuff Instruction, and Execute Instruction commands. DBG ← 03H DBG → RuntimeCounter[15:8] DBG → RuntimeCounter[7:0] Write OCD Control Register (04H). The Write OCD Control Register command writes the data that follows to the OCDCTL register. When the Flash Read Protect Option Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device. DBG ← 04H DBG ← OCDCTL[7:0] Read OCD Control Register (05H). The Read OCD Control Register command reads the value of the OCDCTL register. DBG ← 05H DBG → OCDCTL[7:0] Write Program Counter (06H). The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, the Program Counter (PC) values are discarded. DBG ← 06H DBG ← ProgramCounter[15:8] DBG ← ProgramCounter[7:0]

PS024315-1011 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F0823 Series Product Specification 164 Read Program Counter (07H). The Read Program Counter command reads the value in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, this command returns FFFFH. DBG ← 07H DBG → ProgramCounter[15:8] DBG → ProgramCounter[7:0] Write Register (08H). The Write Register command writes data to the Register File. Data can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If the device is not in DEBUG Mode, the address and data values are discarded. If the Flash Read Protect Option bit is enabled, only writes to the Flash Control Registers are allowed and all other register write data values are discarded. DBG ← 08H DBG ← {4’h0,Register Address[11:8]} DBG ← Register Address[7:0] DBG ← Size[7:0] DBG ← 1–256 data bytes Read Register (09H). The Read Register command reads data from the Register File. Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, this com- mand returns FFH for all the data values. DBG ← 09H DBG ← {4’h0,Register Address[11:8] DBG ← Register Address[7:0] DBG ← Size[7:0] DBG → 1–256 data bytes Write Program Memory (0AH). The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). The on-chip Flash Controller must be written to and unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG Mode or if the Flash Read Protect Option bit is enabled, the data is discarded. DBG ← 0AH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1–65536 data bytes Read Program Memory (0BH). The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG Mode or if the Flash Read Protect Option Bit is enabled, this command returns FFH for the data.

PS024315-1011 P R E L I M I N A R Y On-Chip Debugger Commands Z8 Encore! XP® F0823 Series Product Specification 165 DBG ← 0BH DBG ← Program Memory Address[15:8] DBG ← Program Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1–65536 data bytes Write Data Memory (0CH). The Write Data Memory command writes data to Data Mem- ory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1– 65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not in DEBUG Mode or if the Flash Read Protect Option Bit is enabled, the data is discarded. DBG ← 0CH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG ← 1–65536 data bytes Read Data Memory (0DH). The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in DEBUG Mode, this command returns FFH for the data. DBG ← 0DH DBG ← Data Memory Address[15:8] DBG ← Data Memory Address[7:0] DBG ← Size[15:8] DBG ← Size[7:0] DBG → 1–65536 data bytes Read Program Memory CRC (0EH). The Read Program Memory Cyclic Redundancy Check (CRC) command computes and returns the CRC of Program Memory using the 16- bit CRC-CCITT polynomial. If the device is not in DEBUG Mode, this command returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory. DBG ← 0EH DBG → CRC[15:8] DBG → CRC[7:0] Step Instruction (10H). The Step Instruction steps one assembly instruction at the current Program Counter (PC) location. If the device is not in DEBUG Mode or the Flash Read Protect Option bit is enabled, the OCD ignores this command. DBG ← 10H

PS024315-1011 P R E L I M I N A R Y On-Chip Debugger Control Register Z8 Encore! XP® F0823 Series Product Specification 166 Stuff Instruction (11H). The Stuff command steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0–4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint. If the device is not in DEBUG Mode or the Flash Read Protect Option bit is enabled, the OCD ignores this command. DBG ← 11H DBG ← opcode[7:0] Execute Instruction (12H). The Execute command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over breakpoints. The number of bytes to send for the instruction depends on the opcode. If the device is not in DEBUG Mode or the Flash Read Protect Option bit is enabled, this command reads and discards one byte. DBG ← 12H DBG ← 1–5 byte opcode On-Chip Debugger Control Register Definitions This section describes the features of the On-Chip Debugger Control and Status registers. OCD Control Register The OCD Control Register controls the state of the OCD. This register is used to enter or exit DEBUG Mode and to enable the BRK instruction. It also resets Z8 Encore! XP F0823 Series device. A reset and stop function can be achieved by writing 81H to this register. A reset and go function can be achieved by writing 41H to this register. If the device is in DEBUG Mode, a run function can be implemented by writing 40H to this register.

Table 102. OCD Control Register (OCDCTL) device. It cannot be written to 0. 0 = F0823 Series device is operating in NORMAL Mode. 1 = F0823 Series device is in DEBUG Mode. 0 = Breakpoints are disabled. 1 = Breakpoints are enabled. Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. These bits are reserved and must be 00000 when read. ically cleared to 0 at the end of reset. 1 = Reset the Flash Read Protect Option Bit device.

Table 103. OCD Status Register (OCDSTAT) 0 = FRP bit enabled to allow disabling of many OCD commands. These bits are reserved and must be 00000 when read.

On-chip precision trimmed RC oscillator
External clock drive
On-chip low power Watchdog Timer oscillator In addition, F0823 Series devices contain clock failure detection and recovery circuitry, which allow continued operation despite a failure of the primary oscillator. Operation This chapter discusses the logic used to select the system clock and handle primary oscil- lator failures. A description of the specific operation of each oscillator is outlined else- where in this document. System Clock Selection The oscillator control block selects from the available clocks. Table 104 details each clock source and its usage.

Table 104. Oscillator Configuration and Selection

32.8 kHz or 5.53 MHz
± 4% accuracy when trimmed
No external components required
Unlock and write Oscillator Control Register (OSCCTL) to enable and select oscillator at either 5.53 MHz or 32.8 kHz External Clock Drive
0 to 20 MHz
Accuracy dependent on external clock source
Write GPIO registers to configure PB3 pin for external clock function
Unlock and write OSCCTL to select external system clock
Apply external clock signal to GPIO Internal Watchdog Timer Oscillator
10 kHz nominal
± 40% accuracy; no external compo- nents required
Very Low power consumption
Enable WDT if not enabled and wait until WDT Oscillator is operating.
Unlock and write Oscillator Control Register (OSCCTL) to enable and select oscillator

PS024315-1011 P R E L I M I N A R Y Operation Z8 Encore! XP® F0823 Series Product Specification 170 Unintentional accesses to the Oscillator Control Register can actually stop the chip by switching to a non-functioning oscillator. To prevent this condition, the oscillator control block employs a register unlocking/locking scheme. OSC Control Register Unlocking/Locking To write to the Oscillator Control Register, unlock it by making two writes to the OSC- CTL Register with the values E7H followed by 18H. A third write to the OSCCTL Regis- ter changes the value of the actual register and returns the register to a locked state. Any other sequence of Oscillator Control Register writes has no effect. The values written to unlock the register must be ordered correctly, but are not necessarily consecutive. It is pos- sible to write to or read from other registers within the unlocking/locking operation. When selecting a new clock source, the primary oscillator failure detection circuitry and the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a failure of either oscillator. The Failure detection circuitry can be enabled anytime after a successful write of OSCSEL in the Oscillator Control Register. The internal precision oscillator is enabled by default. If the user code changes to a differ- ent oscillator, it is appropriate to disable the IPO for power savings. Disabling the IPO does not occur automatically. Clock Failure Detection and Recovery Should an oscillator or timer fail, there are methods of recovery, as this section describes. Primary Oscillator Failure Z8 Encore! XP F0823 Series devices can generate non-maskable interrupt-like events when the primary oscillator fails. To maintain system function in this situation, the clock failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the system clock. The Watchdog Timer oscillator must be enabled to allow the recovery. Although this oscillator runs at a much slower speed than the original system clock, the CPU continues to operate, allowing execution of a clock failure vector and software rou- tines that either remedy the oscillator failure or issue a failure alert. This automatic switch- over is not available if the Watchdog Timer is the primary oscillator. It is also unavailable if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the Watchdog Timer reset function outlined in the the Watchdog Timer section on page 91. The primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is pos- sible that a very slow but non-failing clock can generate a failure condition. Under these Caution:

PS024315-1011 P R E L I M I N A R Y Oscillator Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 171 conditions, do not enable the clock failure circuitry (POFEN must be deasserted in the OSCCTL Register). Watchdog Timer Failure In the event of a Watchdog Timer oscillator failure, a similar non-maskable interrupt-like event is issued. This event does not trigger an attendant clock switch-over, but alerts the CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a pri- mary oscillator failure. The failure detection circuitry does not function if the Watchdog Timer is used as the primary oscillator or if the Watchdog Timer oscillator has been dis- abled. For either of these cases, it is necessary to disable the detection circuitry by deas- serting the WDFEN bit of the OSCCTL Register. The Watchdog Timer oscillator failure detection circuit counts system clocks while searching for a Watchdog Timer clock. The logic counts 8004 system clock cycles before determining that a failure has occurred. The system clock rate determines the speed at which the Watchdog Timer failure can be detected. A very slow system clock results in very slow detection times. It is possible to disable the clock failure detection circuitry as well as all functioning clock sources. In this case, the Z8 Encore! XP F0823 Series device ceases functioning and can only be recovered by Power-On Reset. Oscillator Control Register Definitions The following section provides the bit definitions for the Oscillator Control Register. Oscillator Control Register The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes the system clock. The Oscillator Control Register must be unlocked before writing. Writing the two step sequence E7H followed by 18H to the Oscillator Control Register unlocks it. The register is locked at successful completion of a register write to the OSCCTL. Caution:

Table 105. Oscillator Control Register (OSCCTL) 1 = Internal precision oscillator is enabled. 0 = Internal precision oscillator is disabled. This bit is reserved and must be programmed to 0 during writes and to 0 when read. 1 = Watchdog Timer oscillator is enabled. 0 = Watchdog Timer oscillator is disabled. 1 = Failure detection and recovery of primary oscillator is enabled. 0 = Failure detection and recovery of primary oscillator is disabled. 1 = Failure detection of Watchdog Timer oscillator is enabled. 0 = Failure detection of Watchdog Timer oscillator is disabled. 000 = Internal precision oscillator functions as system clock at 5.53 MHz. 001 = Internal precision oscillator functions as system clock at 32 kHz. 011 = Watchdog Timer oscillator functions as system clock. 100 = External clock signal on PB3 functions as system clock.

PS024315-1011 P R E L I M I N A R Y Internal Precision Oscillator Z8 Encore! XP® F0823 Series Product Specification 173 Internal Precision Oscillator The internal precision oscillator (IPO) is designed for use without external components. You can either manually trim the oscillator for a non-standard frequency or use the auto- matic factory-trimmed version to achieve a 5.53 MHz frequency. The features of IPO include:

On-chip RC oscillator that does not require external components
Output frequency of either 5.53 MHz or 32.8 kHz (contains both a fast and a slow mode)
Trimming possible through Flash option bits with user override
Elimination of crystals or ceramic resonators in applications where high timing accu- racy is not required Operation An 8-bit trimming register, incorporated into the design, compensates for absolute varia- tion of oscillator frequency. Once trimmed the oscillator frequency is stable and does not require subsequent calibration. Trimming is performed during manufacturing and is not necessary for you to repeat unless a frequency other than 5.53 MHz (fast mode) or 32.8 kHz (slow mode) is required. This trimming is done at +30°C and a supply voltage of 3.3 V , so accuracy of this operating point is optimal. Power down this block for minimum system power. By default, the oscillator is configured through the Flash Option bits. However, the user code can override these trim values, as described in the Trim Bit Address Space section on page 151. Select one of the two frequencies for the oscillator: 5.53 MHz and 32.8 kHz, using the OSCSEL bits in the Oscillator Control chapter on page 169.

PS024315-1011 P R E L I M I N A R Y eZ8 CPU Instruction Set Z8 Encore! XP® F0823 Series Product Specification 174 eZ8 CPU Instruction Set This chapter describes the following features of the eZ8 CPU instruction set: Assembly Language Programming Introduction: see page 174 Assembly Language Syntax: see page 175 eZ8 CPU Instruction Notation: see page 176 eZ8 CPU Instruction Classes: see page 178 eZ8 CPU Instruction Summary: see page 182 Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called state- ments. Each statement can contain labels, operations, operands, and comments. Labels are assigned to a particular instruction step in a source program. The label identi- fies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example.

mat if you prefer manual program coding or intend to implement your own assembler. assembly syntax and resulting object code is shown in Table 106. JP START ; Everything after the semicolon is a comment. ; program where the START label occurs. LD 234H, #%01 ; Another Load (LD) instruction with two operands. Table 106. Assembly Language Syntax Example 1

ter file range available. The register file size varies, depending on the device type. Table 107. Assembly Language Syntax Example 2 Table 108. Notational Shorthand b Bit b b represents a value from 0 to 7 (000B to 111B). IM Immediate Data #Data Data is a number between 00H to FFH. Ir Indirect Working Register @Rn n = 0–15. Irr Indirect Working Register Pair @RRp p = 0, 2, 4, 6, 8, 10, 12, or 14. r Working Register Rn n = 0–15.

Instruction Set Description sections. Assignment of a value is indicated by an arrow, as shown in the following example. stored in the destination location. Table 109. Additional Symbols Table 108. Notational Shorthand (Continued)

Arithmetic
Bit Manipulation
Block Transfer
CPU Control
Load
Logical
Program Control
Rotate and Shift Tables 110 through 117 contain the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category. Within these tables, the source operand is identified as ‘src’, the destination operand is ‘dst’ and a con- dition code is ‘cc’.

Table 110. Arithmetic Instructions

Table 111. Bit Manipulation Instructions Table 112. Block Transfer Instructions Table 110. Arithmetic Instructions (Continued)

Table 113. CPU Control Instructions Table 114. Load Instructions

Table 115. Logical Instructions Table 116. Program Control Instructions Table 117. Rotate and Shift Instructions

required for the instruction execution. Table 118. eZ8 CPU Instruction Summary Table 117. Rotate and Shift Instructions (Continued)

Table 118. eZ8 CPU Instruction Summary (Continued)

A description of the opcode map data and the abbreviations are provided in Figure 26. lists Opcode Map abbreviations. Figure 26. Opcode Map Cell Description

Table 119. Opcode Map Abbreviations

Figure 27. First Opcode Map

Figure 28. Second Opcode Map after 1FH

Z8 Encore! XP® F0823 Series Product Specification 196

Electrical Characteristics

The data in this chapter represents all known data prior to qualification and characteriza- tion of the F0823 Series of products, and is therefore subject to change. Additional electri- cal characteristics may be found in the individual chapters of this document. Absolute Maximum Ratings Stresses greater than those listed in Table 120 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS). Table 120. Absolute Maximum Ratings Notes: Operating temper ature is specified in DC Characteristics.

This voltage applies to all pins except the following: V DD, AVDD, pins supporting analog input (Port B[5:0], Port
This voltage applies to pins on the 20/28 pin packages supporting analog input (Port B[5:0], Port C[2:0]) and pins

supporting the crystal oscillator (PA0 and PA1).

voltages are referenced to VSS, the primary system ground. Table 121. DC Characteristics nal pins on the 8-pin devices.

This condition excludes all pins that have on-chip pull-ups, when driven Low.
These values are provided for design guid ance only and are not tested in production.

Table 121. DC Characteristics (Continued)

This condition excludes all pins that have on-chip pull-ups, when driven Low.
These values are provided for design guid ance only and are not tested in production.

Table 122. Power Consumption 0.1 2 7.5 µA No peripherals enabled.

Typical conditions are defined as V DD = 3.3 V and +30°C.
Standard temperature is defined as T A = 0°C to +70°C; these values not tested in production for worst case

behavior, but are derived from product characterization and provided for design guidance only.

Extended temperature is defined as T A = –40°C to +105°C; these values not tested in production for worst case

behavior, but are derived from product characterization and provided for design guidance only.

For this block to operate, the band gap circuit is automatically turned on and must be added to the total supply

current. This bandgap current is only added once, regardless of how many peripherals are using it.

information assumes a standard load of 50 pF on all outputs. Table 123. AC Characteristics FSYSCLK System Clock Frequency – 20.0* MHz Read-only from Flash memory. TXIN System Clock Period 50 – ns T CLK = 1/FSYSCLK. TXINH System Clock High Time 20 30 ns T CLK = 50 ns. TXINL System Clock Low Time 20 30 ns T CLK = 50 ns. TXINR System Clock Rise Time – 3 ns T CLK = 50 ns. TXINF System Clock Fall Time – 3 ns T CLK = 50 ns. Note: *System Clock Frequency is limited by the Internal Precision Oscillator on the Z8 Encore! XP F0823 Series. Table 124. Internal Precision Oscillator Electrical Characteristics

Table 125 tabulates the electrical characteristics of the POR and VBO blocks. Table 125. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing guidance only and are not tested in production.

Table 126. Flash Memory Electrical Characteristics and Timing bypassing the Flash Controller. Table 127. Watchdog Timer Electrical Characteristics and Timing

Table 128. Analog-to-Digital Converter Electrical Characteristics and Timing

850 W When the internal ref-

10258 Temperature sensor

512 Temperature sensor

Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
Devices are factory calibrated at V DD = 3.3 V and TA = +30°C, so the ADC is maximally accurate under these
LSBs are defined assuming 10-bit resolution.
This is the maximum recommended resistance seen by the ADC input pin.
The input impedance is inversely proportional to the system clock frequency.

20 MHz5

Table 129. Comparator Electrical Characteristics Table 128. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)

Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
Devices are factory calibrated at V DD = 3.3 V and TA = +30°C, so the ADC is maximally accurate under these
LSBs are defined assuming 10-bit resolution.
This is the maximum recommended resistance seen by the ADC input pin.
The input impedance is inversely proportional to the system clock frequency.

Figure 29. Port Input Sample Timing Table 130. GPIO Port Input Timing

0 Latched

PS024315-1011 P R E L I M I N A R Y Packaging Z8 Encore! XP® F0823 Series Product Specification 210 Packaging Zilog’s F0823 Series of MCUs includes the Z8F0113, Z8F0123, Z8F0213, Z8F0223, Z8F0413, Z8F0423, Z8F0813 and Z8F0823 devices, which are available in the following packages:

8-pin Plastic Dual Inline Package (PDIP)
8-Pin Quad Flat No-Lead Package (QFN)/MLF-S1
20-pin Plastic Dual-Inline Package (PDIP)
20-pin Small Outline Integrated Circuit Package (SOIC)
20-pin Small Shrink Outline Package (SSOP)
28-pin Plastic Dual-Inline Package (PDIP)
28-pin Small Outline Integrated Circuit Package (SOIC)
28-pin Small Shrink Outline Package (SSOP) Current diagrams for each of these packages are published in Zilog’s Packaging Product Specification (PS0072), which is available free for download from the Zilog website. 1. The footprint of the QFN)/MLF-S packag e is identical to that of the 8-pin SOIC package, but with a lower profile.

Z8 Encore! XP® F0823 Series Product Specification 211 Order your F0823 Series products from Zilog using the part numbers shown in Table 135. For more information about ordering, please consult your local Zilog sales office. The Sales Location page on the Zilog website lists all regional offices. Table 135. Z8 Encore! XP F0823 Series Ordering Matrix Z8 Encore! XP F0823 Series with 8 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F0823PB005SG 8 KB 1 KB 6 12 2 4 1 PDIP 8-pin package Z8F0823QB005SG 8 KB 1 KB 6 12 2 4 1 QFN 8-pin package Z8F0823SB005SG 8 KB 1 KB 6 12 2 4 1 SOIC 8-pin package Z8F0823SH005SG 8 KB 1 KB 16 18 2 7 1 SOIC 20-pin package Z8F0823HH005SG 8 KB 1 KB 16 18 2 7 1 SSOP 20-pin package Z8F0823PH005SG 8 KB 1 KB 16 18 2 7 1 PDIP 20-pin package Z8F0823SJ005SG 8 KB 1 KB 22 18 2 8 1 SOIC 28-pin package Z8F0823HJ005SG 8 KB 1 KB 22 18 2 8 1 SSOP 28-pin package Z8F0823PJ005SG 8 KB 1 KB 22 18 2 8 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0823PB005EG 8 KB 1 KB 6 12 2 4 1 PDIP 8-pin package Z8F0823QB005EG 8 KB 1 KB 6 12 2 4 1 QFN 8-pin package Z8F0823SB005EG 8 KB 1 KB 6 12 2 4 1 SOIC 8-pin package Z8F0823SH005EG 8 KB 1 KB 16 18 2 7 1 SOIC 20-pin package Z8F0823HH005EG 8 KB 1 KB 16 18 2 7 1 SSOP 20-pin package Z8F0823PH005EG 8 KB 1 KB 16 18 2 7 1 PDIP 20-pin package Z8F0823SJ005EG 8 KB 1 KB 22 18 2 8 1 SOIC 28-pin package Z8F0823HJ005EG 8 KB 1 KB 22 18 2 8 1 SSOP 28-pin package Z8F0823PJ005EG 8 KB 1 KB 22 18 2 8 1 PDIP 28-pin package

Z8 Encore! XP® F0823 Series Product Specification 212 Z8 Encore! XP F0823 Series with 8 KB Flash Standard Temperature: 0°C to 70°C Z8F0813PB005SG 8 KB 1 KB 6 12 2 0 1 PDIP 8-pin package Z8F0813QB005SG 8 KB 1 KB 6 12 2 0 1 QFN 8-pin package Z8F0813SB005SG 8 KB 1 KB 6 12 2 0 1 SOIC 8-pin package Z8F0813SH005SG 8 KB 1 KB 16 18 2 0 1 SOIC 20-pin package Z8F0813HH005SG 8 KB 1 KB 16 18 2 0 1 SSOP 20-pin package Z8F0813PH005SG 8 KB 1 KB 16 18 2 0 1 PDIP 20-pin package Z8F0813SJ005SG 8 KB 1 KB 24 18 2 0 1 SOIC 28-pin package Z8F0813HJ005SG 8 KB 1 KB 24 18 2 0 1 SSOP 28-pin package Z8F0813PJ005SG 8 KB 1 KB 24 18 2 0 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0813PB005EG 8 KB 1 KB 6 12 2 0 1 PDIP 8-pin package Z8F0813QB005EG 8 KB 1 KB 6 12 2 0 1 QFN 8-pin package Z8F0813SB005EG 8 KB 1 KB 6 12 2 0 1 SOIC 8-pin package Z8F0813SH005EG 8 KB 1 KB 16 18 2 0 1 SOIC 20-pin package Z8F0813HH005EG 8 KB 1 KB 16 18 2 0 1 SSOP 20-pin package Z8F0813PH005EG 8 KB 1 KB 16 18 2 0 1 PDIP 20-pin package Z8F0813SJ005EG 8 KB 1 KB 24 18 2 0 1 SOIC 28-pin package Z8F0813HJ005EG 8 KB 1 KB 24 18 2 0 1 SSOP 28-pin package Z8F0813PJ005EG 8 KB 1 KB 24 18 2 0 1 PDIP 28-pin package Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)

Z8 Encore! XP® F0823 Series Product Specification 213 Z8 Encore! XP F0823 Series with 4 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F0423PB005SG 4 KB 1 KB 6 12 2 4 1 PDIP 8-pin package Z8F0423QB005SG 4 KB 1 KB 6 12 2 4 1 QFN 8-pin package Z8F0423SB005SG 4 KB 1 KB 6 12 2 4 1 SOIC 8-pin package Z8F0423SH005SG 4 KB 1 KB 16 18 2 7 1 SOIC 20-pin package Z8F0423HH005SG 4 KB 1 KB 16 18 2 7 1 SSOP 20-pin package Z8F0423PH005SG 4 KB 1 KB 16 18 2 7 1 PDIP 20-pin package Z8F0423SJ005SG 4 KB 1 KB 22 18 2 8 1 SOIC 28-pin package Z8F0423HJ005SG 4 KB 1 KB 22 18 2 8 1 SSOP 28-pin package Z8F0423PJ005SG 4 KB 1 KB 22 18 2 8 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0423PB005EG 4 KB 1 KB 6 12 2 4 1 PDIP 8-pin package Z8F0423QB005EG 4 KB 1 KB 6 12 2 4 1 QFN 8-pin package Z8F0423SB005EG 4 KB 1 KB 6 12 2 4 1 SOIC 8-pin package Z8F0423SH005EG 4 KB 1 KB 16 18 2 7 1 SOIC 20-pin package Z8F0423HH005EG 4 KB 1 KB 16 18 2 7 1 SSOP 20-pin package Z8F0423PH005EG 4 KB 1 KB 16 18 2 7 1 PDIP 20-pin package Z8F0423SJ005EG 4 KB 1 KB 22 18 2 8 1 SOIC 28-pin package Z8F0423HJ005EG 4 KB 1 KB 22 18 2 8 1 SSOP 28-pin package Z8F0423PJ005EG 4 KB 1 KB 22 18 2 8 1 PDIP 28-pin package

Z8 Encore! XP® F0823 Series Product Specification 214 Z8 Encore! XP F0823 Series with 4 KB Flash Standard Temperature: 0°C to 70°C Z8F0413PB005SG 4 KB 1 KB 6 12 2 0 1 PDIP 8-pin package Z8F0413QB005SG 4 KB 1 KB 6 12 2 0 1 QFN 8-pin package Z8F0413SB005SG 4 KB 1 KB 6 12 2 0 1 SOIC 8-pin package Z8F0413SH005SG 4 KB 1 KB 16 18 2 0 1 SOIC 20-pin package Z8F0413HH005SG 4 KB 1 KB 16 18 2 0 1 SSOP 20-pin package Z8F0413PH005SG 4 KB 1 KB 16 18 2 0 1 PDIP 20-pin package Z8F0413SJ005SG 4 KB 1 KB 24 18 2 0 1 SOIC 28-pin package Z8F0413HJ005SG 4 KB 1 KB 24 18 2 0 1 SSOP 28-pin package Z8F0413PJ005SG 4 KB 1 KB 24 18 2 0 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0413PB005EG 4 KB 1 KB 6 12 2 0 1 PDIP 8-pin package Z8F0413QB005EG 4 KB 1 KB 6 12 2 0 1 QFN 8-pin package Z8F0413SB005EG 4 KB 1 KB 6 12 2 0 1 SOIC 8-pin package Z8F0413SH005EG 4 KB 1 KB 16 18 2 0 1 SOIC 20-pin package Z8F0413HH005EG 4 KB 1 KB 16 18 2 0 1 SSOP 20-pin package Z8F0413PH005EG 4 KB 1 KB 16 18 2 0 1 PDIP 20-pin package Z8F0413SJ005EG 4 KB 1 KB 24 18 2 0 1 SOIC 28-pin package Z8F0413HJ005EG 4 KB 1 KB 24 18 2 0 1 SSOP 28-pin package Z8F0413PJ005EG 4 KB 1 KB 24 18 2 0 1 PDIP 28-pin package

Z8 Encore! XP® F0823 Series Product Specification 215 Z8 Encore! XP F0823 Series with 2 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F0223PB005SG 2 KB 512 B 6 12 2 4 1 PDIP 8-pin package Z8F0223QB005SG 2 KB 512 B 6 12 2 4 1 QFN 8-pin package Z8F0223SB005SG 2 KB 512 B 6 12 2 4 1 SOIC 8-pin package Z8F0223SH005SG 2 KB 512 B 16 18 2 7 1 SOIC 20-pin package Z8F0223HH005SG 2 KB 512 B 16 18 2 7 1 SSOP 20-pin package Z8F0223PH005SG 2 KB 512 B 16 18 2 7 1 PDIP 20-pin package Z8F0223SJ005SG 2 KB 512 B 22 18 2 8 1 SOIC 28-pin package Z8F0223HJ005SG 2 KB 512 B 22 18 2 8 1 SSOP 28-pin package Z8F0223PJ005SG 2 KB 512 B 22 18 2 8 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0223PB005EG 2 KB 512 B 6 12 2 4 1 PDIP 8-pin package Z8F0223QB005EG 2 KB 512 B 6 12 2 4 1 QFN 8-pin package Z8F0223SB005EG 2 KB 512 B 6 12 2 4 1 SOIC 8-pin package Z8F0223SH005EG 2 KB 512 B 16 18 2 7 1 SOIC 20-pin package Z8F0223HH005EG 2 KB 512 B 16 18 2 7 1 SSOP 20-pin package Z8F0223PH005EG 2 KB 512 B 16 18 2 7 1 PDIP 20-pin package Z8F0223SJ005EG 2 KB 512 B 22 18 2 8 1 SOIC 28-pin package Z8F0223HJ005EG 2 KB 512 B 22 18 2 8 1 SSOP 28-pin package Z8F0223PJ005EG 2 KB 512 B 22 18 2 8 1 PDIP 28-pin package

Z8 Encore! XP® F0823 Series Product Specification 216 Z8 Encore! XP F0823 Series with 2 KB Flash Standard Temperature: 0°C to 70°C Z8F0213PB005SG 2 KB 512 B 6 12 2 0 1 PDIP 8-pin package Z8F0213QB005SG 2 KB 512 B 6 12 2 0 1 QFN 8-pin package Z8F0213SB005SG 2 KB 512 B 6 12 2 0 1 SOIC 8-pin package Z8F0213SH005SG 2 KB 512 B 16 18 2 0 1 SOIC 20-pin package Z8F0213HH005SG 2 KB 512 B 16 18 2 0 1 SSOP 20-pin package Z8F0213PH005SG 2 KB 512 B 16 18 2 0 1 PDIP 20-pin package Z8F0213SJ005SG 2 KB 512 B 24 18 2 0 1 SOIC 28-pin package Z8F0213HJ005SG 2 KB 512 B 24 18 2 0 1 SSOP 28-pin package Z8F0213PJ005SG 2 KB 512 B 24 18 2 0 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0213PB005EG 2 KB 512 B 6 12 2 0 1 PDIP 8-pin package Z8F0213QB005EG 2 KB 512 B 6 12 2 0 1 QFN 8-pin package Z8F0213SB005EG 2 KB 512 B 6 12 2 0 1 SOIC 8-pin package Z8F0213SH005EG 2 KB 512 B 16 18 2 0 1 SOIC 20-pin package Z8F0213HH005EG 2 KB 512 B 16 18 2 0 1 SSOP 20-pin package Z8F0213PH005EG 2 KB 512 B 16 18 2 0 1 PDIP 20-pin package Z8F0213SJ005EG 2 KB 512 B 24 18 2 0 1 SOIC 28-pin package Z8F0213HJ005EG 2 KB 512 B 24 18 2 0 1 SSOP 28-pin package Z8F0213PJ005EG 2 KB 512 B 24 18 2 0 1 PDIP 28-pin package

Z8 Encore! XP® F0823 Series Product Specification 217 Z8 Encore! XP F0823 Series with 1 KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0°C to 70°C Z8F0123PB005SG 1 KB 256 B 6 12 2 4 1 PDIP 8-pin package Z8F0123QB005SG 1 KB 256 B 6 12 2 4 1 QFN 8-pin package Z8F0123SB005SG 1 KB 256 B 6 12 2 4 1 SOIC 8-pin package Z8F0123SH005SG 1 KB 256 B 16 18 2 7 1 SOIC 20-pin package Z8F0123HH005SG 1 KB 256 B 16 18 2 7 1 SSOP 20-pin package Z8F0123PH005SG 1 KB 256 B 16 18 2 7 1 PDIP 20-pin package Z8F0123SJ005SG 1 KB 256 B 22 18 2 8 1 SOIC 28-pin package Z8F0123HJ005SG 1 KB 256 B 22 18 2 8 1 SSOP 28-pin package Z8F0123PJ005SG 1 KB 256 B 22 18 2 8 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0123PB005EG 1 KB 256 B 6 12 2 4 1 PDIP 8-pin package Z8F0123QB005EG 1 KB 256 B 6 12 2 4 1 QFN 8-pin package Z8F0123SB005EG 1 KB 256 B 6 12 2 4 1 SOIC 8-pin package Z8F0123SH005EG 1 KB 256 B 16 18 2 7 1 SOIC 20-pin package Z8F0123HH005EG 1 KB 256 B 16 18 2 7 1 SSOP 20-pin package Z8F0123PH005EG 1 KB 256 B 16 18 2 7 1 PDIP 20-pin package Z8F0123SJ005EG 1 KB 256 B 22 18 2 8 1 SOIC 28-pin package Z8F0123HJ005EG 1 KB 256 B 22 18 2 8 1 SSOP 28-pin package Z8F0123PJ005EG 1 KB 256 B 22 18 2 8 1 PDIP 28-pin package

Z8 Encore! XP® F0823 Series Product Specification 218 Z8 Encore! XP F0823 Series with 1 KB Flash Standard Temperature: 0°C to 70°C Z8F0113PB005SG 1 KB 256 B 6 12 2 0 1 PDIP 8-pin package Z8F0113QB005SG 1 KB 256 B 6 12 2 0 1 QFN 8-pin package Z8F0113SB005SG 1 KB 256 B 6 12 2 0 1 SOIC 8-pin package Z8F0113SH005SG 1 KB 256 B 16 18 2 0 1 SOIC 20-pin package Z8F0113HH005SG 1 KB 256 B 16 18 2 0 1 SSOP 20-pin package Z8F0113PH005SG 1 KB 256 B 16 18 2 0 1 PDIP 20-pin package Z8F0113SJ005SG 1 KB 256 B 24 18 2 0 1 SOIC 28-pin package Z8F0113HJ005SG 1 KB 256 B 24 18 2 0 1 SSOP 28-pin package Z8F0113PJ005SG 1 KB 256 B 24 18 2 0 1 PDIP 28-pin package Extended Temperature: –40°C to 105°C Z8F0113PB005EG 1 KB 256 B 6 12 2 0 1 PDIP 8-pin package Z8F0113QB005EG 1 KB 256 B 6 12 2 0 1 QFN 8-pin package Z8F0113SB005EG 1 KB 256 B 6 12 2 0 1 SOIC 8-pin package Z8F0113SH005EG 1 KB 256 B 16 18 2 0 1 SOIC 20-pin package Z8F0113HH005EG 1 KB 256 B 16 18 2 0 1 SSOP 20-pin package Z8F0113PH005EG 1 KB 256 B 16 18 2 0 1 PDIP 20-pin package Z8F0113SJ005EG 1 KB 256 B 24 18 2 0 1 SOIC 28-pin package Z8F0113HJ005EG 1 KB 256 B 24 18 2 0 1 SSOP 28-pin package Z8F0113PJ005EG 1 KB 256 B 24 18 2 0 1 PDIP 28-pin package

Z8 Encore! XP® F0823 Series Product Specification 219 Z8 Encore! XP F0823 Series Development Kit Z8F08A28100KITG Z8 Encore! XP F082A Series Development Kit (20- and 28-Pin) Z8F04A28100KITG Z8 Encore! XP F042A Series Development Kit (20- and 28-Pin) Z8F04A08100KITG Z8 Encore! XP F042A Series Development Kit (8-Pin) ZUSBSC00100ZACG USB Smart Cable Accessory Kit ZUSBOPTSC01ZACG Opto-Isolated U SB Smart Cable Accessory Kit ZENETSC0100ZACG Ethernet Smart Cable Accessory Kit

Z8 Encore! XP® F0823 Series Product Specification 220 Part Number Suffix Designations Zilog part numbers consist of a number of components, as indicated in the following example. Example. Part number Z8F0423SH005SG is an 8-bit 20 MHz Flash MCU with 4 KB of Program Memory and equipped with 6–22 I/O lines and 4–8 ADC channels in a 20-pin SOIC package, operating within a 0ºC to +70ºC temperature range and built using lead- free solder. Z8 F 04 23 S H 005 S G Environmental Flow G = Green Plastic Packaging Compound Temperature Range S = Standard, 0°C to 70°C E = Extended, –40°C to +105°C Speed 020 = 20 MHz Pin Count B = 8 H = 20 J = 28 Package H = SSOP P = PDIP S = SOIC Device Type 23 = 6–22 I/O lines, 4–8 ADC channels 13 = 6–24 I/O lines, no ADC channels Memory Size 08 = 8 KB Flash, 1 KB RAM 04 = 4 KB Flash, 1 KB RAM 02 = 2 KB Flash, 512 B RAM 01 = 1 KB Flash, 256 B RAM Memory Type F = Flash Device Family Z8 = Zilog’s 8-Bit Microcontroller

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 221 Index Numerics 10-bit ADC 4 A absolute maximum ratings 196 AC characteristics 200 ADC 178 architecture 121 block diagram 122 continuous conversion 124 control register 126, 129 control register definitions 126 data high byte register 130 data low bits register 131 electrical characteristics and timing 203 operation 122 single-shot conversion 123 ADCCTL register 126, 129 ADCDH register 130 ADCDL register 131 ADCX 178 ADD 178 add - extended addressing 178 add with carry 178 add with carry - extended addressing 178 additional symbols 177 address space 13 ADDX 178 analog signals 10 analog-to-digital converter (ADC) 121 AND 181 ANDX 181 arithmetic instructions 178 assembly language programming 174 assembly language syntax 175 B B 177 b 176 baud rate generator, UART 108 BCLR 179 binary number suffix 177 BIT 179 bit 176 clear 179 manipulation instructions 179 set 179 set or clear 179 swap 179 test and jump 181 test and jump if non-zero 181 test and jump if zero 181 bit jump and test if non-zero 181 bit swap 181 block diagram 3 block transfer instructions 179 BRK 181 BSET 179 BSWAP 179, 181 BTJ 181 BTJNZ 181 BTJZ 181 C CALL procedure 181 CAPTURE mode 89 CAPTURE/COMPARE mode 89 cc 176 CCF 180 characteristics, electrical 196 clear 180 CLR 180 COM 181 COMPARE 89 compare - extended addressing 178 COMPARE mode 89 compare with carry 178

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 222 compare with carry - extended addressing 178 complement 181 complement carry flag 179, 180 condition code 176 continuous conversion (ADC) 124 CONTINUOUS mode 88 control register definition, UART 108 Control Registers 13, 16 COUNTER modes 89 CP 178 CPC 178 CPCX 178 CPU and peripheral overview 4 CPU control instructions 180 CPX 178 Customer Support 230 D DA 176, 178 data memory 15 DC characteristics 197 debugger, on-chip 156 DEC 178 decimal adjust 178 decrement 178 decrement and jump non-zero 181 decrement word 178 DECW 178 destination operand 177 device, port availability 33 DI 180 direct address 176 disable interrupts 180 DJNZ 181 dst 177 E EI 180 electrical characteristics 196 ADC 203 flash memory and timing 202 GPIO input data sample timing 204 Watchdog Timer 202, 204 enable interrupt 180 ER 176 extended addressing register 176 external pin reset 25 eZ8 CPU features 4 eZ8 CPU instruction classes 178 eZ8 CPU instruction notation 176 eZ8 CPU instruction set 174 eZ8 CPU instruction summary 182 F FCTL register 141, 148, 149 features, Z8 Encore! 1 first opcode map 194 FLAGS 177 flags register 177 flash controller 4 option bit address space 149 option bit configuration - reset 146 program memory address 0000H 149 program memory address 0001H 150 flash memory 134 arrangement 135 byte programming 139 code protection 137 configurations 134 control register definitions 141, 148 controller bypass 140 electrical characteristics and timing 202 flash control register 141, 148, 149 flash option bits 138 flash status register 142 flow chart 136 frequency high and low byte registers 144 mass erase 139 operation 135 operation timing 137 page erase 139 page select register 142, 144 FPS register 142, 144 FSTAT register 142

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 223 G GATED mode 89 general-purpose I/O 33 GPIO 4, 33 alternate functions 34 architecture 34 control register definitions 40 input data sample timing 204 interrupts 40 port A-C pull-up enable sub-registers 47, 48, 49 port A-H address registers 41 port A-H alternate function sub-registers 43 port A-H control registers 42 port A-H data direction sub-registers 43 port A-H high drive enable sub-registers 45 port A-H input data registers 50 port A-H output control sub-registers 44 port A-H output data registers 51 port A-H stop mode recovery sub-registers 46 port availability by device 33 port input timing 205 port output timing 206 H H 177 HALT 180 halt mode 31, 180 hexadecimal number prefix/suffix 177 I I2C 4 IM 176 immediate data 176 immediate operand prefix 177 INC 178 increment 178 increment word 178 INCW 178 indexed 177 indirect address prefix 177 indirect register 176 indirect register pair 176 indirect working register 176 indirect working register pair 176 infrared encoder/decoder (IrDA) 117 Instruction Set 174 instruction set, eZ8 CPU 174 instructions ADC 178 ADCX 178 ADD 178 ADDX 178 AND 181 ANDX 181 arithmetic 178 BCLR 179 BIT 179 bit manipulation 179 block transfer 179 BRK 181 BSET 179 BSWAP 179, 181 BTJ 181 BTJNZ 181 BTJZ 181 CALL 181 CCF 179, 180 CLR 180 COM 181 CP 178 CPC 178 CPCX 178 CPU control 180 CPX 178 DA 178 DEC 178 DECW 178 DI 180 DJNZ 181 EI 180 HALT 180 INC 178 INCW 178 IRET 181 JP 181

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 224 LD 180 LDC 180 LDCI 179, 180 LDE 180 LDEI 179 LDX 180 LEA 180 load 180 logical 181 MULT 179 NOP 180 OR 181 ORX 181 POP 180 POPX 180 program control 181 PUSH 180 PUSHX 180 RCF 179, 180 RET 181 RL 181 RLC 181 rotate and shift 181 RR 182 RRC 182 SBC 179 SCF 179, 180 SRA 182 SRL 182 SRP 180 STOP 180 SUB 179 SUBX 179 SWAP 182 TCM 179 TCMX 179 TM 179 TMX 179 TRAP 181 Watchdog Timer refresh 180 XOR 181 XORX 181 instructions, eZ8 classes of 178 interrupt control register 68 Interrupt Controller 54 interrupt controller architecture 54 interrupt assertion types 57 interrupt vectors and priority 57 operation 56 register definitions 59 software interrupt assertion 58 interrupt edge select register 66 interrupt request 0 register 59 interrupt request 1 register 60 interrupt request 2 register 61 interrupt return 181 interrupt vector listing 54 interrupts UART 105 IR 176 Ir 176 IrDA architecture 117 block diagram 117 control register definitions 120 operation 117 receiving data 119 transmitting data 118 IRET 181 IRQ0 enable high and low bit registers 61 IRQ1 enable high and low bit registers 63 IRQ2 enable high and low bit registers 65 IRR 176 Irr 176 J JP 181 jump, conditional, relative, and relative conditional 181 L LD 180 LDC 180 LDCI 179, 180 LDE 180

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 225 LDEI 179, 180 LDX 180 LEA 180 load 180 load constant 179 load constant to/from program memory 180 load constant with auto-increment addresses 180 load effective address 180 load external data 180 load external data to/from data memory and auto- increment addresses 179 load external to/from data memory and auto-incre- ment addresses 180 load instructions 180 load using extended addressing 180 logical AND 181 logical AND/extended addressing 181 logical exclusive OR 181 logical exclusive OR/extended addressing 181 logical instructions 181 logical OR 181 logical OR/extended addressing 181 low power modes 30 M master interrupt enable 56 memory data 15 program 13 mode CAPTURE 89 CAPTURE/COMPARE 89 CONTINUOUS 88 COUNTER 89 GATED 89 ONE-SHOT 88 PWM 89 modes 89 MULT 179 multiply 179 MULTIPROCESSOR mode, UART 103 N NOP (no operation) 180 notation b 176 cc 176 DA 176 ER 176 IM 176 IR 176 Ir 176 IRR 176 Irr 176 p 176 R 176 r 176 RA 177 RR 177 rr 177 vector 177 X 177 notational shorthand 176 O OCD architecture 156 auto-baud detector/generator 159 baud rate limits 160 block diagram 156 breakpoints 161 commands 162 control register 166 data format 159 DBG pin to RS-232 Interface 157 DEBUG mode 158 debugger break 181 interface 157 serial errors 160 status register 168 timing 207 OCD commands execute instruction (12H) 166 read data memory (0DH) 165 read OCD control register (05H) 163

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 226 read OCD revision (00H) 163 read OCD status register (02H) 163 read program counter (07H) 164 read program memory (0BH) 164 read program memory CRC (0EH) 165 read register (09H) 164 read runtime counter (03H) 163 step instruction (10H) 165 stuff instruction (11H) 166 write data memory (0CH) 165 write OCD control register (04H) 163 write program counter (06H) 163 write program memory (0AH) 164 write register (08H) 164 on-chip debugger (OCD) 156 on-chip debugger signals 10 ONE-SHOT mode 88 opcode map abbreviations 193 cell description 192 first 194 second after 1FH 195 Operational Description 21, 30, 33, 69, 91, 97, 117, 121, 132, 134, 146, 156, 169, 173 OR 181 ordering information 211 ORX 181 P p 176 Packaging 210 part selection guide 2 PC 177 peripheral AC and DC electrical characteristics 201 pin characteristics 11 Pin Descriptions 7 polarity 176 POP 180 pop using extended addressing 180 POPX 180 port availability, device 33 port input timing (GPIO) 205 port output timing, GPIO 206 power supply signals 10 Power-on and Voltage Brownout electrical charac- teristics and timing 201 Power-On Reset (POR) 23 program control instructions 181 program counter 177 program memory 13 PUSH 180 push using extended addressing 180 PUSHX 180 PWM mode 89 PxADDR register 41 PxCTL register 42 R R 176 r 176 RA register address 177 RCF 179, 180 receive IrDA data 119 receiving UART data-interrupt-driven method 102 receiving UART data-polled method 101 register 176 ADC control (ADCCTL) 126, 129 ADC data high byte (ADCDH) 130 ADC data low bits (ADCDL) 131 flash control (FCTL) 141, 148, 149 flash high and low byte (FFREQH and FRE- EQL) 144 flash page select (FPS) 142, 144 flash status (FSTAT) 142 GPIO port A-H address (PxADDR) 41 GPIO port A-H alternate function sub-registers GPIO port A-H control address (PxCTL) 42 GPIO port A-H data direction sub-registers 43 OCD control 166 OCD status 168 UARTx baud rate high byte (UxBRH) 115 UARTx baud rate low byte (UxBRL) 115 UARTx Control 0 (UxCTL0) 112, 115

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 227 UARTx control 1 (UxCTL1) 113 UARTx receive data (UxRXD) 109 UARTx status 0 (UxSTAT0) 110 UARTx status 1 (UxSTAT1) 111 UARTx transmit data (UxTXD) 109 Watchdog Timer control (WDTCTL) 94, 133 watch-dog timer control (WDTCTL) 172 Watchdog Timer reload high byte (WDTH) 95 Watchdog Timer reload low byte (WDTL) 95 Watchdog Timer reload upper byte (WDTU) register file 13 register pair 177 register pointer 177 reset and stop mode characteristics 21 and stop mode recovery 21 carry flag 179 sources 23 RET 181 return 181 RL 181 RLC 181 rotate and shift instructions 181 rotate left 181 rotate left through carry 181 rotate right 182 rotate right through carry 182 RP 177 RR 177, 182 rr 177 RRC 182 S SBC 179 SCF 179, 180 second opcode map after 1FH 195 set carry flag 179, 180 set register pointer 180 shift right arithmetic 182 shift right logical 182 signal descriptions 9 single-sho conversion (ADC) 123 software trap 181 source operand 177 SP 177 SRA 182 src 177 SRL 182 SRP 180 stack pointer 177 STOP 180 STOP mode 30, 180 Stop Mode Recovery sources 26 using a GPIO port pin transition 27, 28 using Watchdog Timer time-out 27 SUB 179 subtract 179 subtract - extended addressing 179 subtract with carry 179 subtract with carry - extended addressing 179 SUBX 179 SWAP 182 swap nibbles 182 symbols, additional 177 T TCM 179 TCMX 179 test complement under mask 179 test complement under mask - extended addressing 179 test under mask 179 test under mask - extended addressing 179 timer signals 9 timers 69 architecture 70 block diagram 70 CAPTURE mode 78, 79, 89 CAPTURE/COMPARE mode 82, 89 COMPARE mode 80, 89 CONTINUOUS mode 71, 88 COUNTER mode 72, 73 COUNTER modes 89 GATED mode 81, 89

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 228 ONE-SHOT mode 70, 88 operating mode 70 PWM mode 75, 76, 89 reading the timer count values 83 reload high and low byte registers 84 timer control register definitions 83 timer output signal operation 83 timers 0-3 control registers 86, 87 high and low byte registers 83, 86 TM 179 TMX 179 tools, hardware and software 220 transmit IrDA data 118 transmitting UART data-polled method 99 transmitting UART dat-interrupt-driven method 100 TRAP 181 U UART 4 architecture 97 baud rate generator 108 control register definitions 108 controller signals 9 interrupts 105 MULTIPROCESSOR mode 103 receiving data using interrupt-driven method 102 receiving data using the polled method 101 transmitting data using the interrupt-driven method 100 transmitting data using the polled method 99 x baud rate high and low registers 115 x control 0 and control 1 registers 112 x status 0 and status 1 registers 110, 111 UxBRH register 115 UxBRL register 115 UxCTL0 register 112, 115 UxCTL1 register 113 UxRXD register 109 UxSTAT0 register 110 UxSTAT1 register 111 UxTXD register 109 V vector 177 Voltage Brownout reset (VBR) 24 W Watchdog Timer approximate time-out delay 91 CNTL 24 control register 94, 171 electrical characteristics and timing 202, 204 interrupt in normal operation 92 interrupt in STOP mode 92 refresh 92, 180 reload unlock sequence 93 reload upper, high and low registers 94 reset 25 reset in normal operation 93 reset in STOP mode 93 time-out response 92 Watchdog Timer Control Register (WDTCTL) 94 WDTCTL register 94, 133, 172 WDTH register 95 WDTL register 95 WDTU register 95 working register 176 working register pair 177 X X 177 XOR 181 XORX 181 Z Z8 Encore! block diagram 3 features 1

PS024315-1011 P R E L I M I N A R Y Index Z8 Encore! XP® F0823 Series Product Specification 229 part selection guide 2

PS024315-1011 P R E L I M I N A R Y Customer Support Z8 Encore! XP® F0823 Series Product Specification 230 Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at  http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other fac- ets about Zilog product offerings, please visit the Zilog Knowledge Base at http:// zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com.

Product Information

Z8F0113 specifications and overview.

Summary

High-Performance 8-Bit Microcontrollers

Description

High-Performance 8-Bit Microcontrollers

Source title Z8F0113 Datasheet(PDF) - Zilog, Inc.

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