Z8E001

Z8E001 ZILOG | Alldatasheet

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P RELIMINARY P RODUCT S PECIFICATION Z8E001 CMOS OTP M ICROCONTROLLER

FEATURES

Microcontroller Core Features n All Instructions Execute in one 1 m s Instruction Cycle with 10 MHz Crystal n 1K x 8 On-Chip OTP EPROM Memory n 64 x 8 General-Purpose Registers (SRAM) n Six Vectored Interrupts with Fixed Priority n Operating Speed: DC - 10 MHz n Six Addressing Modes: R, IR, X, D, RA, & IM Peripheral Features n

13 Total Input/Output Pins

n One 8-Bit I/O Port (Port A) – I/O Bit Programmable – Each Bit Programmable as Push-Pull or Open- Drain n One 5-Bit I/O Port (Port B) – I/O Bit Programmable – Includes Special Functionality: Stop-Mode Recovery Input Comparator Inputs Selectable Edge Interrupts Timer Output n One Analog Comparator n 16-Bit Programmable Watch-Dog Timer (WDT) n Software Programmable Timers Configurable as: – Two 8-Bit Standard Timers and One 16-Bit Standard Timer or – One 16-Bit Standard Timer and One 16-Bit Pulse Width Modulator (PWM) Timer Additional Features n On-Chip Oscillator that Accepts XTAL, Ceramic Resonator, LC, or External Clock n Programmable Options: – EPROM Protect n Power Reduction Modes: – HALT Mode with Peripheral Units Active – STOP Mode with all Functionality Shut Down CMOS/Technology Features n Low-Power Consumption n 3.0V to 5.5V Operating Range @ 0 C to +70 C 4.5V to 5.5V Operating Range @ -40 C to +105 C n 18-Pin DIP,SOIC, and 20-Pin SSOP Packages. Part ROM RAM* Speed Number (KB) (Bytes) (MHz) Z8E001 1 64 10 * General-Purpose

cally desirable with masked ROM versions. /B/W (BYTE is active Low, only). Figure 1. Functional Block Diagram

Figure 2. EPROM Programming Mode Block Diagram

Figure 3. 18-Pin DIP/SOIC Pin Identification/EPROM Programming Mode Table 1. 18-Pin DIP/SOIC Pin Assignments/EPROM Programming Mode

5 ADCLR/V

15 GND Ground

16 NC No Connection

17 XTAL1 1MHz Clock Input

18 ADCLK Address Clock Input

Figure 4. 18-Pin DIP/SOIC Pin Identification Table 2. 18-Pin DIP/SOIC Pin Assignments

18 PB0 Port B, Pin 0 In/Output

Figure 5. 20-Pin SSOP Pin Identification Table 3. 20-Pin SSOP Pin Assignments

6 NC No Connection

15 NC No Connection

20 PB0 Port B, Pin 0 In/Output

Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode Table 4. 20-Pin SSOP Pin Assignments/EPROM Programming Mode

17 GND Ground

18 NC No Connection

19 XTAL1 1MHz Clock Input

20 ADCLK Address Clock Input

CMOS OTP Microcontroller Zilog P R E L I M I N A R Y DS97Z8X1300 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This is a stress rating only; functional operation of the device at any condition above those indicated in the oper- ational sections of these specifications is not implied. Ex- posure to absolute maximum rating conditions for an ex- tended period may affect device reliability. Total power dissipation should not exceed 880 mW for the package. Power dissipation is calculated as follows: Parameter Min Max Units Note Ambient Temperature under Bias –40 +105 C Storage Temperature –65 +150 C Voltage on any Pin with Respect to V SS –0.6 +7 V 1 Voltage on V DD Pin with Respect to V SS –0.3 +7 V Voltage on /RESET Pin with Respect to V SS –0.6 V DD +1 V 2 Total Power Dissipation 880 mW Maximum Allowable Current out of V SS 80 mA Maximum Allowable Current into V DD 80 mA Maximum Allowable Current into an Input Pin –600 +600 m Maximum Allowable Current into an Open-Drain Pin –600 +600 m Maximum Allowable Output Current Sunk by Any I/O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Maximum Allowable Output Current Sunk by Port A 40 mA Maximum Allowable Output Current Sourced by Port A 40 mA Maximum Allowable Output Current Sunk by Port B 40 mA Maximum Allowable Output Current Sourced by Port B 40 mA Notes: 1. This applies to all pins except the /RESET pin and where otherwise noted. 2. There is no input protection diode from pin to V DD 3. This excludes XTAL pins. 4. Device pin is not at an output Low state. Total Power Dissipation = V DD x [I DD - (sum of I OH + sum of [(V DD - V OH ) x I OH + sum of (V x I

TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Figure 7. Test Load Diagram

CMOS OTP Microcontroller Zilog

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DC ELECTRICAL CHARACTERISTICS TA = 0°C to +70 °C Typical [1] Sym Parameter VCC [3] Min Max @ 25 °C Units Conditions Notes VCH Clock Input High Voltage 3.0V 0.7V CC VCC +0.3 1.3 V Driven by External Clock Generator 5.5V 0.7V CC VCC +0.3 2.5 V Driven by External Clock Generator VCL Clock Input Low Voltage 3.0V V SS –0.3 0.2V CC 0.7 V Driven by External Clock Generator 5.5V V SS –0.3 0.2V CC 1.5 V Driven by External Clock Generator VIH Input High Voltage 3.0V 5.5V 0.7VCC 0.7VCC VCC +0.3 VCC +0.3 1.3 2.5 V V VIL Input Low Voltage 3.0V 5.5V VSS –0.3 VSS –0.3 0.2VCC 0.2VCC 0.7 1.5 V V VOH Output High Voltage 3.0V V CC –0.4 3.1 V I OH = –2.0 mA 5.5V V CC –0.4 4.8 V I OH = –2.0 mA VOL1 Output Low Voltage 3.0V 0.6 0.2 V I OL = +4.0 mA 5.5V 0.4 0.1 V I OL = +4.0 mA VOL2 Output Low Voltage 3.0V 1.2 0.5 V I OL = +6 mA, 5.5V 1.2 0.5 V I OL = +12 mA, VRH Reset Input High Voltage 3.0V 0.5VCC VCC 1.1 V 5.5V 0.5V CC VCC 2.2 V VRL Reset Input Low Voltage 3.0V VSS –0.3 0.2V CC 0.9 V 5.5V V SS –0.3 0.2V CC 1.4 V VOFFSET Comparator Input Offset Voltage 3.0V 25.0 10.0 mV 5.5V 25.0 10.0 mV IIL Input Leakage 3.0V –1.0 2.0 0.064 mAV IN = 0V, VCC 5.5V –1.0 2.0 0.064 mAV IN = 0V, VCC IOL Output Leakage 3.0V –1.0 2.0 0.114 mAV IN = 0V, VCC 5.5V –1.0 2.0 0.114 mAV IN = 0V, VCC VICR Comparator Input Common Mode Voltage Range 3.0V V SS –0.3 V CC –1.0 V 7 5.5V V SS –0.3 V CC –1.0 V 7 IIR Reset Input Current 3.0V -10 -60 -30 mA 5.5V -20 -180 -100 mA ICC Supply Current 3.0V 2.5 2.0 mA @ 10 MHz 4,5 5.5V 6.0 4.0 mA @ 10 MHz 4,5 ICC1 Standby Current 3.0V 2.0 1.0 mA HALT Mode V IN = 0V,VCC @ 10 MHz 4,5 5.5V 2.0 1.0 mA HALT Mode V IN = 0V,VCC @ 10 MHz 4,5

Zilog CMOS OTP Microcontroller DS97Z8X1300 P R E L I M I N A R Y 11 TA = 0 °C to +70 °C Typical [1] Sym Parameter VCC [3] Min Max @ 25 °C Units Conditions Notes ICC2 Standby Current 3.0V 500 150 nA STOP Mode V IN = 0V, VCC 6 5.5V 500 250 nA STOP Mode V IN = 0V,VCC 6 Notes: 1. Typical values are measured at VCC = 3.3V and VCC = 5.0V. 2. VSS = 0V = GND 5.0 V +/- 0.5 V. 4. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 5. CL1 = CL2 = 22 pF. 6. Same as note [4] except inputs at VCC . 7. For analog comparator input when analog comparator is enabled.

CMOS OTP Microcontroller Zilog

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DC ELECTRICAL CHARACTERISTICS (Continued) TA = -40°C to +105°C Typical [1] Sym Parameter VCC [3] Min Max @ 25 °C Units Conditions Notes VCH Clock Input High Voltage 4.5V 0.7 V CC VCC +0.3 2.5 V Driven by External Clock Generator 5.5V 0.7 V CC VCC +0.3 2.5 V Driven by External Clock Generator VCL Clock Input Low Voltage 4.5V V SS –0.3 0.2 VCC 1.5 V Driven by External Clock Generator 5.5V V SS –0.3 0.2 VCC 1.5 V Driven by External Clock Generator VIH Input High Voltage 4.5V 0.7 VCC VCC +0.3 2.5 V 5.5V 0.7 V CC VCC +0.3 2.5 V VIL Input Low Voltage 4.5V V SS –0.3 0.2 VCC 1.5 V 5.5V V SS –0.3 0.2 VCC 1.5 V VOH Output High Voltage 4.5V VCC –0.4 4.8 V I OH = –2.0 mA 5.5V V CC –0.4 4.8 V I OH = –2.0 mA VOL1 Output Low Voltage 4.5V 0.4 0.1 V I OL = +4.0 mA 5.5V 0.4 0.1 V I OL = +4.0 mA VOL2 Output Low Voltage 4.5V 1.2 0.5 V I OL = +12 mA, 5.5V 1.2 0.5 V I OL = +12 mA, VRH Reset Input High Voltage 4.5V 0.5V CC VCC 1.1 V 5.5V 0.5V CC VCC 2.2 V VOFFSET Comparator Input Offset Voltage 4.5V 25.0 10.0 mV 5.5V 25.0 10.0 mV IIL Input Leakage 4.5V -1.0 2.0 <1.0 mAV IN = 0V, VCC 5.5V -1.0 2.0 <1.0 mAV IN = 0V, VCC IOL Output Leakage 4.5V -1.0 2.0 <1.0 mAV IN = 0V, VCC 5.5V -1.0 2.0 <1.0 mAV IN = 0V, VCC VICR Comparator Input Common Mode Voltage Range 4.5V 0 V CC –1.5V V 7 5.5V 0 V CC –1.5V V 7 IIR Reset Input Current 4.5V -18 -180 -112 mA 5.5V -18 -180 -112 mA ICC Supply Current 4.5V 7.0 4.0 mA @ 10 MHz 4,5 5.5V 7.0 4.0 mA @ 10 MHz 4,5 ICC1 Standby Current 4.5V 2.0 1.0 mA HALT Mode V IN = 0V, VCC @ 10 MHz 4,5 5.5V 2.0 1.0 mA HALT Mode V IN = 0V, VCC @ 10 MHz 4,5

Zilog CMOS OTP Microcontroller DS97Z8X1300 P R E L I M I N A R Y 13 TA = -40 °C to +105 °C Typical [1] Sym Parameter V CC [3] Min Max @ 25 °C Units Conditions Notes ICC2 Standby Current 4.5V 700 250 nA STOP Mode V IN = 0V, VCC 6 5.5V 700 250 nA STOP Mode V IN = 0V, VCC 6 Notes: 1. Typical values are measured at VCC = 3.3V and VCC = 5.0V. 2. VSS = 0V = GND 5.0 V +/- 0.5 V. 4. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 5. CL1 = CL2 = 22 pF. 6. Same as note [4] except inputs at VCC . 7. For analog comparator input when analog comparator is enabled.

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Figure 8. AC Electrical Timing Diagram

10 MHz

7 Tost

1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.

Zilog CMOS OTP Microcontroller DS97Z8X1300 P R E L I M I N A R Y 15 TA = –40 °C to +105 °C [2] Min Max Units Notes 1 TpC Input Clock Period 4.5V 100 DC ns 1 5.5V 100 DC ns 1

2 TrC,TfC Clock Input Rise

4.5V 15 ns 1 5.5V 15 ns 1 3 TwC Input Clock Width 4.5V 50 ns 1 5.5V 50 ns 1 4 TwIL Int. Request Input Low Time 4.5V 70 ns 1 5.5V 70 ns 1 5 TwIH Int. Request Input High Time 4.5V 5TpC 1 5.5V 5TpC 1

6 Twsm STOP Mode Recovery

Width Spec. 4.5V 12 ns 5.5V 12 ns Oscillator Start-Up Time 4.5V 5TpC 5.5V 5TpC Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.

CMOS OTP Microcontroller Zilog

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The Z8E001 is based on the Zilog Z8Plus Core Architec- ture. This core is capable of addressing up to 64KBytes of program memory and 4KBytes of RAM. Register RAM is accessed as either 8 or 16 bit registers using a combina- tion of 4, 8, and 12 bit addressing modes. The architecture supports up to 15 vectored interrupts from external and in- ternal sources. The processor decodes 44 CISC instruc- tions using six addressing modes. See the Z8 Plus User’s Manual (UM97Z8X0300) for more information. RESET This section describes the Z8E001 reset conditions, reset timing, and register initialization procedures. Reset is gen- erated by the Reset Pin, Watch-Dog Timer (WDT), and Stop-Mode Recovery (SMR). A system reset overrides all other operating conditions and puts the Z8E001 into a known state. To initialize the chip’s internal logic, the /RESET input must be held Low for at least 30 XTAL clock cycles. The control registers and ports are reset to their default conditions after a reset from the /RESET pin. The control registers and ports are not reset to their default conditions after wakeup from Stop Mode or WDT timeout. During RESET, the program counter is loaded with 0020H. I/O ports and control registers are configured to their de- fault reset state. Resetting the Z8E001 does not effect the contents of the general-purpose registers. RESET PIN OPERATION The Z8E001 hardware /RESET pin initializes the control and peripheral registers, as shown in Table 4. Specific re- set values are shown by 1 or 0, while bits whose states are unchanged are indicated by the letter U. /RESET must be held low until the oscillator stabilizes, then for an additional 30 XTAL clock cycles to be sure that the internal reset is complete. The /RESET pin has a Schmitt-Trigger input with a trip point. There is no high side protection diode. The user should place an external diode from /RESET to V CC . A pull-up resistor on the /RESET pin is approximately 500 K-ohms, typical. Program execution starts 10 XTAL clock cycles after /RE- SET has returned High. The initial instruction fetch is from location 0020H. Figure 7 shows reset timing. After a reset, the first routine executed must be one that initializes the TCTLHI control register to the required sys- tem configuration, followed by initialization of the remain- ing control registers.

Table 5. Control and Peripheral Register Reset Values

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Figure 9. Reset Timing

10 XTAL CLOCK CYCLES

Figure 10. Example of External Power-On Reset

Figure 11. Z8E001 Reset Circuitry with WDT and SMR

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if the device enters Stop mode. WDT and SMR flags. A WDT timeout sets the WDT flag. does not reset it to zero, the user must clear it via software. Failure to clear the flag may result in undefined behavior. executing the first instruction after the part leaves RESET. this register to be written. Figure 12. Z8E001 TCTLHI Register for Control of WDT

eout period when coming out of RESET. Bits 2, 1 and 0. These bits are reserved and must be 0. applied to the timers and interrupt logic. NOP instruction immediately before the HALT instruction. from the instruction after the HALT instruction. Figure 13. Time-Out Period of the WDT The default on reset is D6 = D5 = D4 = 1.

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lator and internal system clock. sets: /RESET pin or a STOP-Mode Recovery source. this flag may result in undefined behavior. does not initialize the control registers. n VCC is at the low end of the devices operating range. n Output current sourcing is minimized. ramic resonator, LC clock, or an external clock source. Figure 14. Z8E001 Clock Circuit

pedances (not disturbed by stray effects). to provide the other 180 degrees of phase shift. vides additional phase shift. sible to the oscillator pins of the Z8E001. into the oscillator (Figure 14). Figure 15. Pierce Oscillator with Internal Feedback

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frequency, or crystal Rs is too large. should be greater than 10 Mohms. Figure 16. Circuit Board Design Rules

CMOS OTP Microcontroller Zilog

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The Z8E001 oscillator can use a LC network to generate a XTAL clock (Figure 16). The frequency stays stable over VCC and temperature. The oscillation frequency is determined by the equation: where L is the total inductance including parasitics and CT is the total series capacitance including the parasitics. Simple series capacitance is calculated using the following equation: Sample calculation of capacitance C1 and C2 for 5.83 MHz frequency and inductance value of 27 uH: TIMERS For the Z8E001, 8-bit timers T0 and T1 are available to function as a pair of independent 8-bit standard timers, or they can be cascaded to function as a 16-bit PWM timer. In addition, 8-bit timers T2 and T3 are provided but they can only operate in cascade to function as a 16-bit stan- dard timer. Frequency = 2p (LC T) 1/2 1/ CT If C1 1/CT = 1/C1 + 1/C2 = C2 = 2 C1 = 2CT 5.83 (10^6) = 1 C T = 27.6 pf Thus C1 = 55.2 pf and C2 = 55.2 pf.

Figure 20. Timers Block Diagram

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Figure 21. TCTLLO Register BY CASCADING 8-BIT TIMERS T3(MSB) AND T2(LSB).

Zilog CMOS OTP Microcontroller DS97Z8X1300 P R E L I M I N A R Y 29 Each 8-bit timer is given a pair of registers, which are both readable and writable. One of the registers is defined to contain the auto-initialization value for the timer, while the second register contains the current value for the timer. When a timer is enabled, the timer will decrement whatev- er value is currently held in its count register, and will then continue decrementing until it reaches 0, at which time an interrupt will be generated and the contents of the auto-ini- tialization register are optionally copied into the count val- ue register. If auto-initialization is not enabled, the timer will stop counting upon reaching 0 and control logic will clear the appropriate control register bit to disable the tim- er.This is referred to as "single-shot" operation. If auto-ini- tialization is enabled, the timer will continue counting from the initialization value. Software should not attempt to use registers that are defined as having timer functionality. Software is allowed to write to any register at any time, but care should be taken if timer registers be updated while the timer is enabled. If software updates the count value while the timer is in operation, the timer will continue counting based upon the software-updated value. This can produce strange behavior if the software update occurred at exactly the point that the timer was reaching 0 to trigger an inter- rupt and/or reload. Similarly, if software updates the initialization value regis- ter while the timer is active, the next time that the timer reaches 0, it will be initialized using the updated value. Again, strange behavior could result if the initialization val- ue register is being written while the timer is in the process of being initialized. Whether initialization is done with the new or old value is a function of the exact timing of the write operation. In all cases, the Z8E001 will prioritize the software write above that of a decrementer writeback. However, when hardware clears a control register bit for a timer that is configured for single-shot operation; the clear- ing of the control bit will override a software write. Reading either register can be done at any time, and will have no effect on the functionality of the timer. If a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. In this case, a single interrupt will be generat- ed, and the interrupt will correspond to the even 8-bit timer. For example, timers T2 and T3 are cascaded to form a sin- gle 16-bit timer, so the interrupt for the combined timer will be defined to be that of timer T2 rather than T3. When a timer pair is specified to act as a single 16-bit timer, the even timer registers in the pair (timer T0 or T2) will be de- fined to hold the timer’s least significant byte; while the odd timer in the pair will hold the timer’s most significant byte. In parallel with the posting of the interrupt request, the in- terrupting timer’s count value will be initialized by copying the contents of the auto-initialization value register to the count value register. It should be noted that any time that a timer pair is defined to act as a single 16-bit timer, that the auto-reload function will be performed automatically. All 16-bit timers will continue counting while their interrupt requests are active, and will operate in a free-running man- ner. If interrupts are disabled for a long period of time, it is pos- sible for the timer to decrement to 0 again before its initial interrupt has been responded to. This is a degenerate case, and hardware is not required to detect this condition. When the timer control register is written, all timers that are enabled by the write will begin counting using the value that is held in their count register. An auto-initialization is not performed. All timers can receive an internal clock source only. Each timer that is enabled will be updated ev- ery 8th XTAL clock cycle. If T0 and T1 are defined to work independently, then each will work as an 8-bit timer with a single auto-initialization register; T0ARLO for T0, and T1ARLO for T1. Each timer will assert its predefined interrupt when it times out, and will optionally perform the auto-initialization function. If T0 and T1 are cascaded to form a single 16-bit timer, then the single 16-bit timer will be capable of performing as a Pulse- Width Modulator (PWM). This timer is referred to as T01 to distinguish it as having special functionality that is not available when T0 and T1 act independently. When T01 is enabled, it can use a pair of 16-bit auto-initial- ization registers. In this mode, one 16-bit auto-initialization value is composed of the concatenation of T1ARLO and T0ARLO, and the second auto-initialization value is com- posed of the concatenation of T1ARHI and T0ARHI. When T01 times out, it will alternately initialize its count value us- ing the LO auto-init pair followed by the HI auto-init pair. This functionality corresponds to a PWM where the T1 in- terrupt will define the end of the HI section of the wave- form, and the T0 interrupt will mark the end of the LO por- tion of the PWM waveform. To use the cascaded timers as a PWM, one must initialize the T0 and T1 count registers to work in conjunction with the port pin. The user should initialize the T0 and T1 count registers to the PWM_HI auto-init value to obtain the de- sired PWM behavior. The PWM is arbitrarily defined to use the LO autoreload registers first. This implies that it had just timed out after beginning in the HI portion of the PWM waveform. As such, the PWM is defined to assert the T1 interrupt after the first timeout interval. After the auto-initialization has been completed, decre- menting occurs for the number of counts defined by the PWM_LO registers. When decrementing again reaches 0, the T0 interrupt is asserted; and auto-init using the PWM_HI registers occurs. Decrementing occurs for the number of counts defined by the PWM_HI registers until reaching 0, at which time the the T1 interrupt is asserted, and the cycle begins again.

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by toggling the PB1 output when generating an interrupt. output pin on each timer0 timeout. Figure 22. PortB Special Function Register (T

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The Z8E001 has 13 lines dedicated to input and output. only affect the bit in question. that may be defined for each particular port bit. Figure 25. Z8E001 I/O Ports Registers

the next clock cycle with the newly sampled input data. outputs do not sample the value being driven out. ing the directional control and special function registers. event referred to above could be one or more interrupts. tialization has been completed. Control Register (PTADIR at 0D2H) as seen in Figure 24. ures the corresponding bit in Port A as an input. Figure 26. Port A Directional Control Register

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Figure 27. Port A Configuration with Open-Drain Capability and Schmitt-Trigger

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Figure 30. Port A Directional Control Register Figure 31. Port A Special Function Register

Port B is a 5-bit, bidirectional, CMOS-compatible I/O port. grams of all five Port B pins. control conventions for this register. Table 6. Port B Special Functions Figure 32. Port B Special Function Register

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Figure 33. Port B Pin 0 Diagram

Figure 34. Port B Pin 1 Diagram

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Figure 35. Port B Pin 2 Diagram

Figure 36. Port B Pins 3 and 4 Diagram

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Figure 37. Port B Input Value Register Figure 38. Port B Output Value Register

CMOS OTP Microcontroller Zilog

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Port A and Port B output value registers are not affected by RESET. On RESET, the Port A and Port B directional control reg- isters will be cleared to all zeros, which will define all pins in both ports as inputs. On RESET, since the directional control registers have re- defined all pins as inputs, the Port A and Port B input value registers will have the previously held data overwritten with the current sample of the input pins. On RESET, the Port A and Port B special function regis- ters will be cleared to all zeros, which will deactivate all port special functions. Note: The SMR and WDT timeout events are NOT full device resets. None of the port control registers is effected by either of these events. ANALOG COMPARATOR The Z8E001 includes one on-chip analog comparator. Pin PB4 has a comparator front end. The comparator ref- erence voltage is on pin PB3. Comparator Description The on-chip comparator can process an analog signal on PB4 with reference to the voltage on PB3. The analog function is enabled by programming the Port B Special Function Register bits 3 and 4. When the analog comparator function is enabled, bit 4 of the input register will be defined as holding the synchro- nized output of the comparator, while bit 3 will retain a syn- chronized sample of the reference input. If the interrupts for PB4 are enabled when the comparator special function is selected, the output of the comparator will generate interrupts. COMPARATOR OPERATION The comparator output reflects the relationship between the analog input to the reference input. If the voltage on the analog input is higher than the voltage on the refer- ence input, then the comparator output will be at a high state. If the voltage on the analog input is lower than the voltage on the reference input, then the analog output will be at a Low state. Comparator Definitions VICR The usable voltage range for the positive input and the ref- erence input is called the common mode voltage range (V CR ). The comparator is not guaranteed to work if the input is outside of the VICR range. Voffset The absolute value of the voltage between the positive in- put and the reference input required to make the compar- ator output voltage switch is the input offset voltage (V off- set). IIO For the CMOS voltage comparator input, the input offset current (IIO) is the leakage current of the CMOS input gate. HALT Mode The analog comparator is functional during HALT Mode. If the interrupts are enabled, an interrupt generated by the comparator will cause a return from HALT Mode. STOP Mode The analog comparator is disabled during STOP Mode. The comparator is powered down to prevent it from draw- ing any current.

CMOS OTP Microcontroller Zilog

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PACKAGE INFORMATION

Figure 43. 18-Pin DIP Package Diagram Figure 44. 18-Pin SOIC Package Diagram

Figure 45. 20-Pin SSOP Package Diagram

CMOS OTP Microcontroller Zilog

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ORDERING INFORMATION

For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. CODES Preferred Package P = Plastic DIP Longer Lead Time S = SOIC H = SSOP Preferred Temperature S = 0°C to +70°C E = –40°C to +105°C Speed 10 = 10 MHz Environmental C = Plastic Standard Standard Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Z8E00110PSC Z8E00110SSC Z8E00110HSC Extended Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Z8E00110PEC Z8E00110SEC Z8E00110HEC Example: Z 8E001 10 P S C is a Z86E001, 10 MHz, DIP , 0° to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix

Zilog CMOS OTP Microcontroller DS97Z8X1300 P R E L I M I N A R Y 49 Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non- conformance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. © 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change with- out notice. Devices sold by Zilog, Inc. are covered by war- ranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com