Z8E520 ZILOG | Alldatasheet
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P RELIMINARY P RODUCT S PECIFICATION Z8E520/C520
1.5 MBPS USB L
D EVICE C ONTROLLER F OR M ULTIPROTOCOL P OINTING D EVICES
FEATURES
n Six Vectored Interrupts with Fixed Priority n Processor Speed Dividable by Firmware Control n Operating Current: 5 mA typical in USB Mode; 2.5 mA typical in Serial Mode (@ 3 MHz); 5 mA typical in PS/2 Mode n
16 Total Input/Output Pins (Open-Drain/Push-Pull)
n 6 inputs with 3 level Programmable Reference Comparators n 16-Bit Programmable Watch-Dog Timer (WDT) with Internal RC Oscillator n Software Programmable Timers Configurable as: – Two 8-Bit Standard Timers and One 16-Bit Standard Timer or – One 16-Bit Standard Timer and One 16-Bit Pulse Width Modulator (PWM) Timer n Identical Masked ROM Version (Z8C520) n On-Chip Oscillator that accepts a Ceramic Resonator or External Clock n Hardware Support for PS/2, Serial, USB, and General- Purpose I/O (GPIO) n Power Reduction Modes: – STOP Mode (functionality shut down except SMR) – HALT Mode (XTAL still running-peripherals active) n USB SIE Compliant with USB Spec 1.0 n 4.0 VDC to 6.0 VDC Operating Range @ 0 C to +70 C GENERAL DESCRIPTION Zilog’s Z8E520 (OTP) and Z8C520 (Masked ROM) micro- controllers are low-power Z8 Plus MCUs, designed for the cost-effective implementation of USB and multiprotocol pointing devices. For applications demanding powerful I/O capabilities, the Z8E520's input and output lines are grouped into two ports, and are configurable under software control to provide tim- ing, status signals, or parallel I/O. Both 8-bit and 16-bit timers, with a large number of user se- lectable modes, off-load the system of administering real- time tasks such as counting/timing and I/O data communi- cations. The microcontroller clock frequency is derived from the system clock by a programmable divider under firmware control. The device is capable of functioning in four distinct, select- able communications modes: PS/2, RS232, GPIO (Gener- al-purpose I/O), and USB. The communications mode de- termines the functionality of the two special serial communications pins (PB6 and PB7). The device is placed in the required mode when firmware sets the specified mode bit in the communications control register. The firm- ware interface is similar in all modes. The same buffer area in RAM will accept the data to be transmitted. Up to 8 bytes may be loaded, and the data will actually be transmitted as soon as the appropriate command is issued (setting In Packet Ready in USB mode, for example). Part ROM RAM Speed Number (KB) (Bytes) (MHz) Z8E520 (OTP) 6 176 12 Z8C520 (ROM) 6 176 12
1.5 MBPS USB Device Controller Zilog
Figure 1. Z8E520 Functional Block Diagram
6 Analog
6 K Bytes
description of each mode is detailed below. . The serial baud rate is fixed at 12.5 K baud. support (see section below). tivity bit which is set by the SIE. wake up the microcontroller. tal form to differential drive at the proper levels (Figure 2). Figure 2. Data To/From Z8E520/C520
Figure 3. 20-Pin DIP/SOIC Pin Assignments Table 1. 20-Pin DIP/SOIC Pin Identification
16 XTAL (1) Clock
17 GND Pow er
18 XTAL (2) Clock
Figure 4. 20-Pin DIP/SOIC Pin Assignments: Table 2. 20-Pin DIP/SOIC Pin Identification:
9 TST_CLR Reset Internal Address Counter In
10 PGM Program Pin In
11 ADDRCLK Clock to Address Counter In
16 CLK OUT Output from Clock Inverter Out
17 GND Pow er Ref Pow er
18 CLK 1 MHz to chip In
19 Un used
20 Un used
Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This rating is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 880 mW for the package. Power dissipation is calculated as follows: Total Pow er Dissipation = V DD x [I DD – (sum of I OH + sum of [(V DD – V OH ) x I OH + sum of (V x I Parameter Min Max Units Note Ambient Temperature under Bias –40 +105 C Storage Temperature –65 +150 C Voltage on any Pin with Respect to V SS –0.6 +7 V Voltage on V DD Pin with Respect to V SS –0.3 +7 V Total Pow er Dissipation 880 mW Maxim um Allow able Current out of V SS 80 mA Maxim um Allow able Current into V DD 80 mA Maxim um Allow able Current into an Input Pin –600 +600 m A 1 Maxim um Allow able Current into an Open-Drain Pin –600 +600 m A 2 Maxim um Allow able Sink Output Current by Any I/O Pin 25 mA Maxim um Allow able Source Output Current by Any I/O Pin 25 mA Maxim um Allow able Sink Output Current by Port A 40 mA Maxim um Allow able Source Output Current by Port A 40 mA Maxim um Allow able Sink Output Current by Port B 40 mA Maxim um Allow able Source Output Current by Port B 40 mA Notes: 1. Excludes XTAL pins. 2. Device pin is not at an output Low state.
itive current flows into the referenced pin (Figure 5). = GND = 0V; f = 1.0 MHz; unmeasured pins returned to GND. Figure 5. Test Load Diagram
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DC CHARACTERISTICS: USB MODE Vcc = 4.4V – 5.25V TA = 0°C to +70°C Sym Parameter VCC Min Max Units Conditions Notes VCH Clock Input High Voltage 0.7VCC VCC +0.3 V Driven by External Clock Generator VCL Clock Input Low Voltage VSS –0.3 0.2VCC V Driven by External Clock Generator VIH Input High Voltage 0.7VCC VCC +0.3 V VIL Input Low Voltage VSS –0.3 0.2VCC V VOH Output High Voltage (Port A, B) VCC –0.4 V IOH = –2.0 mA VOL1 Output Low Voltage (Port A, B) 0.6 V IOL = +4.0 mA 4 VOL2 Output Low Voltage (Port A, B)
1.2 V IOL = +6 mA, 4
VOFFSET Compar ator Input Offset Voltage 25.0 mV IIL Input Leakage –1.0 2.0 mA VIN = 0V, VCC IOL Output Leakage –1.0 2.0 mA VIN = 0V, VCC VICR Compar ator Input Common Mode Voltage Range V SS –0.3 VCC –1.0 V ICC Supply Current 6.0V 5.25 6.0 mA @ 6 MHz (Internal open drain) 1,2 ICC1 HAL T Mode 6.0V 3.5 mA @ 6 MHz (no CPU; RC/WDT & Detect; D+/D–; I/O active) 1,2 ICC2 Stop Current 60 mA ICC3 Stop Current w/o RC/WDT 40 mA D+, D– Differential Signaling D– > D+ D+ > D– mV @ >200 mV Difference 3 Notes: 1. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 2. CL1 = CL2 = 22 pF 3. Except for SE0 for EOP and Reset (see 7.1.4 of USB Specification) 4. General-Purpose I/O Mode.
Zilog 1.5 MBPS USB Device Controller DS97KEY2005 P R E L I M I N A R Y 9 DC CHARACTERISTICS: PS/2 MODE Vcc = 4.5V – 5.5V TA = 0°C to +70°C Sym Parameter VCC Min Max Units Conditions Notes VCH Clock Input High Voltage 0.7VCC VCC +0.3 V Driven by External Clock Generator VCL Clock Input Low Voltage VSS –0.3 0.2VCC V Driven by External Clock Generator VIH Input High Voltage 0.7VCC VCC +0.3 V VIL Input Low Voltage VSS –0.3 0.2VCC V VOH Output High Voltage VCC –0.4 V IOH = –2.0 mA VOL1 Output Low Voltage 0.6 V IOL = +4.0 mA VOL2 Output Low Voltage 1.2 V IOL = +6 mA, VOFFSET Compar ator Input Offset Voltage 25.0 mV IIL Input Leakage –1.0 2.0 mA VIN = 0V, VCC IOL Output Leakage –1.0 2.0 mA VIN = 0V, VCC VICR Compar ator Input Common Mode Voltage Range V SS –0.3 VCC –1.0 V ICC Supply Current 5.5V 6.0 mA @ 6 MHz 1,2 ICC1 HAL T Current 5.5V 3.5 mA @ 6 MHz (no CPU; no SIE) 1,2 ICC2 Stop Current 60 mA ICC3 Stop Current w/o RC/WDT 40 mA Notes: 1. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 2. CL1 = CL2 = 22 pF.
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DC CHARACTERISTICS: RS232 MODE Vcc = 4.0V – 6.0V TA = 0°C to +70°C Sym Parameter VCC Min Max Units Conditions Notes VCH Clock Input High Voltage 0.7VCC VCC +0.3 V Driven by External Clock Generator VCL Clock Input Low Voltage VSS –0.3 0.2VCC V Driven by External Clock Generator VIH Input High Voltage 0.7VCC VCC +0.3 V VIL Input Low Voltage VSS –0.3 0.2VCC V VOH Output High Voltage VCC –0.4 V IOH = –2.0 mA VOL1 Output Low Voltage 0.6 V IOL = +4.0 mA VOL2 Output Low Voltage 1.2 V IOL = +6 mA, VOFFSET Compar ator Input Offset Voltage 25.0 mV IIL Input Leakage –1.0 2.0 mA VIN = 0V, VCC IOL Output Leakage –1.0 2.0 mA VIN = 0V, VCC VICR Compar ator Input Common Mode Voltage Range V SS –0.3 VCC –1.0 V ICC Supply Current 6.0V 4.0 mA @ 3 MHz (6 MHz/2) 1,2 ICC1 HAL T Mode 6.0V 3.5 mA @ 3 MHz 1,2 ICC2 Stop Current 60 mA ICC3 Stop Current w/o RC/WDT 40 mA Notes: 1. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 2. CL1 = CL2 = 22 pF.
Zilog 1.5 MBPS USB Device Controller DS97KEY2005 P R E L I M I N A R Y 11 DC CHARACTERISTICS: I/O MODE Vcc = 4.0V – 6.0V TA = 0°C to +70°C Sym Parameter VCC Min Max Units Conditions Notes VCH Clock Input High Voltage 0.7VCC VCC +0.3 V Driven by External Clock Generator VCL Clock Input Low Voltage VSS –0.3 0.2VCC V Driven by External Clock Generator VIH Input High Voltage 0.7VCC VCC +0.3 V VIL Input Low Voltage VSS –0.3 0.2VCC V VOH Output High Voltage VCC –0.4 V IOH = –2.0 mA VOL1 Output Low Voltage 0.6 V IOL = +4.0 mA VOL2 Output Low Voltage 1.2 V IOL = +6 mA, VOFFSET Compar ator Input Offset Voltage 25.0 mV IIL Input Leakage –1.0 2.0 mA VIN = 0V, VCC IOL Output Leakage –1.0 2.0 mA VIN = 0V, VCC VICR Compar ator Input Common Mode Voltage Range V SS –0.3 VCC –1.0 V ICC Supply Current 6.0V 6.0 mA @ 6 MHz 1,2 ICCA 5.5V 6.0 mA @ 5.5V 1,2 ICCB 4.0 mA @ 6.0V (6 MHz/2) ICC1 HAL T w/ RC and WDT 60 mA ICC2 50 mA Notes: 1. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 2. CL1 = CL2 = 22 pF.
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Figure 6. AC Electrical Timing Diagram
6 MHz
1 TpC Input Clock Period 83 DC ns 1
2 TrC,TfC Clock Input Rise & Fall Times 5 ns 1
3 TwC Input Clock Width 37 ns 1
4 TwTinL Timer Input Low Width 70 ns 1
6 TpTin Timer Input Period 4TpC 1
7 TrTin Timer Input Rise & Fall Timer 100 ns 1
10 Twsm Stop-Mode Recovery Width Spec 100TpC ns
12 Twdt W atch-Dog Timer 1000 ms
13 D+, D– Differential Rise and Fall Times (USB Mode) 70 300 nS 3
14 POR Pow er supply; POR rate/Volt level
- Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
- See USB Specification 7.1.1.2
- Corresponds to frequencies of 80 KHz to 20 KHz
(3–0) has a Switch configuration. is programmable from 0–15 mA (in 1 mA increments). tional, push-pull or open drain configurations (Figure 8). Figure 7. Port A (4–7) Sink Configuration Table 3. Port A (4–7) Programmable Current Sink Table
0 Zero Code/Disable mA Disabled
- Setting all (4) ISNK cells to full scale is a violation of the Absolute Maximum Rating Spec.
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Figure 8. Port A (0–3) Switch Configuration
Figure 9. Port B (0–5) Quadrature Configuration Table 4. Programmable Voltage Threshold
- Greatest delta vs. specified delta.
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Table 5. Programmable Voltage Bit Selections (Register Addresses DA–DF)
- If all comparators are off, VREF can be powered off. If in Stop Mode, VREF is powered off.
Table 6. Programmable Load Resistor
- Greatest ratio vs. specified ratio.
Table 7. Programmable Load Resistor Bit Selections (Register Addresses DA–DF
000 No load Resistors No load Resistors
Table 8. Comparator
- Zilog will provide specification.
Figure 10. Port B (6–7) Serial Communication Port
7.5 K P ullup
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6 KB of program memory space at internal locations
Figure 11. Z8E520 Program Memor y Map
160 General-Purpose Registers in group 0–7, SIE Buffers
Figure 12. Register Files Table 9. EP Modes for SIE Buffer (In USB Mode)
000 EP1 OFF, EP2 OFF GPR GPR GPR
001 EP1 IN, EP2 OFF GPR GPR EPI IN Buffer
010 EP1 OUT , EP2 OFF GPR GPR EP1 OUT Buffer
011 EP1 CONTR OL EP1 SETUP Buffer EP1 OUT Buffer EP1 IN Buffer
100 EP1 OUT , EP2 OUT GPR EP2 OUT Buffer EP1 OUT Buffer
101 EP1 IN, EP1 OUT GPR EP 1 OUT Buffer EP1 IN Buffer
110 EP1 OUT , EP1 IN GPR EP 1 IN Buffer EP1 OUT Buffer
111 EP1 IN, EP2 IN GPR EP2 IN Buffer EP1 IN Buffer
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Figure 13. System Registers
Figure 14. T/C Control Registers
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Figure 15. COMM Register s (USB Mode: B0–BF)
Zilog 1.5 MBPS USB Device Controller DS97KEY2005 P R E L I M I N A R Y 23 COMMUNICATION REGISTER DEFINITIONS (USB MODE) The following definitions on pages 23–26 describe in detail the specific USB mode registers as illustrated in Figure 15. PORT A, PORT B : I/O Port data registers. At all times, a read to this port should indicate the current state at the pins. Read/Write. ADDR : Determines the USB Device Address. Cleared by USB or POR Reset. Read/Write. SIE MODE : Determines the mode of the SIE communica- tion pins (Port B7:6). Read/Write. The SIE modes are as follows: GPIO : The SIE is off and the communication lines are standard I/O pins on Port B. USB : Port B7 is D+, which connects to pin 3 on a series A, or series B USB connector and whose conductor is green. Port B6 is D–, which connects to pin 2 on a series A or se- ries B USB connector and whose conductor is white. An external 7.5K pull-up should be provided for D–. PS/2: Port B7 is CLOCK, which connects to pin 5 on a male 6-pin Mini-DIN connector and Port B6 is DATA, which connects to pin 1 on a male 6-pin Mini-DIN connector. These signals are open-drain. The CLOCK pin has an available 7.5 K ohm pull-up internal to the chip. An external 7.5 K ohm pull-up should be provided for DATA. RS232 : Port B7 is serial data out (T x D). Port B6 is serial data in (R x D). These signals are CMOS-level signals, positive logic. Appropriate transceiver circuitry must be added externally to comply with RS232-C signal levels at the device connector. SIE POWER : Powers up the SIE when USB Resume sig- naling has been received, or shuts down SIE in prepara- tion for USB Suspend. Read/Write. FORCE RESUME : Forces a K state on the USB pins. Read/Write. ACTIVITY: This bit is set by the SIE when the state of the USB pins changes. Read/Write. J STATE : This bit is set when the USB is in the ‘J’ state and cleared when in ‘K’ or ‘SE0’. Read only. EP MODE : These bits define the operation of the non-zero endpoints of the SIE. Changing this mode resets the SIE, while writing the same value does not. Read/Write. The EP modes are as follows: SIE Mode Description Port B7 Port B6
00000000 GPIO I/O I/O
00000001 USB D+ D–
00000010 PS/2 CLOCK DATA
00000100 RS232-C 1200 Baud
Other Reserved Reserved Reserved EP Mode Description
000 EP1 OFF, EP2 OFF
001 EP1 IN, EP2 OFF
010 EP1 OUT , EP2 OFF
011 EP1 CONTR OL
100 EP1 OUT , EP2 OUT
101 EP1 IN, EP1 OUT
110 EP1 OUT , EP1 IN
111 EP1 IN EP2 IN
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source flags of a low-priority communications interrupt. position clears interrupt sources. Read/Write. by the SIE, clears IN PACKET READY and IN NAK SENT. SIE may never write to the IN buffer. because IN PACKET READY was clear. Table 10. Low Priority MASK and INTR Conditions
000 EP1 OFF, EP2 OFF OUT
001 EP1 IN EP2 OFF IN
010 EP1 OUT , EP2 OFF OUT
011 EP1 CONTR OL OUT
100 EP1 OUT , EP2 OUT OUT
101 EP1 IN, EP1 OUT OUT
110 EP1 OUT , EP1 IN IN
111 EP1 IN EP2 IN IN
source flags of a high-priority communications interrupt. on EP1. This bit is not valid in EP mode 000. setup stage of a control transfer on EP0. Mode as specified in the USB CSR. Read/Write. clears this bit. STALL takes priority over NAK or ACK. Table 11. EP 1/2 CSR Registers (BA)
000 EP1 OFF, EP2 OFF FORCE
001 EP1 IN EP2 OFF FORCE
010 EP1 OUT , EP2 OFF FORCE
011 EP1 CONTR OL ACK
100 EP1 OUT , EP2 OUT FORCE
101 EP1 IN, EP1 OUT FORCE
110 EP1 OUT , EP1 IN FORCE
111 EP1 IN EP2 IN FORCE
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PACKET READY clears IN NAK SENT. Read/Set. write to this bit. Read/Write. READY or receives a valid setup token (via FORCE NAK). clears OUT N AK SENT. Read/Set. this bit. Read/Clear (if unlocked). firmware should be set FORCE NAK. Read/Set. single, incorrect OUT transaction. shot” behavior. It only handles one OUT transaction. Table 12. EP 1/2 Counts
000 EP1 OFF, EP2 OFF GP R
001 EP1 IN EP2 OFF GPR EP1 IN COUNT 3:0
010 EP1 OUT , EP2 OFF GPR EP1 OUT COUNT 3:0
011 EP1 CONTR OL EP1 OUT COUNT 3:0 EP1 IN COUNT 3:0
100 EP1 OUT , EP2 OUT EP2 OUT COUNT 3:0 EP1 OUT COUNT 3:0
101 EP1 IN, EP1 OUT EP 1 OUT COUNT 3:0 EP1 IN COUNT 3:0
110 EP1 OUT , EP1 IN EP 1 IN COUNT 3:0 EP1 OUT COUNT 3:0
111 EP1 IN EP2 IN EP2 IN COUNT 3:0 EP1 IN COUNT 3:0
Figure 16. COMM Register s (Non-USB Modes: B0–BF)
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COMMUNICATION REGISTER DEFINITIONS (NON-USB MODES) The following definitions describe in detail the specific non- USB mode registers as illustrated in Figure 16. PORT A, PORT B : Same as USB mode. Port B6 and B7 are I/O in the GPIO Mode. SIE MODE : Same as USB mode. LOW PRIORITY INTR : This register contains the IRQ flags of a low-priority communications interrupt. Read/Write. LOW PRIORITY MASK : This register contains mask bits for the IRQ sources specified in the LOW PRIORITY INTR register. A set bit indicates that the corresponding interrupt source is unmasked. n XMIT COMM ERROR : Indicates that a communications error occurred while transmitting a byte. Valid only when the SIE is in PS/2 mode. Indicates that the host aborted the transfer. n XMIT DONE : Indicates that XMIT PACKET SIZE bytes have been sent since XMIT READY was set. HIGH PRIORITY INTR : This register contains the IRQ source flags of a low-priority communications interrupt. The ISR should check these bits to determine the cause of the interrupt. Read/Write. HIGH PRIORITY MASK : This register contains mask bits for the IRQ sources specified in the HIGH PRIORITY INTR register. A set bit indicates that the corresponding interrupt source is unmasked. n OVERRUN ERROR : Indicates that RCV READY was clear when RCV DONE was set. n RCV COMM ERROR : Indicates that a communications error occurred while receiving a byte, resulting in a framing or parity error. In PS/2 mode, it may also indicate that the host aborted its own transmission. n RCV DONE : Indicates that RCV PACKET SIZE bytes have been received since RCV READY was set. COMM CSR : Controls the SIE in PS/2 and RS232-C mode. n XMIT READY : Indicates to the SIE that the XMIT buffer is valid. Cleared by SIE when XMIT DONE is set. Cannot be cleared by firmware. Read/Write. n RCV READY : Indicates to the SIE that the most recent packet received has been handled. Cleared by the SIE after RCV DONE is set. Cannot be cleared by firmware. Read/Write. n RCV PACKET SIZE : Number of bytes to receive before BYTE RECEIVED interrupt. Value may not exceed the size specified in RCV BUFFER SIZE. A “0” indicates that the packet size = the buffer size. Read/Write. n XMIT PACKET SIZE : The number of bytes to send before the XMIT DONE interrupt. A “0” indicates that the packet size = the buffer size n LAST BYTE RECEIVED OFFSET : Indicates the offset in the RECEIVE buffer of the most recent byte received. Read only. n NEXT SEND BYTE OFFSET : Indicates the offset in the XMIT buffer of the next byte to be sent. If the host has aborted a PS/2 transmission, it is the offset of the byte that was aborted. Read only.
Zilog 1.5 MBPS USB Device Controller DS97KEY2005 P R E L I M I N A R Y 29 INITIAL STATES: COMM REGISTERS, UPON CHANGING MODES: INITIAL STATES: PORT CONFIGURATION REGISTERS: All Registers in this state are cleared to 0 on POR. ADDR NAME D7 D6 D5 D4 D3 D2 D1 D0
0 POR T A Cleared by POR,or not changed
1 POR T B Same as Port A
5 SIE
6 CONTR OL ALL 0
7 REGS
A B C D E Uninitialized F
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Figure 17. Port Configuration Registers ( D0–DF)
Zilog 1.5 MBPS USB Device Controller DS97KEY2005 P R E L I M I N A R Y 31 PORT REGISTER DEFINITIONS The following definitions describe in detail the specific port registers as illustrated in Figure 17. WAKE : When set, this pin is capable of waking the device on any edge. PUSH/PULL : When set, this pin is a push-pull output. When clear, this pin is an open-drain output. Ignored if OUTPUT is clear. PULLUP ON : When set, the pull-up resistor is on. OUTPUT : When set, the pin’s output drivers are enabled. However, the pin may be read at any time regardless of the configuration. SINK : Indicates the level of current drawn by the current sink on the pin. When SINK „ 0, the n-channel output tran- sistor is disabled. When SINK = 0, the sink is off and the n- channel output transistor may be enabled according to the OUTPUT bit. DIVIDER : Selects one of the three voltage dividers to be placed on the pin. Divider 0 indicates no divider. VREF : Indicates the voltage reference level for the com- parator. Ignored if COMP ENABLED is clear. COMP ENABLE : When set, the comparator is powered. When clear, the comparator and VREF circuitry are pow- ered down. FUNCTIONAL DESCRIPTIONS Counter/Timers. For the Z8E20, 8-bit timers T0 and T1 are available to function as a pair of independent 8-bit standard timers, or they can be cascaded to function as a 16-bit PWM timer. In addition, 8-bit timers T2 and T3 are provided but they can only operate in cascade to function as a 16-bit standard timer (Figure 18). Each 8-bit timer is provided a pair of registers, which are both readable and writable. One of the registers is defined to contain the auto-initialization value for the timer, while the second register contains the current value for the timer. When a timer is enabled, the timer will decrement whatev- er value is currently held in its count register, and will then continue decrementing until it reaches 0, at which time an interrupt will be generated and the contents of the auto-ini- tialization register are optionally copied into the count val- ue register. If auto-initialization is not enabled, the timer will stop counting upon reaching 0 and control logic will clear the appropriate control register bit to disable the tim- er. This occurrence is referred to as “single-shot” opera- tion. If auto-initialization is enabled, the timer will continue counting from the initialization value. Software should not attempt to use registers that are defined as having timer functionality. Software is allowed to write to any register at any time, but it is not recommended that timer registers be updated while the timer is enabled. If software updates the count value while the timer is in operation, the timer will continue counting based upon the software-updated value. This oc- currence can produce strange behavior if the software up- date occurred at exactly the point that the timer was reach- ing 0 to trigger an interrupt and/or reload. Similarly, if software updates the initialization value regis- ter while the timer is active, the next time that the timer reaches 0, it will be initialized using the updated value. Again, strange behavior could result if the initialization val- ue register is being written while the timer is in the process of being initialized. Whether initialization is done with the new or old value is a function of the exact timing of the write operation. In all cases, the Z8E520 will prioritize the software write above that of a decremented writeback. However, when hardware clears a control register bit for a timer that is configured for single-shot operation; the clear- ing of the control bit will override a software write. Reading either register can be done at any time, and will have no effect on the functionality of the timer. If a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. In this case, a single interrupt will be generat- ed, and the interrupt will correspond to the even 8-bit time. For example, timers T2 and T3 are cascaded to form a sin- gle 16-bit timer, so the interrupt for the combined timer will be defined to be that of timer T2 rather than T3. When a timer pair is specified to act as a single 16-bit timer, the even timer registers in the pair (timer T0 or T2) will be de- fined to hold the timer’s least significant byte; while the odd timer in the pair will hold the timer’s most significant byte. In parallel with the posting of the interrupt request, the in- terrupting timer’s count value will be initialized by copying the contents of the auto-initialization value register to the count value register. Note: Any time that a timer pair is defined to act as a single 16-bit timer, that the auto-reload function will be performed automatically. All 16-bit timers will continue counting while their interrupt requests are active, and will operate in a free-running manner. If interrupts are disabled for a long period of time, it is pos- sible for the timer to decrement to 0 again before its initial interrupt has been responded to. This occurrence is a de- generate case, and hardware is not required to detect this
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updated every 8th XTAL clock cycle. available when T0 and T1 act independently. ing the Lo auto-init pair followed by the Hi auto-init pair. interrupt after the first timeout interval. will continue toggling each time that the timer times out. Figure 18. Z8E520 Timers Block Diagram
time in the program operation. that drives the internal oscillator/WDT can be saved. WDT are programmable –0 to +100%. for that particular interrupt request. either externally or internally. so that the program can decide the source of the reset.
0 TCO
1 TC1
2 TC2
3 COMM HIGH
4 COMM LO W
5 Port
Figure 19. Interrupt Block Diagram Figure 20. Oscillator Configuration
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FUNCTIONAL DESCRIPTIONS (Continued) VBO Circuit. The Voltage Brown Out circuit will detect when voltage has dropped below the normal operating voltage. The chip will maintain full core functionality and RAM values will be preserved during the range from V MIN (VCC = 4V) to VBO ; however, it may not meet worst case AC and DC limits. At VBO , the chip will be placed in reset and maintained in that state until VCC exceeds VBO . When this condition is reached, the chip will resume operation. V BO is set by design to 2.7 V – 0.2 V. STOP. This instruction turns off the internal clock and ex- ternal ceramic resonator oscillation. It reduces the standby current to less than 60 mA. The STOP Mode is terminated by an interrupt. An interrupt from any of the active (en- abled) interrupts will remove the chip from the STOP Mode (Ports 31–33 including the USB reset. Note: The timer cannot generate an interrupt in STOP Mode because the clock is stopped. The interrupt causes the processor to restart the applica- tion program at the address or the vector of the interrupt and continue the program at the end of the interrupt ser- vice routine. In order to enter STOP (or HALT) Mode, it is necessary to first flush the instruction pipeline to avoid sus- pending execution in mid-instruction. As a result, the user must execute a NOP (Opcode=FFH) immediately before the appropriate sleep instruction, such as: FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HAL T ; enter HALT Mode
(UM97Z8X0300) available at your local Zilog sales office. Figure 21. Interrupt Request Register
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Figure 22. Interrupt Mask Register Figure 23. Stack Pointer
Figure 24. TCTLHI Register
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Figure 25. TCTLLO Register BY CASCADING 8-BIT TIMERS T3(MSB) AND T2(LSB). CPU EXECUTION WITH ZIE AT NORMAL 6 MHZ CLOCK RA TE.
Figure 26. Z8E520 Register Pointe the active working register group.
- Register Group 2 is active if RP = 20H.
40 P R E L I M I N A R Y DS97KEY2005
Figure 27. Flags Register
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ORDERING INFORMATION
For fast results, contact your Zilog sales office for assistance in ordering the part required. CODES Package P = Plastic DIP V = Plastic Leaded Chip Carrier F = Quad Flat Pack Speed 06 = 6 MHz Environment C = Plastic Standard Temperature S = 0°C to +70°C
6 MHz 6 MHz
Example: Z 8E520 06 P S C Environmental Flow Temperature Package Speed Product Number Zilog Prefix is a Z8E520, 6 MHz, SOIC , 0°C to +70°C, Plastic Standard Flow
Zilog 1.5 MBPS USB Device Controller DS97KEY2005 P R E L I M I N A R Y 43 Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems and delays. No production release is authorized or committed until the Customer and Zilog have agreed upon a Customer Procurement Specification for this product. Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgment, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. © 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com