Z8922320VEC

Z89223 ZILOG | Alldatasheet

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P RODUCT S PECIFICATION Z89223/273/323/373 16-B IT D IGITAL S IGNAL P ROCESSORS WITH A/D C ONVERTER

FEATURES

5V ±10% 0°C to 70°C Standard Temperature –40°C to +85°C Extended Temperature DSP Core 16-Bit Fixed Point DSP, 24-Bit ALU and Accumulator Single-Cycle Multiply and ALU Operations Six-Level Hardware Stack Six Data RAM Pointers and Sixteen Program Memory Pointers RISC Processor with 30 Instruction Types On-Chip Peripherals 4-Channel, 8-Bit Half-Flash A/D Converter Serial Peripheral Interface (SPI) Three General-Purpose Counter/Timers Two Pulse Width Modulators (PWM) Two Watch-Dog Timers (WDT) Up to 40 Bits of I/O PLL System Clock Three Vectored Interrupts Servicing Eight Sources Low Power Clock Modes with Wake-up Options GENERAL DESCRIPTION The Z893x3 products are high-performance Digital Signal Processors (DSP) with a modified Harvard architecture fea- turing separate program and dual data memory banks. The design is optimized for processing power with a minimum of silicon area. The Z893x3 16/24-Bit architecture accommodates ad- vanced signal processing algorithms. The operating perfor- mance and efficient architecture provide deterministic in- struction execution. Compression, filtering, frequency detection, audio, voice detection, speech synthesis, and oth- er vital algorithms can all be implemented. Six data RAM pointers provide circular buffer capabilities and simultaneous dual operand fetching. Three vectored in- terrupts are complemented by a six-level stack. By integrating a high-speed 4-channel, 8-bit A/D, SPI, three Counter/Timers with PWM and WDT support, and up to 40 bits of I/O, the Z893x3 family provides a compact low-cost system solution. To support a wide variety of development requirements, the Z893x3 DSP product family features the cost-effective Z89223/323 with 8 KWords of ROM. The Z89273/373, an Device Package ROM (Kwords) OTP (Kwords) Data RAM (Words) MIPS Z89223 44-PLCC, 44-PQFP 512 Z89273 44-PLCC 512 Z89323 64-TQFP, 68-PLCC, 80-PQFP 512 Z89373 64-TQFP, 68-PLCC, 80-PQFP 512

any power, grounds, or signals. Figure 1. Z892X3/3x3 Functional Block Diagram

16 MSB

4 Inputs

4 Outputs

External Bus and External Registers. Figure 2. “External” Bus

16-Bit Digital Signal Processors with A/D Converter ZiLOG DS000202-DSP0599 PIN FUNCTIONS EA2–EA0. External Address Bus (output, latched). These pins provide the External Register Address. This address bus is driven during both internal and external accesses. One of up to seven user-defined external registers is selected by the processor for reads or writes. EXT7 is always reserved for use by the processor. ED15–ED0. External Data Bus (input/output). These pins are the data bus for the user-defined external registers, and are shared by Port0. These pins are normally tristated, ex- cept when these registers are specified as destination reg- isters in a write instruction to an external peripheral, or when Port0 is enabled for output. This bus uses the control signals RD/WR, DS, and WAIT, and address pins EA2–EA0. DS . Data Strobe (output). This pin provides the data strobe signal for the ED Bus. DS is active for transfers to/from ex- ternal peripherals only. RD/WR. Read/Write Select (output). This pin controls the data direction signal for the External Data Bus. Data is avail- able from the processor on ED15–ED0 when this signal and DS are both Low. WAIT . Wait State (input). This pin is sampled at the rising edge of the clock with appropriate setup and hold times. A single wait-state can be generated internally by setting the appropriate bits in the wait state register. The user must drive this line if multiple wait states are required. This pin is shared with Port2. CLKI. Clock (input). This pin is the clock circuit input. It can be driven by a signal or connected to a 32 KHz crystal. CLKO. Clock (output). This pin is the clock circuit output. It is used for operation with a 32 KHz crystal and the PLL to generate the system clock. HALT . Halt State (input). This pin stops program execution. The processor continuously executes NOPs and the pro- gram counter remains constant while this pin is held Low. This pin offers an internal pull-up. RESET . Reset (input). This pin resets the processor. It push- es the contents of the Program Counter (PC) onto the stack and then fetches a new PC value from program memory ad- dress 0FFCH after the RESET signal is released. The Status register is set to all zeros. At power-up RAM and other reg- isters are undefined, however, they are left unchanged with subsequent resets. RESET can be asserted asynchronously. AN0–AN3. Analog Inputs (input). These are the analog in- put pins. The analog input signal should be between VALO and VAHI for accurate conversions. VAHI. Analog High Reference Voltage (input). This pin provides the reference for the full scale voltage of the analog input signals. VALO. Analog Low Reference Voltage (input). This pin provides the reference for the zero voltage of the analog in- put signals. AV CC –AGND. Filtered Analog Power and Ground must be provided on separate pins to reduce digital noise in the an- alog circuits. Multifunction Pins. The Z89223/273/323/373 DSP fami- ly offers a user-configurable I/O structure, which means that most of the I/O pins offer dual functions. The function, direction (input or output), and for output, the characteris- tics (push-pull or open drain) are all under user-control, by programming the configuration registers appropriately as described in the I/O Ports section. The following share I/O Port pins: INT0–INT2. External Interrupts (input, edge-triggered). These pins provide three of the eight interrupt sources to the Interrupt Controller. Each is programmable to be rising- edge or falling-edge triggered. The other five interrupt sources are from the on-chip peripherals. CLKOUT. System Clock (output). This pin provides access to the internal processor clock. SDI. Serial Data In (input). This pin is the SPI serial data input. SDO. Serial Data Out (output). This pin is the SPI serial data output. SS. Slave Select (input). This pin is used in SPI Slave Mode only. SS advises the SPI that it is the target of a serial transfer from an external Master. SCLK. SPI Clock (output/input). This pin is an output in Master mode and an input in Slave mode. UI0, UI1. User inputs (input). These general-purpose input pins are directly tested by the conditional branch instruc- tions. They can also be read as bits in the status register. These are asynchronous input signals that require no special clock synchronization. Counter/Timer0 and Counter/Timer1 may use either of these pins as input. UI2. User Input (input). This pin is the input to Counter/Timer 2. TMO0/UO0. Counter/Timer Output or User Output 0 (out- put). Counter/Timer 0 and Counter/Timer 1 can be pro- grammed to provide output on this pin. When User Outputs are enabled, and the Counter/Timer is disabled, this pin pro- vides the complement of Status Register bit 5.

16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599 TMO1/UO1. Counter/Timer Output or User Output 1 (out- put). Counter/Timer 0 and Counter/Timer 1 can be pro- grammed to provide output on this pin. When User Outputs are enabled, and the Counter/Timer is disabled, this pin pro- vides the complement of Status Register bit 6. TMO2. Counter/Timer 2 Output (output). This pin is the output of Counter/Timer 2 P0.15–P0.0. Port0 (input/output). This is a 16-bit user I/O port. Bits can be configured as input or output or globally as open-drain output. When enabled, Port0 uses the 16 data lines of the ED bus. The function of these pins can be dy- namically changed by writing to the Port0 configuration registers. The High byte can also be configured to Port1 as described in the I/O Port section. P1.7–P1.0. Port1 (input/output). These pins are Port1 in- puts or outputs when not configured for use as special pur- pose peripheral interface. The following eight pin functions preempt use of these pins when enabled. INT2, CLKOUT, SDI, SDO, SS, SCLK, UI0, UI1. Note: These pins are not bonded out on the 44-pin packages. P2.7–P2.0. Port2 (input/output). These pins are Port2 in- puts or outputs when not configured as peripheral interfac- es. The following seven pin functions preempt use of P2.6–P2.0 when enabled. INT0, INT1, TMO0/UO0, TMO1/UO1, WAIT, UI2, TMO2. P2.7 does not include a dual function. Note: P2.7–P2.5 are not bonded out on the 44-pin packages. The following port pins are available only on the 80-pin package: P3.7–P3.4. Port3 (output). These pins are Port3 outputs. P3.3–P3.0. Port3 (input). These pins are Port3 inputs.

Figure 3. 44-Pin PLCC Z89223/273 Pin Configuration

Table 1. 44-Pin PLCC Z89223/273 Pin Description

Figure 4. 44-Pin PQFP Z89223/273 Pin Configuration

Table 2. 44-Pin PQFP Z89223/273 Pin Description

Figure 5. 64-Pin TQFP Z89323/373 Pin Configuration

Table 3. 64-Pin TQFP Z89223/273 Pin Description

33 HALT

34 EA0

35 EA1

36 EA2

37 VDD

41 CLKI

42 CLKO

14 VSS

46 LPF

47 RESET

16 VSS

48 VSS

49 VDD

18 VAHI

50 VSS

19 VSS

21 VALO

23 AGND

55 VSS

24 AN0

25 AN1

26 AN2

27 AN3

28 VSS

61 VDD

30 AVCC

31 VDD

63 VSS

32 RD/WR

Figure 6. 68-Pin PLCC Z89323/373 Pin Configuration

Table 4. 68-Pin PLCC Z89323/373 Pin Description

35 AN0

36 AN1

37 AN2

38 AN3

39 VSS

41 AVCC

42 VDD

43 RD/WR

44 HALT

45 EA0

46 EA1

13 VSS

47 EA2

14 VDD

53 CLKI

54 CLKO

24 VSS

58 LPF

59 RESET

26 VSS

60 VSS

28 VDD

62 VSS

29 VAHI

30 VSS

32 VALO

67 VSS

34 AGND

Figure 7. 80-Pin PQFP Z89323/373 Pin Configuration

Table 5. 80-Pin PQFP Z89323/373 Pin Description

41 RD/WR

47 EA1

48 EA2

50 VDD

54 CLKI

55 CLKO

59 LPF

61 RESET

22 VSS

63 VDD

65 VSS

26 VDD

27 VAHI

30 VALO

71 VSS

32 AGND

33 AN0

34 AN1

35 AN2

36 AN3

37 VSS

77 VDD

39 AVCC

79 VSS

40 VDD

16-Bit Digital Signal Processors with A/D Converter ZiLOG DS000202-DSP0599 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This rating is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test con- ditions as noted. All voltages are referenced to Ground. Pos- itive current flows into the referenced pin. Positive current I(+) flows in to the referenced pin. Negative current I(Ð) flows out of the referenced pin. Symbol

Description

–0.3 7.0 V TSTG Storage Temperature –65 150 TA Ambient Operating Temperature “S” device “E” device –40 Figure 8. Test Load Diagram

Table 7. OTP Version: VDD = 5V ±10%, TA = 0°C to +70°C for “S” temperature range Table 6. ROM Version: VDD = 5V ±10%, TA = 0°C to +70°C for “S” temperature range

Figure 9. Z89373 Typical OTP Current Consumption

Table 8. VDD= 5V ±10%, TA = 0°C to +70°C for “S” Temperature Range

20 TCY

2 TCY

3 TCY

Table 9. AVCC–AGND = 5V ±10% Table 10. AVCC–AGND = 5V ±10%

Figure 15. SPI Timing (Master and Slave Modes) *Notes: The polarity of SCLK and SS are programmable by the user. SS is used in Slave Mode only. data reception on the rising edge of SCLK, with SS active Low (default).

in the Instruction Description section. data should first be scaled to avoid truncation errors. Output can shift the data by three bits right or no shift. performs arithmetic, logic, and shift operations. Figure 16. Multiplier Block Diagram

3 Bits Right

• X Register (16)

Figure 17. ALU Block Diagram

16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599 Interrupts. The Z893x3 features three user interrupt inputs which can be programmed to be positive or negative edge- triggered. There are five interrupts generated by internal pe- ripherals: the A/D converter, the Serial Peripheral Interface, and the three Counter/Timers. Internally there are three pri- ority levels. The internal signals for Interrupt service Re- quests are denoted ISR0, ISR1, and ISR2, with ISR0 having the highest priority, and ISR2 the lowest. The user can pro- gram which interrupt sources are enabled, and which sourc- es are serviced by the highest, middle, and lowest priority service routines. An interrupt is serviced at the end of an instruction execution. Two machine cycles are required to enter an interrupt instruction sequence. The PC is pushed onto the stack. The Interrupt Controller fetches the address of the interrupt service routine from the following locations in program memory: At the end of the interrupt service routine, a RET instruction is used to pop the stack into the PC. The Set-Interrupt-Enable-Flag (SIEF) instruction enables the interrupts. Interrupts are automatically disabled when entering an interrupt service routine. Before exiting an in- terrupt service routine the SIEF instruction can be used to reenable interrupts. Registers. In addition to the internal registers for process- ing, control, and configuration, the Z893x3 offers up to sev- en user-defined 16-bit external registers, EXT0–EXT6, de- pending on the Register Bank Select value. The external register address space is shared by the Z893x3 internal pe- ripherals. Selecting banks 0–4 of the EXT Register Assign- ment allows access to/from three to seven of these addresses for general-purpose use. I/O Ports. The Z893X3 DSP family features a user-config- urable I/O structure. Most of the I/O pins include dual func- tions. The Counter/Timer, Serial Peripheral Interface, and External Interrupt Enables determine whether a pin is ded- icated to peripheral or I/O port use. Port0. A 16-bit user I/O port. Bits can be configured as in- put or output or globally as open-drain output. When en- abled, Port0 consumes the 16 data lines used by the ED bus. Port0 function and ED bus use can be dynamically alter- nated by enabling and disabling Port0. Port1. A multifunctional 8-bit port. Bits can be configured as input or output or globally as open-drain output. Port1 also supports INT2, CLKOUT, the Serial Peripheral Inter- face, and User Inputs 0 and 1. Port2. A multifunctional 8-bit port. Bits can be configured as input or output or globally as open-drain output. Port2 also supports INT0 and INT1, all three Counter/Timer out- puts, ED Bus, WAIT, and UI2. Port3. Port3 is an 8-bit user I/O port with 4 bits of input and 4 bits of output. It is available only on the 80-pin package. External Register Usage. The external registers EXT0–EXT6 are accessed using the External Address Bus EA2–EA0, the External Data Bus (ED Bus) ED15–ED0, and control signals DS, WAIT, and RD/WR. These provide a convenient data transfer capability with external periph- erals. Data transfers can be performed in a single-cycle. An internal wait state generator is provided to accommodate slower external peripherals. A single wait state can be im- plemented through control register Bank15/EXT3. For ad- ditional wait states, the WAIT pin can be used. The WAIT pin is monitored only during execution of a read or write instruction to external peripherals on the ED bus. Wait-State Generator. An internal Wait-State generator is provided to accommodate slow external peripherals. A single Wait-State can be implemented through a control register. For additional states, a dedicated pin (WAIT) can be held Low. The WAIT pin is monitored only during ex- ecution of a read or write instruction to external peripherals (ED bus). Analog to Digital Converter. The A/D Converter is a 4- channel, 8-bit half-flash converter. Two external reference voltages provide a scalable input range. The A/D sample rate is determined by a prescaler connected to the system clock. An interrupt is optionally generated at the end of a conversion. The four input channels can be programmed to operate on demand, continuously, or upon an event (timer or interrupt). Counter/Timers (C/T0 and C/T1). These C/Ts are 16-bit with 8-bit prescalers. They also offer the option of being used as PWM generators and include both hardware and software Watch-Dog capabilities. Both C/Ts are identical and can be externally or internally clocked. Either C/T can drive TMO0 or TMO1. Either C/T can drive any of the three interrupt service requests (ISR0, ISR1, or ISR2). Counter/Timer (C/T2). This C/T is 16-bits, externally or internally clocked, and can drive TMO2 and/or any of the three interrupt service requests (ISR0, ISR1, or ISR2). Serial Peripheral Interface (SPI). The Serial Peripheral Interface provides a convenient means of inter-processor and processor-peripheral communication. It offers the ca- pability to transmit and receive simultaneously. The SPI is designed to operate in either master or slave mode. Device ISR0 ISR1 ISR2 Z89223/273/323/373 1FFFH 1FFEH 1FFDH

addressing, short form direct, and register indirect. plier during a multiply instruction. direct addressing, the pointer is automatically modified. Figure 18. Memory Map

chip peripherals when they are enabled. X and Y are two 16-bit input registers for the multiplier. the multiplier is not being used. P holds the result of multiplications and is read-only. selected as a source register in transfer instructions. written. They point to locations in data RAM. modify this register requires two clock cycles. tions and can be written by software. always be read in its entirety. S15–S12 are set/reset by the ALU after an operation. S11–S10 are set/reset by the user input pins. to be scaled and prevents overflows. negative values instead of overflowing. 15–EXT3, and Counter/Timer 0 and 1 are disabled. Table 11. Status Register Bit Functions

the contents of the D-Bus. BUS is used for emulation only. limited method for writing to RAM. external peripherals into the address space of the processor. Table 12. RPL Description Figure 19. Status Register

EXT7 register exists in all Banks. and Peripherals for details. Table 13. EXT Register Assignments Banks 0–4 Table 14. EXT Register Assignments Banks 5–15

Select Field and Interrupt Status Bits. bank is selected as the current working bank. when servicing ISR2, which may come from several sources.

• Load the value of EXT7 into a register or memory location
• Then load that value back into EXT7 Performing these steps clear all of the interrupts that were pending, but leave the Register Bank Select unchanged.

Figure 20. EXT7 Register

to ISR0 (Interrupt Service Request 0). is allocated to ISR1 (Interrupt Service Request 1). terrupt Status Register can be used for polling interrupts. Figure 21. Interrupt Allocation Register

Table 15. I/O Port Bit Allocations Figure 24. Port 0, 1 and 2 Configuration

ED Bus/Port0 pins. See bits 2–0 of Bank15/EXT1. Table 16. Port1 Bit Function Allocation

Table 17. Port2 Bit Function Allocation Figure 27. Bank15/EXT2 Register

16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599 Port3Ñ8-BIt Programmable I/O Port3 is an additional I/O port available only in the 80-pin Bit 8 of Bank15/EXT2 enables and disables Port3. The LSB of Bank2/EXT5 is the Port3 Data Register.

caler value should be set to divide by 40. quentially written to result registers 0, 1, 2 and 3. spective four result registers updated. tive four result registers constantly updated. occurs after the first or fourth conversion. reference voltages, the noise and offsets remain constant. version time will also take longer. Figure 28. ADC Architecture

grammed to occur with either polarity. do not affect the state of the selected pin. to generate a continuous square wave of 50% duty cycle. the end of the current cycle, unless TMR is written. ured to generate a single pulse of programmable duration. retrigger for a new duration. of current cycle, unless TMR is written. at the end of current cycle, unless TMR is written. triggered by an event on the input pin, UI0 or UI1. measure the time during which its input is asserted. to the next rising (falling) edge on the input. be selected as rising or falling or both. Figure 31. Counter/Timer 0 and 1 Block Diagram

and output options, and the mode of operation. into TMR, causing the C/T to be retriggered. write must exceed the prescaler load value. Figure 32. C/T0 and C/T1 Control Register *Note: The user should always program this bit to "0".

GPTL reloads GPT, causing the C/T to be retriggered. description of the I/O port bit allocation. Table 22. C/T2 Bits D15 and D13 Figure 37. Counter/Timer2 Block Diagram

Figure 38. Counter/Timer2 Control Register

flag is reset when RxBUF is read. edge. During slave operation, SCLK is an input. Note: Slave Mode is not available on the 44-pin package. Figure 41. SPI Block Diagram

and peripherals are enabled. switched dynamically during program execution. quired to switch the system clock to PLL Out. are both stopped to reduce power consumption. Out. As a result, the PLL has time to stabilize. Figure 42. System Clock Generator

VCO Frequency = 4 x PLL Divisor x PLL In Frequency. lect bits in the Clock Control Register. some other frequency, but the results are not guaranteed. and XTAL Oscillator are both turned off. wake-up signal is toggled to the specified wake-up polarity. Table 23. Standard Clock Mode Summary Figure 43. System Clock Control Register

16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599 INSTRUCTION SET The addressing modes are: <pregs>, <hwregs>. These modes are used for loads to and from registers within the chip, such as loading to the accumulator, or loading from a pointer register. The names of the registers are specified in the operand field (destination first, then source). <dregs>. This mode is used for access to the lower 16 ad- dresses in each bank of RAM. The 4-bit address comes from 2 bits of the status register and 2 bits of the operand field of the data pointer. Data registers can be used to access data in RAM, but typically are used as pointers to access data from the program memory. <accind>. Similar to the previous mode, the address for the program memory read is stored in the Accumulator. Hence, @A in the second operand field loads the number in mem- ory specified by the address in A. <direct>. The direct mode allows read or write to data RAM from the Accumulator by specifying the absolute address of the RAM in the operand of the instruction. A number be- tween 0 and 255 indicates a location in RAM bank 0, and a number between 256 and 511 indicates a location in RAM bank 1. <limm>. This address mode indicates a long immediate op- erand. A 16-bit word can be loaded directly from the oper- and into the specified register or memory location. <simm>. This address mode indicates a short immediate operand. It is used to load 8-bit data into the specified RAM pointer. <regind>. This mode is used for indirect access to the data RAM. The address of the RAM location is stored in the pointer. The “@” symbol indicates “indirect” and precedes the pointer. For example, @P1:1 refers to the location in RAM bank 1 specified by the value in the pointer. <memind>. This mode is used for indirect access to the program memory. The address of the memory is located in a RAM location, which is specified by the value in a pointer. Therefore, @@P1:1 instructs the processor to read from a location in memory, which is specified by a value in RAM, and the location of the RAM is in turn specified by the value in the pointer. Note: the data pointer can also be used for a memory access in this manner, but only one “@” precedes the pointer. In both cases, each time the addressing mode is used, the memory address stored in RAM is incremented by one to allow easy transfer of sequential data from program memory. Table 24. Instruction Set Addressing Modes <pregs> Pn:b Pointer Registers <dregs> (points to RAM) Dn:b Data Registers <hwregs> X, Y, PC, SR, P, EDn, A, BUS Hardware Registers <accind> (points to Program Memory) Accumulator Memory Indirect <direct> <expression> Direct Address Expression <limm> #<const exp> Long (16-bit) Immediate Value <simm> #<const exp> Short (8-bit) Immediate Value <regind> (points to RAM) @Pn:b Pointer Register Indirect @Pn:b+ Pointer Register Indirect with Increment @Pn:b–LOOP Pointer Register Indirect with Loop Decrement @Pn:b+LOOP Pointer register Indirect with Loop Increment <memind> (points to Program Memory) @@Pn:b Pointer Register Memory Indirect @Dn:b Data Register Memory Indirect @@Pn:b–LOOP Pointer Register Memory Indirect with Loop Decrement @@Pn:b+LOOP Pointer Register Memory Indirect with Loop Increment @@Pn:b+ Pointer Register Memory Indirect with Increment

16-Bit Digital Signal Processors with A/D Converter ZiLOG DS000202-DSP0599 CONDITION CODES The following Instruction Description defines the condition codes supported by the DSP assembler. If the instruction description refers to the <cc> (condition code) symbol in one of its addressing modes, the instruction only executes if the condition is true. Code C Carry EQ Equal (same as Z) F False IE Interrupts Enabled MI Minus NC No Carry NE Not Equal (same as NZ) NIE Not Interrupts Enabled NOV Not Overflow NU0 Not User Zero NU1 Not User One NZ Not zero OV Overflow PL Plus (Positive) User Zero User One UGE Unsigned Greater Than or Equal (Same as NC) ULT Unsigned Less Than (Same as C) Z Zero

16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599 INSTRUCTION DESCRIPTIONS Inst. ABS[<cc>,]<src> <cc>,A A ABS NC, A ABS A ADD Addition ADD<dest>,<src> A,<pregs> A,<dregs> A,<limm> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<simm> ADD A,P0:0 ADD A,D0:0 ADD A,#%1234 ADD A,@@P0:0 ADD A,%F2 ADD A,@P1:1 ADD A,X ADD A, #%12 AND Bitwise AND AND<dest>,<src> A,<pregs> A,<dregs> A,<limm> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<simm> AND A,P2:0 AND A,D0:1 AND A,#%1234 AND A,@@P1:0 AND A,%2C AND A,@P1:2+LOOP AND A,EXT3 AND A, #%12 CALL Subroutine call CALL [<cc>,]<address> <cc>,<direct> <direct> CALL Z,sub2 CALL sub1 CCF Clear C flag CCF None CCF CIEF Clear IE Flag CIEF None CIEF COPF Clear OP flag COPF None COPF CP Comparison CP<src1>,<src2> A,<pregs> A,<dregs> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<limm> A,<simm> CP A,P0:0 CP A,D3:1 CP A,@@P0:1 CP A,%FF CP A,@P2:1+ CP A,STACK CP A,#%FFCF CP A, #%12 DEC Decrement DEC [<cc>,]<dest> <cc>A, A DEC NZ,A DEC A INC Increment INC [<cc>,] <dest> <cc>,A A INC PL,A INC A JP Jump <direct> JP C,Label JP Label

16-Bit Digital Signal Processors with A/D Converter ZiLOG DS000202-DSP0599 INSTRUCTION DESCRIPTIONS (Continued) LD Load destination with source LD<dest>,<src> A,<hwregs> A,<dregs> A,<pregs> A,<regind> A,<memind> A,<direct> <direct>,A <dregs>,<hwregs> <pregs>,<simm> <pregs>,<hwregs> <regind>,<limm> <regind>,<hwregs> <hwregs>,<pregs> <hwregs>,<dregs> <hwregs>,<limm> <hwregs>,<accind> <hwregs>,<memind> <hwregs>,<regind> <hwregs>,<hwregs> LD A,X LD A,D0:0 LD A,P0:1 LD A,@P1:1 LD A,@D0:0 LD A,124 LD 124,A LD D0:0,EXT7 LD P1:1,#%FA LD P1:1,EXT1 LD@P1:1,#1234 LD @P1:1+,X LD Y,P0:0 LD SR,D0:0 LD PC,#%1234 LD X,@A LD Y,@D0:0 LD A,@P0:0–LOOP LD X,EXT6 Notes: When <dest> is <hwregs>, <dest> cannot be P. When <dest> is <hwregs> and <src> is <hwregs>, <dest> cannot be EXTn if <src> is EXTn, <dest> cannot be X if <src> is X, <dest> cannot be SR if <src> is SR. When <src> is <accind> <dest> cannot be A. MLD Multiply MLD <src1>,<src2> [,<bank switch>] <hwregs>,<regind> <hwregs>,<regind>, <bank switch> <regind>,<regind> <regind>,<regind>, <bank switch> MLD A,@P0:0+LOOP MLD A,@P1:0,OFF MLD @P1:1,@P2:0 MLD @P0:1,@P1:0,ON Notes: If src1 is <regind> it must be a bank 1 register. Src2’s <regind must be a bank 0 register. <hwregs> for src1 cannot be X. For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank switch> defaults to ON. MPYA Multiply and add MPYA <src1>,<src2> [,<bank switch>] <hwregs>,<regind> <hwregs>,<regind>, <bank switch> <regind>,<regind> <regind>,<regind>, <bank switch> MPYA A,@P0:0 MPYA A,@P1:0,OFF MPYA @P1:1,@P2:0 MPYA@P0:1,@P1:0,ON Notes: If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register. <hwregs> for src1 cannot be X. For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank switch> defaults to ON. MPYS Multiply and subtract MPYS <src1>,<src2> [,<bank switch>] <hwregs>,<regind> <hwregs>,<regind>, <bank switch> <regind>,<regind> <regind>,<regind>, <bank switch> MPYS A,@P0:0 MPYS A,@P1:0,OFF MPYS @P1:1,@P2:0 MPYS @P0:1,@P1:0,ON Inst.

16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599 Notes: If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register. <hwregs> for src1 cannot be X. For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, <regind> the <bank switch> defaults to ON. NEG Negate NEG <cc>,A <cc>, A A NEG MI,A NEG A NOP No operation NOP None NOP OR Bitwise OR OR <dest>,<src> A,<pregs> A,<dregs> A,<limm> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<simm> OR A,P0:1 OR A, D0:1 OR A,#%2C21 OR A,@@P2:1+ OR A, %2C OR A,@P1:0–LOOP OR A,EXT6 OR A,#%12 POP Pop value from stack POP <dest> <pregs> <dregs> <regind> <hwregs> POP P0:0 POP D0:1 POP @P0:0 POP A PUSH Push value onto stack PUSH <src> <pregs> <dregs> <regind> <hwregs> <limm> <accind> <memind> PUSH P0:0 PUSH D0:1 PUSH @P0:0 PUSH BUS PUSH #12345 PUSH @A PUSH @@P0:0 RET Return from subroutine RET None RET RL Rotate Left RL <cc>,A <cc>,A A RL NZ,A RL A RR Rotate Right RR <cc>,A <cc>,A A RR C,A RR A SCF Set C flag SCF None SCF SIEF Set IE flag SIEF None SIEF SLL Shift left logical SLL [<cc>,]A A SLL NZ,A SLL A SOPF Set OP flag SOPF None SOPF SRA Shift right arithmetic SRA<cc>,A <cc>,A A SRA NZ,A SRA A SUB Subtract SUB<dest>,<src> A,<pregs> A,<dregs> A,<limm> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<simm> SUB A,P1:1 SUB A,D0:1 SUB A,#%2C2C SUB A,@D0:1 SUB A,%15 SUB A,@P2:0–LOOP SUB A,STACK SUB A, #%12 Inst.

16-Bit Digital Signal Processors with A/D Converter ZiLOG DS000202-DSP0599 INSTRUCTION DESCRIPTIONS (Continued) Bank Switch Operand. The third (optional) operand of the MLD, MPYA and MPYS instructions represents wheth- er the bank switch is set to ON or OFF. To illustrate, the keywords ON and OFF are used to state the direction of the switch. These keywords are referenced in the instruction de- scriptions through the <bank switch> symbol. The most no- table capability is that a source operand can be multiplied by itself (squared). XOR Bitwise exclusive OR XOR <dest>,<src> A,<pregs> A,<dregs> A,<limm> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<simm> XOR A,P2:0 XOR A,D0:1 XOR A,#13933 XOR A,@@P2:1+ XOR A,%2F XOR A,@P2:0 XOR A,BUS XOR A, #%12 Inst.

Figure 46. 64-Pin TQFP Package Diagram

Figure 47. 68-Pin PLCC Package Diagram

Figure 48. 80-Pin PQFP Package Diagram

16-Bit Digital Signal Processors with A/D Converter DS000202-DSP0599

ORDERING INFORMATION

For fast results, contact your local ZiLOG sales office for assistance in ordering the part required. CODES Package Type ROM OTP 44-Pin PLCC Z8922320VSC Z8927320VSC Z8922320VEC 44-Pin PQFP Z8922320FSC Z8922320FEC 64-Pin TQFP Z8932320ASC Z8937320ASC Z8932320AEC 68-Pin PLCC Z8932320VSC Z8937320VSC Z8932320VEC 80-Pin PQFP Z8932320FSC Z8937320FSC Z8932320FEC Package V = PLCC A = TQFP F = PQFP Temperature S = 0°C to +70°C E = –40°C to 85°C Speed 20 = 20 MHz Environmental C = Plastic Standard Example: Z 89323 20 V S C Environmental Flow Temperature Package Speed/Bond Out Option Product Number ZiLOG Prefix is a Z89323, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow

16-Bit Digital Signal Processors with A/D Converter ZiLOG DS000202-DSP0599 ©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG, Inc.

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