Z87000 ZILOG | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 50
Technical content
Features
n Transceiver Circuitry Provides Primary Cordless Phone Communications Functions – Digital Downconversion with Automatic Frequency Control (AFC) Loop – FSK Demodulator – FSK Modulator – Symbol Synchronizer – Time Division Duplex (TDD) Transmit and Receive Buffers n On-Chip A/D and D/A to Support 10.7 MHz IF Interface n Bus Interface to Z87010 ADPCM Processor n Static CMOS for Low Power Consumption n 3.0V to 3.6V, -20 C to +70 C, Z87L00 4.5V to 5.5V, -20 C to +70 C, Z87000 n
16.384 MHz Base Clock
The Z87000/Z87L00 FHSS Cordless Telephone Trans- ceiver/Controllers are expressly designed to implement a
900 MHz frequency hopping spread spectrum cordless
telephone compliant with United States FCC regulations for unlicensed operation. The Z87000 and Z87L00 are dis- tinct 5V and 3.3V versions, respectively, of the device. For the sake of brevity, all subsequent references to the Z87000 in this document also apply to the Z87L00, unless specifically noted. The Z87000 supports a specific cordless phone system design that uses frequency hopping and digital modulation to provide extended range, high voice quality, and low sys- tem costs.The Z87000 uses a Zilog 16-bit fixed-point two’s complement static CMOS Digital Signal Processor core as the phone and RF section controller. The Z87000’s DSP core processor further supports control of the RF section’s frequency synthesizer for frequency hopping and the gen- eration of the control messages needed to coordinate in- corporation of the phone’s handset and base station. Device ROM (KWords) RAM* (Words) I/O Lines Package Information Z87000 12 512 32 84-Pin PLCC 100-Pin QFP Z87L00 12 512 32 100-Pin QFP Note: *General-Purpose
bedded software provide a total system solution. Figure 1. System Block Diagram of a Z87000/Z87010 Based Phone
Figure 2. Z87000 Functional Block Diagram
256 Word
Figure 3. 84-Pin PLCC ROM Pin Configuration (Z87000 only)
Table 1. 84-Pin PLCC Pin Description Summary
4 RFTX RF transmit switch control Output
5 SYLE RF synthesizer load enable Output
6 RXON Demodulator “on” indication Output
7 RFRX RF receive switch control Output
9 PWLV RF transmit power level Output
10 RSSI RF receive signals strength indicator Input
12 TX Analog transmit IF signal Output
14 RX Analog receive IF signal Input
17 RFEON RF module on/off control Output
62 TEST Main test mode control Input
64 HBSW Handset/Base Control –
65 CLKOUT Clock output to ADPCM Processor Output
76 VXRDYB ADPCM processor ready signal Output
77 VXSTRB ADPCM processor data strobe Input
78 VXRWB ADPCM read/write control Input
83 CODCLK Clock output to codec Output
Figure 4. 100-Pin QFP Pin Configuration
Table 2. 100-Pin QFP Pin Configuration
5 TX Analog transmit IF signal Output
7 RX Analog receive IF signal Input
9 VREF Analog reference voltage for RX signal –
10 RFEON RF module on/off control Output
63 TEST Main test mode control Input
65 HBSW Handset/bast control Input
67 CLKOUT Clock output to ADPCM processor Output
81 VXRDYB ADPCM processor ready signal Output
82 VXSTRB ADPCM processor data strobe Input
83 VXRWB ADPCM processor read/write control Input
88 CODCLK Clock output to codec Output
94 RFTX RF transmit switch control Output
95 SYLE RF synthesizer load enable Output
96 RXON Demodulator “on” indication Output
97 RFRX RF receive switch control Output
99 PWLV RF transmit power level Input
100 RSSI RF receive signal strength indicator Input
lowing standard test conditions, unless otherwise noted.
- Voltage on all pins with respect to GND.
- Voltage on all inputs WRT VDD
- Voltage on all outputs WRT VDD
Figure 5. Test Load Diagram
Table 3. 5V Table 4. 3.3V – 0.3V Operation (Z87L00)
Table 5. 5V – 0.5V Operation (Z87000)
- 2.3 mA typical at 25°C, 5 volts.
Table 6. 3.3V – 0.3V Operation (Z87L00)
- 1.6 mA typical at 25°C, 3.3 volts.
Table 7. 1-Bit ADC (Temperature: -20/+70°C) Window of time while input signal is applied to sampling capacitor; see next figure. Uncertainty in sampling time due to random variations such as thermal noise.
Figure 6. 1-Bit ADC Definition of Terms Table 8. 8-bit ADC (Temperature -20/+70°C)
- 8-bit ADC only tested for 6-bit resolution.
Table 9. 4-bit DAC (Temperature: -20/+70°C)
Table 10. Clocks, Reset and RF Interface
1 TpC MCLK input clock period (1) 61 61 ns
2 TwC MCLK input clock pulse width 20 40 ns
3 TrC, TfC MCLK input clock rise/fall time 15 ns
4 TrCC, TfCC CLKOUT output clock rise/fall time 2 6 ns
5 TrCO, TfCO CODCLK output clock rise/fall time 2 6 ns
6 TwR RESETB input low width 18 TpC
7 TrRF , TfRF RF output controls rise/fall time (2) 2 6 ns
- RF Controls are RFTX, RFRX, RXON, RFEON, SYLE.
ready/wait output control signal. Table 11. Read Cycles VXRDYB Ready Control Signal Z87000 to ADPCM Proc. Table 12. Write Cycles
8 TsAS Address, Read/Write setup time before Strobe falls 10 ns
9 ThSA Address, Read/Write hold time after Strobe rises 3 ns
10 TaDrS Data read access time after Strobe falls 30 (1) ns
12 TwS Strobe pulse width 20
13 TsDwS Data write setup time before Strobe rises 10 ns
14 ThDwS Data write hold time after Strobe rises 3 ns
15 TaDrRY Data read valid before Ready falls 22 ns
16 TdSRY Strobe high after Ready falls 0 ns
- Requires wait state on ADPCM Processor read cycles
- Requires no write cycle directly following read cycle on ADPCM Processor
Figure 7. Transceiver Output Signal
Figure 8. Read/Write Cycle TImings
Figure 9. Read/Write Cycle Timing with Wait State
Zilog Spread Spectrum Controllers DS96WRL0501 P R E L I M I N A R Y 1-19 PIN FUNCTIONS VDD. Digital power supply. GND. Digital ground. AV DD . Analog power supply. AGND. Analog ground. VREF (analog reference). This signal is the reference volt- age used by the high speed analog comparator to sample the RX input signal. RX (analog input). This is the RX IF receive signal from the RF module, input to the analog comparator and FSK demodulator. It is internally biased to the V REF DC voltage. The IF signal from the RF module should be AC coupled to the RX pin. TX (analog output). This is the IF transmit signal to the RF module, output from the FSK modulator and transmit 4-bit D/A converter. RXON (output; active high or low programmable). This pin reflects the programming of the demodulator turn-on time. RFRX (output; active high or low programmable). Control for the receive switch on the RF module. Active during re- ceive periods. RFTX (output; active high or low programmable). Control for the transmit switch on the RF module. Active during transmit periods. RFEON (output; active high or low programmable). On/off control for the RF module. Active (on) during wake periods. Inactive (off) during sleep periods on the handset. RSSI (analog input). Receive signal strength indicator from RF module, input to the RSSI 8-bit ADC. PWLV (analog output). Power level control for RF module, output from the transmit power 4-bit DAC. SYLE (output). RF synthesizer load enable: latches new frequency hopping control word of external RF synthesiz- er. Programmable polarity. ANT[1..0] (output). Control for optional antenna diversity on the RF module. MCLK (input). Master clock input. CLKOUT (output). Clock output for external ADPCM pro- cessor. CODCLK (output). Clock output for external voice CO- DEC. /RESETB (input, active low). Reset signal. VXADD[2..0] (input). Address bus controlled by external ADPCM processor. The Z87000 acts as peripheral of the Z87010 ADPCM processor. VXDATA7..0. Read/write data bus con- trolled by external Z87010 ADPCM processor. VXSTRB (input). Data strobe signal for the VXDATA bus, controlled by external Z87010. VXRWB (input). Read/write control for the VXDATA bus, controlled by external Z87010. VXRDYB (output, active low). Ready control for the VX- DATA bus. This signal is driven high (de-asserted) by the Z87000 to insert wait states in the Z87010 ADPCM proces- sor accesses. TEST (input, active high). Main test mode control. Must be set to GND. HBSW (input with internal pull-up). Control for hand- set/base configuration. Must be driven high or not connect- ed for handset, low for base. P0[15..0] (input/output). General-purpose I/O port. Direc- tion is bit-programmable. Pins P0[3..0],when configured in input mode, can also be individually programmed as wake- up pins for the Z87000 (wake-up active low; signal internal- ly debounced and synchronized to the bit clock). P1[15..0] (input/output).General-purpose I/O port. Direc- tion is bit-programmable. Pins P114 and P115, when con- figured in input mode, also behave as individually maskable interrupt pins for the core processor (positive edge-triggered). P0 0 WAKEUP0 P0 1 WAKEUP1 P0 2 WAKEUP2 P0 3 WAKEUP3 P1 14 INT0 P1 15 INT2
several additional functional blocks. In Addition, there are the following Shared Blocks. Figure 1. Basic Time Duplex Timing
to retrieve the baseband information. generates the DC level of both VREF and RX input pins. matches the DC impedance seen by the RX pin. that brings the sampled receive signal to baseband. MHz signal brings the receive signal to baseband. to correct the NCO frequency output. tion, and both receiver and transmitter on the handset. Figure 2. Demodulator Block Diagram
2.048 MHz
Spread Spectrum Controllers Zilog 1-22 P R E L I M I N A R Y DS96WRL0501 FUNCTIONAL DESCRIPTION (Continued) Since the data is packed in frames sent alternately from base and handset every 4 ms (TDD), additional synchroni- zation means are necessary. This is realized in a frame synchronizer, based on detection of a “unique word” fol- lowing the preamble. The receiver also features a signal-to-noise ratio detector, which allows the DSP software to detect noisy channels and eliminate them from the frequency hopping cycle. The SNR information is also used by the Z87000 software as a measure the current range between handset and base sta- tion. This information allows the adaptive power control al- gorithm to provide sufficient output power to the RF trans- mitter. Receive Frame Counter The receive frame counter is responsible to keep track of time within the frame. It is initialized by the frame synchro- nizer logic on detection of the unique word. It is then clocked by the recovered bit clock from the bit synchroniz- er. On the base station, the receive frame counter is used as time base for the receiver. On the handset, it is used as time base for both receiver and transmitter. Receive Rate Buffer and Voice Interface The voice signal is generated at the fixed rate of 32 kips by the Z87010 processor, and transmitted/received in bursts of 93.09 kips across the air. Data buffers in the transmitter and receiver are thus necessary to absorb the rate differ- ences over time. These buffers are called “rate buffers”. They can store up to 144 data bits and are organized as an array of 36 4-bit nibbles. The receive rate buffer stores the received data from the demodulator. Incoming bits are arranged in 4-bit nibbles and transferred to successive locations of the rate buffer. When the last location is reached, transfers resume from the beginning (circular buffer). The system design guaran- tees that no buffer overrun nor enduring can occur. The receive rate buffer can be read by the DSP core pro- cessor of the Z87000 or by the Z87010 chip. On the Z87000 side, the buffer can be read as a random-access memory: the processor writes the nibble address in an ad- dress register and reads the 4-bit data from a data register. On the Z87010 side, a voice processor interface logic han- dles the addressing to automatically present the succes- sive voice nibbles to the Z87010 in the order they were re- ceived. Transmit Rate Buffer and Voice Interface The transmit rate buffer stores the data to be modulated. The data is sourced from the Z87010 or the Z87000 core processor. As for the receive rate buffer, the Z87010 sees a unique pipe to write to, while the Z87000 DSP core ac- cesses the rate buffer as random-access memory. The modulator reads from the rate buffer as from a circular buffer. Transmit Frame Timing Counter On the handset, transmission does not start until the re- ceiver has synchronized itself to the signal received from the base station. The transmission timing is based on the recovered clock. No additional counter is necessary. On the base station, the situation is different. Transmission timing is based on a local clock, while the reception’s tim- ing is based on the clock recovered from the incoming re- ceived signal. Two counters, respectively clocked by local and recovered clocks, are necessary to track the transmit and receive signals. Note that the receive clock on the base station tracks the handset’s transmit clock, which is also the handset’s re- ceive clock and tracks the transmit clock of the base sta- tion. As a result, receive and transmit clocks of the base station have exactly the same frequency; only their phases differ. Modulator The modulator consists of a numerically controlled oscilla- tor (NCO) which generates an FSK (Frequency Shift Key- ing) signal at the carrier frequency of 2.508 MHz. The car- rier frequency is shifted plus or minus 32.58 kHz for a “1” or a “0” data bit. To facilitate conformance to FCC regula- tions, the transitions from “1” to “0” or vice-versa are smoothed in order to decrease the amplitude of the side lobes of the transmit signal. In practice, the jump from one frequency to the next is performed in several smaller steps. The carrier frequency is adjustable by the DSP core pro- cessor in order to provide additional frequency adjustment between base and handset. This is provided in case of a frequency offset too large for possible correction by the AFC. The modulator also includes bit inversion logic as dis- cussed in the receiver section.
Zilog Spread Spectrum Controllers DS96WRL0501 P R E L I M I N A R Y 1-23 Transmit 4-Bit DAC The transmit DAC clocks one new NCO value out of the Z87000 every 8.192 MHz period. Only the 10.7 MHz alias frequency component of the transmit signal (2.508 + 8.192 MHz image) is filtered, amplified and upconverted to the 900 MHz ISM band by the companion RF module. Event Trigger Block The event trigger block is responsible for scheduling the different events happening at the bit and frame levels. The event trigger block receives input from the frame counters as well as the register interface of the DSP core processor. The event trigger schedules the following events: n Start of the 4 ms frame: a synthesizer load enable pulse is issued on the SYLE pin n Power-up of the modulator section and transmission of the frame on handset and base station n Use of the bit inversion as function of mode n Power-up of the demodulator section and reception of the frame on handset and base station n Control of RFTX and RFRX output pins, to be used as TDD control signals switching the antenna as well as transmitter and receiver chains on the RF module n Control of RFEON pin, to be used as general on/off switch on the RF module n Control of the Z87000 sleep mode 4-Bit DAC for Setting Transmit Power Level In order to save battery life, the Z87000 only transmits the amount of RF power needed to reach the remote receiver with a sufficient SNR margin. The on-board transmit power 4-bit DAC provides 4 different voltage levels to the power amplifier in the RF module for that purpose. This DAC is di- rectly controlled by the Z87000 software through an output register. 8-Bit ADC for Sampling the Received Signal Strength Indicator (RSSI) RSSI information is typically generated from the last stage of the RF receiver. The RSSI is sampled once per frame by the 8-bit ADC and used by the Z87000 software to com- pute the necessary Transmit Power Level voltages. DSP Core Processor A DSP core processor constitutes the heart of the Z87000. The DSP runs the application software which performs the following functions: n Register initialization n Implementation of high-level phone features; control of phone user interface (keypad, Led, etc.) n Control of the Z87010 ADPCM Processor n Control of the phone line interface n Ring detection by DSP processing n Communication protocol between handset and base station supporting voice and signalling channels n Control of the RF synthesizer and adaptive frequency hopping algorithm n Control of the RF power and adaptive power algorithm n Control of the demodulator (bit synchronizer loop filter, AFC bias estimate filtering) n Control of the modulator (carrier frequency) and adaptive frequency alignment n Signalling between base and handset to support above The DSP core is characterized by an efficient hardware ar- chitecture that allows fast arithmetic operations such as multiplication, addition, subtraction and multiply-accumu- late of two 16-bit operands. Most instructions are executed in one clock cycle. Figure 3. Modulator Block Diagram
vectored interrupts are complemented by a six-level stack. mapped into the DSP core processor’s register interface. Z87000. Arbitration logic resolves access contentions. dressing within the rate buffers. from the Z87010 side is given below. Figure 4. ROM Mapping
ting the BIAS_ENABLE control bit. processed, and written to the CORE_BIAS_DATA field. two’s complement numbers in units of 125 Hz. the MOD_FREQ register fields. Figure 5. AFC Loop and Processor Control
is summarized in the following block diagram. Table 1. AFC and Modulator Control Fields Figure 6. Bit Synchronizer Loop and Processor Control
enough transitions for all transferred data. terms refer to the same unique counter. of count 371, the counters wrap around to 0. the data match, the frame counter is reset. (UW_LOCATION - 84) as shown in the next figure. base station, the UW_LOCATION should be set to 301. Table 2. Bit Synchronizer Control Fields
while (see description of sleep mode). size is determined by the WINDOW_SIZE field. Processor access disabled; bit inversion disabled. Processor access disabled; bit inversion enabled. start indicator bit is set (FRAME_START_IND status field). Figure 7. Frame Counter and UW_LOCATION on Handset
of frame synchronization and basic frame timing. the RF module is in use, and de-asserted in sleep mode. generate the next RF channel, is controlled by two fields. by the DSP core to realize any particular interface timing. cycle architecture of the DSP core. enced to the transmit frame counter. Table 3. Frame Synchronizer Control Fields
Figure 8. RF interface Control Table 4. Timing and RF Interface Control Fields
sleep mode, the RFEON pin is de-asserted. piration of the sleep counter. ly to the base station’s hopping sequence. sary before stopping and after restarting the clock). ply obtained by dividing the 16.384 MHz input clock. eliminating buffer overrun and underrun situations. software to ensure correct reception of all commands. buffers each contain 36 4-bit nibbles. without resetting the address each time. Table 5. Sleep Mode Control Fields Table 6. ADPCM Processor Control Fields
= number of nibbles in rate buffer) after each data read. out resetting the address each time. Figure 9. Rate Buffers Access and ADPCM Processor Interface
8-bit ADC can be used for additional purposes. termine and avoid the noisy channels. through register field TX_PWR_DAC_DATA. pins for the Z87000 (See “Sleep mode” on page 21). Table 7. Data and Control Access to Rate Buffers Table 8. Power Control Table 9. General-Purpose I/O Ports
ter” space, as summarized in the following table. Table 10. Register Summary
can be accessed by a single-cycle software instruction. Table 11. Bank Switching Bank 2 xxxx xxxx x10x xxxx b ADPCM processor interface, RF interface, etc. Table 12. Bank 3 Registers Controls CLKOUT output pin (clock for ADPCM Processor).
- •• 1111 Defines the search window size (in bits) for windowed search mode (for Unique Word or SYNC_D words). Returns 0 Window size=1 Window size =3 (1–1) Window size = 31 (1– 15) BIAS_THRESHOL D R W XXh Bias estimator threshold value Returns 0 Sets the bias value Notes: 1. VP_CLOCK. Internally synchronized to avoid glitches. Changes to this bit take effect immediately. 2. SYLE_POLARITY. Changes to this bit take effect immediately. 3. BIAS_THRESHOLD. The bias threshold must be coded as a negative value (opposite of the threshold value) coded in 2’s complement. The nominal value for the threshold is -46 (=D3h). Internally, this value is sign-extended to 13 bits.
Table 13. Bank 3 Register EXT1
- •• FFh Programs sleep duration in sleep mode Illegal Sleep period=1 frame (4 ms) Sleep period = 255 frames (1.020s) R 00h 01h
- •• FFh Returns value of sleep counter when sleep mode is interrupted by a “wake” signal Normal expiration of sleep counter One frame left before normal expiration 255 frames left before normal expiration Notes: 1. SLEEP_PERIOD. In sleep mode, the RFEON pin is active. Changes to this bit take effect immediately. 2. SLEEP_REMAINING. A non-zero value indicates that the Z87000 was awakened by a key press activating one of the wake-up pins on port 0. In this case, the processor should immediately reset the SLEEP_WAKE field in SSPSTATE to prevent the pro- cess from going back to sleep when the user key press ceases.
Table 14. Bank 3 Register Description Clears the SYNC_ACQ_IND flag.
Clears the SYNC_ACQ_IND flag.
- DBP_STOP_CLOCK. When this bit is set to 1, the ADPCM Processor clock (CLKOUT) is stopped within two clock periods. When
imum specifications for high time and low time are respected.
- BSYNC_GAIN. Changes to this bit take effect immediately.
at the beginning of the frame following the change.
- TX_ENABLE. Global control for all system transmit functions, including RFTX pin control (timing set by the RFTX_PWR_ON/OFF
register fields) and power to the modulator and NCO (timing set by MOD_PWR_ON and the wake/sleep modes).
- Changes to this bit take effect immediately.
- HOP_ENABLE. Changes to this bit take effect immediately.
- SLEEP_WAKE. This bit must be set to enable the core to put itself to sleep via the GO_TO_SLEEP command. The SLEEP_WAKE
- SYNC_AQC_CLEAR. This bit must be set to “1” again after every “clear” operation to allow for the next “clear”.
- FRAME_START_CLEAR. This bit must be set to “1” again after every “clear” operation to allow for the next ?“clear”.
Table 15. Bank 3 Register Description FRAME_COUNTER. Read the double-buffered current value of the Frame Counter. On the handset, a single frame counter is used to clock transmit and receive events. Table 16. Bank 3 Register Description Table 17. Bank 3 Register Description (i.e. for output pins, the output value is returned unless a contention occurs).
Table 18. Bank 3 Register Description Table 19. Bank 3 Register Description Table 20. Bank 2 Register Description Table 21. Bank 2 Register Description the software during the frequency hopping guard time of the next frame.
Table 22. Bank 2 Register Description Access to the bias estimate from the AFC loop. Table 23. Bank 2 Register Description RSSI_DATA. This value is sampled once per frame (4ms) approximately at bit 72 (middle) of the received data. Table 24. Bank 2 Register Description CORE_BIAS_DATA.This value is used if the USE_CORE_BIAS register field is set. It is encoded as a 2’s complement number.
Table 25. Bank 2 Register Description
- MOD_PWR_ON. Controls the turn-on time for the internal modulator and NCO. Only the 7 LSBits of the 9-bit value necessary
a fixed time (number of bits) after the turn-on time: 144 bits on the base station, 148 bits on the handset.
- Changes to this value take effect immediately.
- To disable the modulator continuously, clear TX_ENABLE
Table 26. Bank 2 Register Description
- DEMOD_PWR_ON, DEMOD_PWR_OFF. Controls internal receive hardware and the RXON output pin. The turn-on and off times
- Changes to these values take effect immediately.
- To enable receive power continuously, clear TX_ENABLE and set SYNC_SEARCH_MODE to FULL_SEARCH (this is the case
- The polarity of the RXON output pin is controlled by the RFRX_POLARITY bit in the RFRX_PWR_CTRL register
Table 27. Bank 2 Register Description
- RFTX_PWR_ON, RFTX_PWR_OFF. Controls the RFTX output pin, and thereby the external RF module’s transmitter. The
RFTX_PWR_OFF, the two bits are “01” on the base and “10” on the handset.
- Changes to these values take effect immediately.
- To disable the transmitter continuously, clear TX_ENABLE in SSP_STATE.
Table 28. Bank 1 Register Description
Table 29. Bank 1 Register Description The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register. MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz. These words are encoded as 2’s complement numbers. The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register. MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz. These words are encoded as 2’s complement numbers. Table 30. Bank 1 Register Description Table 31. Bank 1 Register Description
Table 32. Bank 1 Register Description P0_WAKEUP_ENABLE. When enabled, pins P0[3..0] are active low wake-up pins for the Z87000 sleep mode. allow the software to exit sleep mode safely. Table 33. Bank 1 Register Description
Table 34. Bank 0 Register Description Table 35. Bank 0 Register Description Table 36. Bank 0 Register Description
- RFRX_POLARITY. Caution: notice the inverse polarity of the RFRX pin.
- RFRX_PWR_ON, RFRX_PWR_OFF. Controls the RFRX output pin. The turn-on and off times are given in number of trans-
on the base and “10” on the handset.
- Changes to these values take effect immediately.
- To disable transmit power continuously, clear TX_ENABLE.
core processor’s instruction set. Table 37. Instruction Set Summary