Microcontroller

Z87C33

Zilog, Inc.

CMOS Z8짰 MCU Consumer Controller Processor

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ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Product Specification Z87C33 CMOS Z8® MCU Consumer Controller Processor PS015601-1003

©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applica- tions, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

CMOS Z8“ MCU Consumer Controller Processor iii Table of Contents

Table 4. Register Pointer Register—RP FDh/R253 Bank 0h: READ/WRITE . . 13 Table 7. Port Configuration Register—PCON 00h/R0 Bank Fh: WRITE ONLY. 22 Table 8. Stop-Mode Recovery Register 1—SMR1 0Bh/R11 Bank Fh: WRITE Table 11. Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh: WRITE Table 12. Watch-Dog Timer Mode Register—WDTMR 0Fh/R15: WRITE Table 17. Counter/Timer 1 Register—T1 F2h/R242 Bank 0h: READ/WRITE . . 33 Table 18. Prescaler 1 Register—PRE1 F3h/R243 Bank 0h: WRITE ONLY . . . 34 Table 19. Counter/Timer 0 Register—T0 F4h/R244 Bank 0h: READ/WRITE . . 35 Table 20. Prescaler 0 Register—PRE0 F5h/R245 Bank 0h: WRITE ONLY . . . 35 Table 23. Ports 0 and 1 Mode Register—P01M F8h/R248 Bank 0h: WRITE Table 24. Interrupt Priority Register—IPR F9h/R249 Bank 0h: WRITE ONLY . 37 Table 25. Interrupt Request Register—IRQ FAh/R250 Bank 0h: READ/WRITE 38 Table 26. Interrupt Mask Register—IMR FBh/R251 Bank 0h: READ/WRITE . . 39

Table 32. Port Configuration Register—PCON 00h/R0 Bank Fh: WRITE ONLY 43 Table 33. Stop-Mode Recovery Register—SMR 0Bh/R11 Bank Fh: Table 34. Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh: WRITE Table 35. Watch-Dog Timer Mode Register—WDTMR 0Fh/R15 Bank Fh: WRITE

CMOS Z8“ MCU Consumer Controller Processor Architectural Overview ZiLOG’s large Z8® family of 8-bit microcontrollers now includes the Z87C33 prod- uct line, featuring an enhanced wake-up circuitry, programmable Watch-Dog Tim- ers (WDT), and low-noise/EMI options. These enhancements to the Z8 offers a more efficient, cost-effective design and provides the user with increased design flexibility over the standard Z8 microcontroller core. The low-power-consumption CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion. The Z87C33 subfamily features an Expanded Register File (ERF) to allow access to register-mapped peripheral and I/O circuits. Four basic address spaces are available to support this wide range of configurations: Program Memory, Register File, and ERF. The Register File is composed of 237 bytes of general-purpose registers, three I/O port registers, 15 control and status registers. The ERF con- sists of four control registers. For applications demanding powerful I/O capabilities, the Z87C33 offers 24 pins dedicated to input and output. These lines are configurable under software con- trol. The Z87C33 family operates at 4MHz with a voltage range of 3.0 to 5.5VDC. To unburden the system from coping with real-time tasks such as counting/timing, the Z8 offers two on-chip counter/timers with a large number of user-selectable modes. All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. Power connections follow these conventional descriptions: Connection Circuit Device Power VCC VDD Ground GND VSS Note:

CMOS Z8“ MCU Consumer Controller Processor

Features

28-Pin DIP and 28-Pin SOIC 3.0- to 5.5-Volt Operating Range Operating Temperature Ranges: Standard: 0ºC to 70ºC Extended: –40ºC to +105ºC Expanded Register File (ERF)

24 Input/Output Lines

Vectored, Prioritized Interrupts with Programmable Polarity Two Analog Comparators Two Programmable 8-Bit Counter/Timers, each with two 6-Bit Programmable Prescalers VBO/Power-On Reset (POR) Clock-Free Watch-Dog Timer (WDT) Reset On-Chip Oscillator that accepts a Crystal, Ceramic Resonator, LC, RC, or Exter- nal Clock RAM and ROM Protect Table 1. Family Features

Figure 1. Functional Block Diagram

Table 2. 28-Pin DIP/SOIC Pin Configuration

CMOS Z8“ MCU Consumer Controller Processor Pin Functions The following pages describe the function of each available Z87C33 family pin. XIN Crystal Input. This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network, or an external single-phase clock to the on-chip oscillator input. XOUT Crystal Output. This pin connects a parallel-resonant crystal, ceramic reso- nant, LC, or RC network to the on-chip oscillator output. Port 0 (P00–P07). Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port (P03–P00 input/output and P07–P04 input/output), or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble-programmed as outputs and can be globally programmed as either push-pull or open-drain. Low-EMI output buffers are globally programmed by the software.

Figure 3. Port 0 Configuration Port 2 (P27–P20). Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port. by the software. See Figure 5.

CMOS Z8“ MCU Consumer Controller Processor Figure 4.Port 2 Configuration Port 3 (P37–P30). Port 3 is an 8-bit, CMOS-compatible port, with four fixed inputs (P33–P30) and four fixed outputs (P34–P37). Port 3 is configured under software control for Input/Output, Counter/Timers, interrupt, and UART. Port 3, bit 0 input is Schmitt-triggered, and pins P31, P32, and P33 are standard CMOS inputs (no autolatches). Pins P34, P35, P36, P37 are push-pull output lines. Low-EMI output buffers are globally programmed by the software. Two onboard comparators process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming Port 3 Port 2 (I/O) Open Out In PAD Auto Latch 1.5 2.3 Hysteresis VCC @ 5.0V R ~~ 500 kΩ Open Drain (Mask Option)

signals (IRQ3–IRQ0) and timer input and output signals (TIN and TOUT). PCON register bit D0 to 1 (see Figure 5). Table 3. Port 3 Pin Assignments

Figure 5. Port 3 Configuration

CMOS Z8“ MCU Consumer Controller Processor Figure 6.Port 3 Configuration—PCON Register Detail Autolatch. The autolatch places valid CMOS levels on all CMOS inputs (except P33–P31) that are not externally driven. Whether this level is 0 or 1 cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Autolatches are available on Port 0, Port 1, Port 2, and P30. There are no auto latches on P31, P32, and P33. Deletion of all port autolatches is available as an option when the device is programmed. The AUTOLATCH DISABLE option is selected by the customer when the device is programmed. PCON P31 P34 OUT REF (P33) PAD PAD P34 P37

0 P34, P37 Standard Output

1 P34, P37 Comparator Output

REF (P33) P32 P37 OUT Note:

CMOS Z8“ MCU Consumer Controller Processor Functional Description The Z8 MCU incorporates the following functions that enhance the standard Z8® architecture and provide the user with increased design flexibility: Program Memory ROM Protect RAM Protect Working Register File Expanded Register File General-Purpose Registers Stack Pointer Counter/Timers Interrupts Clock Power-On Reset HALT and STOP Modes Port Configuration Register Comparator Stop-Mode Recovery Watch-Dog Timer Voltage Comparator (VLV) RESET. The device is reset in one of the following conditions. Power-On Reset Watch-Dog Timer Stop-Mode Recovery Source Low Voltage Recovery Automatic Power-On Reset circuitry is built into the Z87C33 eliminating the requirement for an external reset circuit to reset upon power-up. Program Memory. The Program Memory addresses up to 4 KB of internal memory. The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available

CMOS Z8“ MCU Consumer Controller Processor interrupts. Address 12 to address 4095 consists of on-chip mask-programmed ROM. The 4 KB program memory is mask programmable. A ROM protect feature pre- vents dumping of the ROM contents by inhibiting execution of LDC, LDCI, LDE, and LDEI instructions to program memory in external program mode. ROM look- up tables can be used with this feature. The ROM Protect option is mask-pro- grammable, to be selected by the customer when the ROM code is submitted. See Figure 7. Figure 7.Program Memory Map ROM Protect. ROM PROTECT provides an additional security function. When the ROM PROTECT option bit is selected, and executing out of Internal Program IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) 65537 ROM On-Chip Reserved 4096 4095 Location of first Byte of Instruction Executed after RESET

CMOS Z8“ MCU Consumer Controller Processor Memory, instructions LDC, LDCI, LDE, and LDEI can read Internal Program Mem- ory. RAM Protect. The upper portion of the RAM’s address spaces 80h to EFh (exclud- ing the control registers) can be protected from writing. The RAM Protect option bit can be selected when the device is programmed. After the mask option is selected, the user activates this feature from the internal ROM code to turn off/on the RAM Protect by loading either a 0 or a 1 into the IMR register, bit D6. A 1 in bit D6 enables the RAM Protect option. Working Register File. The Z8 standard register file (Bank 0) contains 3 I/O port registers, 237 general-purpose registers, and 15 control and status registers. Expanded register file Bank Fh contains 4 system-configuration registers. The working registers are accessed directly or indirectly via an 8-bit address field. As a result, a short 4-bit register address can use the Register Pointer (Table 5 and Figure 9). In the 4-bit mode, the working register file is divided into 16 working reg- ister groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Throughout this document, Bank 0 is referred to as the Z8 Standard Register File. Expanded Register File (ERF). The Z8 register file is expanded to allow for addi- tional system control registers, and for mapping of additional peripheral devices, along with the I/O ports, into the register address area. The Z8 register address space 0 through 255 is implemented as 16 groups of 16 registers per bank (Fig- ures 8 and 9 ). There are 16 banks known as the Expanded Register File (ERF). Bits 7–4 of register RP select the Working Register Group. Bits 3–0 of register RP select the Expanded Register File Bank. Four system configuration registers reside in the Expanded Register File at Bank Fh—PCON, SMR, SMR2, and WDTMR. The remainder of the Expanded Register is not physically implemented, and is open for future expansion. Table 4. Register Pointer Register—RP FDh/R253 Bank 0h: READ/WRITE Note: R = Read, W = Write, X = Indeterminate.

Description

D7–D4 Working Registers R/W Working Register Group Pointer D3–D0 ERF R/W Expanded Register File

CMOS Z8“ MCU Consumer Controller Processor Figure 8.Register Pointer—Detail General-Purpose Registers (GPR). General-purpose registers are undefined after the device is powered up. These registers keep the most recent value after any RESET, as long as the RESET occurs in the VCC voltage-specified operating range. General-purpose registers are not guaranteed to keep their most recent state from a Low-Voltage Protection (VLV) RESET if VCC drops below 1.8V. This upper nibble of the register file address R15 to R0 FF provided by the register pointer specifies R253 (Register Pointer) r7 r6 r5 r4 r3 r2 r1 r0 the active working-register group. The lower nibble of the register file addresses provided by the instruction points to the specified register. Specified Working Register Group Register Group 1 Register Group 0 I/O Ports R15 to R0 R15 to R4* R3 to R0* * Expanded Register File Bank 0 is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP). EF Register Group Fh

CMOS Z8“ MCU Consumer Controller Processor Register E0h-EFh is only accessed via working register and indirect addressing modes. Stack Pointer. The internal register file is used for the stack. An 8-bit Stack Pointer (SPL) is used for the internal stack that resides within the 236 general-purpose registers. Stack Pointer High (SPH) is used as a general-purpose register. SPH and SPL are set to 00h after any RESET or Stop-Mode Recovery. Counter/Timers. There are two 8-bit programmable counter/timers (T0–T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the inter- nal clock only (Figure 10). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that is loaded into the counter. When the counter reaches the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counters are programmed to START, STOP, restart to CONTINUE, or restart from the initial value. The counters can also be programmed to STOP upon reach- ing 0 (SINGLE-PASS mode) or to automatically reload the initial value and con- tinue counting (MODULO–N CONTINUOUS mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divide-by-four, or an external signal input through Port 3. The Timer Mode Register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or nonretriggerable, or as a gate input for the internal clock. The counter/timers are cascaded by connecting the T0 output to the input of T1. TIN mode is enabled by setting PRE1 bit D1 to 0. Note: Note:

CMOS Z8“ MCU Consumer Controller Processor Figure 9.Expanded Register File Architecture REGISTER POINTER RESET CONDITION RESET CONDITION Expanded Register Bank (Fh) Working Register Group 0 Working Register Group Pointer Z8 Working Register File Expanded Register File Pointer 0Fh 00h FF FE FD FC FB FA (F) 0F* (F) 0E (F) 0D* (F) 0C (F) 0A (F) 09 (F) 08 (F) 07 (F) 06 (F) 05 (F) 04 (F) 03 (F) 02 (F) 01 (F) 00* WDTMR Reserved SMR2 Reserved SMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON X X U X X U X X U X U X U X U U U SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 PRE1 TMR Reserved X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 70h Notes X - Indeterminate * - Is not reset via Stop-Mode Recovery - Is not reset via Stop-Mode Recovery, except for bit D0 (F) 0B Expanded Register Bank 0h Working Register Group F F7* F6* FFh F0h

CMOS Z8“ MCU Consumer Controller Processor Figure 10.Counter/Timer Block Diagram Interrupts. The Z8 features six different interrupts from six different sources. These interrupts are maskable and prioritize. The six sources are divided as fol- lows: four sources are claimed by Port 3 lines P33–P30, and two are claimed by counter/timers (Interrupt Types, Sources, and Vectors). The Interrupt Mask Regis- ter globally or individually enables or disables the six interrupt requests. IRQ5 Internal Clock Clock Logic External Clock Internal Clock Gated Clock Triggered Clock TIN P31 OSC Current Value Write Write Read Internal Data Bus Register 6-Bit Down Counter 8-Bit Down Counter PRE1 Initial Value Register Initial Value Register IRQ4 Current Value Write Read Internal Data Bus Register 6-Bit Down Counter 8-Bit Down Counter PRE0 Initial Value Register Initial Value Register Write TOUT P36 D1 SMR D0 SMR

Table 5. Interrupt Types, Sources, and Vectors

branches to the program memory vector location reserved for that interrupt. to determine which of the interrupt requests require service. D7 and D6. The configuration is indicated in Table 7. oscillating from 1MHz to 4MHz. Table 6. IRQ Register*

CMOS Z8“ MCU Consumer Controller Processor programmable and is selectable by the customer at the time the ROM code is submitted. The RC option is available up to 4MHz. The RC oscillator configuration must be an external resistor connected from XIN to XOUT, with a frequency-setting capacitor from XIN to Ground (Figure 12). For better noise immunity, the capacitors should be tied directly to the device Ground pin (VSS). Figure 12.Oscillator Configuration Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscilla- tor is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: Power fail to Power OK status. Stop-Mode Recovery (if D5 of SMR = 1). WDT time-out. The POR time is specified as TPOR. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC/LC oscillators). HALT. HALT turns off the internal CPU clock, but not the CRYSTAL oscillation. The counter/timers, analog comparators, and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts and are either externally or internally generated. This also includes WDT time-out Reset Notes: XTAL1 XTAL2 LC Clock VSS VSS External Clock RC Clock XTAL1 XTAL2 XTAL1 XTAL2 XTAL1 XTAL2 L R VSS** C Ceramic Resonator or Crystal C1, C2 = 47µfd* f = 4MHz C1, C2 = 22 pf L =130 µH* f = 3 MHz* *Preliminary value, including pin parasitics ** Device Ground Pin @5V VCC (TYP) C1 = 44pF* R = 4K ohm f = 3 MHz*

CMOS Z8“ MCU Consumer Controller Processor and VLV Reset. An interrupt request must be enabled and executed to exit HALT mode. After the interrupt service routine, the program continues from the instruc- tion after the HALT. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP (Op Code = FFh) immediately before the appropriate sleep instruction. For example: or STOP. This instruction turns off the internal clock and external crystal oscillation. The STOP instruction also reduces the standby current to 10 µA or less. The ana- log comparators are automatically powered down in STOP-Mode. STOP mode is terminated either by WDT time-out, POR, Stop-Mode Recovery, or any Reset. As a result, the processor restarts the application program at address 000Ch. A WDT time-out in STOP mode affects all registers the same as if a Stop-Mode Recovery occurred via a selected Stop-Mode Recovery source except that the POR delay is enabled even if the delay is selected for disable. If a permanent WDT is selected, the WDT runs in all modes and cannot be stopped or disabled if the onboard RC oscillator is selected to drive the WDT. Port Configuration Register (PCON). The PCON register configures the ports indi- vidually; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on Ports 0, 1, 2, and 3, and low-EMI oscillator. The PCON register is located in the expanded register file at Bank F, location 00h (Table 8). FF NOP ; clear the pipeline STOP ; enter STOP mode FF NOP ; clear the pipeline HALT ; enter HALT mode Note:

CMOS Z8“ MCU Consumer Controller Processor Comparator Output Port 3 (D0). Bit 0 controls the comparator use in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration. The default value is 0. Port 0 Open-Drain (D2). Port 0 is configured as an open-drain by resetting this bit (D2 = 0) or configured as push-pull active by setting this bit (D2 = 1). The default value is 1. Low-EMI Port 0 (D3). Port 0 is configured as a low-EMI port by resetting this bit (D3 = 0) or configured as a Standard Port by setting this bit (D3 = 1). The default value is 1. Table 7. Port Configuration Register—PCON 00h/R0 Bank Fh: WRITE ONLY Note: R = Read, W = Write, X = Indeterminate. W Low-EMI Oscillator 0: Low EMI 1: Standard Port 3 I/O W Port 3 0: Low EMI 1: Standard Port 2 I/O W Port 2 0: Low EMI 1: Standard Reserved W Reserved* 1: Must be "1" Port 0 I/O W Port 0* 0: Low EMI 1: Standard Port 0 I/O W Port 0 0: Open-Drain 1: Push-Pull Active Reserved W Reserved* 1: Must be "1" Port 3 W Port 3 Comparator Output 0: P34, P37 Standard Output 1: P34, P37 Comparator Output

drive, while a 0 configures the oscillator, DS, AS and R/W with low noise drive. LOW-EMI mode reduces the drive of the oscillator (OSC). The default value is 1. divide value and determine the mode of Stop-Mode Recovery (Tables 8 and 11). addresses 0Bh and 0Dh, respectively. source of the Stop-Mode Recovery signal. Table 8. Stop-Mode Recovery Register 1—SMR1 0Bh/R11 Bank Fh: WRITE ONLY, except Bit D7,

CMOS Z8“ MCU Consumer Controller Processor SCLK & TCLK Divide-by-16 Select (D0). Bit D0 of the SMR controls a divide-by-16 prescaler of SCLK & TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). This bit is reset to D0 = 0 after a Stop-Mode Recovery. Reset Note: R = Read, W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset State R Stop Flag 0: POR 1: Stop-Mode Recovery SMR W Stop-Mode Recovery Level 0: Low 1: High STPDLY W Stop Delay 0: Off 1: On D4–D2 SMRSRC W 000 Stop-Mode Recovery Source 1 000: POR only and/or external RESET 001: P30 010: P31 011: P32 100: P33 101: P27 110: P2 NOR 0–3 111: P2 NOR 0–7 EXTCLK W External Clock Divide-by-2 0: SCLK & TCLK = XTAL ÷ 2 1: SCLK & TCLK = XTAL CLK W SCLK & TCLK Divide-by-16 0: Off 2 1: On Notes: 1. Do not use in conjunction with SMR2 Source. 2. Cleared by RESET and SMR.

CMOS Z8“ MCU Consumer Controller Processor External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by- two circuitry. When this bit is 0, the system clock (SCLK) and timer clock (TCLK) are equal to the external clock frequency divided by 2. The SCLK is equal to the external clock frequency when this bit is set (D1 = 1). Using this bit together with D7 of PCON further helps lower EMI (that is, D7 (PCON) = 0, D1 (SMR) = 1). The default setting is 0. Maximum external clock frequency is 4 MHz when SMR bit D1 = 1 where SCLK & TCLK = XIN. Stop-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR specify the wake-up source of the Stop-Mode Recovery (Figure and Stop-Mode Recov- ery Source). When the Stop-Mode Recovery Sources are selected in this register, then SMR2 register bits D0,D1 must be set to 0. If the Port 2 pin is configured as an output, this output level is read by the SMR circuitry. Figure 13.Stop-Mode Recovery Source Note: P30 P31 P32 P33 P27 SMR M U X P33 From Pads Digital/Analog Mode Select (P3M) Stop-Mode Recovery Edge Select (SMR) To P33 Data Latch and IRQ1 SMR2 P20 P23 P20 P27 To POR RESET VDD VDD P20 P27 P20 P23 SMR2 SMR2 SMR SMR SMR SMR D1 D0 0 0 D1 D0 0 1 D1 D0 1 0 D4 D3 D2 0 0 0 D4 D3 D2 0 0 0 0 1 0 0 1 1 D4 D3 D2 1 0 0 D4 D3 D2 1 0 1 D4 D3 D2 1 1 0 D4 D3 D2 1 1 1 SMR

active for at least 5 TPC. The clock source must be RC/LC/external clock driven. bit (warm) indicates that the device awakens by a Stop-Mode Recovery source. this register then SMR register bits D2, D3, and D4 must be 0. Table 9. Stop-Mode Recovery Source Table 10. Stop-Mode Recovery Register 2

CMOS Z8“ MCU Consumer Controller Processor Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven by an onboard RC oscillator or exter- nal oscillator from the XIN pin. The POR clock source is selected with bit 4 of the WDT register (Table 15). WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. The WDTMR must be written to within the first 60 internal system clocks. After that, the WDTMR is WRITE-protected. WDT time-out while in STOP mode does not reset SMR, PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers, but the POR delay counter is still enabled even though the SMR stop delay is disabled. Logical AND of P20 through P23 Logical AND of P20 through P27 Table 11. Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh: WRITE ONLY Note: R = Read, W = Write, X = Indeterminate. D7–D2 Reserved W X Reserved—must be 0 D1–D0 STOP Mode W Stop-Mode Recovery Source 2* 00: POR only 01: AND P20, P21, P22, P23 10: AND P20, P21, P22, P23, P24, P25, P26, P27 11: Reserved Note: *Do not use in conjunction with SMR Source.

CMOS Z8“ MCU Consumer Controller Processor WDT Time Select (D0,D1). Selects the WDT time period and is configured as indi- cated in Table 14. WDTMR During HALT (D2). This bit determines whether or not the WDT is active during HALT mode. A 1 indicates active during HALT. The default is 1. Table 12. Watch-Dog Timer Mode Register—WDTMR 0Fh/R15: WRITE ONLY Note: R = Read, W = Write, X = Indeterminate. D7–D5 Reserved W X Reserved—must be 0 XIN W XIN/INT RC Select for WDT 0: On-Board RC 1: XIN WDT W WDT During STOP WDT W WDT During HALT D1–D0 WDT Tap W WDT Tap Int RC OSC System Clock 00: 3.5 ms

128 SCLK

01: 7.0 ms

256 SCLK

10: 14.0 ms

512 SCLK

11: 56.0 ms

2048 SCLK

Note: Not used in conjunction with SMR Source. Table 13. WDT Time Select

CMOS Z8“ MCU Consumer Controller Processor WDTMR During STOP (D3). This bit determines whether or not the WDT is active during STOP mode. Because the XIN clock is stopped during STOP mode, the on- board RC must be selected as the clock source to the POR counter. A 1 indicates active during STOP. The default is 1. If the permanent WDT programming option is selected, the WDT runs in all modes and cannot be stopped or disabled if the on board RC oscillator is selected as the clock source for WDT. Clock Source for WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XIN. The default configuration of this bit is 0 which selects the internal RC oscillator. WDTMR Register Accessibility. The WDTMR register is accessible only during the first 64 internal system clock cycles from the execution of the first instruction after Power-On Reset, Watch-Dog Reset, or Stop-Mode Recovery. After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank Fh of the Expanded Register File at address location 0Fh (Figure 14). The WDT is permanently enabled (automatically enabled after RESET) through a programmable option. The option is selected when the device is programmed. In this mode, WDT is always activated when the device comes out of RESET. Execution of the WDT instruction serves to refresh the WDT time-out period. WDT operation in the HALT and STOP modes is controlled by WDTMR programming. If this option is not selected when the device is programmed, the WDT must be activated by the user through the WDT instruction and is always disabled by any reset to the device. Note: Note:

CMOS Z8“ MCU Consumer Controller Processor Figure 14.Resets and Watch-Dog Timer Example Voltage Comparator Low-Voltage Protection. An onboard Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. RESET is globally driven if VCC is below the specified voltage (Low-Voltage Protection). The minimum oper- ating voltage varies with the temperature and operating frequency, while the Low- Voltage Protection (VLV) varies with temperature only. The Low-Voltage Protection trip voltage (VLV) is less than 3V and more than 1.4V under the following conditions. At 25ºC, the device functions normally at or above 3.0V. Below 3.0V, the device functions normally until the Low-Voltage Protection trip point (VLV) is reached for the temperatures and operating frequencies in Table 15. The device is guaranteed to function normally at supply voltages above the Low-Voltage Protection trip Clear CLK

18 Clock RESET

4 Clock

I hhh bbbmc cbcbb IInternal RESET M U X 7ms POR 3.5ms 7ms 14ms 56ms CK WDT/POR Counter Chain CLK WDT TAP SELECT XTAL WDT Select (WDTMR) Clock Source Select (WDTMR) Internal RC OSC VDD VLV VLV Operating Voltage Det. WDT WWW WDT From Stop Mode Recovery Source Stop Delay Select (SMR)

and process parameters (Figure 15). is dependent on SMR Bit 0 1 setting. Table 14. Maximum (VLV) Conditions:

The Z87C33 offers 2 banks of registers, as detailed in the following pages. WRITE and reset states for bits D7–D0 are listed in Table 16. Table 15. Expanded Register File Registers—Reset States Note: *Not reset with a Stop-Mode Recovery.

CMOS Z8“ MCU Consumer Controller Processor Counter/Timer 1 Register The Counter/Timer 1 Register, T1, controls timing and counter functions. READ/ WRITE and reset states for bits D7–D0 are listed in Table 17. Table 16. Timer Mode Register—TMR F1h/R241 Bank 0h: READ/WRITE D7–D6 TOUT Mode R/W TOUT Mode 00: Off 01: T0 Output 10: T1 Output 11: Internal Clock Output D5–D4 TIN Mode R/W TIN Mode 00: External Clock Input 01: Gate Input 10: Trigger Input (nonretriggerable) 11: Trigger Input (retriggerable) T1 Count R/W T1 Count 0: Disable 1: Enable R/W 0: No Function 1: Load T1 T0 Count R/W T0 Count 0: Disable 1: Enable R/W 0: No Function 1: Load T0 Table 17. Counter/Timer 1 Register—T1 F2h/R242 Bank 0h: READ/WRITE

CMOS Z8“ MCU Consumer Controller Processor Prescaler 1 Register The Prescaler 1 Register, PRE1, controls clocking functions. READ/WRITE and reset states for bits D7–D0 are listed in Table 18. Counter/Timer 0 Register The Counter/Timer 0 Register, T0, controls timing and counter functions. READ/ WRITE and reset states for bits D7–D0 are listed in Table 19. Reset State X X X X X X X X Note: R = Read, W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset State D7–D0 R X T1 Current Value W X T1 Automatic Reload Value Range = 1–256 decimal; 01h–00h Table 18. Prescaler 1 Register—PRE1 F3h/R243 Bank 0h: WRITE ONLY Note: W = Write, X = Indeterminate. D7–D2 Prescaler W X Prescaler Modulo Range = 1–64 decimal; 01h–00h Clock W Clock Source 0: T1 External Timing Input (TIN) Mode 1: T1 Internal Count W Count Mode 0: T1 Single Pass 1: T1 Modulo N

CMOS Z8“ MCU Consumer Controller Processor Prescaler 0 Register The Prescaler 0 Register PRE0 controls clocking functions. WRITE and reset states for bits D7–D0 are listed in Table 20. Table 19. Counter/Timer 0 Register—T0 F4h/R244 Bank 0h: READ/WRITE Note: R = Read, W = Write, X = Indeterminate. D7–D0 R X T0 Current Value W X T0 automatic Reload Value Range = 1–256 decimal; 01h - 00h Table 20. Prescaler 0 Register—PRE0 F5h/R245 Bank 0h: WRITE ONLY Note: W = Write, X = Indeterminate. D7–D2 Prescaler W X Prescaler Modulo Range = 1–64 decimal; 01h–00h Reserved W X Reserved—must be 0 Count W Count Mode 0: T0 Single Pass 1: T0 Modulo N

CMOS Z8“ MCU Consumer Controller Processor Port 2 Mode Register The Port 2 Mode Register, P2M, controls Port 2 I/O functions. WRITE and reset states for bits D7–D0 are listed in Table 21. Port 3 Mode Register The Port 3 Mode Register P3M controls Port 3 I/O functions. WRITE and reset states for bits D7–D0 are listed in Table 22. Table 21. Port 2 Mode Register—P2M F6h/R246 Bank 0h: WRITE ONLY D7–D0 P20–P27 W P20–P27 I/O Definition 0: Defines bit as Output 1: Defines bit as Input Table 22. Port 3 Mode Register—P3M F7h/R247 Bank 0h: WRITE ONLY D7–D2 Reserved W Reserved—must be 00 Port 3 W Port 3 0: P31, P32 DIGITAL mode 1: P31, P32 ANALOG mode Port 2 W Port 2 0: Open-Drain 1: Push-Pull

CMOS Z8“ MCU Consumer Controller Processor Ports 0 and 1 Mode Register The Ports 0 and 1 Mode Register, P01M, controls port and timing functions for Ports 0 and 1. WRITE and reset states for bits D7–D0 are listed in Table 23. Interrupt Priority Register The Interrupt Priority Register, IPR, prioritizes interrupt functions. WRITE and reset states for bits D7–D0 are listed in Table 24. Table 23. Ports 0 and 1 Mode Register—P01M F8h/R248 Bank 0h: WRITE ONLY W Reserved - Must be 0 P04–P07 W P04–P07 Mode* 0: Output 1: Input Reserved W External Memory Timing Reserved - Must be 0 D4–D3 Reserved W P10–P17 Mode* 00: Reserved - Must be 0 Stack W Stack Selection* 0: Reserved 1: Must be "1" Reserved W Reserved - Must be 0 P00–P03 W P00–P03 Mode* 0: Output 1: Input Table 24. Interrupt Priority Register—IPR F9h/R249 Bank 0h: WRITE ONLY Note: W = Write, X = Indeterminate.

CMOS Z8“ MCU Consumer Controller Processor Interrupt Request Register The Interrupt Request Register, IRQ, controls interrupt functions. READ/WRITE and reset states for bits D7–D0 are listed in Table 25. Bit Position Bit Field R/W Reset State D7–D6 Reserved W XX Reserved—must be 0 IRQ3, IRQ5 W X IRQ3, IRQ5 Priority (Group A) 0: IRQ5 > IRQ3 1: IRQ3 > IRQ5 D4,D3,D0 Interrupt W XXX Interrupt Group Priority 000: Reserved 001: C > A > B 010: A > B > C 011: A > C > B 100: B > C > A 101: C > B > A 110: B > A > C 111: Reserved IRQ0, IRQ2 W X IRQ0, IRQ2 Priority (Group B) 0: IRQ2 > IRQ0 1: IRQ0 > IRQ2 IRQ1, IRQ4 W X IRQ1, IRQ4 Priority (Group C) 0: IRQ1 > IRQ4 1: IRQ4 > IRQ1 Table 25. Interrupt Request Register—IRQ FAh/R250 Bank 0h: READ/WRITE

CMOS Z8“ MCU Consumer Controller Processor Interrupt Mask Register The Interrupt Mask Register, IMR, controls interrupt functions. READ/WRITE and reset states for bits D7–D0 are listed in Table 26. Bit Position Bit Field R/W Reset State D7–D6 Interrupt Edge R/W Interrupt Edge 00: P31 ↓ P32 ↓ 01: P31 ↓ P32 ↑ 10: P31 ↑ P32 ↓ 11: P31 ↑↓ P32 ↑↓ IRQ5 R/W Interrupt IRQ5 = T1 0: No Interrupt pending 1: Interrupt pending IRQ4 R/W Interrupt IRQ4 = T0 0: No Interrupt pending 1: Interrupt pending IRQ3 R/W Interrupt IRQ3 = P30 Input 0: No Interrupt pending 1: Interrupt pending IRQ2 R/W Interrupt IRQ2 = P31 Input 0: No Interrupt pending 1: Interrupt pending IRQ1 R/W Interrupt IRQ1 = P33 Input 0: No Interrupt pending 1: Interrupt pending IRQ0 R/W Interrupt IRQ0 = P32 Input 0: No Interrupt pending 1: Interrupt pending Table 26. Interrupt Mask Register—IMR FBh/R251 Bank 0h: READ/WRITE

CMOS Z8“ MCU Consumer Controller Processor Flags Register The CPU sets flags in the Flags Register, FLAGS, to allow the user to perform tests based on differing logical states. READ/WRITE and reset states for bits D7– D0 are listed in Table 27. Reset X X X X X X X Note: R = Read, W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset State 1: Enable interrupts 0: Disable interrupts RAM Protect R/W X RAM Protect 1: Enable RAM Protect* 0: Disable RAM Protect D5–D0 IRQ5–IRQ0 R/W X Interrupt Request 1: Enable IRQ0–IRQ5 0: Disable IRQ0–IRQ5 Note: * Must select RAM Protect Mask Option Table 27. Flags Register—FLAGS FCh/R252 Bank 0h: READ/WRITE Note: R = Read, W = Write, X = Indeterminate. X Carry Flag Zero R/W X Zero Flag Sign R/W X Sign Flag Overflow R/W X Overflow Flag Decimal Adjust R/W X Decimal Adjust Flag Half Carry R/W X Half Carry Flag Note: *Not affected by RESET.

CMOS Z8“ MCU Consumer Controller Processor Register Pointer Register The Register Pointer Register, RP, controls pointer functions in the working regis- ters. READ/WRITE and reset states for bits D7–D0 are listed in Table 28. General Purpose Register The General Purpose Register (GPR) READ/WRITE and reset states for bits D7– D0 are listed in Table 29. User R/W X User Flag F2* User R/W X User Flag F1* Table 28. Register Pointer—RP FDh/R253 Bank 0h: READ/WRITE D7–D4 Working Register Pointer R/W Working Register Pointer D3–D0 Expanded Register File Bank R/W Expanded Register File Bank Table 29. General Purpose—GPR FEh/R254 Bank 0h: READ/WRITE Note: *Not affected by RESET.

CMOS Z8“ MCU Consumer Controller Processor Stack Pointer Low Register The Stack Pointer Low Register, SPL, controls pointer functions in the lower byte. READ/WRITE and reset states for bits D7–D0 are listed in Table 30. Expanded Register File, Bank Fh Expanded Register File Bank Fh contains 4 registers that perform the Port Config- uration, Stop-Mode Recovery, and Watch-Dog Timer Mode functions, as shown in Tables 31 through 35. These 4 registers are not reset by a Stop-Mode Recovery. Table 31 lists the reset states of all 4 Bank Fh registers. Bit Position Bit Field R/W Reset State D7–D0 GPR R/W General Purpose Register (D7-D0) Table 30. Stack Pointer Low—SPL FFh/R255 Bank 0h: READ/WRITE D7–D0 SPL R/W Stack Pointer Lower Byte (SP7–SP0) Table 31. Expanded Register File Registers—Reset States Note: *Not reset with a Stop-Mode Recovery. Note: **Not reset with a Stop-Mode Recovery except Bit D7.

CMOS Z8“ MCU Consumer Controller Processor Port Configuration Register The Port Configuration Register, PCON, controls the configurations of Ports 0, 2, and 3. WRITE and reset states for bits D7–D0 are listed in Table 32. 07h Reserved 08h Reserved 09h Reserved 0Ah Reserved 0Bh SMR** 0Ch Reserved 0Dh SMR2* X X X X X X 0Eh Reserved 0Fh WDTMR* X X X Table 32. Port Configuration Register—PCON 00h/R0 Bank Fh: WRITE ONLY W Low-EMI Oscillator 0: Low EMI 1: Standard Port 3 I/O W Port 3 0: Low EMI 1: Standard Port 2 I/O W Port 2 0: Low EMI 1: Standard Table 31. Expanded Register File Registers—Reset States (Continued) Note: *Not reset with a Stop-Mode Recovery. Note: **Not reset with a Stop-Mode Recovery except Bit D7.

CMOS Z8“ MCU Consumer Controller Processor Stop-Mode Recovery Register The Stop-Mode Recovery Register, SMR, controls clocking functions. READ/ WRITE and reset states for bits D7–D0 are listed in Table 33. Reserved W Reserved 1: Reserved must be "1" Port 0 I/O W Port 0† 0: Low EMI 1: Standard Port 0 I/O W Port 0 0: Open-Drain 1: Push-Pull Active Reserved W Reserved 1: Reserved must be "1" Port 3 W Port 3 Comparator Output 0: P34, P37 Standard Output 1: P34, P37 Comparator Output Table 33. Stop-Mode Recovery Register—SMR 0Bh/R11 Bank Fh:READ/WRITE R Stop Flag3 0: POR 1: Stop Recovery Stop-Mode Recovery W Stop-Mode Recovery Level 0: Low 1: High Notes: 1. For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR is used to select the Stop-Mode Recovery Source, bits D1–D0 of SMR2 must be 0. 2. Cleared by RESET and SMR. 3. Not reset after Stop-Mode Recovery. Bit Position Bit Field R/W Reset State

CMOS Z8“ MCU Consumer Controller Processor Stop Delay W Stop Delay 0: Off 1: On D4–D2 Stop Mode W 000 Stop-Mode Recovery Source2 000: POR only and/or external RESET 001: P30 010: P31 011: P32 100: P33 101: P27 110: P2 NOR 0–3 111: P2 NOR 0–7 Clock W External Clock Divide-by-2 0: SCLK &TCLK = XIN ÷ 2 1: SCLK &TCLK = X IN SCLK/TCLK W SCLK/TCLK Divide-by-16 0: Off 1: On Bit Position Bit Field R/W Reset State Notes: 1. For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR is used to select the Stop-Mode Recovery Source, bits D1–D0 of SMR2 must be 0. 2. Cleared by RESET and SMR. 3. Not reset after Stop-Mode Recovery.

CMOS Z8“ MCU Consumer Controller Processor Stop-Mode Recovery Register 2 The Stop-Mode Recovery Register, SMR2, controls additional Port 2 clocking functions. WRITE and reset states for bits D7–D0 are listed in Table 34. Watch-Dog Timer Mode Register The Watch-Dog Timer Mode Register, WDTMR, controls Watch-Dog Timer func- tions. WRITE and reset states for bits D7–D0 are listed in Table 35. Table 34. Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh: WRITE ONLY Note: W = Write, X = Indeterminate. D7–D2 Reserved W X Reserved—must be 0 D1–D0 STOP Mode W Stop-Mode Recovery Source 2* 00: POR only 01: AND P20, P21, P22, P23 10: AND P20, P21, P22, P23, P24, P25, P26, P27 11: Reserved Note: For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR2 is used to select the Stop-Mode Recovery Source, bits D4–D2 of SMR must be 0. Not used in conjunction with SMR Source. Table 35. Watch-Dog Timer Mode Register—WDTMR 0Fh/R15 Bank Fh: WRITE ONLY Note: W = Write, X = Indeterminate.

CMOS Z8“ MCU Consumer Controller Processor

Electrical Characteristics

Stresses greater than the Absolute Maximum Ratings listed in Table 36 may cause permanent damage to the device. This rating is a stress rating only. Func- tional operation of the device at any condition above those indicated in the opera- tional sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Bit Position Bit Field R/W Reset State D7–D5 Reserved W X Reserved—must be 0 XIN W X IN Input/Internal RC Select for WDT 0: On-Board RC 1: X IN WDT W WDT During STOP 0: WDT disabled during STOP mode 1: WDT enabled during STOP mode WDT W WDT During HALT 0: WDT disabled during HALT mode 1: WDT enabled during HALT mode D1–D0 WDT Tap W WDT Tap Int. RC Osc. System Clock 00: 3.5 ms 01: 7 ms 10: 14 ms 11: 56 ms Note: Not used in conjunction with SMR Source. Table 36. Absolute Maximum Ratings

Applies to all pins except Crystal pins and where otherwise noted.
There is no input protection diode from pin to VDD and current into pin is limited to ±600 µA.
Excludes XIN and XOUT pins.
Device pin is not at an output Low state.

Table 36. Absolute Maximum Ratings (Continued)

Table 37. DC Electrical Characteristics at Standard Temperature

0.7 VCC