Z87200

Z87200 ZILOG | Alldatasheet

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P RODUCT S PECIFICATION Z87200 S PREAD PECTRUM T RANSCEIVER

FEATURES

n Complete Direct Sequence Spread-Spectrum Transceiver in a Single CMOS IC n Programmable Functionality Supports Many Different Operational Modes n Acquires Within One Symbol Duration Using Digital PN Matched Filter n Two Independent PN Sequences, Each up to 64 Chips Long for Distinct Processing of the Acquisition/Preamble Symbol and Subsequent Data Symbols n Power Management Features n Optional Spectral Whitening Code Generation n Full- or Half-Duplex Operation Benefits n High Performance and High Reliability for Reduced Manufacturing Costs n Ideal for a Wide Range of Wireless Applications Including Data Acquisition Systems, Transaction Systems, and Wireless Local Area Networks (WLANs) n Fast Response and Very Low Overhead when Operating in Burst Modes n Allows High Processing Gain to Maximize the Acquisition Probability, then Reduced Code Length for Increased Data Rate n Reduced Power Consumption n Randomizes Data to Meet Regulatory Requirements n Permits Dual Frequency (Frequency Division Duplex) or Single Frequency (Time Division Duplex) Operation n Small Footprint, Surface Mount GENERAL DESCRIPTION The Z87200 is a programmable single-chip, spread-spec- trum, direct-sequence transceiver. The Z87200 incorpo- rates Stanford Telecom spread-spectrum and wireless technology and is identical to Stanford Telecom's STEL- 2000A. By virtue of its fast acquisition capabilities and its ability to support a wide range of data rates and spread- spectrum parameters, the Z87200 spread-spectrum trans- ceiver supports the implementation of a wide range of burst data communications applications. Available in both 45- and 20-MHz versions, the Z87200 performs all the digital processing required to implement a fast-acquisition direct sequence (such as pseudonoise- or PN-modulated), spread-spectrum full- or half-duplex sys- tem. Differentially encoded BPSK and QPSK are fully sup- ported. The receiver section can also handle differentially encoded pi/4 QPSK. A block diagram of the Z87200 is shown in Figure 1; its pin configuration is shown in Z87200 receive functions integrate the capabilities of a digital downconverter, PN matched filter, and DPSK demodula- tor, where the input signal is an analog-to-digital converted I.F. signal. Z87200 transmit functions include a differential BPSK/QPSK encoder, PN modulator (spreader), and BPSK/QPSK modulator, where the transmitter output is a sampled digitally modulated signal ready for external digi- Device Min PN Rate* (Mchips) Max Data Rate* (Mbps) Speed (MHz) Package Z87200 11 2.048 20/45 100-Pin PQFP Note: *45 MHz only

Spread-Spectrum Transceiver Zilog 4-2 DS96WRL0400 GENERAL DESCRIPTION (Continued) tal-to-analog conversion (or, if preferred, the spread base- band signal may be output to an external modulator). These transceiver functions have been designed and inte- grated for the transmission and reception of bursts of spread data. In particular, the PN Matched Filter has two distinct PN coefficient registers (rather than a single one) in order to speed and improve signal acquisition perfor- mance by automatically switching from one to the other upon signal acquisition. The Z87200 is thus optimized to provide reliable, high-speed wireless data communica- tions. Symbol-Synchronous PN Modulation The Z87200 operates with symbol-synchronous PN mod- ulation in both transmit and receive modes. Symbol-syn- chronous PN modulation refers to operation where the PN code is aligned with the symbol transitions and repeats once per symbol. By synchronizing a full PN code cycle over a symbol duration, acquisition of the PN code at the receiver simultaneously provides symbol synchronization, thereby significantly improving overall acquisition time. As a result of the Z87200's symbol-synchronous PN mod- ulation, the data rate is defined by the PN chip rate and length of the PN code; that is, by the number of chips per symbol, where a “chip” is a single “bit” of the PN code. The PN chip rate, R c chips/second, is programmable to as much as 1/4 the rate of RXIFCLK, and the PN code length, N, can be programmed up to a value of 64. When operat- ing with BPSK modulation, the data rate for a PN code of length N and PN chip rate R C chips/sec is R C /N bps. When operating with QPSK modulation (or p /4 QPSK with an ex- ternal modulator), two bits of data are transmitted per sym- bol, and the data rate for a PN code of length N and PN chip rate R c chips/sec is 2R c /N bps. Conversely, for a giv- en data rate R b bps, the length N of the PN code defines the PN chip rate R c as N x R b chips/sec for BPSK or as (N x R b )/2 chips/sec for QPSK. The data rate R b and the PN code length N, however, can- not generally be arbitrarily chosen. United States FCC Part 15.247 regulations require a minimum processing gain of 10 dB for unlicensed operation in the Industrial, Scientific, and Medical (ISM) bands, implying that the value of N must be at least 10. To implement such a short code, a Barker code of length 11 would typically be used in order to obtain desirable auto- and cross-correlation properties, although compliance with FCC regulations depends upon the over- all system implementation. The Z87200 further includes transmit and receive code overlay generators to insure that signals spread with such a short PN code length pos- sess the spectral properties required by FCC regulations. The receiver clock rate established by RXIFCLK must be at least four times the receive PN spreading rate and is lim- ited to a maximum speed of 45.056 MHz in the 45 MHz Z87200 and 20.0 MHz in the 20 MHz Z87200. The ensuing discussion is in terms of the 45 MHz Z87200, but the nu- merical values may be scaled proportionately for the 20 MHz version. As a result of the maximum 45.056 MHz RX- IFCLK, the maximum supported PN chip rate is 11.264 Mchips/second. When operating with BPSK modulation, the maximum data rate for a PN code of length N is 11.264/N Mbps. When operating with QPSK modulation (or p /4 QPSK with an external modulator), two bits of data are transmitted per symbol, and the data rate for a PN code of length N is 22.528/N Mbps. Conversely, for a given data rate R b , the length N of the PN code employed must be such that the product of N x R b is less than 11.264 Mchips/sec (for BPSK) or 22.528 Mchips/sec (for QPSK). For the 45 MHz Z87200, then, a PN code length of 11 im- plies that the maximum data rate that can be supported in compliance with the processing gain requirements of FCC regulations is 2.048 Mbps using differential QPSK. Note again, however, that FCC compliance using the Z87200 with a PN code of length 11 depends upon the overall sys- tem implementation.

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-3 Z87200 I.F. Interface The Z87200 receiver circuitry employs an NCO and com- plex multiplier referenced to RXIFCLK to perform frequen- cy downconversion, where the input I.F. sampling rate and the clock rate of RXIFCLK must be identical. In “complex input” or Quadrature Sampling Mode, external dual ana- log-to-digital converters (ADCs) sample quadrature I.F. signals so that the Z87200 can perform true full single sideband downconversion directly from I.F. to baseband. At PN chip rates less than one-eighth the value of RXIF- CLK, downconversion may also be effected using a single ADC in “real input” or Direct I.F. Sampling Mode. The input I.F. frequency is not limited by the capabilities of the Z87200. The highest frequency to which the NCO can be programmed is 50% of the I.F. sampling rate (the fre- quency of RXIFCLK); moreover, the signal bandwidth, NCO frequency, and I.F. sampling rate are all interrelated, as discussed in Higher I.F. frequencies, however, can be supported by using one of the aliases of the NCO frequen- cy generated by the sampling process. For example, a spread signal presented to the Z87200’s receiver ADCs at an I.F. frequency of f I.F. , where f RXIFCLK < f I.F. < 2 x f RXIF- CLK , can generally, as allowed by the signal’s bandwidth, be supported by programming the Z87200’s NCO to a fre- quency of (f I.F. - f RXIFCLK ), as discussed in Appendix A of this product specification. The maximum I.F. frequency is then limited by the track-and-hold capabilities of the ADC(s) selected. Signals at I.F. frequencies up to about

100 MHz can be processed by currently available 8-bit

ADCs, but the implementation cost as well as the perfor- mance can typically be improved by using an I.F. frequen- cy of 30 MHz or lower. Downconversion to baseband is then accomplished digitally by the Z87200, with a pro- grammable loop filter provided to establish a frequency tracking loop. Burst and Continuous Data Modes The Z87200 is designed to operate in either burst or con- tinuous mode: in burst mode, built-in symbol counters al- low bursts of up to 65,533 symbols to be automatically transmitted or received; in continuous mode, the data is simply treated as a burst of infinite length. The Z87200’s use of a digital PN Matched Filter for code detection and despreading permits signal and symbol timing acquisition in just one symbol. The fast acquisition properties of this design are exploited by preceding each data burst with a single Acquisition/Preamble symbol, allowing different PN codes (at the same PN chip rate) to independently spread the Acquisition/Preamble and data symbols. In this way, a long PN code with high processing gain can be used for the Acquisition/Preamble symbol to maximize the proba- bility of burst detection, and a shorter PN code can be used thereafter to permit a higher data rate. To improve performance in the presence of high noise and interference levels, the Z87200 receiver’s symbol timing recovery circuit incorporates a “flywheel circuit” to maxi- mize the probability of correct symbol timing. This circuit will insert a symbol clock pulse if the correlation peak ob- tained by the PN Matched Filter fails to exceed the pro- grammed detect threshold at the expected time during a given symbol. During each burst, a missed detect counter tallies each such event to monitor performance and allow a burst to be aborted in the presence of abnormally high in- terference. A timing gate circuit further minimizes the prob- ability of false correlation peak detection and consequent false symbol clock generation due to noise or interference. To minimize power consumption, individual sections of the device can be turned off when not in use. For example, the receiver circuitry can be turned off during transmission and, conversely, the transmitter circuitry can be turned off during reception when the Z87200 is operating in a half- duplex/time division duplex (TDD) system. If the NCO is not being used as the BPSK/QPSK modulator (that is, if an external modulator is being used), the NCO can also be turned off during transmission to conserve still more pow- er. Conclusion The fast acquisition characteristics of the Z87200 make it ideal for use in applications where bursts are transmitted relatively infrequently. In such cases, the device can be controlled so that it is in full “sleep” mode with all receiver, transmitter, and NCO functions turned off over the majority of the burst cycle, thereby significantly reducing the aggre- gate power consumption. Since the multiply operations of the PN Matched Filter consume a major part of the overall power required during receiver operation, two independent power-saving techniques are also built into the PN Matched Filter to reduce consumption during operation by a significant factor for both short and long PN spreading codes. The above features make the Z87200 an extremely versatile and useful device for spread-spectrum data communications. Operating at its highest rates, the Z87200 is suitable for use in wireless Local Area Network implementations, while its programmability allows it to be used in a variety of data acquisition, telemetry, and transaction system applications.

Figure 1. Z87200 Block Diagram

Figure 2. Z87200 100-Pin PQFP Pin Description

Table 1. 100-Pin PQFP Pin Description

2 RXQIN0 Rx Q-Channel Input

3 RXQIN1 Rx Q-Channel Input (Bit 1)

4 RXQIN2 Rx Q-Channel Input (Bit 2)

5 RXQIN3 Rx Q-Channel Input (Bit 3)

6 RXQIN4 Rx Q-Channel Input (Bit 4)

7 RXQIN5 Rx Q-Channel Input (Bit 5)

8 RXQIN6 Rx Q-Channel Input (Bit 6)

9 RXQIN7 Rx Q-Channel Input

10 RXXE Manual Receiver Enable

17 MTXE Manual Transmitter Enable

18 TXIN Transmitter Input

19 TXMCHP Transmitter Manual Chip Pulse

20 DATA0 Data Bus (Bit 0; LSB)

21 DATA1 Data Bus (Bit 1)

22 DATA2 Data Bus (Bit 2)

23 DATA3 Data Bus (Bit 3)

24 DATA4 Data Bus (Bit 4)

25 DATA5 Data Bus (Bit 5)

26 DATA6 Data Bus (Bit 6)

27 DATA7 Data Bus (Bit 7; MSB)

32 ADDR0 Address Bus (Bit 0; LSB)

33 ADDR1 Address Bus (Bit 1)

34 ADDR2 Address Bus (Bit 2)

35 ADDR3 Address Bus (Bit 3)

36 ADDR4 Address Bus (Bit 4)

37 ADDR5 Address Bus (Bit 5)

38 ADDR6 Address Bus (Bit 6; MSB)

41 RXTEST7 Receiver Test Output (Bit 7)

42 RXTEST6 Receiver Test Output (Bit 6)

43 RXTEST5 Receiver Test Output (Bit 5)

44 RXTEST4 Receiver Test Output (Bit 4)

45 RXTEST3 Receiver Test Output (Bit 3)

46 RXTEST2 Receiver Test Output (Bit 2)

47 RXTEST1 Receiver Test Output (Bit 1)

48 RXTEST0 Receiver Test Output (Bit 0)

52 RXSYMPLS Receiver Symbol Pulse

53 RXSPLPLS Receiver Sample Pulse

55 RXQOUT Receiver Q Channel Output

56 RXIOUT Receiver I Channel Output

57 RXOUT Receiver Output

59 TXTEST Transmitter Test Output

60 TXACQPLS Transmitter Acquisition Pulse

61 TXTRKPLS Transmitter Data Track Pulse

62 TXCHPPLS Transmitter Chip Pulse

63 TXBITPLS Transmitter Bit Pulse

76 TXQOUT Tx Q-Channel Output

77 TXIOUT Tx I-Channel Output

78 TXACTIVE Transmitter Active

83 RXACTIVE Receiver Active

84 RXMSMPL Receiver Manual Sample Clock

85 MFLD Manual Frequency Load

86 MNCOEN Manual NCO Enable

87 RXMABRT Receiver Manual Abort

88 RXMDET Receiver Manual Detect

91 RXIIN0 Rx I-Channel Input

92 RXIIN1 Rx I-Channel Input (Bit 1)

93 RXIIN2 Rx I-Channel Input (Bit 2)

94 RXIIN3 Rx I-Channel Input (Bit 3)

95 RXIIN4 Rx I-Channel Input (Bit 4)

96 RXIIN5 Rx I-Channel Input (Bit 5)

97 RXIIN6 Rx I-Channel Input (Bit 6)

98 RXIIN7 Rx I-Channel Input (

I.C. denotes Internal Connection. Do not use for vias.

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-7 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. Exposure to ab- solute maximum rating conditions for extended period may affect device reliability. D.C. CHARACTERISTICS Operating Conditions: V DD = 5.0V 5%, V SS = 0V Symbol Parameter Range Units T STG Storage Temperature –55 to +150 C V DD (max) Supply Voltage on V DD –0.3 to + 7 Volts V I (max) Input Voltage –0.3 to V DD +0.3 Volts I I DC Input Current 10 mA T A Operating Temperature (Ambient) 0 to +70 C T A = 0 to +70 C Typ Symbol Parameter Min Max @ 25 C Units Conditions I DDQ Supply Current, Quiescent 1.0 mA Static, no clock I DD Supply Current, Operational 380 170 [Note] mA mA f RXIFCLK = 45.056 MHz f RXIFCLK = 20 MHz V IH (min) High Level Input Voltage 0.7V DD VDD +.3 2.6 Volts Logic ‘1’ VIL(min) Low Level Input Voltage V SS –.3 0.2V DD 1.5 Volts Logic ‘0’ IIH (min) High Level Input Current 10 mA All inputs, VIN = VDD IIL (max) Low Level Input Current –10 mA TXIFCLK, RXIFCLK, /RESET only, VIN = VSS IIL(max) Low Level Input Current –130 –15 –45 mA All other inputs, VIN = VSS VOH (min) High Level Output Voltage VDD –0.4 Volts I O = –2.0 mA, all outputs VOL (max) Low Level Output Voltage 0.4 0.1 Volts I O = +2.0 mA, all outputs IOS Output Short Circuit Current 20 130 65 mA V OUT = VDD , VDD = max C Input Capacitance 2 pF All inputs C OUT Output Capacitance 4 pF All outputs Notes: 1. The operational supply current depends on how the Z87200 is configured. Typical current consumption can be approximated as follows: 2. IDD =5xfRXIFCLK +13 x fCHIP mA, 3. where fRXIFCLK is the frequency of RXIFCLK and fCHIP is the PN chip rate, both in MHz.

Figure 3. Microprocessor Interface Timing

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-9 A.C. CHARACTERISTICS - TRANSMITTER Operating Conditions: VDD = 5.0V –5%, VSS = 0V TA 0°C to +70°C Symbol Parameter Min Max Units Conditions fTXIFCLK TXIFCLK Frequency 45.056 20.0 MHz MHz Z0200045FSC Z0200020FSC or if TXIFOUT is used t CH TXIFCLK Pulse width, High 10 ns tCL TXIFCLK Pulse width, Low 10 ns tSU TXIN to TXIFCLK setup 3 ns tHD TXIN to TXIFCLK hold 5 ns tCT TXIFCLK to TXBITPLS, TXTRKPLS, XACQPLS, TXIOUT or TXQOUT delay 35 ns Notes: 1. The number of TXIFCLK cycles per cycle of TXCHPPLS is determined by the data stored in bits 5-0 of address 41H . It is shown as 2 in Figure 8 but can be set from 2 to 64. 2. The width of the TXBITPLS, TXTRKPLS and TXACQPLS signal pulses is equal to the period of TXCHPPLS; that is, equal to the PN chip period. 3. In QPSK mode, the TXBITPLS signal pulses high twice during each symbol period, once during the center chip and once during the last chip. If the number of chips per symbol is even, the number of chip periods between the TXBITPLS pulse at the end of the previous symbol and the one in the center of the symbol will be one more than the number of chip periods between the TXBITPLS pulse in the center of the symbol and the one at the end. The falling edge of the second pulse corre- sponds to the end of the symbol period. 4. The TXTRKPLS signal pulses high once each symbol period, during the last chip period of that symbol. The falling edge cor- responds to the end of the symbol period. 5. The TXACQPLS signal pulses high once each burst, transmission, during the last chip of the Acquisition/Preamble symbol. The falling edge corresponds to the end of this symbol period.

Figure 4. Transmitter Input/Output Timing

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-11 A.C. CHARACTERISTICS - RECEIVER Operating Conditions: VDD = 5.0V –5%, VSS = 0V TA = 0° to +70°C Symbol Parameter Min Max. Units Conditions f RXIFCLK RXIFCLK Frequency 45.056 20.0 MHz MHz Z8720045FSC Z8720020FSC tCH RXIFCLK Pulse width, High 10 ns tCL RXIFCLK Pulse width, Low 10 ns tSU RXIIN or RXQIN to RXIFCLK setup 3n s tHD RXIIN or RXQIN to RXIFCLK hold 7n s tCR RXIFCLK to RXSPLPLS, RXSYMPLS, or /RXDRDY delay 35 ns t CD RXIFCLK to RXOUT, RXIOUT, or RXQOUT delay 35 ns Notes: 1. The number of RXIFCLK cycles per cycle of RXSPLPLS is determined by the data stored in bits 5-0 of address 02H . It is shown as 2 in Figure 9, but can be set from 2 to 64. 2. The rising edge of /RXDRDY should be used to clock out the data (RXOUT, RXIOUT, or RXQOUT).

Figure 5. Receiver Input/Output

Figure 6. /OEN to RXTEST 7-0 Timing

transmit (TXMCHP) and receive (RXMSMPL) chip rates. of data corresponding to each QPSK symbol. four possible new input states. Table 2. QPSK Differential Encoder Sequence

to improve burst acquisition performance.

1. Since the NCO operates at a rate defined by RXIFCLK,

external modulator for their transmission. Table 3. DQPSK Differential Encoder Sequence

Spread-Spectrum Transceiver Zilog 4-16 DS96WRL0400 FUNCTIONAL BLOCKS (Continued) Frequency Control Register and NCO The Z87200 incorporates a Numerically Controlled Oscil- lator (NCO) to synthesize a local oscillator signal for both the transmitter’s modulator and receiver’s downconverter. The NCO is clocked by the master receiver clock signal, RXIFCLK, and generates quadrature outputs with 32-bit frequency resolution. The NCO frequency is controlled by the value stored in the 32-bit Frequency Control Register, occupying 4 bytes at addresses 03 H to 06H . To avoid de- structive in-band aliasing, the NCO should not be pro- grammed to be greater than 50% of RXIFCLK. As desired by the user, the output of the Z87200 receiver’s Loop Filter can then be added or subtracted to adjust the NCO’s fre- quency control word and create a closed-loop frequency tracking loop. If the receiver is disabled, either manually or automatically at the end of a burst, the Loop Filter output correcting the NCO’s Frequency Control Word is disabled. When simultaneously operating both the transmitter and receiver, however, the receiver’s frequency tracking loop affects the NCO signals to both the receive and transmit sides, a feature which can either be used to advantage in the overall system design or must be compensated in the programming of the Z87200 or in the system design. Downconverter The Z87200 incorporates a Quadrature (Single Sideband) Downconverter which digitally downconverts the sampled and digitized receive I.F. signal to baseband. Use of the Loop Filter and the NCO’s built-in frequency tracking loop permits the received signal to be accurately downconvert- ed to baseband. The Downconverter includes a complex multiplier in which the 8-bit receiver input signal is multiplied by the sine and cosine signals generated by the NCO. In Quadrature Sam- pling Mode, two ADCs provide quadrature (complex) in- puts I IN and QIN, while, in Direct I.F. Sampling Mode, a sin- gle ADC provides IIN as a real input. The input signals can be accepted in either two’s complement or offset binary formats according to the setting of bit 3 of address 01 H . In Direct I.F. Sampling Mode, the unused RXQIN Q channel input (Q IN) should be held to “zero” according to the ADC input format selected. The outputs of the Downconverter’s complex multiplier are then: I OUT = IIN . cos(w t) – Q IN . sin(w t) Q OUT = IIN . sin(w t) + Q IN . cos(w t) where w =2 pfnco These outputs are fed into the I and Q channel Integrate and Dump Filters. The Integrate and Dump Filters allow the samples from the complex multiplier (at the I.F. sam- pling rate, the frequency of RXIFCLK) to be integrated over a number of sample periods. The dump rate of these filters (the baseband sampling rate) can be controlled either by an internally generated dump clock or by an external input signal (RXMSMPL) according to the setting of bit 0 of ad- dress 01 H . Note that, while the receiver will extract exact PN and symbol timing information from the received sig- nal, the baseband sampling rate must be twice the nominal PN chip rate for proper receiver operation and less than or equal to one-half the frequency of RXIFCLK. If twice the PN chip rate is a convenient integer sub-multiple of RXIF- CLK, then an internal clock can be derived by frequency di- viding RXIFCLK according to the divisor stored in bits 5-0 of address 02 H ; otherwise, an external baseband sampling clock provided by RXMSMPL must be used. The I.F. sampling rate, the baseband sampling rate, and the input signal levels determine the magnitudes of the In- tegrate and Dump Filters’ accumulator outputs, and a pro- grammable viewport is provided at the outputs of the Inte- grate and Dump Filters to select the appropriate output bits as the 3-bit inputs to the PN Matched Filter. The viewport circuitry here and elsewhere within the Z87200’s receiver is designed with saturation protection so that extreme val- ues above or below the selected range are limited to the correct maximum or minimum value for the selected view- port range. Both viewports for the I and Q channels of the Integrate and Dump Filters are controlled by the values stored in bits 7-4 of address 01 H . Receiver PN Code Register and PN Matched Filter As discussed for the Z87200 transmitter, the Z87200 re- ceiver is designed for burst signal operation in which each burst begins with a single Acquisition/Preamble symbol and is then followed by data symbols for information trans- mittal. Complementing operation of the Z87200’s transmit- ter, two separate and independent PN codes may be em- ployed in the receiver’s PN Matched Filter, one for despreading the Acquisition/Preamble symbol, and one for the information data symbols. The code lengths are com- pletely independent of each other and can be each up to 64 chips long. A block diagram of the PN Matched Filter is shown in Figure 3.

Spread-Spectrum Transceiver Zilog 4-17 DS96WRL0400 The Z87200 contains a fully programmable 64-tap com- plex (dual I and Q channel) PN Matched Filter with coeffi- cients which can be set to –1 or zero according to the con- tents of either the Acquisition/Preamble or Data Symbol Code Coefficient Registers. By setting the coefficients of the end taps of the filter to zero, the effective length of the filter can be reduced for use with PN codes shorter than 64 bits. Power consumption may also be reduced by turning off those blocks of 7 taps for which all the coefficients are zero, using bits 6-0 of address 39H. Each ternary coeffi- cient is stored as a 2-bit number so that a PN code of length N is stored as N 2-bit non-zero PN coefficients. Note that, as a convention, throughout this document the first PN Matched Filter tap encountered by the signal as it en- ters the I and Q channel tapped delay lines is referred to as “Tap 0.” Tap 63 is then the last tap of the PN Matched Filter. The start of each burst is expected to be a single symbol PN-spread by the Acquisition/Preamble code. The receiv- er section of the Z87200 is automatically configured into acquisition mode so that the Matched Filter Acquisi- tion/Preamble Coefficients stored in addresses 07 H to 16H are used to despread the received signal. Provided that this symbol is successfully detected, the receiver will auto- matically switch from acquisition mode, and the Matched Filter Data Symbol Coefficients stored in addresses 17 H to 26H will then be used to despread subsequent symbols. To allow the system to sample the incoming signal asyn- chronously (at the I.F. sampling rate) with respect to the PN spreading rate, the PN Matched Filter is designed to operate with two signal samples (at the baseband sam- pling rate) per chip. A front end processor (FEP) operating on both the I and Q channels averages the incoming data over each chip period by adding each incoming baseband sample to the previous one: FEP OUT = FEPIN (1 + z –1) After the addition, the output of the FEP is rounded to a 3- bit offset 2’s complement word with an effective range of –3.5 such that the rounding process does not introduce any bias to the data. The FEP can be disabled by setting bit 0 of address 27 H to 1, but for normal operation the FEP should be enabled. The PN Matched Filter computes the cross-correlation be- tween the I and Q channel signals and the locally stored PN code coefficients at the baseband sampling rate, which is twice per chip. The 3-bit signals from each tap in the PN Matched Filter are multiplied by the corresponding coeffi- cient in two parallel tapped delay lines. Each delay line consists of 64 multipliers which multiply the delayed 3-bit signals by zero or –1 according to the value of the tap coefficient. The products from the I and Q tapped delay lines are added together in the I and Q Adders to form the sums of the products, representing the complex cross-cor- relation factor. The correlation I and Q outputs are thus: n = 63 Output (I, Q)=S Datan(I, Q) * Coefficientn(I, Q) n = 0 These I and Q channel PN Matched Filter outputs are 10- bit signals, with I and Q channel programmable viewports provided to select the appropriate output bits as the 8-bit inputs to the Power Detector and DPSK Demodulator blocks. Both I and Q channel viewports are jointly con- trolled by the data stored in bits 1-0 of address 28 H and are saturation protected. Two power saving methods are used in the PN Matched Filter of the Z87200. As discussed previously, the first method allows power to be shut off in the unused taps of the PN Matched Filter when the filter length is configured to be less than 64 taps. The second method is a propri- etary technique that (transparently to the user) shuts down the entire PN Matched Filter during portions of each sym- bol period.

Max{Abs(I),Abs(Q)} + 1/2 Min{Abs(I), Abs(Q)}. Figure 7. PN Matched Filter

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-19 To detect this maximum correlation in each symbol period, the signal power value is compared against a 10-bit user- programmable threshold value. A symbol clock pulse is generated each time the power value exceeds the thresh- old value to indicate a symbol detect. Since the Acquisi- tion/Preamble symbol and subsequent data symbols can have different PN codes with different peak correlation val- ues (which depend on the PN code length and code prop- erties), the Z87200 is equipped with two separate thresh- old registers to store the Acquisition/Preamble Threshold value (stored in addresses 29 H and 2AH ) and the Data Symbol Threshold value (stored in addresses 2BH and 2C H ). The device will automatically use the appropriate value depending on whether it is in acquisition mode or not. Since spread-spectrum receivers are frequently designed to operate under extremely adverse signal-to-noise ratio conditions, the Z87200 is equipped with a “flywheel circuit” to enhance the operation of the symbol tracking function by introducing memory to the PN Matched Filter operation. This circuit is designed to ignore false detects at inappro- priate times in each symbol period and to insert a symbol clock pulse at the appropriate time if the symbol detection is missed. The flywheel circuit operates by its a priori knowledge of when the next detect pulse is expected. A priori, the expected pulse will occur one symbol period af- ter the last correctly detected one, and a window of –1 baseband sample time is therefore used to gate the detect pulse. Any detects generated outside this time window are ignored, while a symbol detect pulse will be inserted into the symbol clock stream if the power level does not exceed the threshold within the window, corresponding to a missed detect. An inserted symbol detect signal will be generated precisely one symbol after the last valid detect, the nominal symbol length being determined by the value of Rx Chips Per Data Symbol stored in address 2D H . The cross-correlation characteristics of a noisy received signal with the noise-free local PN code used in the Z87200’s PN Matched Filter may result in “smearing” of the peak power value over adjacent chip periods. Such smearing can result in two or three consecutive power val- ues (typically, the on-time and one-sample early and late values) exceeding the threshold. A maximum power selec- tor circuit is incorporated in the Z87200 to choose the high- est of any three consecutive power levels each time this occurs, thereby enhancing the probability that the optimum symbol timing will be chosen in such cases. If desired, this function can be disabled by setting bit 3 of address 30 H high. The Z87200 also includes a circuit to keep track of missed detects; that is, those cases where no peak power level ex- ceeds the set threshold. An excessively high rate of missed detects is an indication of poor signal quality and can be used to abort the reception of a burst of data. The number of symbols expected in each receive burst, up to a maximum of 65,533, is stored in addresses 2E H and 30H . A counter is used to count the number of missed detects in each burst, and the system can be configured to automat- ically abort a burst and return to acquisition mode if this number exceeds the Missed Detects per Burst Threshold value stored in address 2F H . Under normal operating con- ditions, the Z87200 will automatically return to acquisition mode when the number of symbols processed in the burst is equal to the value of the data stored in address 2E H and 30H . To permit the processing of longer bursts or continu- ous data, this function can be disabled by setting bit 6 of address 30 H high. Differential Demodulator Both DPSK demodulation and carrier discrimination are supported in the Z87200 receiver by the calculation of “Dot” and “Cross” products using the despread I and Q channel information generated by the PN Matched Filter for the current and previous symbols. A block diagram of the DPSK Demodulator’s I and Q channel processing is shown in Let I k and Qk represent the I and Q channel out- puts, respectively, for the kth symbol. The Dot and Cross products can then be defined as: Dot(k) = I k Ik-1 + Qk Q k-1; and, Cross(k) = Qk Ik-1 - Ik Qk-1. Examination of these products in the complex plane re- veals that the Dot and Cross products are the real and imaginary results, respectively, of complex multiplication of the current and previous symbols. The Dot product alone thus allows determination of the phase shift between successive BPSK symbols, while the Dot and Cross prod- ucts together allow determination of the integer number of p/2 phase shifts between successive QPSK symbols. Dif- ferential encoding of the source data implies that an abso- lute phase reference is not required, and thus knowledge of the phase shift between successive symbols derived from the Dot and Cross products unambiguously permits correct demodulation. Implementation of this approach is simplified if the polari- ties (the signs) alone of the Dot and Cross products pro- vide the information required to make the correct symbol decision. For BPSK and p/4 QPSK signals, no modifica- tions are needed: in BPSK, the sign of the Dot product fully captures the signal constellation, while, in p/4 QPSK, the signal constellation intrinsically includes the phase rotation needed to align the decision boundaries with the four pos- sible combinations of the Dot and Cross product polarities. For QPSK signals, a fixed phase rotation of p/4 (45°) is in- troduced in the DPSK Demodulator to the previous symbol to simplify the decision algorithm. Rotation of the previous symbol is controlled by the settings of bits 0 and 1 of ad- dress 33 H , allowing the previous symbol to be rotated by 0° or –45°. As noted, for BPSK or p/4 QPSK signals, a ro- tation of 0° should be programmed, but, for QPSK signals,

where Sign[.] represents the polarity of the argument. FD = (Cross x Sign[Dot]) – (Dot x Sign[Cross]). Figure 8. DPSK Demodulator I and Q Channel Processing

the Loop Filter characteristics. is latched and processed by RXIFCLK. Figure 9. Frequency Discriminator and Loop Filter Detail

Spread-Spectrum Transceiver Zilog 4-22 DS96WRL0400 FUNCTIONAL BLOCKS (Continued) Note that if the Z87200 is to be used in Direct I.F. Sampling Mode, then the I.F. signal should be input to the RXIIN in- put port only. RXQIN must then be held to arithmetic zero according to the chosen ADC format as selected by bit 3 of address 01 H . In other words, to support Direct I.F. Sam- pling, RXQIN must be tied to a value of 127 or 128 if offset binary input format has been selected or to a value of 0 if two’s complement input format has been selected. RXMSMPL (Pin 84) Receiver Manual Sample Clock. RXMSMPL enables the user to externally generate (independent of the I.F. sam- pling clock, RXIFCLK) the baseband sampling clock used for all processing after the digital downconverter, including the dump rate of the Integrate and Dump filters. This fea- ture is useful in cases where a specific baseband sample rate is required that may not be derived by the internal sample rate timing generator which generates clock sig- nals at integer sub-multiples of RXIFCLK. The signal is in- ternally synchronized to RXIFCLK to avoid intrinsic race or hazard timing conditions. There must be at least two cy- cles of RXIFCLK to every cycle of RXMSMPL, and RXMSMPL should be set to twice the nominal receive PN chip rate. When bit 0 of address 01 H is set high, a rising edge on RXMSMPL will initiate a baseband sampling clock pulse to the Integrate and Dump filters and subsequent circuitry (e.g., PN Matched Filter, DPSK Demodulator, Power Esti- mator, etc.). The rising edge of RXMSMPL is synchronized internally so that, on the second rising edge of RXIFCLK that follows the rising edge of RXMSMPL, a pulse is inter- nally generated that clocks the circuitry that follows. On the third rising RXIFCLK edge, the contents of the Integrate and Dump Filters of the Downconverter are transferred to the PN Matched Filter. The extra one RXIFCLK delay be- fore transfer of the contents of the filters enables the inter- nally generated baseband sampling clock to be free of race conditions at the interface between the Downconvert- er and PN Matched Filter. RXMDET (Pin 88) Receiver Manual Detect. RXMDET enables the user to externally generate symbol timing, bypassing and overrid- ing the internal symbol power estimation and tracking cir- cuitry. This function may be useful when the dynamic char- acteristics of the transmission environment require unusual adjustments to the symbol timing. When bit 0 of address 30 H is set high (Manual Detect En- able) and when bit 0 of address 31H is set low, a rising edge of RXMDET will generate a symbol correlation detect pulse. The function can also be performed by means of bit 0 of address 31 H . The RXMDET input and bit 0 of address 31H are logically ORed together so that, when either one is held low, a rising edge on the other triggers the manual detect function. The rising edge of RXMDET is synchro- nized internally so that, on the second rising edge of the baseband sampling clock that follows the rising edge of RXMDET, the correlated outputs of the PN Matched Filter I and Q channels will be transferred to the DPSK demodu- lator. RXMABRT (Pin 87) Receiver Manual Abort. RXMABRT enables the user to manually force the Z87200 to cease reception of the cur- rent burst of data symbols and prepare for acquisition of a new burst. This function can be used to reset the receiver and prepare to receive a priority transmission signal under precise timing control, giving the user the ability to control the current status of the receiver for reasons of priority, sig- nal integrity, etc. When bit 0 of address 32 H is set low, a rising edge on RXMABRT will execute the abort function. The function can also be performed under microprocessor control by means of bit 0 of address 32 H . The RXMABRT input and bit 0 of address 32H are logically ORed together so that, when either one is held low, a rising edge on the other trig- gers the abort function. The second rising edge of the baseband sampling clock that follows a rising edge of RXMABRT will execute the abort and also clear the sym- bols-per-burst, samples-per-symbol, and missed-detects- per-burst counters. The counters will be reactivated on the detection of the next burst preamble or by a manual detect signal. RXIFCLK (Pin 12) Receiver I.F. Clock. RXIFCLK is the master clock of the NCO and all the receiver blocks. All clocks in the receiver section and the NCO, internal or external, are generated or synchronized internally to the rising edge of RXIFCLK. The frequency of RXIFCLK must be at least four times the PN chip rate of the received signal. When bit 0 of address 01 H is set low, the baseband sampling clock, required to be at twice the nominal PN chip rate, will be derived from RXIF- CLK according to the setting of bits 5-0 of address 02 H . MNCOEN (Pin 86) Manual NCO Enable. MNCOEN allows the power con- sumed by the operation of the NCO circuitry to be mini- mized when the Z87200 is not receiving and not transmit- ting data. The NCO can also be disabled while the Z87200 is transmitting as long as the Z87200’s on-chip BPSK/QPSK modulator is not being used. With the instan- taneous acquisition properties of the PN Matched Filter, it is often desirable to shut down the receiver circuitry to re- duce power consumption, resuming reception periodically until an Acquisition/Preamble symbol is acquired. Setting MNCOEN low holds the NCO in a reset state; setting MN- COEN high then reactivates the NCO, where it is neces- sary to then reload the frequency control word into the

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-23 NCO. Note that MNCOEN operates independently of MTXEN and MRXEN, where those pins have similar con- trol over the transmit and receive circuitry, respectively. MNCOEN performs the same function as bit 0 of address H , and these two signals are logically ORed together to form the overall control function. When bit 0 of address 37H is set low, MNCOEN controls the activity of the NCO cir- cuitry; when MNCOEN is set low, bit 0 of address 37 H con- trols the activity of the NCO circuitry. When either bit 0 or MNCOEN (whichever is in control, as defined above) goes low, a reset sequence occurs on the following RXIFCLK cycle to effectively disable all of the NCO circuitry, al- though the user programmable control registers are not af- fected by this power down sequence. Upon reactivation (when either MNCOEN or bit 0 of ad- dress 37 H return high), the NCO must be reloaded with fre- quency control information either by means of the MFLD input or by writing 01 H into address 00H . MTXEN (Pin 17) Manual Transmitter Enable. A rising edge on MTXEN causes the transmit sequence to begin, where the Z87200 first transmits a single Acquisition/Preamble symbol fol- lowed by data symbols. MTXEN should be set low after the last symbol has been transmitted. When MTXEN is set low, power consumption of the transmitter circuit is mini- mized. MTXEN operates independently of MRXEN and MNCOEN, where these signals have similar control over the receive and NCO circuitry, respectively. MTXEN performs the same function as bit 1 of address H . and these two signals are logically ORed together to form the overall control function. When bit 1 of address 37H is set low, MTXEN controls the activity of the transmitter circuitry, and, when MTXEN is set low, bit 1 of address 37H controls the activity of the transmitter circuitry. A rising edge on either MTXEN or bit 1 (whichever is in control, as defined above) initiates a transmit sequence. A falling edge initiates a reset sequence on the following TXIFCLK cycle to disable all of the transmitter data path, although the user programmable control registers are not affected by the power down sequence. MRXEN (Pin 10) Manual Receiver Enable. MRXEN allows power con- sumption of the Z87200 receiver circuitry to be minimized when the device is not receiving. With the instantaneous acquisition properties of the PN Matched Filter, it is often desirable to shut down the receiver circuitry to reduce pow- er consumption, resuming reception periodically until an Acquisition/Preamble symbol is acquired. Setting MRXEN low reduces the power consumption substantially. When MRXEN is set high, the receiver will automatically power up in acquisition mode regardless of its prior state when it was powered down. MRXEN operates independently of MTXEN and MNCOEN, where these signals have similar control over the transmit and NCO circuitry, respectively. MRXEN performs the same function as bit 2 of address H , and these two signals are logically ORed together to form the overall control function. When bit 2 of address 37H is set low, MRXEN controls the activity of the receiver cir- cuitry and, when MRXEN is set low, bit 2 of address 37 H controls the activity of the receiver circuitry. When either MRXEN or bit 2 (whichever is in control, as defined above) goes low, a reset sequence begins on the following RXIF- CLK cycle and continues through a total of six RXIFCLK cycles to virtually disable all of the receiver data paths. The user-programmable control registers are not affected by the power-down sequence, with the exception of RXTEST 7-0 Function Select (address 38H ), which is reset to 0. If the RXTEST7-0 bus is being used to read any func- tion other than the PN Matched Filter I and Q inputs, the value required must be rewritten after re-enabling the re- ceiver. TXIN (Pin 18) Transmit Input. TXIN supports input of the information data to be transmitted by the Z87200. In BPSK mode, the transmitter requires one bit per symbol period; in QPSK mode, two bits are required per symbol period. To initiate and enable transmission of the data, the user must raise MTXEN high. Data for transmission is request- ed with TXBITPLS, where one or two pulses per symbol are generated depending on whether the device is in BPSK or QPSK mode as set by bit 0 of address 40 H . To al- low monitoring of the state of the transmitter, the Z87200 will pulse TXACQPLS after the initial Acquisition/Preamble symbol is transmitted; the transmission of each subse- quent symbol is indicated by pulses of TXTRKPLS. If programmed for BPSK mode, data is requested by the Z87200 by a rising edge of output signal TXBITPLS, where TKBITPLS is generated once per symbol, one chip period before the end of the current symbol. At the end of the sym- bol duration, the TXIN data is latched into the device. TX- BITPLS falls low immediately following the rising edge of TXIFCLK, which latches the TXIN value, and is generated repeatedly at the symbol rate as long as the input signal MTXEN remains high. In QPSK mode, data is requested by the Z87200 by a ris- ing edge of output signal TXBITPLS, where this signal is generated twice per symbol, first one chip period before the middle of the symbol and then one chip period before the end of the symbol. TXBITPLS requests the data exact- ly one chip cycle before latching the TXIN data into the de- vice. TXBITPLS falls low immediately following the rising edge of TXIFCLK, which latches the TXIN value.

Spread-Spectrum Transceiver Zilog 4-24 DS96WRL0400 FUNCTIONAL BLOCKS (Continued) TXMCHP (Pin 19) Transmit Manual Chip Pulse. TXMCHP enables the user to provide the PN chip rate clock pulses from an external source. This feature is useful in cases where a specific chip rate is required that cannot be derived by the internal clock generator which generates clocks of integer sub- multiples of TXIFCLK. The signal is internally synchro- nized to TXIFCLK to avoid intrinsic race or hazard timing conditions. When bit 2 of address 40 H is set high, a rising edge on TXMCHP will generate the chip clock to the differential en- coder and the following circuitry (Acquisition/Preamble and Data Symbol PN spreaders, etc.). The rising edge of TXMCHP is synchronized internally so that, on the third rising edge of TXIFCLK following the rising edge of TXM- CHP, the PN code combined with the differentially encod- ed signal will change, generating the next chip. TXIFCLK (Pin 14) Transmitter I.F. Clock. TXIFCLK is the master clock of the transmitter. All transmitter clocks, internal or external, are generated or synchronized internally to the rising edge of TXIFCLK. The rate of TXIFCLK must be at least twice the transmit PN chip rate. It may be convenient to use the same external signal for both TXIFCLK and RXIFCLK, in which case the frequency of TXIFCLK will be at least four times the PN chip rate as required for RXIFCLK. Moreover, if the Z87200’s on-chip BPSK/QPSK Modulator is to be used, TXIFCLK and RXIFCLK must be identical and should not exceed 20 MHz. MFLD (Pin 85) Manual Frequency Load. MFLD is used to load a fre- quency control value into the NCO. The NCO may be load- ed in various ways, but MFLD provides a synchronized ex- ternal method of updating the NCO, while the other methods involve setting bit 0 of address 00H or using the programmable loop filter timing circuitry. MFLD is internal- ly synchronized to RXIFCLK to avoid internal race or haz- ard timing conditions. The MFLD input and bit 0 of address 00H are logically ORed together so that, when either one is held low, a rising edge on the other triggers the frequency load function manually. The rising edge of MFLD is synchronized inter- nally so that, on the sixth following rising edge of RXIF- CLK, the frequency control word is completely registered into the NCO accumulator. The frequency load command must not be repeated until the six RXIFCLK cycle delay is completed. /WR (Pin 28) Write Bar. /WR is used to latch user-configurable informa- tion into the control registers. It is important to note that the control registers are transparent latches while /WR is set low. The information will be latched when /WR returns high. DATA 7-0 and ADDR6-0 should be stable while /WR is set low in order to avoid undesirable effects. DATA 7-0 (Pins 20-27) Data Bus. DATA 7-0 is an 8-bit microprocessor interface bus that provides access to all internal control register in- puts for programming. DATA 7-0 is used in conjunction with the ADDR6-0 and /WR signals to set the values of the con- trol registers. ADDR 6-0 (Pins 32-38) Address Bus. ADDR 6-0 is a 7-bit address bus that selects the control register location into which the information pro- vided on the DATA 7-0 bus will be written. ADDR6-0 is used in conjunction with /WR and DATA7-0 to write the informa- tion into the registers. /CSEL (Pin 29) Chip Select Bar. /CSEL is provided to enable or disable the microprocessor operation of the Z87200. When /CSEL is set high, the ADDR 6-0 and /WR become disabled and have no effect on the device. When /CSEL is set low, the device is in its normal mode of operation and ADDR 6-0 and /WR are active. /OEN (Pin 49) Output Enable Bar. /OEN is provided to enable or disable the RXTEST 7-0 output bus. When /OEN is set high, the RXTEST 7-0 bus will have a high impedance, allowing it to be connected to other busses, such as DATA7-0. When /OEN is set low, the RXTEST7-0 bus will be active, allowing the RXTEST function selected to be accessed. /RESET (Pin 16) Reset Bar. /RESET is the master reset of the Z87200, clearing the control registers as well as the contents within the receiver, transmitter, and NCO data paths when it is set low. Setting /RESET high enables operation of the cir- cuitry.

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-25 OUTPUT SIGNALS TXIOUT (Pin 77) Transmitter In-Phase Output. TXIOUT is the in-phase output transmission signal that has been differentially en- coded and PN spread. TXIOUT changes on the rising edge of TXIFCLK following the falling edge of TXCHPPLS. TXQOUT (Pin 76) Transmitter Quadrature-Phase Output. TXQOUT is the quadrature-phase output transmission signal that has been differentially encoded and PN spread. TXQOUT changes on the rising edge of TXIFCLK following the fall- ing edge of TXCHPPLS. TXIFOUT 7-0 (Pins 66-73) Transmitter I.F. Output. TXIFOUT 7-0 is the modulated transmit output signal from the on-chip BPSK/QPSK mod- ulator. The signal is composed of the sum of the modulat- ed TXIOUT and TXQOUT signals, modulated by the NCO cosine and sine outputs, respectively. Since the modulator is driven by the Z87200’s NCO, TXIFOUT 7-0 changes on the rising edges of RXIFCLK, and operation of the BPSK/QPSK modulator requires that RXIFCLK and TXIF- CLK be identical and their common frequency not exceed 20 MHz. TXIFOUT 7-0 may be in either two’s complement or offset binary format according to the setting of bit 1 of address 40 H . TXACQPLS (Pin 60) Transmitter Acquisition Pulse. TXACQPLS is an output signal generated at the final chip of the Acquisition/Pream- ble symbol. The Acquisition/Preamble symbol is generat- ed automatically by the Z87200 upon user command (ei- ther via bit 1 of address 37 H or MTXEN input) and immediately precedes transmission of user data. TXACQ- PLS is then provided to the user to indicate when the final chip of the Acquisition/Preamble symbol is being transmit- ted. TXBITPLS (Pin 63) Transmitter Bit Pulse. TXBITPLS is an output signal used to support transmission timing of user data for either BPSK or QPSK modes, as programmed by bit 0 of 40 H . In BPSK mode, user-provided data is requested by the Z87200 by a rising edge of TXBITPLS once per symbol. TXBITPLS requests the data one chip period before the TXIN data is latched into the device, and TXBITPLS falls low immediately following the rising edge of TXIFCLK, where TXIFCLK latches the TXIN value. In QPSK mode, user-provided data is requested by the Z87200 by a rising edge of output signal TXBITPLS which occurs twice per symbol, first one chip period before the middle of the symbol and then one chip period before the end of the symbol. TXBITPLS requests the data exactly one chip cycle period before the TXIN data is latched into the device. TXBITPLS falls low immediately following the rising edge of TXIFCLK, where TXIFCLK latches the TXIN value. In both BPSK and QPSK modes, the data must be valid on the second rising edge of TXIFCLK after the rising edge of TXBITPLS. TXCHPPLS (Pin 62) Transmitter Chip Pulse. TXCHPPLS is an output signal used to support transmission timing for the device. TXCH- PPLS pulses high for one TXIFCLK cycle at the PN chip rate defined by the user. The chip rate is set either by pro- gramming a value in bits 5-0 of address 41 H or through use of the external TXMCHP signal. TXTRKPLS (Pin 61) Transmitter Data Track Pulse. TXTRKPLS is an output signal that allows monitoring of data symbol transmis- sions. A rising edge of output signal TXTRKPLS occurs one chip period before the end of the current data symbol transmission. TXTRKPLS then falls low immediately fol- lowing the rising edge of TXIFCLK. TXACTIVE (Pin 78) Transmitter Active. A high level on TXACTIVE indicates that the transmitter is sending data symbols. This signal will be set high at the end of the Acquisition/Preamble sym- bol, indicating the start of the first chip of the first data sym- bol at the TXIOUT and TXQOUT pins. It will be set low at the end of the last chip period of the last data symbol of the burst at the TXIOUT and TXQOUT pins. RXOUT (Pin 57) Receiver Output. RXOUT is the output data of the receiv- er following downconversion, despreading and demodula- tion. In BPSK mode, one data bit is provided per symbol; in QPSK mode, two data bits are provided per symbol with a half-symbol separation between the bits. Note that, when the Z87200 is operated in burst mode, the data will be in- valid during the first symbol of each burst; that is, in BPSK mode the first bit will be invalid, and in QPSK mode the first two bits will be invalid. RXIOUT (Pin 56) Receiver I Channel Output. RXIOUT is the I channel out- put data before dibit-to-serial conversion. RXIOUT can be used in conjunction with the RXQOUT signal in applica- tions where the QPSK output data is required as parallel bit pairs. Note that, when the Z87200 is operated in burst mode, the first bit of RXIOUT in each burst will be invalid RXQOUT (Pin 55). Receiver Q Channel Output. RXQOUT is the Q channel output data before dibit-to-serial conversion. RXQOUT can be used in conjunction with the RXIOUT signal in ap- plications where the QPSK data is required as parallel bit

mode, the first bit of RXQOUT in each burst will be invalid. when a new RXOUT signal is generated. signal that provides internal timing information to the user. the rising edge of RXSPLPLS. PLPLS preceding the falling edge of RXSYMPLS. Table 4. Receiver Test Functions

ranging from 0 to 255 (0H to FFH ). then the appropriate value must be rewritten. speeds greater than 20 MHz will be indeterminate. Table 5. Transmitter Test Functions Figure 10. Transmitter and Receiver Test Points

Spread-Spectrum Transceiver Zilog 4-28 DS96WRL0400 CONTROL REGISTERS Setting the Control Registers The majority of the Z87200 control registers are complete- ly independent and can be set or modified in any order. Two exceptions, however, exist: n First, any time that the NCO is disabled, either through use of pin MNCOEN or bit 0 of address 37 H , the frequency control word must be reloaded, either through use of pin MFLD or bit 0 of address 00 H , once the NCO is re-enabled. n Second, setting bit 2 of address 37H to zero to disable the receiver will also cause the data in address 38H to be set to zero, thereby possibly changing the receiver test point(s) that will be observed on the RXTEST pins. Address 38 H must be loaded with its desired value after bit 2 of address 37H is again set to 1. Downconverter Registers Address 00H : Bit 0 — Frequency Control Word Load This bit is used to load a frequency control value into the NCO, thereby changing its output frequency. The signal is internally synchronized to RXIFCLK to avoid intrinsic race or hazard timing conditions. The loading of the NCO may be performed by various means. Setting this bit provides a synchronized internal means to control update of the NCO. Alternatively, the MFLD pin or the Z87200’s programmable loop filter timing circuitry may be used. The MFLD input and bit 0 of address 00 H are logically ORed together so that, when either one is held low, a rising edge on the other triggers the frequency load function manually. The rising edge of this bit is synchronized inter- nally so that, on the following sixth rising edge of RXIF- CLK, the frequency control word is completely registered into the NCO accumulator. The frequency load command must not be repeated until after a delay of six RXIFCLK cy- cles. Address 01 H : Bit 0 — Manual Sample Clock Enable This bit selects the source of the internal baseband sam- pling clock, which should be at twice the nominal PN chip rate. The clock reference may be either supplied externally by RXMSMPL or generated internally from RXIFCLK. When this bit is set high, the baseband sampling rate of the receiver is controlled by the external RXMSMPL signal. When it is set low, the sampling clock is generated inter- nally (at a rate determined by the Sample Rate Control counter and set by bits 5-0 of address 02 H ) and the RXMSMPL input is ignored. Bit 1 — Invert Loop Filter Value This bit allows the sign of the output signal from the loop filter to be inverted, thereby negating the value of the sig- nal. The capability to invert the loop filter value permits the carrier frequency error component generated in the de- modulator to be either added to or subtracted from the Fre- quency Control Word of the NCO. The correct setting will depend on several factors, including whether high-side or low-side downconversion is used. When this bit is set low, the loop filter output is negated be- fore being summed with the Frequency Control Word of the NCO and is thus subtracted from the FCW; when this bit is set high, the loop filter output is not negated and is added to the FCW. Bit 2 — NCO Accumulator Carry In This bit is primarily used as an internal test function and should be set low for normal operation. When this bit is set high, 1 LSB is added to the NCO accumulator each clock cycle. When it is set low, the NCO accumulator is not af- fected. Bit 3 — Two’s Complement Input The RXIIN 7-0 and RXQIN7-0 input signals can be in either two’s complement or offset binary formats. Since all inter- nal processing in the device operates with two’s comple- ment format signals, it is necessary to convert the RXIIN 0 and RXQIN7-0 inputs in offset binary format to two’s com- plement format by inverting the MSBs. When this bit is set high, the device expects two’s comple- ment format inputs on RXIIN7-0 and RXQIN7-0. When it is set low, the device expects offset binary format on RXIIN7- 0 and RXQIN7-0. In two’s complement format, the 8-bit in- put values range from –128 to +127 (80H to 7FH ); in offset binary format, the values range from 0 to +255 (00H to FFH ).

each byte is stored in bit 0 of each register. Z87200 with a dual (I and Q channel) PN Matched Filter. Table 6. Integrate & Dump Filter Viewport Control Table 7. Integrate & Dump Filter Viewport Control

PN Matched Filter outputs before the viewport is applied. Table 8. PN Matched Filter Tap Values Table 9. Acquisition/Preamble Coefficient Storage Table 10. Data Symbol Coefficient Storage

the positive or negative boundary was exceeded. symbol, missed detects, etc. Max{Abs(I),Abs(Q)}+1/2 Min{Abs(I), Abs(Q)}. successful correlation is assumed to have been detected. successful correlation is assumed to have been detected. Table 11. Matched Filter Viewport Control

1 X Bits 9-2

Table 12. Acquisition/Preamble Threshold Storage

ter is provided for such use. not exceed the Data Symbol Threshold value. will be generated internally and tallied for the current burst. tion mode to await the next burst. symbols that would normally be successfully acquired. through dynamic setting of this bit. symbol stored in bits 5-0 of address 2DH . beginning demodulation of the data symbol information. Table 13. Data Symbol Threshold Storage

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-33 sert missed detect pulses; when set low, normal operation will be enabled whereby data symbols are automatically processed immediately following detection of an Acquisi- tion/Preamble symbol. Bit 3 — Bypass Max. Power Selector The Z87200’s receiver acquisition and tracking circuitry in- cludes a function that continuously selects the highest es- timated power level out of the three most recent consecu- tive estimated power levels from the PN Matched Filter. As the contents of the sliding 3-sample window change each cycle of the baseband sampling clock, a new determina- tion of the highest power level is made from the current set of the three most recent power level values. The correlated I and Q channel values within the 3-sample window corre- sponding in time to the highest observed power level are then available to be processed in the demodulator. This function assures that, within any 3-sample period, the I and Q channel values corresponding to the highest esti- mated power level will be selected over the two other pairs of correlated values even if the estimated power levels of the other pairs exceed the programmed threshold. The Maximum Power Selector is used in normal operation of the Z87200 so that the tracking algorithm discriminates by estimated power levels rather than exact timing intervals, thereby allowing the receiver to adjust to dynamic changes of the symbol phase. In cases where specific correlation values are desired regardless of their associated power level, bit 3 of address 30 H enables the 3-sample power dis- criminator to be bypassed, thereby making the outputs of the PN Matched Filter available directly to the demodula- tor. When this bit is set high, the Maximum Power Selector is bypassed; when it is set low, the Selector is enabled, where this is the normal operating mode. Bit 4 — Half Symbol Pulse Off The Z87200 generates two bit clock pulses per symbol when operating in QPSK mode, one at the mid-point of each symbol and one at the end of each symbol. These clocks are used by the Output Processor to manage data flow. When this bit is set high, the mid-point pulse is sup- pressed; when it is set low, the device operates in its nor- mal mode. This function is primarily used for test purposes and should not normally be used. Bit 5 — Missed Detects Per Burst Off To monitor the quality of the received burst data symbols, the Symbol Tracking Processor keeps track of the cumu- lative number of received data symbols per burst whose estimated correlation power level did not exceed the spec- ified Data Symbol Threshold value. When the accumulat- ed number of missed detects equals the Missed Detects per Burst Threshold value stored in address 2F H , the de- vice will terminate the reception of the current burst with the next missed detect and return to acquisition mode to await the next burst. When bit 5 is set low, the “missed detect” function operates normally; when set high, this function is disabled, allowing the device to be operated until the end of the specified data burst even when the number of “missed detects” exceeds the Missed Detects per Burst Threshold. Bit 6 — Receiver Symbols Per Burst Off The data stored in addresses 2E H and 3AH defines the number of data symbols per burst that will be processed by the receiver. This unsigned value must range from 3 to 65,535 (0003 H to FFFFH ), and the number of data symbols per burst will be this value minus 2. Once the number of data symbols processed by the receiver exceeds this num- ber, the burst is assumed to have ended and the receiver will immediately return to acquisition mode. When bit 6 is set high, the function is disabled, providing an option to track data symbols under external control for bursts of more than 65,533 data symbols or indefinitely for continuous transmission; when set low, the function will operate normally as defined by the value stored in ad- dresses 2E H and 3AH . Address 31H : Bit 0 — Manual Detect Pulse This bit provides the user a means to externally generate symbol timing, bypassing and overriding the internal sym- bol power estimation and tracking circuitry. This function may be useful in applications where the dynamic charac- teristics of the transmission environment require unusual adjustments to the symbol timing. When bit 0 of address 30 H is set high (Manual Detect En- able) and when RXMDET is low, a rising edge on this bit will generate a detect pulse. The function can also be per- formed by means of the RXMDET input signal. Bit 0 of ad- dress 31 H and the RXMDET input are logically ORed to- gether so that, when either one is held low, a rising edge on the other triggers the manual detect function. The rising edge of this bit is synchronized internally so that on the second rising edge of the baseband sampling clock that follows, the rising edge of bit 0 will transfer the I and Q channel correlated output values of the PN Matched Filter to the DPSK Demodulator. Address 32 H : Bit 0 — Receiver Manual Abort This bit enables the user to manually force the Z87200 to cease reception of the present burst of data symbols and prepare for acquisition of a new burst. This function can be used to reset the receiver and prepare to receive a priority transmission signal under precise timing control, giving the user the ability to control the current state of the receiver as needed.

amble symbol or by a manual detect signal. tion) for conventional QPSK signals. in the system and the length of the period between bursts. start from its initial state at the start of each burst. Loop Filter block to implement the Z87200’s AFC function. Table 15. AFC Viewport Control

Bits 4-0 control the gain factor K2 within the Loop Filter. n, where n is the 5-bit K2 Gain Value. This bit enables or disables the K2 path of the Loop Filter. by the accumulator will compound the error over time. it is low, a zero will be added. Bits 4-0 control the gain factor K1 within the Loop Filter. This bit enables or disables the K1 path of the Loop Filter. enables the path and turns on K1. ditional Doppler offsets are to be ignored. cesses the frequency error information in the usual way. Table 16. K2 Gain Values Table 17. K1 Gain Values

bit will precede the Q-channel bit in each symbol period. channel bit each symbol period. of the values of bits 0 and 1. loop AFC for carrier frequency acquisition and tracking. 16-0 x DotMSB ) – (Dot16-0 x CrossMSB ). it is set high, the outputs are inverted. ceive circuitry, respectively. over the receive and NCO circuitry, respectively. Table 18. Output Processor Modes

are not affected by the power down sequence. control over the transmit and NCO circuitry, respectively. rapidly than once per symbol may be indeterminate. puts, then the appropriate value must be rewritten. powered when the device is in acquisition mode. sition mode to await the next burst. Table 19. Matched Filter Tap Power Control

rate be consistent with Direct I.F. Sampling Mode. QPSK mode transmission. and differential encoding. symbol duration, the TXIN data is latched into the device. the rising edge of TXIFCLK, which latches the TXIN value. Table 20. Receiver Overlay Code Select

0 Overlay Code Disabled

the PN code, which may be useful in some cases. trols data symbol timing in the transmitter. number of chips per data symbol will be this value plus 1. configuration of the stored bits is as shown in Table 20. sequent data symbols is analogous. Table 21. Acquisition/Preamble Symbol Codes

tion of the bits stored is as shown in Table 22. spectral lines even when the data itself is not random. Table 22. Data Symbol Codes Table 23. Transmitter Overlay Code Select

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-41 REGISTER SUMMARY Table 24. Register Summary

Contents

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00H NCO Load 01H Integrate and Dump Filter Viewport Control 2’s C. Input NCO C’In Inv. LF RXMSMPL 02H Receiver Baseboard Sampling Rate Control 03-06H NCO Frequency Control Word (32 bits) 07-16H Matched Filter Acquisition/Preamble Symbol Coefficients 27H FEP Disable 28H MF Viewport Control 29-2AH Acquisition/Preamble Symbol Threshold, Bits 9-0 2B-2CH Data Symbol Threshold, Bits 9-0 2D H Receiver Chips Per Data Symbol 2EH Receiver Data Symbols per Burst, Bits 7-0 2FH Missed Detects Per Burst Threshold 30H Rx Symb/ Burst Off Missed Det. Per Bst. Off Half Symb Pulse Off Bypass Max Power Sel. Force Cont. Acquis. Manual Punctual Man. Det. Enable 31H Man. Det. 32H Man. Abort 33H AFC Viewport Control LF Clr. Dis. Unused (0) Signal Rotation Control 34H Carry In K2 On K2 Gain Value 35H L2 Freeze K1 On K2 Gain Value 36H Inv. O/p BPSK En. Rev. I & Q 38H RXTEST7-0 Function Select 39H Matched Filter Power Saver 3AH Receiver Data Symbols per Burst, Bits 15-8 3BH Receiver Overlay Sel IF Lpbk En MF Lpbk En 3C-3FH 40H Inv. Symb. TXMXHP O’Bin. O/p TX BPSK 41H TXIFCLK Cycles per Chip 42H Tx Chips per Data Symbol 43H Tx Chips per Acquisition/Preamble Symbol 44-4BH Transmitter Acquisition/Preamble Code (64 bits) 4C-53H TransmitterData Symbol Code (64 bits) 54H Unused (0) Transmitter Overlay Select

and the on-chip NCO in its quadrature mode. Using the Z87200 with a Single ADC in Direct I.F. ADC used in Quadrature Sampling Mode are not required. rate that can be supported by the Z87200 in Direct I.F. can be supported by Quadrature Sampling Mode. sions can be readily identified. Figure 11. Spectra of Signals in Direct I.F. Sampling Mode

Figure 13. The bandwidth B is the two-sided bandwidth, nal bandwidth; that is, 1/2B<f1. with no mirror reflections of the input spectrum created. pass filter as shown in line 6. conversion and filtering will also be spectrally inverted. type is BPSK, there is no effect on the demodulated data.

for positive integer n and positive B and f1. for positive integer n and positive B and f1. form true single sideband downconversion to baseband. Figure 15. Spectra of Signals in Quadrature Sampling Mode

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-47 Differential Demodulation As noted in the preceding text, computation of the “Dot” and “Cross” products is fundamental to operation of the DPSK Demodulator and Frequency Discriminator. Let I k and Qk represent the I and Q channel inputs, respectively, for the kth symbol after downconversion and despreading. The Dot and Cross products can then be defined as: Dot(k) = Ik Ik-1 + Qk Qk-1; and, Cross(k) = Qk Ik-1 - Ik Qk-1 In the complex domain, these products can be seen to have been defined to form the complex conjugate product between two input samples, one symbol apart. Let the k th input sample, sin(k), be defined as: sin(k) = I(k) + j Q(k), where I(k) and Q(k) are the 8-bit peak power PN Matched Filter I and Q channel outputs directed to the DPSK De- modulator. In polar form, s in(k) may be conveniently de- fined as: sin(k) = A(k)e jØ(k) with A(k) Ø(k) = arctan Simple substitution then shows that the complex conjugate product between consecutive symbols (with an arbitrary phase shift introduced to the previous symbol value) may be expressed as: s out(k)= sin(k) [sin(k–1) . w fixed]* = Dot(k) + j Cross(k) where w fixed = arbitrary fixed phase rotation; Dot(k)= Re[sout(k)]; and, Cross(k)= Im[sout(k)]* The fixed phase rotation w fixed has been introduced to later simplify the decision criteria. The ability to express real and imaginary parts of the complex conjugate product between consecutive symbols with the Dot and Cross products is the key to their use in DPSK demodulation. DBPSK Demodulation In DPSK, the phase difference between successive sam- ples is due to the data modulation phase differences, DØmod, plus any induced phase rotation between sym- bols, DØrot, resulting from, for example, a frequency offset between the received signal’s I.F. and that provided by the Downconverter. For DBPSK, the data modulation differ- ences DØmod can take only the values of 0° or 180°. Ex- pressing the complex phase difference [Ø(k)-Ø(k-1)] in terms of these components, the decision can be seen to be based on: Sout (k)=A(k) A(k-1) ejØ(k)*e-jØ(k-1) = A(k) *A(k1)*ej[DØ mod (k)+DØ rot(k)] For DBPSK, only the real part of sout(k), Dot(k), is needed to determine the modulated phase transition: Dot(k)= A(k)*A(k-1)*cos(DØ mod (k)+DØrot(k)) = –A(k)*A(k-1)*cos(DØ rot(k)) where the sign is determined by the transmitted data since cos[DØ mod (k)] = –1* As a result, Dot(k)» –A2(k) if the amplitude of the signal is constant for consecutive symbols and if the phase rotation DØ rot(k) between sym- bols is small. The Z87200 DPSK Demodulator can thus use the sign of the Dot product in order to make DBPSK symbol decisions without the introduction of any fixed phase rotation.

Spread-Spectrum Transceiver Zilog 4-48 DS96WRL0400 THEORY OF OPERATION (Continued) DQPSK Demodulation For DQPSK modulation, the possible phase shifts be- tween successive symbols due to the modulation are 0°, 90°, 180°, and 270°. Here, introduction of a phase shift fixed) of –45° to the previous symbol in the calculation of the Dot and Cross products is desired in order shift the possible phase differences to 45°, 135°, 225°, or 315° so that the DQPSK decision boundaries coincide with the signs of the Dot and Cross products. In the Z87200 DPSK demodulator, phase rotation is accomplished in the signal rotation block by the following transformation of the I and Q channel values: I rot(k)=[ I(k) - Q(k)]/2 for 45° rotation Irot(k)=[ I(k) + Q(k)]/2 for –45° rotation Q rot(k)=[ I(k) + Q(k)]/2 for 45° rotation Q rot(k)=-[ I(k) + Q(k)]/2 for –45° rotation The divide-by-2 is part of the signal rotation function. This transformation is equivalent to multiplying by (1 – j)/2 or (1/Ö2)ejØ(fixed) where Øfixed is –45°. In this case, sout(k) be- comes: sout(k)=A(k).A(k-1)*ejØ(k)*e–jØ(k-1)*[w fixed]* =A(k).A(k-1)*ej[DØ mod (k)+DØ rot (k)]* (1/Ö2)ejØ(fixed) so that Dot(k)»(1/Ö2)A(k)*A(k-1)*cos(DØ mod (k) - Øfixed) Cross(k)»(1/Ö2)A(k)*A(k-1)*sin(DØ mod (k) - Øfixed) where the phase rotation DØ rot(k) due to the frequency off- set between symbols has been assumed negligible. A summary of the Dot(k) and Cross(k) products for the possible values of DØ mod (k) and Øfixed is shown below, il- lustrating how the sign of the Dot and Cross products allow the symbol decision to be made: p/4 QPSK Demodulation The Z87200 DPSK Demodulator decision logic is de- signed so that correct DQPSK decisions are made with a signal rotation of Ø fixed= –45°. For p/4 QPSK modulation, however, the modulator itself inserts 45° between consec- utive symbols, and the possible phase shifts between suc- cessive symbols due to modulation are 45°, 135°, 225°, and 315°. As a result, the DPSK Demodulator should be configured for p/4 QPSK with Ø fixed=0°. DQPSK Phasing and I/Q Channel Reversal The Z87200 uses Differential BPSK and QPSK modulation and demodulation, meaning that the data is modulated on the carrier as phase changes. At the demodulator, the data is recovered by monitoring the phase change over a sym- bol period. The Z87200 provides configuration control to specifically address DPSK phasing and I/Q channel reversal: the Sig- nal Rotation control register, bits 0 and 1 of address 33 H , and the Reverse I and Q control register, bit 0 of address H . The first register causes an insertion of –45° in phase between consecutive symbols at the receiver, while the second register switches the I and Q channels presented to the DPSK demodulator. As discussed in the Z87200 ap- pendix, the introduction of a phase shift between consec- utive symbols changes the mapping of the input data with respect to the decision boundaries defined by the "Cross" and "Dot" product axes. Assuming that the transmitted DQPSK modulation phas- ing is differentially encoded as defined in Table 3, the phase shift between consecutive symbols should always be set to –45°; that is, bits 1 and 0 of address 33 H should be set to 11. Similarly, when the transmission path from modulator to demodulator does not introduce a frequency (or phase direction) reversal, the "reverse I and Q" control function should be disabled; that is, bit 0 of address 36H should be set to 0. Note that, in the case of DBPSK, the phase increments are either 0 or 180° and frequency re- versal has no impact. If frequency reversal does take place, however, correct DQPSK demodulation can be achieved by enabling I and Q reversal; that is, the entry into bit 0 of address 36 H should be set to 1. Frequency reversal may occur in the up or down conversion process, depending on which mixing product is selected for further processing. No reversal oc- curs when the following conditions exist: when the mixing Q(k) I(k) . I2(K)+Q2(k) Ø fixed = -45° Ø fixed = +45° DØ mod (k) Dot(k) Cross (k) DØ mod (k) Dot(k) Cross (k) 0° +A 2 +A 2 0° +A 2 –A2 90° –A2 +A 2 90° +A 2 +A 2 180° –A2 –A2 180° –A2 +A 2 270° +A 2 –A2 270° –A2 –A2

Zilog Spread-Spectrum Transceiver DS96WRL0400 4-49 at the transmitter is performed by processing the sum fre- quency of the local oscillator and the modulator; when the mixing at the receiver is performed by subtracting the local oscillator from the incoming signal; and when the in-phase and quadrature inputs into the I and Q analog-to-digital converters are correctly connected such that the in-phase component leads the quadrature component by 90°. Un- der these conditions, bit 0 of address 36 H should be set to 0; otherwise, the I and Q channels may need to be re- versed at the DPSK demodulator (by setting bit 0 of ad- dress 36 H to 1) in order to achieve proper demodulation. Frequency Error Signal Generation The frequency discriminator function or error signal is gen- erated based on the Dot and Cross products. The objec- tive is an error signal that is proportional to the sine of the phase difference between the present and prior symbol af- ter correcting for the estimated phase increments due to data modulation. In the Z87200 Frequency Discriminator, the frequency error is calculated through a decision-direct- ed cross-product algorithm and is then used with the Loop Filter to correct the NCO frequency. Assuming an input sin(k), where: s in(k) = I(k) + j Q(k), the algorithm calculates the frequency discriminator func- tion for DBPSK, sAFC/BPSK (k), as: SAFC/BPSK (k)=SIGN[Dot(k)]*Cross(k) =SIGN[Dot(k)]*A(k)*A(k-1)*sin(Ø(k)-Ø(k-1)) =SIGN[Dot(k)]*A(k)*A(k-1)*sin(DØmod(k) + DØrot(k)) »SIGN[Dot(k)]*A2(k)*cos[DØmod(k)]*sin[DØrot(k)] »A2(k)*sin[DØrot(k)]* The final result assumes that the amplitude of the signal is constant over consecutive symbols and shows that the discriminator function is directly related to the change in phase between successive symbols. Since the interval be- tween successive symbols is fixed, the discriminator func- tion can be interpreted as a frequency error signal. For DQPSK signals, the Z87200 computes the discrimina- tor function S AFC/QPSK (k) as: SAFC/QPSK( k)=SIGN[Dot(k)] Cross(k) - SIGN[Cross(k)] Dot(k), where the above expression can be reduced to the same as for DBPSK, SAFC/QPSK (k)»A2(k)*sin(DØrot(k)). BPSK/QPSK Modulation The Z87200 incorporates a Direct Digital Synthesizer (DDS) to implement its on-chip BPSK/QPSK modulator. In the Z87200 design, the NCO and thus the sampling clock for the modulator is driven by fRXIFCLK; for this reason, both TXIFCLK and RXIFCLK must be common if the on- chip BPSK/QPSK modulator is to be used. The BPSK/QPSK modulator can then be used to generate the transmit output signal at a programmable IF frequency, thereby eliminating the need for an external modulator. Because it is a sampled data system like the Downconvert- er of the Z87200, however, care must be taken to ensure that the results of aliasing do not adversely affect the out- put transmit signal.

modulator, when programmed to generate a signal at I.F. OUT is less than fRXIFCLK/2. quency fOUT , and the sampling rate fRXIFCLK. baseband component and first alias. Figure 16. Spectrum of DDS modulated at 0.1 x fRXIFCLK

Figure 17. Spectrum of DDS modulated at 0.1 x f

ferent, as shown in Figure 20. aliasing distortion which cannot be eliminated by filtering. Figure 18. Spectrum of DDS Modulated at 0.4 x f

1. Although the distortion is still fairly severe, adequate

Figure 19. Spectrum of DDS Modulated at 0.4 x f