Z86U18 ZILOG | Alldatasheet
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P RELIMINARY P RODUCT S PECIFICATION Z86U18 USB D EVICE C ONTROLLER WITH CMOS Z86K15 MCU
FEATURES
n USB Serial Interface Engine, Transceiver, and MCU Intergrated for USB Function Controller n +4.0V to +5.5V Operating Range n Low Power Consumption: 60 mW @ 6 MHz n Digital Inputs CMOS Levels with Internal Pull-Up Resistors n Four Direct Connect LED Drive Ports n Power-On Reset (POR), Hardware Watch-Dog Timer (WDT) n Intergrated USB Transceiver @ 1.5 Mb/sec n For Use In A Variety of Applications Including Keyboards and Game Controllers n Programmable 8-Bit Counter/Timer, with 6-Bit Programmable Prescaler n Five Vectored, Priority Interrupts from Five Different Sources n On-Chip Oscillator, Which Accepts A Crystal, Ceramic Resonator, LC or External Clock Drive (all clock speeds @ 6 MHz) n Low System EMI Emission n HALT/STOP Modes GENERAL DESCRIPTION The Z86U18 USB Controller is a member of the Z8 MCU family. The Z86U18 is characterized by a flexible I/O scheme, an efficient register architecture, and a number of ancillary features. It contains a dedicated USB interface (transceiver and SIE). For applications demanding powerful I/O capabilities, the Z86U18 (40- and 44-pin versions) provides 32 pins dedi- cated to application input and output. These lines are grouped into four ports, each port consists of eight lines and are configurable under software control to provide tim- ing, status signals, and serial or parallel I/O ports. It also has 2 pins to connect directly to the USB cable. To unburden the system from coping with real-time tasks, such as counting/timing and I/O data communications, the Z86U18 offers an on-chip counter/timer with a large num- ber of user-selectable modes. The Z86U18 achieves low EMI by means of several circuit implementations in the output drivers and clock circuitry of the device. With fast execution, efficient use of memory, sophisticated interrupt, input/output bit-manipulation capabilities, and easy hardware/software system expansion, along with low cost and low power consumption, the Z86U18 meets the needs of a variety of sophisticated applications (Figure 1: Functional Block Diagram) Notes : All signals with a preceding front slash, "/", are ac- tive Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Device ROM (KB) RAM (Bytes) I/O Lines Speed (MHz) Z86U18 4 188 32 6
a programmable timer for warm reset (USB reset). 4 EFT requirements in a system. : Drive to 3-pin ceramic resonator (@ 6 MHz). : From ceramic resonator or crystal. Figure 1. Z86U18 Functional Block Diagram
4 KB ROM
ital form to differential drive at the proper levels. Register File Memory at locations 010 to 017. vices will handle the full 12 Mb/sec data rate. pend Interrupt, it stops all the clocks. Resume by sending J to K transition on D+ and D- pins. develop code to be placed into the ROM of U18s. to Zilog and placed into the ROM of the Z86U18. Figure 2. Data To/From K86U18
may affect device reliability. itive current flows into the referenced pin (Figure 7). = GND = 0V; f = 1.0 MHz; unmeasured pins returned to GND.
- Voltage on all pins with respect to GND.
Figure 7. Test Load Diagram
Zilog USB Device Controller with CMOS Z86K15 MCU DS97KEY0102 P R E L I M I N A R Y DC CHARACTERISTICS V CC = 4.0V to 5.5V @ 0 C to +70 C Sym Parameter Min Max Unit Condition V CH Clock Input High Voltage 0.7 V CC V CC + 0.3V V Driven by External Clock Generator V CL Clock Input Low Voltage GND Ð0.3 0.2 V CC V Driven by External Clock Generator V IH Input High Voltage 0.7 V CC VCC + 0.3 V VIL Input Low Voltage GND Ð0.3 0.2 V CC V VOH Output High Voltage V CC Ð0.4 V I OH = Ð2.0 mA VOH Output High Voltage V CC Ð0.6 V I OH = Ð2.0 mA (see note 1 below.) VOL Output Low Voltage .4 V I OL= 4 mA VOL Output Low Voltage .8 V I OL= 4 mA (see note 1 below.) IOL Output Low 10 20 mA V OL= VCC Ð2.2 V (see note 1 below.) IOL Output Leakage Ð1 1 mAV IN = 0V, 5.25V ICC VCC Supply Current 12 mA @ 6.0 MHz ICC1 Halt Mode Current TBD mA @ 6.0 MHz ICC2 Stop Mode Current 10 mA Rp Pull Up Resistor 6.76 14.04 K ohm Rp Pull Up Resistor (P26-P25) 1.8 3 K ohm VUSB Voltage Regulator Output 3.0 3.6 V D+,D- Differential Signaling D- > D+ D+ > D- mV @ > 200mV Difference (see note 2 below) Notes: 1. Ports P37-P34. These may be used for LEDs or as general-purpose outputs requiring high sink current. 2. Except for SE0 for EOP and RESET (See 7.1.4 of USB Specification).
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Figure 8. Additional Timing
Zilog USB Device Controller with CMOS Z86K15 MCU DS97KEY0102 P R E L I M I N A R Y 9 AC ELECTRICAL CHARACTERISTICS Additional Timing Table TA=0°C to +70°C 5.0V, 6 MHz No Symbol Parameter Min Max Units Notes
1 TpC Input Clock Period 150 250 ns 1
2 TrC,TfC Clock Input Rise & Fall Times 25 ns 1
3 TwC Input Clock Width 37 ns 1
4 TwTinL Timer Input Low Width 70 ns 1
5 TwTinH Timer Input High Width 2.5TpC 1
6 TpTin Timer Input Period 4TpC 1
7 TrTin Timer Input Rise & Fall Timer 100 ns 1
8 TwIL Int. Request Low Time 70 ns 1,2 9 TwIH Int. Request Input High Time 3TpC 1,2
10 Twsm Stop-Mode Recovery Width Spec 5TpC ns
11 Tost Oscillator Start-up Time 5TpC ns
12 Twdt Watch-Dog Timer 3,0 ms
13 D+, D- Differential Rise and Fall Times 70 300 nS 3
Notes: 1. Timing Reference uses 0.7 V CC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31) 3. See USB Specification 7.1.1.2
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1 are 8-bit open drain output (Figure 9). Figure 9. Port 0 and Port 1 ConÞguration
Port with 4-bit input, 4-bit programmable I/O (Figure 10). and P26 have 2.4 K (±25 percent) pull-up resistor. Figure 10. Port 2 ConÞguration
10.4 KInput
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tors and outputs are capable of directly driving LED. Figure 11. Port 3 ConÞguration
10.4 Kohms
4 KB of program memory space at internal locations (Fig-
that correspond to the six available interrupts. tion of the active working register group. Register File Space. These 8 registers (as defined on pp. tions 0 to BFh, including the I/O port registers at 0-3. Figure 12. Program Memory Map Figure 13. Register Pointer Register
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Figure 14. Register File Architecture
rupt request, IRQ4, is generated. disturbing its value or count mode. Figure 15. Counter/Timers Block Diagram
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is automatically reset to 0 when accessed. is 1, and a 1 indicates active during HALT. Figure 16. WDT Turn-On Timing After Reset
- Reset Delay = POR 98.57 ms at 6 MHz.
18 Tpc
USB Device Controller with CMOS Z86K15 MCU Zilog
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FUNCTIONAL DESCRIPTION (Continued) Power-On-Reset (POR). A timer circuit is triggered by the system oscillator and is used for the Power-On Reset (POR) timer function. The POR time allows V CC and the os- cillator circuit to stabilize before instruction execution be- gins. POR period is defined as: The POR timer circuit is a one-shot timer triggered by low- er fail to Power OK status. The POR time is a nominal 100 ms at 6 MHz. The POR time is bypassed after Stop-Mode Recovery. HALT. HALT turns off the internal CPU clock, but not the oscillator. The counter/timer and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The Z86U18 recov- ers by interrupts, either externally or internally. USB Reset. Detection by the SIE of a reset from the Host will cause the chip to reset. The reset will be remembered so that the program can decide the source of the reset. The USB Reset will act even if the chip is in the STOP mode. STOP. This instruction turns off the internal clock and ex- ternal crystal oscillation. It reduces the standby current to less than 10 mA. The STOP Mode is terminated by an in- terrupt. An interrupt from any of the active (enabled) inter- rupts will remove the chip from the STOP Mode ( Ports 31- 33 and the USB reset). The timer can not do this as the clock is stopped. This causes the processor to restart the application program at the address or the vector of the in- terrupt and continue the program at the end of the interrupt service routine. In order to enter STOP (or HALT) Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode=FFH) immediately be- fore the appropriate sleep instruction, such as: POR (ms) = 98 ms FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode
Figure 19. Timer Mode Register Figure 20. Counter/Timer 0 Register Figure 21. Prescaler 0 Register Figure 22. Port 2 Mode Register
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
Figure 23. Port 2 Open Drain Register Figure 24. Interrupt Priority Register Figure 25. Interrupt Request Register
0 Port 2 Open-Drain
1 Port 2 Push-Pull
0 OFF *
0 POR/WDT*
1 Stop Recovery
0 POR*
1 WDT Timeout
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Figure 26. Interrupt Mask Register Figure 27. Flag Register Figure 28. Register Pointer
1 Enables IRQ5-IRQ0
Figure 29. Stack Pointer
Table 1. Address Offset Figure 30. Function Address Register register with the address received from the host.
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Figure 31. Endpoint 0 CS Register 7 Serviced Setup End W R The microcontroller writes a 1 to this register to clear setup end bit.
6 Serviced Outpacket
5 Send STALL W R If the microcontroller decodes an invalid descriptor, it writes a 1 to this
a set feature or clear feature USB command from the host.
4 Setup End R W If the function receives a new setup transaction before the previous one
3 Data End W R During the data phase of a control transfer after the microcontroller has
2 Force STALL R W The SIE writes to this register, when it encounters a protocol violation,
and issues a STALL handshake to the current control transfer.
1 In Packet Ready W R During the data phase, after the microcontroller has Þlled the data, it sets
this bit. It is cleared by SIE upon successful transmittion of data. clears this bit by writing it to Serviced Out Packet Ready bit. Figure 32. Endpoint 0 Write Count Register 2:0 R W The contents indicates the number of bytes in the FIFO.
Figure 33. Endpoint 0 FIFO Register 7:0 R/W R/W This is the Endpoint 0 FIFO data register. Figure 34. IN CS Register size to these bits. The default value = 8 Bytes.
1 Force STALL R/W W The SIE writes this register, when it encounters a protocol violation, and
it, when it receives a CLEAR_FEATURE (ENDPOINT_STALL). SIE upon successful transmission of data. Figure 35. IN FIFO Register 7:0 W R The microcontroller writes IN data to this register.
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Figure 36. Interrupt Register 3 Resume Interupt R W The ßag is sent on the Host signal to resume operations. 2 Suspend Interrupt R W The bit is set when theSuspend signaling is received from the host.
1 IN Endpoint Interrupt R W This bit is set upon:
0 Endpoint 0 Interrupt R W This bit set by SIE upon:
Figure 37. Misc. Register that particular interrupt is disabled.
1 Send Resume W R The microcontroller writes a 1 to this bit, while in suspend mode, and
set high for a duration of at least 10 ms by microcontroller.
0 Suspend R/W W This bit is set by the SIE when, the microcontroller is to enter suspend
or after it receives a resume out interrupt, and the clocks have started.
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Figure 40. 28-Pin PDIP Figure 41. 44-Pin PLCC
Figure 42. 40-Pin DIP
USB Device Controller with CMOS Z86K15 MCU Zilog
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ORDERING INFORMATION
For fast results, contact your Zilog sales office for assistance in ordering the part desired. CODES Package P = Plastic DIP V = Plastic Leaded Chip Carrier F = Quad Flat Pack Speed 06 = 6 MHz Environment C = Plastic Standard Temperature S = 0°C to +70°C © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ZilogÕs products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
6 MHz 6 MHz 6 MHz 6 MHz 6 MHz
40-Pin DIP 44-Pin PLCC 44-PIN QFP 28-Pin DIP 28-Pin SOIC Z86U18PSC Z86U18VSC Z86U18FSC Z86U18PSC Z86U18SSC Example: Z 86U18 05 P S C Environmental Flow T emperature Package Speed Product Number Zilog Prefix is a Z86U18, 6 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Zilog USB Device Controller with CMOS Z86K15 MCU DS97KEY0102 P R E L I M I N A R Y 29
USB Device Controller with CMOS Z86K15 MCU Zilog